Mercurial > hg > truffle
annotate src/share/vm/opto/phase.cpp @ 3109:3664989976e2
Merge
author | Gilles Duboscq <gilles.duboscq@oracle.com> |
---|---|
date | Fri, 01 Jul 2011 12:57:10 +0200 |
parents | 3763ca6579b7 |
children | ee138854b3a6 |
rev | line source |
---|---|
0 | 1 /* |
2249 | 2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
921
diff
changeset
|
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
921
diff
changeset
|
20 * or visit www.oracle.com if you need additional information or have any |
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
921
diff
changeset
|
21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
26 #include "code/nmethod.hpp" | |
27 #include "compiler/compileBroker.hpp" | |
28 #include "opto/compile.hpp" | |
29 #include "opto/node.hpp" | |
30 #include "opto/phase.hpp" | |
0 | 31 |
32 #ifndef PRODUCT | |
33 int Phase::_total_bytes_compiled = 0; | |
34 | |
35 elapsedTimer Phase::_t_totalCompilation; | |
36 elapsedTimer Phase::_t_methodCompilation; | |
37 elapsedTimer Phase::_t_stubCompilation; | |
38 #endif | |
39 | |
40 // The next timers used for LogCompilation | |
41 elapsedTimer Phase::_t_parser; | |
42 elapsedTimer Phase::_t_escapeAnalysis; | |
43 elapsedTimer Phase::_t_optimizer; | |
44 elapsedTimer Phase::_t_idealLoop; | |
45 elapsedTimer Phase::_t_ccp; | |
46 elapsedTimer Phase::_t_matcher; | |
47 elapsedTimer Phase::_t_registerAllocation; | |
48 elapsedTimer Phase::_t_output; | |
49 | |
50 #ifndef PRODUCT | |
51 elapsedTimer Phase::_t_graphReshaping; | |
52 elapsedTimer Phase::_t_scheduler; | |
418 | 53 elapsedTimer Phase::_t_blockOrdering; |
0 | 54 elapsedTimer Phase::_t_macroExpand; |
55 elapsedTimer Phase::_t_peephole; | |
56 elapsedTimer Phase::_t_codeGeneration; | |
57 elapsedTimer Phase::_t_registerMethod; | |
58 elapsedTimer Phase::_t_temporaryTimer1; | |
59 elapsedTimer Phase::_t_temporaryTimer2; | |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
60 elapsedTimer Phase::_t_idealLoopVerify; |
0 | 61 |
62 // Subtimers for _t_optimizer | |
63 elapsedTimer Phase::_t_iterGVN; | |
64 elapsedTimer Phase::_t_iterGVN2; | |
65 | |
66 // Subtimers for _t_registerAllocation | |
67 elapsedTimer Phase::_t_ctorChaitin; | |
68 elapsedTimer Phase::_t_buildIFGphysical; | |
69 elapsedTimer Phase::_t_computeLive; | |
70 elapsedTimer Phase::_t_regAllocSplit; | |
71 elapsedTimer Phase::_t_postAllocCopyRemoval; | |
72 elapsedTimer Phase::_t_fixupSpills; | |
73 | |
74 // Subtimers for _t_output | |
75 elapsedTimer Phase::_t_instrSched; | |
76 elapsedTimer Phase::_t_buildOopMaps; | |
77 #endif | |
78 | |
79 //------------------------------Phase------------------------------------------ | |
80 Phase::Phase( PhaseNumber pnum ) : _pnum(pnum), C( pnum == Compiler ? NULL : Compile::current()) { | |
605 | 81 // Poll for requests from shutdown mechanism to quiesce compiler (4448539, 4448544). |
0 | 82 // This is an effective place to poll, since the compiler is full of phases. |
83 // In particular, every inlining site uses a recursively created Parse phase. | |
84 CompileBroker::maybe_block(); | |
85 } | |
86 | |
87 #ifndef PRODUCT | |
88 static const double minimum_reported_time = 0.0001; // seconds | |
89 static const double expected_method_compile_coverage = 0.97; // % | |
90 static const double minimum_meaningful_method_compile = 2.00; // seconds | |
91 | |
92 void Phase::print_timers() { | |
93 tty->print_cr ("Accumulated compiler times:"); | |
94 tty->print_cr ("---------------------------"); | |
95 tty->print_cr (" Total compilation: %3.3f sec.", Phase::_t_totalCompilation.seconds()); | |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
96 tty->print (" method compilation : %3.3f sec", Phase::_t_methodCompilation.seconds()); |
0 | 97 tty->print ("/%d bytes",_total_bytes_compiled); |
98 tty->print_cr (" (%3.0f bytes per sec) ", Phase::_total_bytes_compiled / Phase::_t_methodCompilation.seconds()); | |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
99 tty->print_cr (" stub compilation : %3.3f sec.", Phase::_t_stubCompilation.seconds()); |
0 | 100 tty->print_cr (" Phases:"); |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
101 tty->print_cr (" parse : %3.3f sec", Phase::_t_parser.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
102 tty->print_cr (" optimizer : %3.3f sec", Phase::_t_optimizer.seconds()); |
0 | 103 if( Verbose || WizardMode ) { |
2249 | 104 if (DoEscapeAnalysis) { |
105 // EA is part of Optimizer. | |
106 tty->print_cr (" escape analysis: %3.3f sec", Phase::_t_escapeAnalysis.seconds()); | |
107 } | |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
108 tty->print_cr (" iterGVN : %3.3f sec", Phase::_t_iterGVN.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
109 tty->print_cr (" idealLoop : %3.3f sec", Phase::_t_idealLoop.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
110 tty->print_cr (" idealLoopVerify: %3.3f sec", Phase::_t_idealLoopVerify.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
111 tty->print_cr (" ccp : %3.3f sec", Phase::_t_ccp.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
112 tty->print_cr (" iterGVN2 : %3.3f sec", Phase::_t_iterGVN2.seconds()); |
2249 | 113 tty->print_cr (" macroExpand : %3.3f sec", Phase::_t_macroExpand.seconds()); |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
114 tty->print_cr (" graphReshape : %3.3f sec", Phase::_t_graphReshaping.seconds()); |
0 | 115 double optimizer_subtotal = Phase::_t_iterGVN.seconds() + |
116 Phase::_t_idealLoop.seconds() + Phase::_t_ccp.seconds() + | |
117 Phase::_t_graphReshaping.seconds(); | |
118 double percent_of_optimizer = ((optimizer_subtotal == 0.0) ? 0.0 : (optimizer_subtotal / Phase::_t_optimizer.seconds() * 100.0)); | |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
119 tty->print_cr (" subtotal : %3.3f sec, %3.2f %%", optimizer_subtotal, percent_of_optimizer); |
0 | 120 } |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
121 tty->print_cr (" matcher : %3.3f sec", Phase::_t_matcher.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
122 tty->print_cr (" scheduler : %3.3f sec", Phase::_t_scheduler.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
123 tty->print_cr (" regalloc : %3.3f sec", Phase::_t_registerAllocation.seconds()); |
0 | 124 if( Verbose || WizardMode ) { |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
125 tty->print_cr (" ctorChaitin : %3.3f sec", Phase::_t_ctorChaitin.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
126 tty->print_cr (" buildIFG : %3.3f sec", Phase::_t_buildIFGphysical.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
127 tty->print_cr (" computeLive : %3.3f sec", Phase::_t_computeLive.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
128 tty->print_cr (" regAllocSplit : %3.3f sec", Phase::_t_regAllocSplit.seconds()); |
0 | 129 tty->print_cr (" postAllocCopyRemoval: %3.3f sec", Phase::_t_postAllocCopyRemoval.seconds()); |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
130 tty->print_cr (" fixupSpills : %3.3f sec", Phase::_t_fixupSpills.seconds()); |
0 | 131 double regalloc_subtotal = Phase::_t_ctorChaitin.seconds() + |
132 Phase::_t_buildIFGphysical.seconds() + Phase::_t_computeLive.seconds() + | |
133 Phase::_t_regAllocSplit.seconds() + Phase::_t_fixupSpills.seconds() + | |
134 Phase::_t_postAllocCopyRemoval.seconds(); | |
135 double percent_of_regalloc = ((regalloc_subtotal == 0.0) ? 0.0 : (regalloc_subtotal / Phase::_t_registerAllocation.seconds() * 100.0)); | |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
136 tty->print_cr (" subtotal : %3.3f sec, %3.2f %%", regalloc_subtotal, percent_of_regalloc); |
0 | 137 } |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
138 tty->print_cr (" blockOrdering : %3.3f sec", Phase::_t_blockOrdering.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
139 tty->print_cr (" peephole : %3.3f sec", Phase::_t_peephole.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
140 tty->print_cr (" codeGen : %3.3f sec", Phase::_t_codeGeneration.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
141 tty->print_cr (" install_code : %3.3f sec", Phase::_t_registerMethod.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
142 tty->print_cr (" -------------- : ----------"); |
0 | 143 double phase_subtotal = Phase::_t_parser.seconds() + |
144 Phase::_t_optimizer.seconds() + Phase::_t_graphReshaping.seconds() + | |
145 Phase::_t_matcher.seconds() + Phase::_t_scheduler.seconds() + | |
418 | 146 Phase::_t_registerAllocation.seconds() + Phase::_t_blockOrdering.seconds() + |
0 | 147 Phase::_t_codeGeneration.seconds() + Phase::_t_registerMethod.seconds(); |
148 double percent_of_method_compile = ((phase_subtotal == 0.0) ? 0.0 : phase_subtotal / Phase::_t_methodCompilation.seconds()) * 100.0; | |
149 // counters inside Compile::CodeGen include time for adapters and stubs | |
150 // so phase-total can be greater than 100% | |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
151 tty->print_cr (" total : %3.3f sec, %3.2f %%", phase_subtotal, percent_of_method_compile); |
0 | 152 |
153 assert( percent_of_method_compile > expected_method_compile_coverage || | |
154 phase_subtotal < minimum_meaningful_method_compile, | |
155 "Must account for method compilation"); | |
156 | |
157 if( Phase::_t_temporaryTimer1.seconds() > minimum_reported_time ) { | |
158 tty->cr(); | |
159 tty->print_cr (" temporaryTimer1: %3.3f sec", Phase::_t_temporaryTimer1.seconds()); | |
160 } | |
161 if( Phase::_t_temporaryTimer2.seconds() > minimum_reported_time ) { | |
162 tty->cr(); | |
163 tty->print_cr (" temporaryTimer2: %3.3f sec", Phase::_t_temporaryTimer2.seconds()); | |
164 } | |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
165 tty->print_cr (" output : %3.3f sec", Phase::_t_output.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
166 tty->print_cr (" isched : %3.3f sec", Phase::_t_instrSched.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
167 tty->print_cr (" bldOopMaps : %3.3f sec", Phase::_t_buildOopMaps.seconds()); |
0 | 168 } |
169 #endif |