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3960
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1 /*
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2 * Copyright (c) 2003, 2011, Oracle and/or its affiliates. All rights reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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20 * or visit www.oracle.com if you need additional information or have any
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21 * questions.
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22 *
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23 */
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24
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25 #ifndef OS_CPU_BSD_X86_VM_ORDERACCESS_BSD_X86_INLINE_HPP
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26 #define OS_CPU_BSD_X86_VM_ORDERACCESS_BSD_X86_INLINE_HPP
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27
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28 #include "runtime/atomic.hpp"
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29 #include "runtime/orderAccess.hpp"
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30 #include "vm_version_x86.hpp"
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31
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32 // Implementation of class OrderAccess.
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33
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34 inline void OrderAccess::loadload() { acquire(); }
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35 inline void OrderAccess::storestore() { release(); }
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36 inline void OrderAccess::loadstore() { acquire(); }
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37 inline void OrderAccess::storeload() { fence(); }
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38
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39 inline void OrderAccess::acquire() {
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40 volatile intptr_t local_dummy;
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41 #ifdef AMD64
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42 __asm__ volatile ("movq 0(%%rsp), %0" : "=r" (local_dummy) : : "memory");
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43 #else
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44 __asm__ volatile ("movl 0(%%esp),%0" : "=r" (local_dummy) : : "memory");
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45 #endif // AMD64
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46 }
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47
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48 inline void OrderAccess::release() {
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49 // Avoid hitting the same cache-line from
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50 // different threads.
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51 volatile jint local_dummy = 0;
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52 }
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53
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54 inline void OrderAccess::fence() {
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55 if (os::is_MP()) {
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56 // always use locked addl since mfence is sometimes expensive
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57 #ifdef AMD64
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58 __asm__ volatile ("lock; addl $0,0(%%rsp)" : : : "cc", "memory");
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59 #else
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60 __asm__ volatile ("lock; addl $0,0(%%esp)" : : : "cc", "memory");
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61 #endif
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62 }
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63 }
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64
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65 inline jbyte OrderAccess::load_acquire(volatile jbyte* p) { return *p; }
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66 inline jshort OrderAccess::load_acquire(volatile jshort* p) { return *p; }
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67 inline jint OrderAccess::load_acquire(volatile jint* p) { return *p; }
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68 inline jlong OrderAccess::load_acquire(volatile jlong* p) { return Atomic::load(p); }
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69 inline jubyte OrderAccess::load_acquire(volatile jubyte* p) { return *p; }
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70 inline jushort OrderAccess::load_acquire(volatile jushort* p) { return *p; }
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71 inline juint OrderAccess::load_acquire(volatile juint* p) { return *p; }
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72 inline julong OrderAccess::load_acquire(volatile julong* p) { return Atomic::load((volatile jlong*)p); }
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73 inline jfloat OrderAccess::load_acquire(volatile jfloat* p) { return *p; }
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74 inline jdouble OrderAccess::load_acquire(volatile jdouble* p) { return *p; }
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75
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76 inline intptr_t OrderAccess::load_ptr_acquire(volatile intptr_t* p) { return *p; }
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77 inline void* OrderAccess::load_ptr_acquire(volatile void* p) { return *(void* volatile *)p; }
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78 inline void* OrderAccess::load_ptr_acquire(const volatile void* p) { return *(void* const volatile *)p; }
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79
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80 inline void OrderAccess::release_store(volatile jbyte* p, jbyte v) { *p = v; }
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81 inline void OrderAccess::release_store(volatile jshort* p, jshort v) { *p = v; }
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82 inline void OrderAccess::release_store(volatile jint* p, jint v) { *p = v; }
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83 inline void OrderAccess::release_store(volatile jlong* p, jlong v) { Atomic::store(v, p); }
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84 inline void OrderAccess::release_store(volatile jubyte* p, jubyte v) { *p = v; }
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85 inline void OrderAccess::release_store(volatile jushort* p, jushort v) { *p = v; }
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86 inline void OrderAccess::release_store(volatile juint* p, juint v) { *p = v; }
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87 inline void OrderAccess::release_store(volatile julong* p, julong v) { Atomic::store((jlong)v, (volatile jlong*)p); }
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88 inline void OrderAccess::release_store(volatile jfloat* p, jfloat v) { *p = v; }
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89 inline void OrderAccess::release_store(volatile jdouble* p, jdouble v) { *p = v; }
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90
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91 inline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { *p = v; }
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92 inline void OrderAccess::release_store_ptr(volatile void* p, void* v) { *(void* volatile *)p = v; }
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93
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94 inline void OrderAccess::store_fence(jbyte* p, jbyte v) {
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95 __asm__ volatile ( "xchgb (%2),%0"
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96 : "=q" (v)
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97 : "0" (v), "r" (p)
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98 : "memory");
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99 }
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100 inline void OrderAccess::store_fence(jshort* p, jshort v) {
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101 __asm__ volatile ( "xchgw (%2),%0"
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102 : "=r" (v)
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103 : "0" (v), "r" (p)
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104 : "memory");
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105 }
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106 inline void OrderAccess::store_fence(jint* p, jint v) {
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107 __asm__ volatile ( "xchgl (%2),%0"
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108 : "=r" (v)
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109 : "0" (v), "r" (p)
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110 : "memory");
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111 }
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112
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113 inline void OrderAccess::store_fence(jlong* p, jlong v) {
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114 #ifdef AMD64
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115 __asm__ __volatile__ ("xchgq (%2), %0"
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116 : "=r" (v)
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117 : "0" (v), "r" (p)
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118 : "memory");
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119 #else
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120 *p = v; fence();
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121 #endif // AMD64
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122 }
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123
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124 // AMD64 copied the bodies for the the signed version. 32bit did this. As long as the
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125 // compiler does the inlining this is simpler.
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126 inline void OrderAccess::store_fence(jubyte* p, jubyte v) { store_fence((jbyte*)p, (jbyte)v); }
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127 inline void OrderAccess::store_fence(jushort* p, jushort v) { store_fence((jshort*)p, (jshort)v); }
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128 inline void OrderAccess::store_fence(juint* p, juint v) { store_fence((jint*)p, (jint)v); }
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129 inline void OrderAccess::store_fence(julong* p, julong v) { store_fence((jlong*)p, (jlong)v); }
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130 inline void OrderAccess::store_fence(jfloat* p, jfloat v) { *p = v; fence(); }
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131 inline void OrderAccess::store_fence(jdouble* p, jdouble v) { *p = v; fence(); }
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132
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133 inline void OrderAccess::store_ptr_fence(intptr_t* p, intptr_t v) {
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134 #ifdef AMD64
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135 __asm__ __volatile__ ("xchgq (%2), %0"
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136 : "=r" (v)
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137 : "0" (v), "r" (p)
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138 : "memory");
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139 #else
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140 store_fence((jint*)p, (jint)v);
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141 #endif // AMD64
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142 }
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143
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144 inline void OrderAccess::store_ptr_fence(void** p, void* v) {
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145 #ifdef AMD64
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146 __asm__ __volatile__ ("xchgq (%2), %0"
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147 : "=r" (v)
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148 : "0" (v), "r" (p)
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149 : "memory");
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150 #else
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151 store_fence((jint*)p, (jint)v);
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152 #endif // AMD64
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153 }
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154
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155 // Must duplicate definitions instead of calling store_fence because we don't want to cast away volatile.
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156 inline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) {
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157 __asm__ volatile ( "xchgb (%2),%0"
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158 : "=q" (v)
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159 : "0" (v), "r" (p)
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160 : "memory");
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161 }
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162 inline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) {
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163 __asm__ volatile ( "xchgw (%2),%0"
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164 : "=r" (v)
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165 : "0" (v), "r" (p)
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166 : "memory");
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167 }
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168 inline void OrderAccess::release_store_fence(volatile jint* p, jint v) {
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169 __asm__ volatile ( "xchgl (%2),%0"
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170 : "=r" (v)
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171 : "0" (v), "r" (p)
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172 : "memory");
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173 }
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174
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175 inline void OrderAccess::release_store_fence(volatile jlong* p, jlong v) {
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176 #ifdef AMD64
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177 __asm__ __volatile__ ( "xchgq (%2), %0"
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178 : "=r" (v)
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179 : "0" (v), "r" (p)
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180 : "memory");
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181 #else
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182 release_store(p, v); fence();
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183 #endif // AMD64
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184 }
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185
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186 inline void OrderAccess::release_store_fence(volatile jubyte* p, jubyte v) { release_store_fence((volatile jbyte*)p, (jbyte)v); }
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187 inline void OrderAccess::release_store_fence(volatile jushort* p, jushort v) { release_store_fence((volatile jshort*)p, (jshort)v); }
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188 inline void OrderAccess::release_store_fence(volatile juint* p, juint v) { release_store_fence((volatile jint*)p, (jint)v); }
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189 inline void OrderAccess::release_store_fence(volatile julong* p, julong v) { release_store_fence((volatile jlong*)p, (jlong)v); }
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190
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191 inline void OrderAccess::release_store_fence(volatile jfloat* p, jfloat v) { *p = v; fence(); }
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192 inline void OrderAccess::release_store_fence(volatile jdouble* p, jdouble v) { *p = v; fence(); }
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193
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194 inline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) {
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195 #ifdef AMD64
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196 __asm__ __volatile__ ( "xchgq (%2), %0"
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197 : "=r" (v)
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198 : "0" (v), "r" (p)
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199 : "memory");
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200 #else
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201 release_store_fence((volatile jint*)p, (jint)v);
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202 #endif // AMD64
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203 }
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204 inline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) {
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205 #ifdef AMD64
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206 __asm__ __volatile__ ( "xchgq (%2), %0"
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207 : "=r" (v)
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208 : "0" (v), "r" (p)
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209 : "memory");
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210 #else
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211 release_store_fence((volatile jint*)p, (jint)v);
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212 #endif // AMD64
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213 }
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214
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215 #endif // OS_CPU_BSD_X86_VM_ORDERACCESS_BSD_X86_INLINE_HPP
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