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annotate jvmci/com.oracle.jvmci.code/src/com/oracle/jvmci/code/MemoryBarriers.java @ 21798:395ac43a8578

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moved JVMCI sources from graal/ to jvmci/ directory
author Doug Simon <doug.simon@oracle.com>
date Tue, 09 Jun 2015 00:22:49 +0200
parents graal/com.oracle.jvmci.code/src/com/oracle/jvmci/code/MemoryBarriers.java@48c1ebd24120
children
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1 /*
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2 * Copyright (c) 2011, 2011, Oracle and/or its affiliates. All rights reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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20 * or visit www.oracle.com if you need additional information or have any
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21 * questions.
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22 */
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23 package com.oracle.jvmci.code;
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24
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25 /**
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26 * Constants and intrinsic definition for memory barriers.
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27 *
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28 * The documentation for each constant is taken from Doug Lea's <a
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29 * href="http://gee.cs.oswego.edu/dl/jmm/cookbook.html">The JSR-133 Cookbook for Compiler
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30 * Writers</a>.
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31 * <p>
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32 * The {@code JMM_*} constants capture the memory barriers necessary to implement the Java Memory
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33 * Model with respect to volatile field accesses. Their values are explained by this comment from
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34 * templateTable_i486.cpp in the HotSpot source code:
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35 *
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36 * <pre>
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37 * Volatile variables demand their effects be made known to all CPU's in
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38 * order. Store buffers on most chips allow reads &amp; writes to reorder; the
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39 * JMM's ReadAfterWrite.java test fails in -Xint mode without some kind of
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40 * memory barrier (i.e., it's not sufficient that the interpreter does not
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41 * reorder volatile references, the hardware also must not reorder them).
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42 *
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43 * According to the new Java Memory Model (JMM):
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44 * (1) All volatiles are serialized wrt to each other.
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45 * ALSO reads &amp; writes act as acquire &amp; release, so:
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46 * (2) A read cannot let unrelated NON-volatile memory refs that happen after
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47 * the read float up to before the read. It's OK for non-volatile memory refs
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48 * that happen before the volatile read to float down below it.
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49 * (3) Similarly, a volatile write cannot let unrelated NON-volatile memory refs
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50 * that happen BEFORE the write float down to after the write. It's OK for
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51 * non-volatile memory refs that happen after the volatile write to float up
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52 * before it.
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53 *
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54 * We only put in barriers around volatile refs (they are expensive), not
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55 * _between_ memory refs (which would require us to track the flavor of the
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56 * previous memory refs). Requirements (2) and (3) require some barriers
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57 * before volatile stores and after volatile loads. These nearly cover
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58 * requirement (1) but miss the volatile-store-volatile-load case. This final
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59 * case is placed after volatile-stores although it could just as well go
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60 * before volatile-loads.
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61 * </pre>
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62 */
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63 public class MemoryBarriers {
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64
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65 /**
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66 * The sequence {@code Load1; LoadLoad; Load2} ensures that {@code Load1}'s data are loaded
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67 * before data accessed by {@code Load2} and all subsequent load instructions are loaded. In
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68 * general, explicit {@code LoadLoad} barriers are needed on processors that perform speculative
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69 * loads and/or out-of-order processing in which waiting load instructions can bypass waiting
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70 * stores. On processors that guarantee to always preserve load ordering, these barriers amount
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71 * to no-ops.
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72 */
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73 public static final int LOAD_LOAD = 0x0001;
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74
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75 /**
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76 * The sequence {@code Load1; LoadStore; Store2} ensures that {@code Load1}'s data are loaded
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77 * before all data associated with {@code Store2} and subsequent store instructions are flushed.
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78 * {@code LoadStore} barriers are needed only on those out-of-order processors in which waiting
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79 * store instructions can bypass loads.
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80 */
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81 public static final int LOAD_STORE = 0x0002;
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82
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83 /**
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84 * The sequence {@code Store1; StoreLoad; Load2} ensures that {@code Store1}'s data are made
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85 * visible to other processors (i.e., flushed to main memory) before data accessed by
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86 * {@code Load2} and all subsequent load instructions are loaded. {@code StoreLoad} barriers
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87 * protect against a subsequent load incorrectly using {@code Store1}'s data value rather than
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88 * that from a more recent store to the same location performed by a different processor.
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89 * Because of this, on the processors discussed below, a {@code StoreLoad} is strictly necessary
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90 * only for separating stores from subsequent loads of the same location(s) as were stored
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91 * before the barrier. {@code StoreLoad} barriers are needed on nearly all recent
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92 * multiprocessors, and are usually the most expensive kind. Part of the reason they are
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93 * expensive is that they must disable mechanisms that ordinarily bypass cache to satisfy loads
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94 * from write-buffers. This might be implemented by letting the buffer fully flush, among other
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95 * possible stalls.
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96 */
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97 public static final int STORE_LOAD = 0x0004;
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98
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99 /**
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100 * The sequence {@code Store1; StoreStore; Store2} ensures that {@code Store1}'s data are
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101 * visible to other processors (i.e., flushed to memory) before the data associated with
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102 * {@code Store2} and all subsequent store instructions. In general, {@code StoreStore} barriers
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103 * are needed on processors that do not otherwise guarantee strict ordering of flushes from
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104 * write buffers and/or caches to other processors or main memory.
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105 */
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106 public static final int STORE_STORE = 0x0008;
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107
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108 public static final int JMM_PRE_VOLATILE_WRITE = LOAD_STORE | STORE_STORE;
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109 public static final int JMM_POST_VOLATILE_WRITE = STORE_LOAD | STORE_STORE;
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110 public static final int JMM_PRE_VOLATILE_READ = 0;
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111 public static final int JMM_POST_VOLATILE_READ = LOAD_LOAD | LOAD_STORE;
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112
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113 public static String barriersString(int barriers) {
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114 StringBuilder sb = new StringBuilder();
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115 sb.append((barriers & LOAD_LOAD) != 0 ? "LOAD_LOAD " : "");
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116 sb.append((barriers & LOAD_STORE) != 0 ? "LOAD_STORE " : "");
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117 sb.append((barriers & STORE_LOAD) != 0 ? "STORE_LOAD " : "");
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118 sb.append((barriers & STORE_STORE) != 0 ? "STORE_STORE " : "");
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119 return sb.toString().trim();
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120 }
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121 }