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1 /*
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2 * Copyright 1999-2006 Sun Microsystems, Inc. All Rights Reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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20 * CA 95054 USA or visit www.sun.com if you need additional information or
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21 * have any questions.
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22 *
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23 */
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24
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25 # include "incls/_precompiled.incl"
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26 # include "incls/_c1_FrameMap_x86.cpp.incl"
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27
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28 const int FrameMap::pd_c_runtime_reserved_arg_size = 0;
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29
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30 LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool) {
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31 LIR_Opr opr = LIR_OprFact::illegalOpr;
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32 VMReg r_1 = reg->first();
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33 VMReg r_2 = reg->second();
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34 if (r_1->is_stack()) {
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35 // Convert stack slot to an SP offset
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36 // The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value
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37 // so we must add it in here.
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38 int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
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39 opr = LIR_OprFact::address(new LIR_Address(rsp_opr, st_off, type));
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40 } else if (r_1->is_Register()) {
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41 Register reg = r_1->as_Register();
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42 if (r_2->is_Register()) {
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43 Register reg2 = r_2->as_Register();
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44 opr = as_long_opr(reg2, reg);
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45 } else if (type == T_OBJECT) {
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46 opr = as_oop_opr(reg);
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47 } else {
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48 opr = as_opr(reg);
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49 }
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50 } else if (r_1->is_FloatRegister()) {
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51 assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
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52 int num = r_1->as_FloatRegister()->encoding();
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53 if (type == T_FLOAT) {
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54 opr = LIR_OprFact::single_fpu(num);
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55 } else {
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56 opr = LIR_OprFact::double_fpu(num);
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57 }
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58 } else if (r_1->is_XMMRegister()) {
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59 assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
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60 int num = r_1->as_XMMRegister()->encoding();
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61 if (type == T_FLOAT) {
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62 opr = LIR_OprFact::single_xmm(num);
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63 } else {
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64 opr = LIR_OprFact::double_xmm(num);
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65 }
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66 } else {
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67 ShouldNotReachHere();
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68 }
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69 return opr;
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70 }
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71
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72
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73 LIR_Opr FrameMap::rsi_opr;
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74 LIR_Opr FrameMap::rdi_opr;
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75 LIR_Opr FrameMap::rbx_opr;
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76 LIR_Opr FrameMap::rax_opr;
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77 LIR_Opr FrameMap::rdx_opr;
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78 LIR_Opr FrameMap::rcx_opr;
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79 LIR_Opr FrameMap::rsp_opr;
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80 LIR_Opr FrameMap::rbp_opr;
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81
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82 LIR_Opr FrameMap::receiver_opr;
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83
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84 LIR_Opr FrameMap::rsi_oop_opr;
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85 LIR_Opr FrameMap::rdi_oop_opr;
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86 LIR_Opr FrameMap::rbx_oop_opr;
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87 LIR_Opr FrameMap::rax_oop_opr;
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88 LIR_Opr FrameMap::rdx_oop_opr;
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89 LIR_Opr FrameMap::rcx_oop_opr;
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90
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91 LIR_Opr FrameMap::rax_rdx_long_opr;
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92 LIR_Opr FrameMap::rbx_rcx_long_opr;
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93 LIR_Opr FrameMap::fpu0_float_opr;
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94 LIR_Opr FrameMap::fpu0_double_opr;
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95 LIR_Opr FrameMap::xmm0_float_opr;
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96 LIR_Opr FrameMap::xmm0_double_opr;
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97
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98 LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, };
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99 LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, };
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100 LIR_Opr FrameMap::_caller_save_xmm_regs[] = { 0, };
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101
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102 XMMRegister FrameMap::_xmm_regs [8] = { 0, };
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103
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104 XMMRegister FrameMap::nr2xmmreg(int rnr) {
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105 assert(_init_done, "tables not initialized");
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106 return _xmm_regs[rnr];
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107 }
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108
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109 //--------------------------------------------------------
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110 // FrameMap
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111 //--------------------------------------------------------
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112
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113 void FrameMap::init() {
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114 if (_init_done) return;
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115
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116 assert(nof_cpu_regs == 8, "wrong number of CPU registers");
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117 map_register(0, rsi); rsi_opr = LIR_OprFact::single_cpu(0); rsi_oop_opr = LIR_OprFact::single_cpu_oop(0);
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118 map_register(1, rdi); rdi_opr = LIR_OprFact::single_cpu(1); rdi_oop_opr = LIR_OprFact::single_cpu_oop(1);
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119 map_register(2, rbx); rbx_opr = LIR_OprFact::single_cpu(2); rbx_oop_opr = LIR_OprFact::single_cpu_oop(2);
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120 map_register(3, rax); rax_opr = LIR_OprFact::single_cpu(3); rax_oop_opr = LIR_OprFact::single_cpu_oop(3);
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121 map_register(4, rdx); rdx_opr = LIR_OprFact::single_cpu(4); rdx_oop_opr = LIR_OprFact::single_cpu_oop(4);
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122 map_register(5, rcx); rcx_opr = LIR_OprFact::single_cpu(5); rcx_oop_opr = LIR_OprFact::single_cpu_oop(5);
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123 map_register(6, rsp); rsp_opr = LIR_OprFact::single_cpu(6);
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124 map_register(7, rbp); rbp_opr = LIR_OprFact::single_cpu(7);
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125
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126 rax_rdx_long_opr = LIR_OprFact::double_cpu(3 /*eax*/, 4 /*edx*/);
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127 rbx_rcx_long_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 5 /*ecx*/);
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128 fpu0_float_opr = LIR_OprFact::single_fpu(0);
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129 fpu0_double_opr = LIR_OprFact::double_fpu(0);
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130 xmm0_float_opr = LIR_OprFact::single_xmm(0);
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131 xmm0_double_opr = LIR_OprFact::double_xmm(0);
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132
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133 _caller_save_cpu_regs[0] = rsi_opr;
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134 _caller_save_cpu_regs[1] = rdi_opr;
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135 _caller_save_cpu_regs[2] = rbx_opr;
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136 _caller_save_cpu_regs[3] = rax_opr;
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137 _caller_save_cpu_regs[4] = rdx_opr;
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138 _caller_save_cpu_regs[5] = rcx_opr;
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139
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140
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141 _xmm_regs[0] = xmm0;
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142 _xmm_regs[1] = xmm1;
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143 _xmm_regs[2] = xmm2;
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144 _xmm_regs[3] = xmm3;
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145 _xmm_regs[4] = xmm4;
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146 _xmm_regs[5] = xmm5;
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147 _xmm_regs[6] = xmm6;
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148 _xmm_regs[7] = xmm7;
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149
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150 for (int i = 0; i < 8; i++) {
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151 _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i);
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152 _caller_save_xmm_regs[i] = LIR_OprFact::single_xmm(i);
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153 }
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154
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155 _init_done = true;
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156
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157 VMRegPair regs;
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158 BasicType sig_bt = T_OBJECT;
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159 SharedRuntime::java_calling_convention(&sig_bt, ®s, 1, true);
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160 receiver_opr = as_oop_opr(regs.first()->as_Register());
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161 assert(receiver_opr == rcx_oop_opr, "rcvr ought to be rcx");
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162 }
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163
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164
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165 Address FrameMap::make_new_address(ByteSize sp_offset) const {
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166 // for rbp, based address use this:
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167 // return Address(rbp, in_bytes(sp_offset) - (framesize() - 2) * 4);
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168 return Address(rsp, in_bytes(sp_offset));
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169 }
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170
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171
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172 // ----------------mapping-----------------------
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173 // all mapping is based on rbp, addressing, except for simple leaf methods where we access
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174 // the locals rsp based (and no frame is built)
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175
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176
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177 // Frame for simple leaf methods (quick entries)
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178 //
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179 // +----------+
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180 // | ret addr | <- TOS
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181 // +----------+
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182 // | args |
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183 // | ...... |
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184
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185 // Frame for standard methods
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186 //
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187 // | .........| <- TOS
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188 // | locals |
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189 // +----------+
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190 // | old rbp, | <- EBP
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191 // +----------+
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192 // | ret addr |
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193 // +----------+
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194 // | args |
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195 // | .........|
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196
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197
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198 // For OopMaps, map a local variable or spill index to an VMRegImpl name.
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199 // This is the offset from sp() in the frame of the slot for the index,
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200 // skewed by VMRegImpl::stack0 to indicate a stack location (vs.a register.)
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201 //
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202 // framesize +
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203 // stack0 stack0 0 <- VMReg
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204 // | | <registers> |
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205 // ...........|..............|.............|
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206 // 0 1 2 3 x x 4 5 6 ... | <- local indices
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207 // ^ ^ sp() ( x x indicate link
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208 // | | and return addr)
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209 // arguments non-argument locals
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210
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211
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212 VMReg FrameMap::fpu_regname (int n) {
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213 // Return the OptoReg name for the fpu stack slot "n"
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214 // A spilled fpu stack slot comprises to two single-word OptoReg's.
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215 return as_FloatRegister(n)->as_VMReg();
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216 }
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217
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218 LIR_Opr FrameMap::stack_pointer() {
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219 return FrameMap::rsp_opr;
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220 }
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221
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222
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223 bool FrameMap::validate_frame() {
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224 return true;
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225 }
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