annotate src/cpu/x86/vm/icache_x86.hpp @ 71:3d62cb85208d

6662967: Optimize I2D conversion on new x86 Summary: Use CVTDQ2PS and CVTDQ2PD for integer values conversions to float and double values on new AMD cpu. Reviewed-by: sgoldman, never
author kvn
date Wed, 19 Mar 2008 15:33:25 -0700
parents a61af66fc99e
children c18cbe5936b8
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1 /*
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2 * Copyright 1997-2004 Sun Microsystems, Inc. All Rights Reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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20 * CA 95054 USA or visit www.sun.com if you need additional information or
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21 * have any questions.
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22 *
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23 */
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24
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25 // Interface for updating the instruction cache. Whenever the VM modifies
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26 // code, part of the processor instruction cache potentially has to be flushed.
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27
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28 // On the x86, this is a no-op -- the I-cache is guaranteed to be consistent
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29 // after the next jump, and the VM never modifies instructions directly ahead
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30 // of the instruction fetch path.
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31
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32 // [phh] It's not clear that the above comment is correct, because on an MP
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33 // system where the dcaches are not snooped, only the thread doing the invalidate
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34 // will see the update. Even in the snooped case, a memory fence would be
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35 // necessary if stores weren't ordered. Fortunately, they are on all known
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36 // x86 implementations.
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37
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38 class ICache : public AbstractICache {
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39 public:
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40 #ifdef AMD64
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41 enum {
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42 stub_size = 64, // Size of the icache flush stub in bytes
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43 line_size = 32, // Icache line size in bytes
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44 log2_line_size = 5 // log2(line_size)
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45 };
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46
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47 // Use default implementation
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48 #else
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49 enum {
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50 stub_size = 16, // Size of the icache flush stub in bytes
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51 line_size = BytesPerWord, // conservative
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52 log2_line_size = LogBytesPerWord // log2(line_size)
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53 };
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54 #endif // AMD64
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55 };