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0
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1 /*
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2 * Copyright 1997-2007 Sun Microsystems, Inc. All Rights Reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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20 * CA 95054 USA or visit www.sun.com if you need additional information or
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21 * have any questions.
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22 *
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23 */
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24
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25 # include "incls/_precompiled.incl"
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26 # include "incls/_nativeInst_x86.cpp.incl"
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27
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28 void NativeInstruction::wrote(int offset) {
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29 ICache::invalidate_word(addr_at(offset));
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30 }
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31
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32
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33 void NativeCall::verify() {
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34 // Make sure code pattern is actually a call imm32 instruction.
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35 int inst = ubyte_at(0);
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36 if (inst != instruction_code) {
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37 tty->print_cr("Addr: " INTPTR_FORMAT " Code: 0x%x", instruction_address(),
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38 inst);
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39 fatal("not a call disp32");
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40 }
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41 }
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42
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43 address NativeCall::destination() const {
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44 // Getting the destination of a call isn't safe because that call can
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45 // be getting patched while you're calling this. There's only special
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46 // places where this can be called but not automatically verifiable by
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47 // checking which locks are held. The solution is true atomic patching
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48 // on x86, nyi.
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49 return return_address() + displacement();
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50 }
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51
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52 void NativeCall::print() {
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53 tty->print_cr(PTR_FORMAT ": call " PTR_FORMAT,
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54 instruction_address(), destination());
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55 }
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56
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57 // Inserts a native call instruction at a given pc
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58 void NativeCall::insert(address code_pos, address entry) {
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59 intptr_t disp = (intptr_t)entry - ((intptr_t)code_pos + 1 + 4);
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60 #ifdef AMD64
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61 guarantee(disp == (intptr_t)(jint)disp, "must be 32-bit offset");
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62 #endif // AMD64
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63 *code_pos = instruction_code;
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64 *((int32_t *)(code_pos+1)) = (int32_t) disp;
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65 ICache::invalidate_range(code_pos, instruction_size);
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66 }
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67
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68 // MT-safe patching of a call instruction.
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69 // First patches first word of instruction to two jmp's that jmps to them
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70 // selfs (spinlock). Then patches the last byte, and then atomicly replaces
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71 // the jmp's with the first 4 byte of the new instruction.
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72 void NativeCall::replace_mt_safe(address instr_addr, address code_buffer) {
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73 assert(Patching_lock->is_locked() ||
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74 SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
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75 assert (instr_addr != NULL, "illegal address for code patching");
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76
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77 NativeCall* n_call = nativeCall_at (instr_addr); // checking that it is a call
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78 if (os::is_MP()) {
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79 guarantee((intptr_t)instr_addr % BytesPerWord == 0, "must be aligned");
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80 }
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81
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82 // First patch dummy jmp in place
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83 unsigned char patch[4];
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84 assert(sizeof(patch)==sizeof(jint), "sanity check");
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85 patch[0] = 0xEB; // jmp rel8
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86 patch[1] = 0xFE; // jmp to self
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87 patch[2] = 0xEB;
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88 patch[3] = 0xFE;
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89
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90 // First patch dummy jmp in place
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91 *(jint*)instr_addr = *(jint *)patch;
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92
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93 // Invalidate. Opteron requires a flush after every write.
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94 n_call->wrote(0);
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95
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96 // Patch 4th byte
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97 instr_addr[4] = code_buffer[4];
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98
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99 n_call->wrote(4);
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100
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101 // Patch bytes 0-3
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102 *(jint*)instr_addr = *(jint *)code_buffer;
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103
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104 n_call->wrote(0);
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105
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106 #ifdef ASSERT
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107 // verify patching
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108 for ( int i = 0; i < instruction_size; i++) {
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109 address ptr = (address)((intptr_t)code_buffer + i);
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110 int a_byte = (*ptr) & 0xFF;
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111 assert(*((address)((intptr_t)instr_addr + i)) == a_byte, "mt safe patching failed");
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112 }
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113 #endif
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114
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115 }
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116
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117
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118 // Similar to replace_mt_safe, but just changes the destination. The
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119 // important thing is that free-running threads are able to execute this
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120 // call instruction at all times. If the displacement field is aligned
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121 // we can simply rely on atomicity of 32-bit writes to make sure other threads
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122 // will see no intermediate states. Otherwise, the first two bytes of the
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123 // call are guaranteed to be aligned, and can be atomically patched to a
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124 // self-loop to guard the instruction while we change the other bytes.
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125
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126 // We cannot rely on locks here, since the free-running threads must run at
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127 // full speed.
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128 //
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129 // Used in the runtime linkage of calls; see class CompiledIC.
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130 // (Cf. 4506997 and 4479829, where threads witnessed garbage displacements.)
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131 void NativeCall::set_destination_mt_safe(address dest) {
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132 debug_only(verify());
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133 // Make sure patching code is locked. No two threads can patch at the same
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134 // time but one may be executing this code.
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135 assert(Patching_lock->is_locked() ||
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136 SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
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137 // Both C1 and C2 should now be generating code which aligns the patched address
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138 // to be within a single cache line except that C1 does not do the alignment on
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139 // uniprocessor systems.
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140 bool is_aligned = ((uintptr_t)displacement_address() + 0) / cache_line_size ==
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141 ((uintptr_t)displacement_address() + 3) / cache_line_size;
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142
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143 guarantee(!os::is_MP() || is_aligned, "destination must be aligned");
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144
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145 if (is_aligned) {
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146 // Simple case: The destination lies within a single cache line.
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147 set_destination(dest);
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148 } else if ((uintptr_t)instruction_address() / cache_line_size ==
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149 ((uintptr_t)instruction_address()+1) / cache_line_size) {
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150 // Tricky case: The instruction prefix lies within a single cache line.
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151 intptr_t disp = dest - return_address();
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152 #ifdef AMD64
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153 guarantee(disp == (intptr_t)(jint)disp, "must be 32-bit offset");
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154 #endif // AMD64
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155
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156 int call_opcode = instruction_address()[0];
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157
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158 // First patch dummy jump in place:
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159 {
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160 u_char patch_jump[2];
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161 patch_jump[0] = 0xEB; // jmp rel8
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162 patch_jump[1] = 0xFE; // jmp to self
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163
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164 assert(sizeof(patch_jump)==sizeof(short), "sanity check");
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165 *(short*)instruction_address() = *(short*)patch_jump;
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166 }
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167 // Invalidate. Opteron requires a flush after every write.
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168 wrote(0);
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169
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170 // (Note: We assume any reader which has already started to read
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171 // the unpatched call will completely read the whole unpatched call
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172 // without seeing the next writes we are about to make.)
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173
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174 // Next, patch the last three bytes:
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175 u_char patch_disp[5];
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176 patch_disp[0] = call_opcode;
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177 *(int32_t*)&patch_disp[1] = (int32_t)disp;
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178 assert(sizeof(patch_disp)==instruction_size, "sanity check");
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179 for (int i = sizeof(short); i < instruction_size; i++)
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180 instruction_address()[i] = patch_disp[i];
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181
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182 // Invalidate. Opteron requires a flush after every write.
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183 wrote(sizeof(short));
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184
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185 // (Note: We assume that any reader which reads the opcode we are
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186 // about to repatch will also read the writes we just made.)
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187
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188 // Finally, overwrite the jump:
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189 *(short*)instruction_address() = *(short*)patch_disp;
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190 // Invalidate. Opteron requires a flush after every write.
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191 wrote(0);
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192
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193 debug_only(verify());
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194 guarantee(destination() == dest, "patch succeeded");
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195 } else {
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196 // Impossible: One or the other must be atomically writable.
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197 ShouldNotReachHere();
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198 }
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199 }
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200
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201
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202 void NativeMovConstReg::verify() {
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203 #ifdef AMD64
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204 // make sure code pattern is actually a mov reg64, imm64 instruction
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205 if ((ubyte_at(0) != Assembler::REX_W && ubyte_at(0) != Assembler::REX_WB) ||
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206 (ubyte_at(1) & (0xff ^ register_mask)) != 0xB8) {
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207 print();
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208 fatal("not a REX.W[B] mov reg64, imm64");
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209 }
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210 #else
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211 // make sure code pattern is actually a mov reg, imm32 instruction
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212 u_char test_byte = *(u_char*)instruction_address();
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213 u_char test_byte_2 = test_byte & ( 0xff ^ register_mask);
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214 if (test_byte_2 != instruction_code) fatal("not a mov reg, imm32");
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215 #endif // AMD64
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216 }
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217
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218
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219 void NativeMovConstReg::print() {
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220 tty->print_cr(PTR_FORMAT ": mov reg, " INTPTR_FORMAT,
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221 instruction_address(), data());
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222 }
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223
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224 //-------------------------------------------------------------------
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225
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226 #ifndef AMD64
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227
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228 void NativeMovRegMem::copy_instruction_to(address new_instruction_address) {
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229 int inst_size = instruction_size;
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230
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231 // See if there's an instruction size prefix override.
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232 if ( *(address(this)) == instruction_operandsize_prefix &&
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233 *(address(this)+1) != instruction_code_xmm_code ) { // Not SSE instr
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234 inst_size += 1;
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235 }
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236 if ( *(address(this)) == instruction_extended_prefix ) inst_size += 1;
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237
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238 for (int i = 0; i < instruction_size; i++) {
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239 *(new_instruction_address + i) = *(address(this) + i);
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240 }
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241 }
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242
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243 void NativeMovRegMem::verify() {
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244 // make sure code pattern is actually a mov [reg+offset], reg instruction
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245 u_char test_byte = *(u_char*)instruction_address();
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246 if ( ! ( (test_byte == instruction_code_reg2memb)
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247 || (test_byte == instruction_code_mem2regb)
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248 || (test_byte == instruction_code_mem2regl)
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249 || (test_byte == instruction_code_reg2meml)
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250 || (test_byte == instruction_code_mem2reg_movzxb )
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251 || (test_byte == instruction_code_mem2reg_movzxw )
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252 || (test_byte == instruction_code_mem2reg_movsxb )
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253 || (test_byte == instruction_code_mem2reg_movsxw )
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254 || (test_byte == instruction_code_float_s)
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255 || (test_byte == instruction_code_float_d)
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256 || (test_byte == instruction_code_long_volatile) ) )
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257 {
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258 u_char byte1 = ((u_char*)instruction_address())[1];
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259 u_char byte2 = ((u_char*)instruction_address())[2];
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260 if ((test_byte != instruction_code_xmm_ss_prefix &&
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261 test_byte != instruction_code_xmm_sd_prefix &&
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262 test_byte != instruction_operandsize_prefix) ||
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263 byte1 != instruction_code_xmm_code ||
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264 (byte2 != instruction_code_xmm_load &&
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265 byte2 != instruction_code_xmm_lpd &&
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266 byte2 != instruction_code_xmm_store)) {
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267 fatal ("not a mov [reg+offs], reg instruction");
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268 }
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269 }
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270 }
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271
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272
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273 void NativeMovRegMem::print() {
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274 tty->print_cr("0x%x: mov reg, [reg + %x]", instruction_address(), offset());
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275 }
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276
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277 //-------------------------------------------------------------------
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278
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279 void NativeLoadAddress::verify() {
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280 // make sure code pattern is actually a mov [reg+offset], reg instruction
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281 u_char test_byte = *(u_char*)instruction_address();
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282 if ( ! (test_byte == instruction_code) ) {
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283 fatal ("not a lea reg, [reg+offs] instruction");
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284 }
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285 }
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286
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287
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288 void NativeLoadAddress::print() {
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289 tty->print_cr("0x%x: lea [reg + %x], reg", instruction_address(), offset());
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290 }
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291
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292 #endif // !AMD64
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293
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294 //--------------------------------------------------------------------------------
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295
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296 void NativeJump::verify() {
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297 if (*(u_char*)instruction_address() != instruction_code) {
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298 fatal("not a jump instruction");
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299 }
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300 }
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301
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302
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303 void NativeJump::insert(address code_pos, address entry) {
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304 intptr_t disp = (intptr_t)entry - ((intptr_t)code_pos + 1 + 4);
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305 #ifdef AMD64
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306 guarantee(disp == (intptr_t)(int32_t)disp, "must be 32-bit offset");
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307 #endif // AMD64
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308
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309 *code_pos = instruction_code;
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310 *((int32_t*)(code_pos + 1)) = (int32_t)disp;
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311
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312 ICache::invalidate_range(code_pos, instruction_size);
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313 }
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314
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315 void NativeJump::check_verified_entry_alignment(address entry, address verified_entry) {
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316 // Patching to not_entrant can happen while activations of the method are
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317 // in use. The patching in that instance must happen only when certain
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318 // alignment restrictions are true. These guarantees check those
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319 // conditions.
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320 #ifdef AMD64
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321 const int linesize = 64;
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322 #else
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323 const int linesize = 32;
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324 #endif // AMD64
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325
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326 // Must be wordSize aligned
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327 guarantee(((uintptr_t) verified_entry & (wordSize -1)) == 0,
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328 "illegal address for code patching 2");
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329 // First 5 bytes must be within the same cache line - 4827828
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330 guarantee((uintptr_t) verified_entry / linesize ==
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331 ((uintptr_t) verified_entry + 4) / linesize,
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332 "illegal address for code patching 3");
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333 }
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334
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335
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336 // MT safe inserting of a jump over an unknown instruction sequence (used by nmethod::makeZombie)
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337 // The problem: jmp <dest> is a 5-byte instruction. Atomical write can be only with 4 bytes.
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338 // First patches the first word atomically to be a jump to itself.
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339 // Then patches the last byte and then atomically patches the first word (4-bytes),
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340 // thus inserting the desired jump
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341 // This code is mt-safe with the following conditions: entry point is 4 byte aligned,
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342 // entry point is in same cache line as unverified entry point, and the instruction being
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343 // patched is >= 5 byte (size of patch).
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344 //
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345 // In C2 the 5+ byte sized instruction is enforced by code in MachPrologNode::emit.
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346 // In C1 the restriction is enforced by CodeEmitter::method_entry
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347 //
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348 void NativeJump::patch_verified_entry(address entry, address verified_entry, address dest) {
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349 // complete jump instruction (to be inserted) is in code_buffer;
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350 unsigned char code_buffer[5];
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351 code_buffer[0] = instruction_code;
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352 intptr_t disp = (intptr_t)dest - ((intptr_t)verified_entry + 1 + 4);
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353 #ifdef AMD64
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354 guarantee(disp == (intptr_t)(int32_t)disp, "must be 32-bit offset");
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355 #endif // AMD64
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356 *(int32_t*)(code_buffer + 1) = (int32_t)disp;
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357
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358 check_verified_entry_alignment(entry, verified_entry);
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359
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360 // Can't call nativeJump_at() because it's asserts jump exists
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361 NativeJump* n_jump = (NativeJump*) verified_entry;
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362
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363 //First patch dummy jmp in place
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364
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365 unsigned char patch[4];
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366 assert(sizeof(patch)==sizeof(int32_t), "sanity check");
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367 patch[0] = 0xEB; // jmp rel8
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368 patch[1] = 0xFE; // jmp to self
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369 patch[2] = 0xEB;
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370 patch[3] = 0xFE;
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371
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372 // First patch dummy jmp in place
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373 *(int32_t*)verified_entry = *(int32_t *)patch;
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374
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375 n_jump->wrote(0);
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376
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377 // Patch 5th byte (from jump instruction)
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378 verified_entry[4] = code_buffer[4];
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379
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380 n_jump->wrote(4);
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381
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382 // Patch bytes 0-3 (from jump instruction)
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383 *(int32_t*)verified_entry = *(int32_t *)code_buffer;
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384 // Invalidate. Opteron requires a flush after every write.
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385 n_jump->wrote(0);
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386
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387 }
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388
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389 void NativePopReg::insert(address code_pos, Register reg) {
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390 assert(reg->encoding() < 8, "no space for REX");
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391 assert(NativePopReg::instruction_size == sizeof(char), "right address unit for update");
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392 *code_pos = (u_char)(instruction_code | reg->encoding());
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393 ICache::invalidate_range(code_pos, instruction_size);
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394 }
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395
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396
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397 void NativeIllegalInstruction::insert(address code_pos) {
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398 assert(NativeIllegalInstruction::instruction_size == sizeof(short), "right address unit for update");
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399 *(short *)code_pos = instruction_code;
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400 ICache::invalidate_range(code_pos, instruction_size);
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401 }
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402
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403 void NativeGeneralJump::verify() {
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404 assert(((NativeInstruction *)this)->is_jump() ||
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405 ((NativeInstruction *)this)->is_cond_jump(), "not a general jump instruction");
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406 }
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407
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408
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409 void NativeGeneralJump::insert_unconditional(address code_pos, address entry) {
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410 intptr_t disp = (intptr_t)entry - ((intptr_t)code_pos + 1 + 4);
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411 #ifdef AMD64
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412 guarantee(disp == (intptr_t)(int32_t)disp, "must be 32-bit offset");
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413 #endif // AMD64
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414
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415 *code_pos = unconditional_long_jump;
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416 *((int32_t *)(code_pos+1)) = (int32_t) disp;
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417 ICache::invalidate_range(code_pos, instruction_size);
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418 }
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419
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420
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421 // MT-safe patching of a long jump instruction.
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422 // First patches first word of instruction to two jmp's that jmps to them
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423 // selfs (spinlock). Then patches the last byte, and then atomicly replaces
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424 // the jmp's with the first 4 byte of the new instruction.
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425 void NativeGeneralJump::replace_mt_safe(address instr_addr, address code_buffer) {
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426 assert (instr_addr != NULL, "illegal address for code patching (4)");
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427 NativeGeneralJump* n_jump = nativeGeneralJump_at (instr_addr); // checking that it is a jump
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428
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429 // Temporary code
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430 unsigned char patch[4];
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431 assert(sizeof(patch)==sizeof(int32_t), "sanity check");
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432 patch[0] = 0xEB; // jmp rel8
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433 patch[1] = 0xFE; // jmp to self
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434 patch[2] = 0xEB;
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435 patch[3] = 0xFE;
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436
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437 // First patch dummy jmp in place
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438 *(int32_t*)instr_addr = *(int32_t *)patch;
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439 n_jump->wrote(0);
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440
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441 // Patch 4th byte
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442 instr_addr[4] = code_buffer[4];
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443
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444 n_jump->wrote(4);
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445
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446 // Patch bytes 0-3
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447 *(jint*)instr_addr = *(jint *)code_buffer;
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448
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449 n_jump->wrote(0);
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450
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451 #ifdef ASSERT
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452 // verify patching
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453 for ( int i = 0; i < instruction_size; i++) {
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454 address ptr = (address)((intptr_t)code_buffer + i);
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455 int a_byte = (*ptr) & 0xFF;
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456 assert(*((address)((intptr_t)instr_addr + i)) == a_byte, "mt safe patching failed");
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457 }
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458 #endif
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459
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460 }
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461
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462
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463
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464 address NativeGeneralJump::jump_destination() const {
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465 int op_code = ubyte_at(0);
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466 bool is_rel32off = (op_code == 0xE9 || op_code == 0x0F);
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467 int offset = (op_code == 0x0F) ? 2 : 1;
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468 int length = offset + ((is_rel32off) ? 4 : 1);
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469
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470 if (is_rel32off)
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471 return addr_at(0) + length + int_at(offset);
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472 else
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473 return addr_at(0) + length + sbyte_at(offset);
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474 }
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