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1 /*
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2 * Copyright 1997-2006 Sun Microsystems, Inc. All Rights Reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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20 * CA 95054 USA or visit www.sun.com if you need additional information or
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21 * have any questions.
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22 *
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23 */
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24
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25 // We have interfaces for the following instructions:
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26 // - NativeInstruction
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27 // - - NativeCall
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28 // - - NativeMovConstReg
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29 // - - NativeMovConstRegPatching
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30 // - - NativeMovRegMem
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31 // - - NativeMovRegMemPatching
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32 // - - NativeJump
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33 // - - NativeIllegalOpCode
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34 // - - NativeGeneralJump
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35 // - - NativeReturn
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36 // - - NativeReturnX (return with argument)
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37 // - - NativePushConst
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38 // - - NativeTstRegMem
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39
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40 // The base class for different kinds of native instruction abstractions.
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41 // Provides the primitive operations to manipulate code relative to this.
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42
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43 class NativeInstruction VALUE_OBJ_CLASS_SPEC {
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44 friend class Relocation;
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45
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46 public:
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47 enum Intel_specific_constants {
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48 nop_instruction_code = 0x90,
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49 nop_instruction_size = 1
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50 };
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51
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52 bool is_nop() { return ubyte_at(0) == nop_instruction_code; }
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53 inline bool is_call();
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54 inline bool is_illegal();
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55 inline bool is_return();
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56 inline bool is_jump();
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57 inline bool is_cond_jump();
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58 inline bool is_safepoint_poll();
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59 inline bool is_mov_literal64();
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60
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61 protected:
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62 address addr_at(int offset) const { return address(this) + offset; }
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63
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64 s_char sbyte_at(int offset) const { return *(s_char*) addr_at(offset); }
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65 u_char ubyte_at(int offset) const { return *(u_char*) addr_at(offset); }
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66
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67 jint int_at(int offset) const { return *(jint*) addr_at(offset); }
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68
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69 intptr_t ptr_at(int offset) const { return *(intptr_t*) addr_at(offset); }
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70
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71 oop oop_at (int offset) const { return *(oop*) addr_at(offset); }
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72
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73
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74 void set_char_at(int offset, char c) { *addr_at(offset) = (u_char)c; wrote(offset); }
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75 void set_int_at(int offset, jint i) { *(jint*)addr_at(offset) = i; wrote(offset); }
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76 void set_ptr_at (int offset, intptr_t ptr) { *(intptr_t*) addr_at(offset) = ptr; wrote(offset); }
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77 void set_oop_at (int offset, oop o) { *(oop*) addr_at(offset) = o; wrote(offset); }
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78
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79 // This doesn't really do anything on Intel, but it is the place where
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80 // cache invalidation belongs, generically:
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81 void wrote(int offset);
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82
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83 public:
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84
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85 // unit test stuff
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86 static void test() {} // override for testing
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87
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88 inline friend NativeInstruction* nativeInstruction_at(address address);
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89 };
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90
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91 inline NativeInstruction* nativeInstruction_at(address address) {
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92 NativeInstruction* inst = (NativeInstruction*)address;
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93 #ifdef ASSERT
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94 //inst->verify();
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95 #endif
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96 return inst;
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97 }
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98
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99 inline NativeCall* nativeCall_at(address address);
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100 // The NativeCall is an abstraction for accessing/manipulating native call imm32/rel32off
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101 // instructions (used to manipulate inline caches, primitive & dll calls, etc.).
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102
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103 class NativeCall: public NativeInstruction {
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104 public:
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105 enum Intel_specific_constants {
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106 instruction_code = 0xE8,
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107 instruction_size = 5,
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108 instruction_offset = 0,
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109 displacement_offset = 1,
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110 return_address_offset = 5
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111 };
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112
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113 enum { cache_line_size = BytesPerWord }; // conservative estimate!
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114
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115 address instruction_address() const { return addr_at(instruction_offset); }
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116 address next_instruction_address() const { return addr_at(return_address_offset); }
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117 int displacement() const { return (jint) int_at(displacement_offset); }
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118 address displacement_address() const { return addr_at(displacement_offset); }
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119 address return_address() const { return addr_at(return_address_offset); }
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120 address destination() const;
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121 void set_destination(address dest) {
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122 #ifdef AMD64
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123 assert((labs((intptr_t) dest - (intptr_t) return_address()) &
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124 0xFFFFFFFF00000000) == 0,
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125 "must be 32bit offset");
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126 #endif // AMD64
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127 set_int_at(displacement_offset, dest - return_address());
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128 }
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129 void set_destination_mt_safe(address dest);
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130
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131 void verify_alignment() { assert((intptr_t)addr_at(displacement_offset) % BytesPerInt == 0, "must be aligned"); }
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132 void verify();
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133 void print();
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134
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135 // Creation
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136 inline friend NativeCall* nativeCall_at(address address);
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137 inline friend NativeCall* nativeCall_before(address return_address);
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138
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139 static bool is_call_at(address instr) {
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140 return ((*instr) & 0xFF) == NativeCall::instruction_code;
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141 }
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142
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143 static bool is_call_before(address return_address) {
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144 return is_call_at(return_address - NativeCall::return_address_offset);
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145 }
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146
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147 static bool is_call_to(address instr, address target) {
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148 return nativeInstruction_at(instr)->is_call() &&
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149 nativeCall_at(instr)->destination() == target;
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150 }
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151
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152 // MT-safe patching of a call instruction.
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153 static void insert(address code_pos, address entry);
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154
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155 static void replace_mt_safe(address instr_addr, address code_buffer);
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156 };
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157
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158 inline NativeCall* nativeCall_at(address address) {
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159 NativeCall* call = (NativeCall*)(address - NativeCall::instruction_offset);
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160 #ifdef ASSERT
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161 call->verify();
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162 #endif
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163 return call;
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164 }
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165
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166 inline NativeCall* nativeCall_before(address return_address) {
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167 NativeCall* call = (NativeCall*)(return_address - NativeCall::return_address_offset);
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168 #ifdef ASSERT
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169 call->verify();
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170 #endif
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171 return call;
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172 }
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173
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174 // An interface for accessing/manipulating native mov reg, imm32 instructions.
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175 // (used to manipulate inlined 32bit data dll calls, etc.)
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176 class NativeMovConstReg: public NativeInstruction {
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177 #ifdef AMD64
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178 static const bool has_rex = true;
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179 static const int rex_size = 1;
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180 #else
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181 static const bool has_rex = false;
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182 static const int rex_size = 0;
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183 #endif // AMD64
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184 public:
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185 enum Intel_specific_constants {
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186 instruction_code = 0xB8,
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187 instruction_size = 1 + rex_size + wordSize,
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188 instruction_offset = 0,
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189 data_offset = 1 + rex_size,
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190 next_instruction_offset = instruction_size,
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191 register_mask = 0x07
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192 };
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193
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194 address instruction_address() const { return addr_at(instruction_offset); }
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195 address next_instruction_address() const { return addr_at(next_instruction_offset); }
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196 intptr_t data() const { return ptr_at(data_offset); }
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197 void set_data(intptr_t x) { set_ptr_at(data_offset, x); }
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198
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199 void verify();
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200 void print();
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201
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202 // unit test stuff
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203 static void test() {}
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204
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205 // Creation
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206 inline friend NativeMovConstReg* nativeMovConstReg_at(address address);
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207 inline friend NativeMovConstReg* nativeMovConstReg_before(address address);
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208 };
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209
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210 inline NativeMovConstReg* nativeMovConstReg_at(address address) {
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211 NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_offset);
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212 #ifdef ASSERT
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213 test->verify();
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214 #endif
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215 return test;
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216 }
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217
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218 inline NativeMovConstReg* nativeMovConstReg_before(address address) {
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219 NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_size - NativeMovConstReg::instruction_offset);
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220 #ifdef ASSERT
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221 test->verify();
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222 #endif
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223 return test;
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224 }
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225
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226 class NativeMovConstRegPatching: public NativeMovConstReg {
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227 private:
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228 friend NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) {
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229 NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_offset);
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230 #ifdef ASSERT
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231 test->verify();
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232 #endif
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233 return test;
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234 }
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235 };
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236
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237 #ifndef AMD64
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238
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239 // An interface for accessing/manipulating native moves of the form:
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240 // mov[b/w/l] [reg + offset], reg (instruction_code_reg2mem)
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241 // mov[b/w/l] reg, [reg+offset] (instruction_code_mem2reg
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242 // mov[s/z]x[w/b] [reg + offset], reg
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243 // fld_s [reg+offset]
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244 // fld_d [reg+offset]
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245 // fstp_s [reg + offset]
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246 // fstp_d [reg + offset]
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247 //
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248 // Warning: These routines must be able to handle any instruction sequences
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249 // that are generated as a result of the load/store byte,word,long
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250 // macros. For example: The load_unsigned_byte instruction generates
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251 // an xor reg,reg inst prior to generating the movb instruction. This
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252 // class must skip the xor instruction.
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253
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254 class NativeMovRegMem: public NativeInstruction {
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255 public:
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256 enum Intel_specific_constants {
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257 instruction_code_xor = 0x33,
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258 instruction_extended_prefix = 0x0F,
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259 instruction_code_mem2reg_movzxb = 0xB6,
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260 instruction_code_mem2reg_movsxb = 0xBE,
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261 instruction_code_mem2reg_movzxw = 0xB7,
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262 instruction_code_mem2reg_movsxw = 0xBF,
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263 instruction_operandsize_prefix = 0x66,
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264 instruction_code_reg2meml = 0x89,
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265 instruction_code_mem2regl = 0x8b,
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266 instruction_code_reg2memb = 0x88,
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267 instruction_code_mem2regb = 0x8a,
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268 instruction_code_float_s = 0xd9,
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269 instruction_code_float_d = 0xdd,
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270 instruction_code_long_volatile = 0xdf,
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271 instruction_code_xmm_ss_prefix = 0xf3,
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272 instruction_code_xmm_sd_prefix = 0xf2,
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273 instruction_code_xmm_code = 0x0f,
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274 instruction_code_xmm_load = 0x10,
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275 instruction_code_xmm_store = 0x11,
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276 instruction_code_xmm_lpd = 0x12,
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277
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278 instruction_size = 4,
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279 instruction_offset = 0,
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280 data_offset = 2,
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281 next_instruction_offset = 4
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282 };
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283
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284 address instruction_address() const {
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285 if (*addr_at(instruction_offset) == instruction_operandsize_prefix &&
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286 *addr_at(instruction_offset+1) != instruction_code_xmm_code) {
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287 return addr_at(instruction_offset+1); // Not SSE instructions
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288 }
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289 else if (*addr_at(instruction_offset) == instruction_extended_prefix) {
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290 return addr_at(instruction_offset+1);
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291 }
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292 else if (*addr_at(instruction_offset) == instruction_code_xor) {
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293 return addr_at(instruction_offset+2);
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294 }
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295 else return addr_at(instruction_offset);
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296 }
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297
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298 address next_instruction_address() const {
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299 switch (*addr_at(instruction_offset)) {
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300 case instruction_operandsize_prefix:
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301 if (*addr_at(instruction_offset+1) == instruction_code_xmm_code)
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302 return instruction_address() + instruction_size; // SSE instructions
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303 case instruction_extended_prefix:
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304 return instruction_address() + instruction_size + 1;
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305 case instruction_code_reg2meml:
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306 case instruction_code_mem2regl:
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307 case instruction_code_reg2memb:
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308 case instruction_code_mem2regb:
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309 case instruction_code_xor:
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310 return instruction_address() + instruction_size + 2;
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311 default:
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312 return instruction_address() + instruction_size;
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313 }
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314 }
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315 int offset() const{
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316 if (*addr_at(instruction_offset) == instruction_operandsize_prefix &&
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317 *addr_at(instruction_offset+1) != instruction_code_xmm_code) {
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318 return int_at(data_offset+1); // Not SSE instructions
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319 }
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320 else if (*addr_at(instruction_offset) == instruction_extended_prefix) {
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321 return int_at(data_offset+1);
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322 }
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323 else if (*addr_at(instruction_offset) == instruction_code_xor ||
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324 *addr_at(instruction_offset) == instruction_code_xmm_ss_prefix ||
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325 *addr_at(instruction_offset) == instruction_code_xmm_sd_prefix ||
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326 *addr_at(instruction_offset) == instruction_operandsize_prefix) {
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327 return int_at(data_offset+2);
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328 }
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329 else return int_at(data_offset);
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330 }
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331
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332 void set_offset(int x) {
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333 if (*addr_at(instruction_offset) == instruction_operandsize_prefix &&
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334 *addr_at(instruction_offset+1) != instruction_code_xmm_code) {
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335 set_int_at(data_offset+1, x); // Not SSE instructions
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336 }
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337 else if (*addr_at(instruction_offset) == instruction_extended_prefix) {
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338 set_int_at(data_offset+1, x);
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339 }
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340 else if (*addr_at(instruction_offset) == instruction_code_xor ||
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341 *addr_at(instruction_offset) == instruction_code_xmm_ss_prefix ||
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342 *addr_at(instruction_offset) == instruction_code_xmm_sd_prefix ||
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343 *addr_at(instruction_offset) == instruction_operandsize_prefix) {
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344 set_int_at(data_offset+2, x);
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345 }
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346 else set_int_at(data_offset, x);
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347 }
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348
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349 void add_offset_in_bytes(int add_offset) { set_offset ( ( offset() + add_offset ) ); }
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350 void copy_instruction_to(address new_instruction_address);
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351
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352 void verify();
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353 void print ();
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354
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355 // unit test stuff
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356 static void test() {}
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357
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358 private:
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359 inline friend NativeMovRegMem* nativeMovRegMem_at (address address);
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360 };
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361
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362 inline NativeMovRegMem* nativeMovRegMem_at (address address) {
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363 NativeMovRegMem* test = (NativeMovRegMem*)(address - NativeMovRegMem::instruction_offset);
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364 #ifdef ASSERT
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365 test->verify();
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366 #endif
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367 return test;
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368 }
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369
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370 class NativeMovRegMemPatching: public NativeMovRegMem {
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371 private:
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372 friend NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address) {
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373 NativeMovRegMemPatching* test = (NativeMovRegMemPatching*)(address - instruction_offset);
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374 #ifdef ASSERT
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375 test->verify();
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376 #endif
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377 return test;
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378 }
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379 };
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380
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381
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382
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383 // An interface for accessing/manipulating native leal instruction of form:
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384 // leal reg, [reg + offset]
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385
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386 class NativeLoadAddress: public NativeMovRegMem {
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387 public:
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388 enum Intel_specific_constants {
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389 instruction_code = 0x8D
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390 };
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391
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392 void verify();
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393 void print ();
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394
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395 // unit test stuff
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396 static void test() {}
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397
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398 private:
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399 friend NativeLoadAddress* nativeLoadAddress_at (address address) {
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400 NativeLoadAddress* test = (NativeLoadAddress*)(address - instruction_offset);
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401 #ifdef ASSERT
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402 test->verify();
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403 #endif
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404 return test;
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405 }
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406 };
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407
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408 #endif // AMD64
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409
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410 // jump rel32off
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411
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412 class NativeJump: public NativeInstruction {
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413 public:
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414 enum Intel_specific_constants {
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415 instruction_code = 0xe9,
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416 instruction_size = 5,
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417 instruction_offset = 0,
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418 data_offset = 1,
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419 next_instruction_offset = 5
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420 };
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421
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422 address instruction_address() const { return addr_at(instruction_offset); }
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423 address next_instruction_address() const { return addr_at(next_instruction_offset); }
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424 address jump_destination() const {
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425 address dest = (int_at(data_offset)+next_instruction_address());
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426 #ifdef AMD64 // What is this about?
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427 // return -1 if jump to self
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428 dest = (dest == (address) this) ? (address) -1 : dest;
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429 #endif // AMD64
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430 return dest;
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431 }
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432
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433 void set_jump_destination(address dest) {
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434 intptr_t val = dest - next_instruction_address();
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435 #ifdef AMD64
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436 if (dest == (address) -1) { // can't encode jump to -1
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437 val = -5; // jump to self
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438 } else {
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439 assert((labs(val) & 0xFFFFFFFF00000000) == 0,
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440 "must be 32bit offset");
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441 }
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442 #endif // AMD64
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443 set_int_at(data_offset, (jint)val);
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444 }
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445
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446 // Creation
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447 inline friend NativeJump* nativeJump_at(address address);
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448
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449 void verify();
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450
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451 // Unit testing stuff
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452 static void test() {}
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453
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454 // Insertion of native jump instruction
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455 static void insert(address code_pos, address entry);
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456 // MT-safe insertion of native jump at verified method entry
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457 static void check_verified_entry_alignment(address entry, address verified_entry);
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458 static void patch_verified_entry(address entry, address verified_entry, address dest);
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459 };
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460
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461 inline NativeJump* nativeJump_at(address address) {
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462 NativeJump* jump = (NativeJump*)(address - NativeJump::instruction_offset);
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463 #ifdef ASSERT
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464 jump->verify();
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465 #endif
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466 return jump;
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467 }
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468
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469 // Handles all kinds of jump on Intel. Long/far, conditional/unconditional
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470 class NativeGeneralJump: public NativeInstruction {
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471 public:
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472 enum Intel_specific_constants {
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473 // Constants does not apply, since the lengths and offsets depends on the actual jump
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474 // used
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475 // Instruction codes:
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476 // Unconditional jumps: 0xE9 (rel32off), 0xEB (rel8off)
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477 // Conditional jumps: 0x0F8x (rel32off), 0x7x (rel8off)
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478 unconditional_long_jump = 0xe9,
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479 unconditional_short_jump = 0xeb,
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480 instruction_size = 5
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481 };
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482
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483 address instruction_address() const { return addr_at(0); }
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484 address jump_destination() const;
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485
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486 // Creation
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487 inline friend NativeGeneralJump* nativeGeneralJump_at(address address);
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488
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489 // Insertion of native general jump instruction
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490 static void insert_unconditional(address code_pos, address entry);
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491 static void replace_mt_safe(address instr_addr, address code_buffer);
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492
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493 void verify();
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494 };
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495
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496 inline NativeGeneralJump* nativeGeneralJump_at(address address) {
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497 NativeGeneralJump* jump = (NativeGeneralJump*)(address);
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498 debug_only(jump->verify();)
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499 return jump;
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500 }
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501
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502 class NativePopReg : public NativeInstruction {
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503 public:
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504 enum Intel_specific_constants {
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505 instruction_code = 0x58,
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506 instruction_size = 1,
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507 instruction_offset = 0,
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508 data_offset = 1,
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509 next_instruction_offset = 1
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510 };
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511
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512 // Insert a pop instruction
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513 static void insert(address code_pos, Register reg);
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514 };
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515
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516
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517 class NativeIllegalInstruction: public NativeInstruction {
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518 public:
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519 enum Intel_specific_constants {
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520 instruction_code = 0x0B0F, // Real byte order is: 0x0F, 0x0B
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521 instruction_size = 2,
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522 instruction_offset = 0,
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523 next_instruction_offset = 2
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524 };
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525
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526 // Insert illegal opcode as specific address
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527 static void insert(address code_pos);
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528 };
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529
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530 // return instruction that does not pop values of the stack
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531 class NativeReturn: public NativeInstruction {
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532 public:
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533 enum Intel_specific_constants {
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534 instruction_code = 0xC3,
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535 instruction_size = 1,
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536 instruction_offset = 0,
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537 next_instruction_offset = 1
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538 };
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539 };
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540
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541 // return instruction that does pop values of the stack
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542 class NativeReturnX: public NativeInstruction {
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543 public:
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544 enum Intel_specific_constants {
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|
545 instruction_code = 0xC2,
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|
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546 instruction_size = 2,
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|
|
547 instruction_offset = 0,
|
|
|
548 next_instruction_offset = 2
|
|
|
549 };
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550 };
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|
551
|
|
|
552 // Simple test vs memory
|
|
|
553 class NativeTstRegMem: public NativeInstruction {
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|
|
554 public:
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|
|
555 enum Intel_specific_constants {
|
|
|
556 instruction_code_memXregl = 0x85
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|
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557 };
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558 };
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559
|
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560 inline bool NativeInstruction::is_illegal() { return (short)int_at(0) == (short)NativeIllegalInstruction::instruction_code; }
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561 inline bool NativeInstruction::is_call() { return ubyte_at(0) == NativeCall::instruction_code; }
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562 inline bool NativeInstruction::is_return() { return ubyte_at(0) == NativeReturn::instruction_code ||
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|
563 ubyte_at(0) == NativeReturnX::instruction_code; }
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|
|
564 inline bool NativeInstruction::is_jump() { return ubyte_at(0) == NativeJump::instruction_code ||
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|
|
565 ubyte_at(0) == 0xEB; /* short jump */ }
|
|
|
566 inline bool NativeInstruction::is_cond_jump() { return (int_at(0) & 0xF0FF) == 0x800F /* long jump */ ||
|
|
|
567 (ubyte_at(0) & 0xF0) == 0x70; /* short jump */ }
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|
|
568 inline bool NativeInstruction::is_safepoint_poll() {
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|
|
569 #ifdef AMD64
|
|
|
570 return ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl &&
|
|
|
571 ubyte_at(1) == 0x05 && // 00 rax 101
|
|
|
572 ((intptr_t) addr_at(6)) + int_at(2) == (intptr_t) os::get_polling_page();
|
|
|
573 #else
|
|
|
574 return ( ubyte_at(0) == NativeMovRegMem::instruction_code_mem2regl ||
|
|
|
575 ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl ) &&
|
|
|
576 (ubyte_at(1)&0xC7) == 0x05 && /* Mod R/M == disp32 */
|
|
|
577 (os::is_poll_address((address)int_at(2)));
|
|
|
578 #endif // AMD64
|
|
|
579 }
|
|
|
580
|
|
|
581 inline bool NativeInstruction::is_mov_literal64() {
|
|
|
582 #ifdef AMD64
|
|
|
583 return ((ubyte_at(0) == Assembler::REX_W || ubyte_at(0) == Assembler::REX_WB) &&
|
|
|
584 (ubyte_at(1) & (0xff ^ NativeMovConstReg::register_mask)) == 0xB8);
|
|
|
585 #else
|
|
|
586 return false;
|
|
|
587 #endif // AMD64
|
|
|
588 }
|
