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1 /*
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2 * Copyright 1997-2006 Sun Microsystems, Inc. All Rights Reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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20 * CA 95054 USA or visit www.sun.com if you need additional information or
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21 * have any questions.
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22 *
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23 */
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24
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25 class VM_Version: public Abstract_VM_Version {
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26 public:
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27 // cpuid result register layouts. These are all unions of a uint32_t
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28 // (in case anyone wants access to the register as a whole) and a bitfield.
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29
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30 union StdCpuid1Eax {
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31 uint32_t value;
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32 struct {
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33 uint32_t stepping : 4,
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34 model : 4,
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35 family : 4,
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36 proc_type : 2,
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37 : 2,
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38 ext_model : 4,
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39 ext_family : 8,
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40 : 4;
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41 } bits;
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42 };
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43
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44 union StdCpuid1Ebx { // example, unused
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45 uint32_t value;
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46 struct {
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47 uint32_t brand_id : 8,
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48 clflush_size : 8,
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49 threads_per_cpu : 8,
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50 apic_id : 8;
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51 } bits;
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52 };
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53
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54 union StdCpuid1Ecx {
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55 uint32_t value;
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56 struct {
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57 uint32_t sse3 : 1,
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58 : 2,
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59 monitor : 1,
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60 : 1,
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61 vmx : 1,
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62 : 1,
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63 est : 1,
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64 : 1,
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65 ssse3 : 1,
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66 cid : 1,
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67 : 2,
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68 cmpxchg16: 1,
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69 : 4,
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70 dca : 1,
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71 : 4,
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72 popcnt : 1,
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73 : 8;
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74 } bits;
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75 };
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76
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77 union StdCpuid1Edx {
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78 uint32_t value;
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79 struct {
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80 uint32_t : 4,
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81 tsc : 1,
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82 : 3,
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83 cmpxchg8 : 1,
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84 : 6,
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85 cmov : 1,
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86 : 7,
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87 mmx : 1,
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88 fxsr : 1,
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89 sse : 1,
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90 sse2 : 1,
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91 : 1,
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92 ht : 1,
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93 : 3;
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94 } bits;
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95 };
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96
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97 union DcpCpuid4Eax {
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98 uint32_t value;
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99 struct {
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100 uint32_t cache_type : 5,
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101 : 21,
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102 cores_per_cpu : 6;
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103 } bits;
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104 };
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105
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106 union DcpCpuid4Ebx {
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107 uint32_t value;
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108 struct {
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109 uint32_t L1_line_size : 12,
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110 partitions : 10,
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111 associativity : 10;
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112 } bits;
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113 };
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114
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115 union ExtCpuid1Ecx {
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116 uint32_t value;
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117 struct {
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118 uint32_t LahfSahf : 1,
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119 CmpLegacy : 1,
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120 : 4,
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121 abm : 1,
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122 sse4a : 1,
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123 misalignsse : 1,
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124 prefetchw : 1,
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125 : 22;
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126 } bits;
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127 };
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128
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129 union ExtCpuid1Edx {
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130 uint32_t value;
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131 struct {
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132 uint32_t : 22,
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133 mmx_amd : 1,
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134 mmx : 1,
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135 fxsr : 1,
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136 : 4,
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137 long_mode : 1,
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138 tdnow2 : 1,
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139 tdnow : 1;
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140 } bits;
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141 };
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142
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143 union ExtCpuid5Ex {
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144 uint32_t value;
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145 struct {
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146 uint32_t L1_line_size : 8,
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147 L1_tag_lines : 8,
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148 L1_assoc : 8,
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149 L1_size : 8;
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150 } bits;
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151 };
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152
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153 union ExtCpuid8Ecx {
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154 uint32_t value;
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155 struct {
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156 uint32_t cores_per_cpu : 8,
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157 : 24;
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158 } bits;
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159 };
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160
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161 protected:
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162 static int _cpu;
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163 static int _model;
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164 static int _stepping;
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165 static int _cpuFeatures; // features returned by the "cpuid" instruction
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166 // 0 if this instruction is not available
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167 static const char* _features_str;
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168
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169 enum {
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170 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX)
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171 CPU_CMOV = (1 << 1),
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172 CPU_FXSR = (1 << 2),
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173 CPU_HT = (1 << 3),
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174 CPU_MMX = (1 << 4),
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175 CPU_3DNOW= (1 << 5), // 3DNow comes from cpuid 0x80000001 (EDX)
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176 CPU_SSE = (1 << 6),
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177 CPU_SSE2 = (1 << 7),
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178 CPU_SSE3 = (1 << 8), // sse3 comes from cpuid 1 (ECX)
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179 CPU_SSSE3= (1 << 9),
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180 CPU_SSE4 = (1 <<10),
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181 CPU_SSE4A= (1 <<11)
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182 } cpuFeatureFlags;
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183
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184 // cpuid information block. All info derived from executing cpuid with
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185 // various function numbers is stored here. Intel and AMD info is
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186 // merged in this block: accessor methods disentangle it.
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187 //
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188 // The info block is laid out in subblocks of 4 dwords corresponding to
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189 // rax, rbx, rcx and rdx, whether or not they contain anything useful.
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190 struct CpuidInfo {
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191 // cpuid function 0
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192 uint32_t std_max_function;
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193 uint32_t std_vendor_name_0;
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194 uint32_t std_vendor_name_1;
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195 uint32_t std_vendor_name_2;
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196
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197 // cpuid function 1
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198 StdCpuid1Eax std_cpuid1_rax;
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199 StdCpuid1Ebx std_cpuid1_rbx;
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200 StdCpuid1Ecx std_cpuid1_rcx;
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201 StdCpuid1Edx std_cpuid1_rdx;
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202
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203 // cpuid function 4 (deterministic cache parameters)
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204 DcpCpuid4Eax dcp_cpuid4_rax;
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205 DcpCpuid4Ebx dcp_cpuid4_rbx;
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206 uint32_t dcp_cpuid4_rcx; // unused currently
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207 uint32_t dcp_cpuid4_rdx; // unused currently
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208
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209 // cpuid function 0x80000000 // example, unused
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210 uint32_t ext_max_function;
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211 uint32_t ext_vendor_name_0;
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212 uint32_t ext_vendor_name_1;
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213 uint32_t ext_vendor_name_2;
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214
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215 // cpuid function 0x80000001
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216 uint32_t ext_cpuid1_rax; // reserved
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217 uint32_t ext_cpuid1_rbx; // reserved
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218 ExtCpuid1Ecx ext_cpuid1_rcx;
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219 ExtCpuid1Edx ext_cpuid1_rdx;
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220
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221 // cpuid functions 0x80000002 thru 0x80000004: example, unused
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222 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
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223 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
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224 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
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225
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226 // cpuid function 0x80000005 //AMD L1, Intel reserved
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227 uint32_t ext_cpuid5_rax; // unused currently
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228 uint32_t ext_cpuid5_rbx; // reserved
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229 ExtCpuid5Ex ext_cpuid5_rcx; // L1 data cache info (AMD)
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230 ExtCpuid5Ex ext_cpuid5_rdx; // L1 instruction cache info (AMD)
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231
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232 // cpuid function 0x80000008
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233 uint32_t ext_cpuid8_rax; // unused currently
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234 uint32_t ext_cpuid8_rbx; // reserved
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235 ExtCpuid8Ecx ext_cpuid8_rcx;
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236 uint32_t ext_cpuid8_rdx; // reserved
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237 };
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238
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239 // The actual cpuid info block
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240 static CpuidInfo _cpuid_info;
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241
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242 // Extractors and predicates
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243 static bool is_extended_cpu_family() {
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244 const uint32_t Extended_Cpu_Family = 0xf;
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245 return _cpuid_info.std_cpuid1_rax.bits.family == Extended_Cpu_Family;
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246 }
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247 static uint32_t extended_cpu_family() {
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248 uint32_t result = _cpuid_info.std_cpuid1_rax.bits.family;
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249 if (is_extended_cpu_family()) {
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250 result += _cpuid_info.std_cpuid1_rax.bits.ext_family;
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251 }
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252 return result;
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253 }
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254 static uint32_t extended_cpu_model() {
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255 uint32_t result = _cpuid_info.std_cpuid1_rax.bits.model;
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256 if (is_extended_cpu_family()) {
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257 result |= _cpuid_info.std_cpuid1_rax.bits.ext_model << 4;
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258 }
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259 return result;
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260 }
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261 static uint32_t cpu_stepping() {
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262 uint32_t result = _cpuid_info.std_cpuid1_rax.bits.stepping;
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263 return result;
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264 }
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265 static uint logical_processor_count() {
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266 uint result = threads_per_core();
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267 return result;
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268 }
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269 static uint32_t feature_flags() {
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270 uint32_t result = 0;
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271 if (_cpuid_info.std_cpuid1_rdx.bits.cmpxchg8 != 0)
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272 result |= CPU_CX8;
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273 if (_cpuid_info.std_cpuid1_rdx.bits.cmov != 0)
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274 result |= CPU_CMOV;
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275 if (_cpuid_info.std_cpuid1_rdx.bits.fxsr != 0 || is_amd() &&
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276 _cpuid_info.ext_cpuid1_rdx.bits.fxsr != 0)
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277 result |= CPU_FXSR;
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278 // HT flag is set for multi-core processors also.
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279 if (threads_per_core() > 1)
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280 result |= CPU_HT;
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281 if (_cpuid_info.std_cpuid1_rdx.bits.mmx != 0 || is_amd() &&
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282 _cpuid_info.ext_cpuid1_rdx.bits.mmx != 0)
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283 result |= CPU_MMX;
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284 if (is_amd() && _cpuid_info.ext_cpuid1_rdx.bits.tdnow != 0)
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285 result |= CPU_3DNOW;
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286 if (_cpuid_info.std_cpuid1_rdx.bits.sse != 0)
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287 result |= CPU_SSE;
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288 if (_cpuid_info.std_cpuid1_rdx.bits.sse2 != 0)
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289 result |= CPU_SSE2;
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290 if (_cpuid_info.std_cpuid1_rcx.bits.sse3 != 0)
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291 result |= CPU_SSE3;
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292 if (_cpuid_info.std_cpuid1_rcx.bits.ssse3 != 0)
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293 result |= CPU_SSSE3;
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294 if (is_amd() && _cpuid_info.ext_cpuid1_rcx.bits.sse4a != 0)
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295 result |= CPU_SSE4A;
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296 return result;
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297 }
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298
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299 static void get_processor_features();
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300
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301 public:
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302 // Offsets for cpuid asm stub
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303 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
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304 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_rax); }
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305 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_rax); }
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306 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_rax); }
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307 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_rax); }
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308 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_rax); }
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309
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310 // Initialization
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311 static void initialize();
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312
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313 // Asserts
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314 static void assert_is_initialized() {
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315 assert(_cpuid_info.std_cpuid1_rax.bits.family != 0, "VM_Version not initialized");
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316 }
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317
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318 //
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319 // Processor family:
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320 // 3 - 386
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321 // 4 - 486
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322 // 5 - Pentium
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323 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
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324 // Pentium M, Core Solo, Core Duo, Core2 Duo
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325 // family 6 model: 9, 13, 14, 15
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326 // 0x0f - Pentium 4, Opteron
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327 //
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328 // Note: The cpu family should be used to select between
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329 // instruction sequences which are valid on all Intel
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330 // processors. Use the feature test functions below to
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331 // determine whether a particular instruction is supported.
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332 //
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333 static int cpu_family() { return _cpu;}
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334 static bool is_P6() { return cpu_family() >= 6; }
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335
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336 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
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337 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
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338
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339 static uint cores_per_cpu() {
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340 uint result = 1;
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341 if (is_intel()) {
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342 result = (_cpuid_info.dcp_cpuid4_rax.bits.cores_per_cpu + 1);
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343 } else if (is_amd()) {
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344 result = (_cpuid_info.ext_cpuid8_rcx.bits.cores_per_cpu + 1);
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345 }
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346 return result;
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347 }
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348
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349 static uint threads_per_core() {
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350 uint result = 1;
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351 if (_cpuid_info.std_cpuid1_rdx.bits.ht != 0) {
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352 result = _cpuid_info.std_cpuid1_rbx.bits.threads_per_cpu /
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353 cores_per_cpu();
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354 }
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355 return result;
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356 }
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357
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358 static intx L1_data_cache_line_size() {
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359 intx result = 0;
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360 if (is_intel()) {
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361 result = (_cpuid_info.dcp_cpuid4_rbx.bits.L1_line_size + 1);
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362 } else if (is_amd()) {
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363 result = _cpuid_info.ext_cpuid5_rcx.bits.L1_line_size;
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364 }
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365 if (result < 32) // not defined ?
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366 result = 32; // 32 bytes by default on x86
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367 return result;
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368 }
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369
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370 //
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371 // Feature identification
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372 //
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373 static bool supports_cpuid() { return _cpuFeatures != 0; }
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374 static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; }
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375 static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; }
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376 static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; }
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377 static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; }
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378 static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; }
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379 static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; }
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380 static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; }
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381 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; }
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382 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; }
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383 static bool supports_sse4() { return (_cpuFeatures & CPU_SSE4) != 0; }
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384 //
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385 // AMD features
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386 //
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387 static bool supports_3dnow() { return (_cpuFeatures & CPU_3DNOW) != 0; }
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388 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_rdx.bits.mmx_amd != 0; }
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389 static bool supports_3dnow2() { return is_amd() && _cpuid_info.ext_cpuid1_rdx.bits.tdnow2 != 0; }
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390 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; }
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391
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392 static bool supports_compare_and_exchange() { return true; }
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393
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394 static const char* cpu_features() { return _features_str; }
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395
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396 static intx allocate_prefetch_distance() {
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397 // This method should be called before allocate_prefetch_style().
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398 //
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399 // Hardware prefetching (distance/size in bytes):
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400 // Pentium 3 - 64 / 32
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401 // Pentium 4 - 256 / 128
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402 // Athlon - 64 / 32 ????
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403 // Opteron - 128 / 64 only when 2 sequential cache lines accessed
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404 // Core - 128 / 64
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405 //
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406 // Software prefetching (distance in bytes / instruction with best score):
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407 // Pentium 3 - 128 / prefetchnta
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408 // Pentium 4 - 512 / prefetchnta
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409 // Athlon - 128 / prefetchnta
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410 // Opteron - 256 / prefetchnta
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411 // Core - 256 / prefetchnta
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412 // It will be used only when AllocatePrefetchStyle > 0
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413
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414 intx count = AllocatePrefetchDistance;
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415 if (count < 0) { // default ?
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416 if (is_amd()) { // AMD
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417 if (supports_sse2())
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418 count = 256; // Opteron
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419 else
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420 count = 128; // Athlon
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421 } else { // Intel
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422 if (supports_sse2())
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423 if (cpu_family() == 6) {
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424 count = 256; // Pentium M, Core, Core2
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425 } else {
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426 count = 512; // Pentium 4
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427 }
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428 else
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429 count = 128; // Pentium 3 (and all other old CPUs)
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430 }
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431 }
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432 return count;
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433 }
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434 static intx allocate_prefetch_style() {
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435 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
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436 // Return 0 if AllocatePrefetchDistance was not defined or
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437 // prefetch instruction is not supported.
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438 return (AllocatePrefetchDistance > 0 &&
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439 (supports_3dnow() || supports_sse())) ? AllocatePrefetchStyle : 0;
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440 }
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441 };
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