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585
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1 /*
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2 * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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20 * CA 95054 USA or visit www.sun.com if you need additional information or
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21 * have any questions.
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22 *
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23 */
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24
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25 # include "incls/_precompiled.incl"
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26 # include "incls/_vm_version_x86.cpp.incl"
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27
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28
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29 int VM_Version::_cpu;
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30 int VM_Version::_model;
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31 int VM_Version::_stepping;
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32 int VM_Version::_cpuFeatures;
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33 const char* VM_Version::_features_str = "";
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34 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
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35
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36 static BufferBlob* stub_blob;
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37 static const int stub_size = 300;
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38
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39 extern "C" {
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40 typedef void (*getPsrInfo_stub_t)(void*);
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41 }
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42 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
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43
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44
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45 class VM_Version_StubGenerator: public StubCodeGenerator {
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46 public:
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47
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48 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
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49
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50 address generate_getPsrInfo() {
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51 // Flags to test CPU type.
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52 const uint32_t EFL_AC = 0x40000;
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53 const uint32_t EFL_ID = 0x200000;
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54 // Values for when we don't have a CPUID instruction.
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55 const int CPU_FAMILY_SHIFT = 8;
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56 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
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57 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
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58
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59 Label detect_486, cpu486, detect_586, std_cpuid1;
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60 Label ext_cpuid1, ext_cpuid5, done;
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61
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62 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
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63 # define __ _masm->
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64
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65 address start = __ pc();
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66
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67 //
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68 // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info);
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69 //
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70 // LP64: rcx and rdx are first and second argument registers on windows
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71
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72 __ push(rbp);
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73 #ifdef _LP64
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74 __ mov(rbp, c_rarg0); // cpuid_info address
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75 #else
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76 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
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77 #endif
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78 __ push(rbx);
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79 __ push(rsi);
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80 __ pushf(); // preserve rbx, and flags
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81 __ pop(rax);
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82 __ push(rax);
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83 __ mov(rcx, rax);
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84 //
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85 // if we are unable to change the AC flag, we have a 386
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86 //
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87 __ xorl(rax, EFL_AC);
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88 __ push(rax);
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89 __ popf();
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90 __ pushf();
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91 __ pop(rax);
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92 __ cmpptr(rax, rcx);
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93 __ jccb(Assembler::notEqual, detect_486);
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94
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95 __ movl(rax, CPU_FAMILY_386);
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96 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
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97 __ jmp(done);
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98
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99 //
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100 // If we are unable to change the ID flag, we have a 486 which does
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101 // not support the "cpuid" instruction.
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102 //
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103 __ bind(detect_486);
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104 __ mov(rax, rcx);
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105 __ xorl(rax, EFL_ID);
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106 __ push(rax);
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107 __ popf();
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108 __ pushf();
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109 __ pop(rax);
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110 __ cmpptr(rcx, rax);
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111 __ jccb(Assembler::notEqual, detect_586);
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112
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113 __ bind(cpu486);
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114 __ movl(rax, CPU_FAMILY_486);
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115 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
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116 __ jmp(done);
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117
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118 //
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119 // At this point, we have a chip which supports the "cpuid" instruction
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120 //
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121 __ bind(detect_586);
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122 __ xorl(rax, rax);
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123 __ cpuid();
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124 __ orl(rax, rax);
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125 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input
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126 // value of at least 1, we give up and
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127 // assume a 486
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128 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
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129 __ movl(Address(rsi, 0), rax);
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130 __ movl(Address(rsi, 4), rbx);
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131 __ movl(Address(rsi, 8), rcx);
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132 __ movl(Address(rsi,12), rdx);
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133
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134 __ cmpl(rax, 3); // Is cpuid(0x4) supported?
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135 __ jccb(Assembler::belowEqual, std_cpuid1);
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136
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137 //
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138 // cpuid(0x4) Deterministic cache params
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139 //
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140 __ movl(rax, 4);
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141 __ xorl(rcx, rcx); // L1 cache
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142 __ cpuid();
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143 __ push(rax);
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144 __ andl(rax, 0x1f); // Determine if valid cache parameters used
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145 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache
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146 __ pop(rax);
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147 __ jccb(Assembler::equal, std_cpuid1);
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148
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149 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
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150 __ movl(Address(rsi, 0), rax);
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151 __ movl(Address(rsi, 4), rbx);
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152 __ movl(Address(rsi, 8), rcx);
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153 __ movl(Address(rsi,12), rdx);
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154
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155 //
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156 // Standard cpuid(0x1)
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157 //
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158 __ bind(std_cpuid1);
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159 __ movl(rax, 1);
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160 __ cpuid();
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161 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
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162 __ movl(Address(rsi, 0), rax);
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163 __ movl(Address(rsi, 4), rbx);
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164 __ movl(Address(rsi, 8), rcx);
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165 __ movl(Address(rsi,12), rdx);
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166
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167 __ movl(rax, 0x80000000);
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168 __ cpuid();
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169 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported?
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170 __ jcc(Assembler::belowEqual, done);
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171 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported?
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172 __ jccb(Assembler::belowEqual, ext_cpuid1);
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173 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported?
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174 __ jccb(Assembler::belowEqual, ext_cpuid5);
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175 //
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176 // Extended cpuid(0x80000008)
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177 //
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178 __ movl(rax, 0x80000008);
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179 __ cpuid();
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180 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
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181 __ movl(Address(rsi, 0), rax);
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182 __ movl(Address(rsi, 4), rbx);
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183 __ movl(Address(rsi, 8), rcx);
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184 __ movl(Address(rsi,12), rdx);
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185
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186 //
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187 // Extended cpuid(0x80000005)
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188 //
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189 __ bind(ext_cpuid5);
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190 __ movl(rax, 0x80000005);
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191 __ cpuid();
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192 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
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193 __ movl(Address(rsi, 0), rax);
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194 __ movl(Address(rsi, 4), rbx);
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195 __ movl(Address(rsi, 8), rcx);
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196 __ movl(Address(rsi,12), rdx);
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197
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198 //
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199 // Extended cpuid(0x80000001)
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200 //
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201 __ bind(ext_cpuid1);
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202 __ movl(rax, 0x80000001);
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203 __ cpuid();
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204 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
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205 __ movl(Address(rsi, 0), rax);
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206 __ movl(Address(rsi, 4), rbx);
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207 __ movl(Address(rsi, 8), rcx);
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208 __ movl(Address(rsi,12), rdx);
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209
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210 //
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211 // return
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212 //
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213 __ bind(done);
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214 __ popf();
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215 __ pop(rsi);
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216 __ pop(rbx);
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217 __ pop(rbp);
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218 __ ret(0);
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219
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220 # undef __
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221
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222 return start;
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223 };
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224 };
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225
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226
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227 void VM_Version::get_processor_features() {
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228
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229 _cpu = 4; // 486 by default
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230 _model = 0;
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231 _stepping = 0;
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232 _cpuFeatures = 0;
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233 _logical_processors_per_package = 1;
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234
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235 if (!Use486InstrsOnly) {
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236 // Get raw processor info
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237 getPsrInfo_stub(&_cpuid_info);
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238 assert_is_initialized();
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239 _cpu = extended_cpu_family();
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240 _model = extended_cpu_model();
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241 _stepping = cpu_stepping();
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242
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243 if (cpu_family() > 4) { // it supports CPUID
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244 _cpuFeatures = feature_flags();
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245 // Logical processors are only available on P4s and above,
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246 // and only if hyperthreading is available.
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247 _logical_processors_per_package = logical_processor_count();
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248 }
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249 }
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250
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251 _supports_cx8 = supports_cmpxchg8();
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252
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253 #ifdef _LP64
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254 // OS should support SSE for x64 and hardware should support at least SSE2.
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255 if (!VM_Version::supports_sse2()) {
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256 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
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257 }
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258 #endif
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259
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260 // If the OS doesn't support SSE, we can't use this feature even if the HW does
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261 if (!os::supports_sse())
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262 _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
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263
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264 if (UseSSE < 4) {
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265 _cpuFeatures &= ~CPU_SSE4_1;
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266 _cpuFeatures &= ~CPU_SSE4_2;
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267 }
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268
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269 if (UseSSE < 3) {
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270 _cpuFeatures &= ~CPU_SSE3;
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271 _cpuFeatures &= ~CPU_SSSE3;
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272 _cpuFeatures &= ~CPU_SSE4A;
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273 }
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274
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275 if (UseSSE < 2)
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276 _cpuFeatures &= ~CPU_SSE2;
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277
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278 if (UseSSE < 1)
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279 _cpuFeatures &= ~CPU_SSE;
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280
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281 if (logical_processors_per_package() == 1) {
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282 // HT processor could be installed on a system which doesn't support HT.
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283 _cpuFeatures &= ~CPU_HT;
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284 }
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285
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286 char buf[256];
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287 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
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288 cores_per_cpu(), threads_per_core(),
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289 cpu_family(), _model, _stepping,
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290 (supports_cmov() ? ", cmov" : ""),
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291 (supports_cmpxchg8() ? ", cx8" : ""),
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292 (supports_fxsr() ? ", fxsr" : ""),
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293 (supports_mmx() ? ", mmx" : ""),
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294 (supports_sse() ? ", sse" : ""),
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295 (supports_sse2() ? ", sse2" : ""),
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296 (supports_sse3() ? ", sse3" : ""),
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297 (supports_ssse3()? ", ssse3": ""),
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298 (supports_sse4_1() ? ", sse4.1" : ""),
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299 (supports_sse4_2() ? ", sse4.2" : ""),
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300 (supports_mmx_ext() ? ", mmxext" : ""),
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301 (supports_3dnow() ? ", 3dnow" : ""),
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302 (supports_3dnow2() ? ", 3dnowext" : ""),
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303 (supports_sse4a() ? ", sse4a": ""),
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304 (supports_ht() ? ", ht": ""));
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305 _features_str = strdup(buf);
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306
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307 // UseSSE is set to the smaller of what hardware supports and what
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308 // the command line requires. I.e., you cannot set UseSSE to 2 on
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309 // older Pentiums which do not support it.
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310 if( UseSSE > 4 ) UseSSE=4;
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311 if( UseSSE < 0 ) UseSSE=0;
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312 if( !supports_sse4_1() ) // Drop to 3 if no SSE4 support
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313 UseSSE = MIN2((intx)3,UseSSE);
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314 if( !supports_sse3() ) // Drop to 2 if no SSE3 support
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315 UseSSE = MIN2((intx)2,UseSSE);
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316 if( !supports_sse2() ) // Drop to 1 if no SSE2 support
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317 UseSSE = MIN2((intx)1,UseSSE);
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318 if( !supports_sse () ) // Drop to 0 if no SSE support
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319 UseSSE = 0;
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320
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321 // On new cpus instructions which update whole XMM register should be used
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322 // to prevent partial register stall due to dependencies on high half.
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323 //
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324 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
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325 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
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326 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
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327 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
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328
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329 if( is_amd() ) { // AMD cpus specific settings
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330 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
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331 // Use it on new AMD cpus starting from Opteron.
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332 UseAddressNop = true;
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333 }
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334 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
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335 // Use it on new AMD cpus starting from Opteron.
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336 UseNewLongLShift = true;
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337 }
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338 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
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339 if( supports_sse4a() ) {
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340 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
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341 } else {
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342 UseXmmLoadAndClearUpper = false;
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343 }
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344 }
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345 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
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346 if( supports_sse4a() ) {
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347 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
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348 } else {
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349 UseXmmRegToRegMoveAll = false;
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350 }
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351 }
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352 if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
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353 if( supports_sse4a() ) {
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354 UseXmmI2F = true;
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355 } else {
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356 UseXmmI2F = false;
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357 }
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358 }
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359 if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
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360 if( supports_sse4a() ) {
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361 UseXmmI2D = true;
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362 } else {
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363 UseXmmI2D = false;
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364 }
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365 }
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366 }
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367
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368 if( is_intel() ) { // Intel cpus specific settings
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369 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
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370 UseStoreImmI16 = false; // don't use it on Intel cpus
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371 }
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372 if( cpu_family() == 6 || cpu_family() == 15 ) {
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373 if( FLAG_IS_DEFAULT(UseAddressNop) ) {
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374 // Use it on all Intel cpus starting from PentiumPro
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375 UseAddressNop = true;
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376 }
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377 }
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378 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
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379 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
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380 }
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381 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
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382 if( supports_sse3() ) {
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383 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
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384 } else {
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385 UseXmmRegToRegMoveAll = false;
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386 }
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387 }
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388 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
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389 #ifdef COMPILER2
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390 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
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391 // For new Intel cpus do the next optimization:
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392 // don't align the beginning of a loop if there are enough instructions
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393 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
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394 // in current fetch line (OptoLoopAlignment) or the padding
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395 // is big (> MaxLoopPad).
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396 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
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397 // generated NOP instructions. 11 is the largest size of one
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398 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
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399 MaxLoopPad = 11;
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400 }
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401 #endif // COMPILER2
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402 if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) {
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403 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
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404 }
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405 if( supports_sse4_2() && supports_ht() ) { // Newest Intel cpus
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406 if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) {
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407 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
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408 }
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409 }
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410 }
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411 }
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412
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413 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
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414 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
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415
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416 // set valid Prefetch instruction
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417 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
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418 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
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419 if( ReadPrefetchInstr == 3 && !supports_3dnow() ) ReadPrefetchInstr = 0;
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420 if( !supports_sse() && supports_3dnow() ) ReadPrefetchInstr = 3;
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421
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422 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
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423 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
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424 if( AllocatePrefetchInstr == 3 && !supports_3dnow() ) AllocatePrefetchInstr=0;
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425 if( !supports_sse() && supports_3dnow() ) AllocatePrefetchInstr = 3;
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426
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427 // Allocation prefetch settings
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428 intx cache_line_size = L1_data_cache_line_size();
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429 if( cache_line_size > AllocatePrefetchStepSize )
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430 AllocatePrefetchStepSize = cache_line_size;
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431 if( FLAG_IS_DEFAULT(AllocatePrefetchLines) )
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432 AllocatePrefetchLines = 3; // Optimistic value
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433 assert(AllocatePrefetchLines > 0, "invalid value");
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434 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
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435 AllocatePrefetchLines = 1; // Conservative value
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436
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437 AllocatePrefetchDistance = allocate_prefetch_distance();
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438 AllocatePrefetchStyle = allocate_prefetch_style();
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439
|
|
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440 if( AllocatePrefetchStyle == 2 && is_intel() &&
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441 cpu_family() == 6 && supports_sse3() ) { // watermark prefetching on Core
|
|
|
442 #ifdef _LP64
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|
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443 AllocatePrefetchDistance = 384;
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|
|
444 #else
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|
|
445 AllocatePrefetchDistance = 320;
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|
|
446 #endif
|
|
|
447 }
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|
|
448 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
|
|
|
449
|
|
|
450 #ifdef _LP64
|
|
|
451 // Prefetch settings
|
|
|
452 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
|
|
|
453 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
|
|
|
454 PrefetchFieldsAhead = prefetch_fields_ahead();
|
|
|
455 #endif
|
|
|
456
|
|
|
457 #ifndef PRODUCT
|
|
|
458 if (PrintMiscellaneous && Verbose) {
|
|
|
459 tty->print_cr("Logical CPUs per core: %u",
|
|
|
460 logical_processors_per_package());
|
|
|
461 tty->print_cr("UseSSE=%d",UseSSE);
|
|
|
462 tty->print("Allocation: ");
|
|
|
463 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow()) {
|
|
|
464 tty->print_cr("no prefetching");
|
|
|
465 } else {
|
|
|
466 if (UseSSE == 0 && supports_3dnow()) {
|
|
|
467 tty->print("PREFETCHW");
|
|
|
468 } else if (UseSSE >= 1) {
|
|
|
469 if (AllocatePrefetchInstr == 0) {
|
|
|
470 tty->print("PREFETCHNTA");
|
|
|
471 } else if (AllocatePrefetchInstr == 1) {
|
|
|
472 tty->print("PREFETCHT0");
|
|
|
473 } else if (AllocatePrefetchInstr == 2) {
|
|
|
474 tty->print("PREFETCHT2");
|
|
|
475 } else if (AllocatePrefetchInstr == 3) {
|
|
|
476 tty->print("PREFETCHW");
|
|
|
477 }
|
|
|
478 }
|
|
|
479 if (AllocatePrefetchLines > 1) {
|
|
|
480 tty->print_cr(" %d, %d lines with step %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
|
|
|
481 } else {
|
|
|
482 tty->print_cr(" %d, one line", AllocatePrefetchDistance);
|
|
|
483 }
|
|
|
484 }
|
|
|
485
|
|
|
486 if (PrefetchCopyIntervalInBytes > 0) {
|
|
|
487 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
|
|
|
488 }
|
|
|
489 if (PrefetchScanIntervalInBytes > 0) {
|
|
|
490 tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
|
|
|
491 }
|
|
|
492 if (PrefetchFieldsAhead > 0) {
|
|
|
493 tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
|
|
|
494 }
|
|
|
495 }
|
|
|
496 #endif // !PRODUCT
|
|
|
497 }
|
|
|
498
|
|
|
499 void VM_Version::initialize() {
|
|
|
500 ResourceMark rm;
|
|
|
501 // Making this stub must be FIRST use of assembler
|
|
|
502
|
|
|
503 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
|
|
|
504 if (stub_blob == NULL) {
|
|
|
505 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
|
|
|
506 }
|
|
|
507 CodeBuffer c(stub_blob->instructions_begin(),
|
|
|
508 stub_blob->instructions_size());
|
|
|
509 VM_Version_StubGenerator g(&c);
|
|
|
510 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
|
|
|
511 g.generate_getPsrInfo());
|
|
|
512
|
|
|
513 get_processor_features();
|
|
|
514 }
|
