Mercurial > hg > truffle
annotate src/share/vm/c1/c1_LinearScan.cpp @ 1721:413ad0331a0c
6977924: Changes for 6975078 produce build error with certain gcc versions
Summary: The changes introduced for 6975078 assign badHeapOopVal to the _allocation field in the ResourceObj class. In 32 bit linux builds with certain versions of gcc this assignment will be flagged as an error while compiling allocation.cpp. In 32 bit builds the constant value badHeapOopVal (which is cast to an intptr_t) is negative. The _allocation field is typed as an unsigned intptr_t and gcc catches this as an error.
Reviewed-by: jcoomes, ysr, phh
| author | johnc |
|---|---|
| date | Wed, 18 Aug 2010 10:59:06 -0700 |
| parents | 126ea7725993 |
| children | 87b64980e2f1 |
| rev | line source |
|---|---|
| 0 | 1 /* |
|
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2 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
|
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 25 #include "incls/_precompiled.incl" | |
| 26 #include "incls/_c1_LinearScan.cpp.incl" | |
| 27 | |
| 28 | |
| 29 #ifndef PRODUCT | |
| 30 | |
| 31 static LinearScanStatistic _stat_before_alloc; | |
| 32 static LinearScanStatistic _stat_after_asign; | |
| 33 static LinearScanStatistic _stat_final; | |
| 34 | |
| 35 static LinearScanTimers _total_timer; | |
| 36 | |
| 37 // helper macro for short definition of timer | |
| 38 #define TIME_LINEAR_SCAN(timer_name) TraceTime _block_timer("", _total_timer.timer(LinearScanTimers::timer_name), TimeLinearScan || TimeEachLinearScan, Verbose); | |
| 39 | |
| 40 // helper macro for short definition of trace-output inside code | |
| 41 #define TRACE_LINEAR_SCAN(level, code) \ | |
| 42 if (TraceLinearScanLevel >= level) { \ | |
| 43 code; \ | |
| 44 } | |
| 45 | |
| 46 #else | |
| 47 | |
| 48 #define TIME_LINEAR_SCAN(timer_name) | |
| 49 #define TRACE_LINEAR_SCAN(level, code) | |
| 50 | |
| 51 #endif | |
| 52 | |
| 53 // Map BasicType to spill size in 32-bit words, matching VMReg's notion of words | |
| 54 #ifdef _LP64 | |
| 55 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 2, 2, 0, 1, -1}; | |
| 56 #else | |
| 57 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 1, 1, 0, 1, -1}; | |
| 58 #endif | |
| 59 | |
| 60 | |
| 61 // Implementation of LinearScan | |
| 62 | |
| 63 LinearScan::LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map) | |
| 64 : _compilation(ir->compilation()) | |
| 65 , _ir(ir) | |
| 66 , _gen(gen) | |
| 67 , _frame_map(frame_map) | |
| 68 , _num_virtual_regs(gen->max_virtual_register_number()) | |
| 69 , _has_fpu_registers(false) | |
| 70 , _num_calls(-1) | |
| 71 , _max_spills(0) | |
| 72 , _unused_spill_slot(-1) | |
| 73 , _intervals(0) // initialized later with correct length | |
| 74 , _new_intervals_from_allocation(new IntervalList()) | |
| 75 , _sorted_intervals(NULL) | |
| 76 , _lir_ops(0) // initialized later with correct length | |
| 77 , _block_of_op(0) // initialized later with correct length | |
| 78 , _has_info(0) | |
| 79 , _has_call(0) | |
| 80 , _scope_value_cache(0) // initialized later with correct length | |
| 81 , _interval_in_loop(0, 0) // initialized later with correct length | |
| 82 , _cached_blocks(*ir->linear_scan_order()) | |
| 304 | 83 #ifdef X86 |
| 0 | 84 , _fpu_stack_allocator(NULL) |
| 85 #endif | |
| 86 { | |
| 87 assert(this->ir() != NULL, "check if valid"); | |
| 88 assert(this->compilation() != NULL, "check if valid"); | |
| 89 assert(this->gen() != NULL, "check if valid"); | |
| 90 assert(this->frame_map() != NULL, "check if valid"); | |
| 91 } | |
| 92 | |
| 93 | |
| 94 // ********** functions for converting LIR-Operands to register numbers | |
| 95 // | |
| 96 // Emulate a flat register file comprising physical integer registers, | |
| 97 // physical floating-point registers and virtual registers, in that order. | |
| 98 // Virtual registers already have appropriate numbers, since V0 is | |
| 99 // the number of physical registers. | |
| 100 // Returns -1 for hi word if opr is a single word operand. | |
| 101 // | |
| 102 // Note: the inverse operation (calculating an operand for register numbers) | |
| 103 // is done in calc_operand_for_interval() | |
| 104 | |
| 105 int LinearScan::reg_num(LIR_Opr opr) { | |
| 106 assert(opr->is_register(), "should not call this otherwise"); | |
| 107 | |
| 108 if (opr->is_virtual_register()) { | |
| 109 assert(opr->vreg_number() >= nof_regs, "found a virtual register with a fixed-register number"); | |
| 110 return opr->vreg_number(); | |
| 111 } else if (opr->is_single_cpu()) { | |
| 112 return opr->cpu_regnr(); | |
| 113 } else if (opr->is_double_cpu()) { | |
| 114 return opr->cpu_regnrLo(); | |
| 304 | 115 #ifdef X86 |
| 0 | 116 } else if (opr->is_single_xmm()) { |
| 117 return opr->fpu_regnr() + pd_first_xmm_reg; | |
| 118 } else if (opr->is_double_xmm()) { | |
| 119 return opr->fpu_regnrLo() + pd_first_xmm_reg; | |
| 120 #endif | |
| 121 } else if (opr->is_single_fpu()) { | |
| 122 return opr->fpu_regnr() + pd_first_fpu_reg; | |
| 123 } else if (opr->is_double_fpu()) { | |
| 124 return opr->fpu_regnrLo() + pd_first_fpu_reg; | |
| 125 } else { | |
| 126 ShouldNotReachHere(); | |
| 304 | 127 return -1; |
| 0 | 128 } |
| 129 } | |
| 130 | |
| 131 int LinearScan::reg_numHi(LIR_Opr opr) { | |
| 132 assert(opr->is_register(), "should not call this otherwise"); | |
| 133 | |
| 134 if (opr->is_virtual_register()) { | |
| 135 return -1; | |
| 136 } else if (opr->is_single_cpu()) { | |
| 137 return -1; | |
| 138 } else if (opr->is_double_cpu()) { | |
| 139 return opr->cpu_regnrHi(); | |
| 304 | 140 #ifdef X86 |
| 0 | 141 } else if (opr->is_single_xmm()) { |
| 142 return -1; | |
| 143 } else if (opr->is_double_xmm()) { | |
| 144 return -1; | |
| 145 #endif | |
| 146 } else if (opr->is_single_fpu()) { | |
| 147 return -1; | |
| 148 } else if (opr->is_double_fpu()) { | |
| 149 return opr->fpu_regnrHi() + pd_first_fpu_reg; | |
| 150 } else { | |
| 151 ShouldNotReachHere(); | |
| 304 | 152 return -1; |
| 0 | 153 } |
| 154 } | |
| 155 | |
| 156 | |
| 157 // ********** functions for classification of intervals | |
| 158 | |
| 159 bool LinearScan::is_precolored_interval(const Interval* i) { | |
| 160 return i->reg_num() < LinearScan::nof_regs; | |
| 161 } | |
| 162 | |
| 163 bool LinearScan::is_virtual_interval(const Interval* i) { | |
| 164 return i->reg_num() >= LIR_OprDesc::vreg_base; | |
| 165 } | |
| 166 | |
| 167 bool LinearScan::is_precolored_cpu_interval(const Interval* i) { | |
| 168 return i->reg_num() < LinearScan::nof_cpu_regs; | |
| 169 } | |
| 170 | |
| 171 bool LinearScan::is_virtual_cpu_interval(const Interval* i) { | |
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172 #if defined(__SOFTFP__) || defined(E500V2) |
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173 return i->reg_num() >= LIR_OprDesc::vreg_base; |
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174 #else |
| 0 | 175 return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() != T_FLOAT && i->type() != T_DOUBLE); |
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176 #endif // __SOFTFP__ or E500V2 |
| 0 | 177 } |
| 178 | |
| 179 bool LinearScan::is_precolored_fpu_interval(const Interval* i) { | |
| 180 return i->reg_num() >= LinearScan::nof_cpu_regs && i->reg_num() < LinearScan::nof_regs; | |
| 181 } | |
| 182 | |
| 183 bool LinearScan::is_virtual_fpu_interval(const Interval* i) { | |
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184 #if defined(__SOFTFP__) || defined(E500V2) |
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185 return false; |
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186 #else |
| 0 | 187 return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE); |
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188 #endif // __SOFTFP__ or E500V2 |
| 0 | 189 } |
| 190 | |
| 191 bool LinearScan::is_in_fpu_register(const Interval* i) { | |
| 192 // fixed intervals not needed for FPU stack allocation | |
| 193 return i->reg_num() >= nof_regs && pd_first_fpu_reg <= i->assigned_reg() && i->assigned_reg() <= pd_last_fpu_reg; | |
| 194 } | |
| 195 | |
| 196 bool LinearScan::is_oop_interval(const Interval* i) { | |
| 197 // fixed intervals never contain oops | |
| 198 return i->reg_num() >= nof_regs && i->type() == T_OBJECT; | |
| 199 } | |
| 200 | |
| 201 | |
| 202 // ********** General helper functions | |
| 203 | |
| 204 // compute next unused stack index that can be used for spilling | |
| 205 int LinearScan::allocate_spill_slot(bool double_word) { | |
| 206 int spill_slot; | |
| 207 if (double_word) { | |
| 208 if ((_max_spills & 1) == 1) { | |
| 209 // alignment of double-word values | |
| 210 // the hole because of the alignment is filled with the next single-word value | |
| 211 assert(_unused_spill_slot == -1, "wasting a spill slot"); | |
| 212 _unused_spill_slot = _max_spills; | |
| 213 _max_spills++; | |
| 214 } | |
| 215 spill_slot = _max_spills; | |
| 216 _max_spills += 2; | |
| 217 | |
| 218 } else if (_unused_spill_slot != -1) { | |
| 219 // re-use hole that was the result of a previous double-word alignment | |
| 220 spill_slot = _unused_spill_slot; | |
| 221 _unused_spill_slot = -1; | |
| 222 | |
| 223 } else { | |
| 224 spill_slot = _max_spills; | |
| 225 _max_spills++; | |
| 226 } | |
| 227 | |
| 228 int result = spill_slot + LinearScan::nof_regs + frame_map()->argcount(); | |
| 229 | |
| 230 // the class OopMapValue uses only 11 bits for storing the name of the | |
| 231 // oop location. So a stack slot bigger than 2^11 leads to an overflow | |
| 232 // that is not reported in product builds. Prevent this by checking the | |
| 233 // spill slot here (altough this value and the later used location name | |
| 234 // are slightly different) | |
| 235 if (result > 2000) { | |
| 236 bailout("too many stack slots used"); | |
| 237 } | |
| 238 | |
| 239 return result; | |
| 240 } | |
| 241 | |
| 242 void LinearScan::assign_spill_slot(Interval* it) { | |
| 243 // assign the canonical spill slot of the parent (if a part of the interval | |
| 244 // is already spilled) or allocate a new spill slot | |
| 245 if (it->canonical_spill_slot() >= 0) { | |
| 246 it->assign_reg(it->canonical_spill_slot()); | |
| 247 } else { | |
| 248 int spill = allocate_spill_slot(type2spill_size[it->type()] == 2); | |
| 249 it->set_canonical_spill_slot(spill); | |
| 250 it->assign_reg(spill); | |
| 251 } | |
| 252 } | |
| 253 | |
| 254 void LinearScan::propagate_spill_slots() { | |
| 255 if (!frame_map()->finalize_frame(max_spills())) { | |
| 256 bailout("frame too large"); | |
| 257 } | |
| 258 } | |
| 259 | |
| 260 // create a new interval with a predefined reg_num | |
| 261 // (only used for parent intervals that are created during the building phase) | |
| 262 Interval* LinearScan::create_interval(int reg_num) { | |
| 263 assert(_intervals.at(reg_num) == NULL, "overwriting exisiting interval"); | |
| 264 | |
| 265 Interval* interval = new Interval(reg_num); | |
| 266 _intervals.at_put(reg_num, interval); | |
| 267 | |
| 268 // assign register number for precolored intervals | |
| 269 if (reg_num < LIR_OprDesc::vreg_base) { | |
| 270 interval->assign_reg(reg_num); | |
| 271 } | |
| 272 return interval; | |
| 273 } | |
| 274 | |
| 275 // assign a new reg_num to the interval and append it to the list of intervals | |
| 276 // (only used for child intervals that are created during register allocation) | |
| 277 void LinearScan::append_interval(Interval* it) { | |
| 278 it->set_reg_num(_intervals.length()); | |
| 279 _intervals.append(it); | |
| 280 _new_intervals_from_allocation->append(it); | |
| 281 } | |
| 282 | |
| 283 // copy the vreg-flags if an interval is split | |
| 284 void LinearScan::copy_register_flags(Interval* from, Interval* to) { | |
| 285 if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::byte_reg)) { | |
| 286 gen()->set_vreg_flag(to->reg_num(), LIRGenerator::byte_reg); | |
| 287 } | |
| 288 if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::callee_saved)) { | |
| 289 gen()->set_vreg_flag(to->reg_num(), LIRGenerator::callee_saved); | |
| 290 } | |
| 291 | |
| 292 // Note: do not copy the must_start_in_memory flag because it is not necessary for child | |
| 293 // intervals (only the very beginning of the interval must be in memory) | |
| 294 } | |
| 295 | |
| 296 | |
| 297 // ********** spill move optimization | |
| 298 // eliminate moves from register to stack if stack slot is known to be correct | |
| 299 | |
| 300 // called during building of intervals | |
| 301 void LinearScan::change_spill_definition_pos(Interval* interval, int def_pos) { | |
| 302 assert(interval->is_split_parent(), "can only be called for split parents"); | |
| 303 | |
| 304 switch (interval->spill_state()) { | |
| 305 case noDefinitionFound: | |
| 306 assert(interval->spill_definition_pos() == -1, "must no be set before"); | |
| 307 interval->set_spill_definition_pos(def_pos); | |
| 308 interval->set_spill_state(oneDefinitionFound); | |
| 309 break; | |
| 310 | |
| 311 case oneDefinitionFound: | |
| 312 assert(def_pos <= interval->spill_definition_pos(), "positions are processed in reverse order when intervals are created"); | |
| 313 if (def_pos < interval->spill_definition_pos() - 2) { | |
| 314 // second definition found, so no spill optimization possible for this interval | |
| 315 interval->set_spill_state(noOptimization); | |
| 316 } else { | |
| 317 // two consecutive definitions (because of two-operand LIR form) | |
| 318 assert(block_of_op_with_id(def_pos) == block_of_op_with_id(interval->spill_definition_pos()), "block must be equal"); | |
| 319 } | |
| 320 break; | |
| 321 | |
| 322 case noOptimization: | |
| 323 // nothing to do | |
| 324 break; | |
| 325 | |
| 326 default: | |
| 327 assert(false, "other states not allowed at this time"); | |
| 328 } | |
| 329 } | |
| 330 | |
| 331 // called during register allocation | |
| 332 void LinearScan::change_spill_state(Interval* interval, int spill_pos) { | |
| 333 switch (interval->spill_state()) { | |
| 334 case oneDefinitionFound: { | |
| 335 int def_loop_depth = block_of_op_with_id(interval->spill_definition_pos())->loop_depth(); | |
| 336 int spill_loop_depth = block_of_op_with_id(spill_pos)->loop_depth(); | |
| 337 | |
| 338 if (def_loop_depth < spill_loop_depth) { | |
| 339 // the loop depth of the spilling position is higher then the loop depth | |
| 340 // at the definition of the interval -> move write to memory out of loop | |
| 341 // by storing at definitin of the interval | |
| 342 interval->set_spill_state(storeAtDefinition); | |
| 343 } else { | |
| 344 // the interval is currently spilled only once, so for now there is no | |
| 345 // reason to store the interval at the definition | |
| 346 interval->set_spill_state(oneMoveInserted); | |
| 347 } | |
| 348 break; | |
| 349 } | |
| 350 | |
| 351 case oneMoveInserted: { | |
| 352 // the interval is spilled more then once, so it is better to store it to | |
| 353 // memory at the definition | |
| 354 interval->set_spill_state(storeAtDefinition); | |
| 355 break; | |
| 356 } | |
| 357 | |
| 358 case storeAtDefinition: | |
| 359 case startInMemory: | |
| 360 case noOptimization: | |
| 361 case noDefinitionFound: | |
| 362 // nothing to do | |
| 363 break; | |
| 364 | |
| 365 default: | |
| 366 assert(false, "other states not allowed at this time"); | |
| 367 } | |
| 368 } | |
| 369 | |
| 370 | |
| 371 bool LinearScan::must_store_at_definition(const Interval* i) { | |
| 372 return i->is_split_parent() && i->spill_state() == storeAtDefinition; | |
| 373 } | |
| 374 | |
| 375 // called once before asignment of register numbers | |
| 376 void LinearScan::eliminate_spill_moves() { | |
| 377 TIME_LINEAR_SCAN(timer_eliminate_spill_moves); | |
| 378 TRACE_LINEAR_SCAN(3, tty->print_cr("***** Eliminating unnecessary spill moves")); | |
| 379 | |
| 380 // collect all intervals that must be stored after their definion. | |
| 381 // the list is sorted by Interval::spill_definition_pos | |
| 382 Interval* interval; | |
| 383 Interval* temp_list; | |
| 384 create_unhandled_lists(&interval, &temp_list, must_store_at_definition, NULL); | |
| 385 | |
| 386 #ifdef ASSERT | |
| 387 Interval* prev = NULL; | |
| 388 Interval* temp = interval; | |
| 389 while (temp != Interval::end()) { | |
| 390 assert(temp->spill_definition_pos() > 0, "invalid spill definition pos"); | |
| 391 if (prev != NULL) { | |
| 392 assert(temp->from() >= prev->from(), "intervals not sorted"); | |
| 393 assert(temp->spill_definition_pos() >= prev->spill_definition_pos(), "when intervals are sorted by from, then they must also be sorted by spill_definition_pos"); | |
| 394 } | |
| 395 | |
| 396 assert(temp->canonical_spill_slot() >= LinearScan::nof_regs, "interval has no spill slot assigned"); | |
| 397 assert(temp->spill_definition_pos() >= temp->from(), "invalid order"); | |
| 398 assert(temp->spill_definition_pos() <= temp->from() + 2, "only intervals defined once at their start-pos can be optimized"); | |
| 399 | |
| 400 TRACE_LINEAR_SCAN(4, tty->print_cr("interval %d (from %d to %d) must be stored at %d", temp->reg_num(), temp->from(), temp->to(), temp->spill_definition_pos())); | |
| 401 | |
| 402 temp = temp->next(); | |
| 403 } | |
| 404 #endif | |
| 405 | |
| 406 LIR_InsertionBuffer insertion_buffer; | |
| 407 int num_blocks = block_count(); | |
| 408 for (int i = 0; i < num_blocks; i++) { | |
| 409 BlockBegin* block = block_at(i); | |
| 410 LIR_OpList* instructions = block->lir()->instructions_list(); | |
| 411 int num_inst = instructions->length(); | |
| 412 bool has_new = false; | |
| 413 | |
| 414 // iterate all instructions of the block. skip the first because it is always a label | |
| 415 for (int j = 1; j < num_inst; j++) { | |
| 416 LIR_Op* op = instructions->at(j); | |
| 417 int op_id = op->id(); | |
| 418 | |
| 419 if (op_id == -1) { | |
| 420 // remove move from register to stack if the stack slot is guaranteed to be correct. | |
| 421 // only moves that have been inserted by LinearScan can be removed. | |
| 422 assert(op->code() == lir_move, "only moves can have a op_id of -1"); | |
| 423 assert(op->as_Op1() != NULL, "move must be LIR_Op1"); | |
| 424 assert(op->as_Op1()->result_opr()->is_virtual(), "LinearScan inserts only moves to virtual registers"); | |
| 425 | |
| 426 LIR_Op1* op1 = (LIR_Op1*)op; | |
| 427 Interval* interval = interval_at(op1->result_opr()->vreg_number()); | |
| 428 | |
| 429 if (interval->assigned_reg() >= LinearScan::nof_regs && interval->always_in_memory()) { | |
| 430 // move target is a stack slot that is always correct, so eliminate instruction | |
| 431 TRACE_LINEAR_SCAN(4, tty->print_cr("eliminating move from interval %d to %d", op1->in_opr()->vreg_number(), op1->result_opr()->vreg_number())); | |
| 432 instructions->at_put(j, NULL); // NULL-instructions are deleted by assign_reg_num | |
| 433 } | |
| 434 | |
| 435 } else { | |
| 436 // insert move from register to stack just after the beginning of the interval | |
| 437 assert(interval == Interval::end() || interval->spill_definition_pos() >= op_id, "invalid order"); | |
| 438 assert(interval == Interval::end() || (interval->is_split_parent() && interval->spill_state() == storeAtDefinition), "invalid interval"); | |
| 439 | |
| 440 while (interval != Interval::end() && interval->spill_definition_pos() == op_id) { | |
| 441 if (!has_new) { | |
| 442 // prepare insertion buffer (appended when all instructions of the block are processed) | |
| 443 insertion_buffer.init(block->lir()); | |
| 444 has_new = true; | |
| 445 } | |
| 446 | |
| 447 LIR_Opr from_opr = operand_for_interval(interval); | |
| 448 LIR_Opr to_opr = canonical_spill_opr(interval); | |
| 449 assert(from_opr->is_fixed_cpu() || from_opr->is_fixed_fpu(), "from operand must be a register"); | |
| 450 assert(to_opr->is_stack(), "to operand must be a stack slot"); | |
| 451 | |
| 452 insertion_buffer.move(j, from_opr, to_opr); | |
| 453 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting move after definition of interval %d to stack slot %d at op_id %d", interval->reg_num(), interval->canonical_spill_slot() - LinearScan::nof_regs, op_id)); | |
| 454 | |
| 455 interval = interval->next(); | |
| 456 } | |
| 457 } | |
| 458 } // end of instruction iteration | |
| 459 | |
| 460 if (has_new) { | |
| 461 block->lir()->append(&insertion_buffer); | |
| 462 } | |
| 463 } // end of block iteration | |
| 464 | |
| 465 assert(interval == Interval::end(), "missed an interval"); | |
| 466 } | |
| 467 | |
| 468 | |
| 469 // ********** Phase 1: number all instructions in all blocks | |
| 470 // Compute depth-first and linear scan block orders, and number LIR_Op nodes for linear scan. | |
| 471 | |
| 472 void LinearScan::number_instructions() { | |
| 473 { | |
| 474 // dummy-timer to measure the cost of the timer itself | |
| 475 // (this time is then subtracted from all other timers to get the real value) | |
| 476 TIME_LINEAR_SCAN(timer_do_nothing); | |
| 477 } | |
| 478 TIME_LINEAR_SCAN(timer_number_instructions); | |
| 479 | |
| 480 // Assign IDs to LIR nodes and build a mapping, lir_ops, from ID to LIR_Op node. | |
| 481 int num_blocks = block_count(); | |
| 482 int num_instructions = 0; | |
| 483 int i; | |
| 484 for (i = 0; i < num_blocks; i++) { | |
| 485 num_instructions += block_at(i)->lir()->instructions_list()->length(); | |
| 486 } | |
| 487 | |
| 488 // initialize with correct length | |
| 489 _lir_ops = LIR_OpArray(num_instructions); | |
| 490 _block_of_op = BlockBeginArray(num_instructions); | |
| 491 | |
| 492 int op_id = 0; | |
| 493 int idx = 0; | |
| 494 | |
| 495 for (i = 0; i < num_blocks; i++) { | |
| 496 BlockBegin* block = block_at(i); | |
| 497 block->set_first_lir_instruction_id(op_id); | |
| 498 LIR_OpList* instructions = block->lir()->instructions_list(); | |
| 499 | |
| 500 int num_inst = instructions->length(); | |
| 501 for (int j = 0; j < num_inst; j++) { | |
| 502 LIR_Op* op = instructions->at(j); | |
| 503 op->set_id(op_id); | |
| 504 | |
| 505 _lir_ops.at_put(idx, op); | |
| 506 _block_of_op.at_put(idx, block); | |
| 507 assert(lir_op_with_id(op_id) == op, "must match"); | |
| 508 | |
| 509 idx++; | |
| 510 op_id += 2; // numbering of lir_ops by two | |
| 511 } | |
| 512 block->set_last_lir_instruction_id(op_id - 2); | |
| 513 } | |
| 514 assert(idx == num_instructions, "must match"); | |
| 515 assert(idx * 2 == op_id, "must match"); | |
| 516 | |
| 517 _has_call = BitMap(num_instructions); _has_call.clear(); | |
| 518 _has_info = BitMap(num_instructions); _has_info.clear(); | |
| 519 } | |
| 520 | |
| 521 | |
| 522 // ********** Phase 2: compute local live sets separately for each block | |
| 523 // (sets live_gen and live_kill for each block) | |
| 524 | |
| 525 void LinearScan::set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill) { | |
| 526 LIR_Opr opr = value->operand(); | |
| 527 Constant* con = value->as_Constant(); | |
| 528 | |
| 529 // check some asumptions about debug information | |
| 530 assert(!value->type()->is_illegal(), "if this local is used by the interpreter it shouldn't be of indeterminate type"); | |
| 531 assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands"); | |
| 532 assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands"); | |
| 533 | |
| 534 if ((con == NULL || con->is_pinned()) && opr->is_register()) { | |
| 535 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); | |
| 536 int reg = opr->vreg_number(); | |
| 537 if (!live_kill.at(reg)) { | |
| 538 live_gen.set_bit(reg); | |
| 539 TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for value %c%d, LIR op_id %d, register number %d", value->type()->tchar(), value->id(), op->id(), reg)); | |
| 540 } | |
| 541 } | |
| 542 } | |
| 543 | |
| 544 | |
| 545 void LinearScan::compute_local_live_sets() { | |
| 546 TIME_LINEAR_SCAN(timer_compute_local_live_sets); | |
| 547 | |
| 548 int num_blocks = block_count(); | |
| 549 int live_size = live_set_size(); | |
| 550 bool local_has_fpu_registers = false; | |
| 551 int local_num_calls = 0; | |
| 552 LIR_OpVisitState visitor; | |
| 553 | |
| 554 BitMap2D local_interval_in_loop = BitMap2D(_num_virtual_regs, num_loops()); | |
| 555 local_interval_in_loop.clear(); | |
| 556 | |
| 557 // iterate all blocks | |
| 558 for (int i = 0; i < num_blocks; i++) { | |
| 559 BlockBegin* block = block_at(i); | |
| 560 | |
| 561 BitMap live_gen(live_size); live_gen.clear(); | |
| 562 BitMap live_kill(live_size); live_kill.clear(); | |
| 563 | |
| 564 if (block->is_set(BlockBegin::exception_entry_flag)) { | |
| 565 // Phi functions at the begin of an exception handler are | |
| 566 // implicitly defined (= killed) at the beginning of the block. | |
| 567 for_each_phi_fun(block, phi, | |
| 568 live_kill.set_bit(phi->operand()->vreg_number()) | |
| 569 ); | |
| 570 } | |
| 571 | |
| 572 LIR_OpList* instructions = block->lir()->instructions_list(); | |
| 573 int num_inst = instructions->length(); | |
| 574 | |
| 575 // iterate all instructions of the block. skip the first because it is always a label | |
| 576 assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label"); | |
| 577 for (int j = 1; j < num_inst; j++) { | |
| 578 LIR_Op* op = instructions->at(j); | |
| 579 | |
| 580 // visit operation to collect all operands | |
| 581 visitor.visit(op); | |
| 582 | |
| 583 if (visitor.has_call()) { | |
| 584 _has_call.set_bit(op->id() >> 1); | |
| 585 local_num_calls++; | |
| 586 } | |
| 587 if (visitor.info_count() > 0) { | |
| 588 _has_info.set_bit(op->id() >> 1); | |
| 589 } | |
| 590 | |
| 591 // iterate input operands of instruction | |
| 592 int k, n, reg; | |
| 593 n = visitor.opr_count(LIR_OpVisitState::inputMode); | |
| 594 for (k = 0; k < n; k++) { | |
| 595 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k); | |
| 596 assert(opr->is_register(), "visitor should only return register operands"); | |
| 597 | |
| 598 if (opr->is_virtual_register()) { | |
| 599 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); | |
| 600 reg = opr->vreg_number(); | |
| 601 if (!live_kill.at(reg)) { | |
| 602 live_gen.set_bit(reg); | |
| 603 TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for register %d at instruction %d", reg, op->id())); | |
| 604 } | |
| 605 if (block->loop_index() >= 0) { | |
| 606 local_interval_in_loop.set_bit(reg, block->loop_index()); | |
| 607 } | |
| 608 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu(); | |
| 609 } | |
| 610 | |
| 611 #ifdef ASSERT | |
| 612 // fixed intervals are never live at block boundaries, so | |
| 613 // they need not be processed in live sets. | |
| 614 // this is checked by these assertions to be sure about it. | |
| 615 // the entry block may have incoming values in registers, which is ok. | |
| 616 if (!opr->is_virtual_register() && block != ir()->start()) { | |
| 617 reg = reg_num(opr); | |
| 618 if (is_processed_reg_num(reg)) { | |
| 619 assert(live_kill.at(reg), "using fixed register that is not defined in this block"); | |
| 620 } | |
| 621 reg = reg_numHi(opr); | |
| 622 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { | |
| 623 assert(live_kill.at(reg), "using fixed register that is not defined in this block"); | |
| 624 } | |
| 625 } | |
| 626 #endif | |
| 627 } | |
| 628 | |
| 629 // Add uses of live locals from interpreter's point of view for proper debug information generation | |
| 630 n = visitor.info_count(); | |
| 631 for (k = 0; k < n; k++) { | |
| 632 CodeEmitInfo* info = visitor.info_at(k); | |
| 633 ValueStack* stack = info->stack(); | |
| 634 for_each_state_value(stack, value, | |
| 635 set_live_gen_kill(value, op, live_gen, live_kill) | |
| 636 ); | |
| 637 } | |
| 638 | |
| 639 // iterate temp operands of instruction | |
| 640 n = visitor.opr_count(LIR_OpVisitState::tempMode); | |
| 641 for (k = 0; k < n; k++) { | |
| 642 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k); | |
| 643 assert(opr->is_register(), "visitor should only return register operands"); | |
| 644 | |
| 645 if (opr->is_virtual_register()) { | |
| 646 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); | |
| 647 reg = opr->vreg_number(); | |
| 648 live_kill.set_bit(reg); | |
| 649 if (block->loop_index() >= 0) { | |
| 650 local_interval_in_loop.set_bit(reg, block->loop_index()); | |
| 651 } | |
| 652 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu(); | |
| 653 } | |
| 654 | |
| 655 #ifdef ASSERT | |
| 656 // fixed intervals are never live at block boundaries, so | |
| 657 // they need not be processed in live sets | |
| 658 // process them only in debug mode so that this can be checked | |
| 659 if (!opr->is_virtual_register()) { | |
| 660 reg = reg_num(opr); | |
| 661 if (is_processed_reg_num(reg)) { | |
| 662 live_kill.set_bit(reg_num(opr)); | |
| 663 } | |
| 664 reg = reg_numHi(opr); | |
| 665 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { | |
| 666 live_kill.set_bit(reg); | |
| 667 } | |
| 668 } | |
| 669 #endif | |
| 670 } | |
| 671 | |
| 672 // iterate output operands of instruction | |
| 673 n = visitor.opr_count(LIR_OpVisitState::outputMode); | |
| 674 for (k = 0; k < n; k++) { | |
| 675 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k); | |
| 676 assert(opr->is_register(), "visitor should only return register operands"); | |
| 677 | |
| 678 if (opr->is_virtual_register()) { | |
| 679 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); | |
| 680 reg = opr->vreg_number(); | |
| 681 live_kill.set_bit(reg); | |
| 682 if (block->loop_index() >= 0) { | |
| 683 local_interval_in_loop.set_bit(reg, block->loop_index()); | |
| 684 } | |
| 685 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu(); | |
| 686 } | |
| 687 | |
| 688 #ifdef ASSERT | |
| 689 // fixed intervals are never live at block boundaries, so | |
| 690 // they need not be processed in live sets | |
| 691 // process them only in debug mode so that this can be checked | |
| 692 if (!opr->is_virtual_register()) { | |
| 693 reg = reg_num(opr); | |
| 694 if (is_processed_reg_num(reg)) { | |
| 695 live_kill.set_bit(reg_num(opr)); | |
| 696 } | |
| 697 reg = reg_numHi(opr); | |
| 698 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { | |
| 699 live_kill.set_bit(reg); | |
| 700 } | |
| 701 } | |
| 702 #endif | |
| 703 } | |
| 704 } // end of instruction iteration | |
| 705 | |
| 706 block->set_live_gen (live_gen); | |
| 707 block->set_live_kill(live_kill); | |
| 708 block->set_live_in (BitMap(live_size)); block->live_in().clear(); | |
| 709 block->set_live_out (BitMap(live_size)); block->live_out().clear(); | |
| 710 | |
| 711 TRACE_LINEAR_SCAN(4, tty->print("live_gen B%d ", block->block_id()); print_bitmap(block->live_gen())); | |
| 712 TRACE_LINEAR_SCAN(4, tty->print("live_kill B%d ", block->block_id()); print_bitmap(block->live_kill())); | |
| 713 } // end of block iteration | |
| 714 | |
| 715 // propagate local calculated information into LinearScan object | |
| 716 _has_fpu_registers = local_has_fpu_registers; | |
| 717 compilation()->set_has_fpu_code(local_has_fpu_registers); | |
| 718 | |
| 719 _num_calls = local_num_calls; | |
| 720 _interval_in_loop = local_interval_in_loop; | |
| 721 } | |
| 722 | |
| 723 | |
| 724 // ********** Phase 3: perform a backward dataflow analysis to compute global live sets | |
| 725 // (sets live_in and live_out for each block) | |
| 726 | |
| 727 void LinearScan::compute_global_live_sets() { | |
| 728 TIME_LINEAR_SCAN(timer_compute_global_live_sets); | |
| 729 | |
| 730 int num_blocks = block_count(); | |
| 731 bool change_occurred; | |
| 732 bool change_occurred_in_block; | |
| 733 int iteration_count = 0; | |
| 734 BitMap live_out(live_set_size()); live_out.clear(); // scratch set for calculations | |
| 735 | |
| 736 // Perform a backward dataflow analysis to compute live_out and live_in for each block. | |
| 737 // The loop is executed until a fixpoint is reached (no changes in an iteration) | |
| 738 // Exception handlers must be processed because not all live values are | |
| 739 // present in the state array, e.g. because of global value numbering | |
| 740 do { | |
| 741 change_occurred = false; | |
| 742 | |
| 743 // iterate all blocks in reverse order | |
| 744 for (int i = num_blocks - 1; i >= 0; i--) { | |
| 745 BlockBegin* block = block_at(i); | |
| 746 | |
| 747 change_occurred_in_block = false; | |
| 748 | |
| 749 // live_out(block) is the union of live_in(sux), for successors sux of block | |
| 750 int n = block->number_of_sux(); | |
| 751 int e = block->number_of_exception_handlers(); | |
| 752 if (n + e > 0) { | |
| 753 // block has successors | |
| 754 if (n > 0) { | |
| 755 live_out.set_from(block->sux_at(0)->live_in()); | |
| 756 for (int j = 1; j < n; j++) { | |
| 757 live_out.set_union(block->sux_at(j)->live_in()); | |
| 758 } | |
| 759 } else { | |
| 760 live_out.clear(); | |
| 761 } | |
| 762 for (int j = 0; j < e; j++) { | |
| 763 live_out.set_union(block->exception_handler_at(j)->live_in()); | |
| 764 } | |
| 765 | |
| 766 if (!block->live_out().is_same(live_out)) { | |
| 767 // A change occurred. Swap the old and new live out sets to avoid copying. | |
| 768 BitMap temp = block->live_out(); | |
| 769 block->set_live_out(live_out); | |
| 770 live_out = temp; | |
| 771 | |
| 772 change_occurred = true; | |
| 773 change_occurred_in_block = true; | |
| 774 } | |
| 775 } | |
| 776 | |
| 777 if (iteration_count == 0 || change_occurred_in_block) { | |
| 778 // live_in(block) is the union of live_gen(block) with (live_out(block) & !live_kill(block)) | |
| 779 // note: live_in has to be computed only in first iteration or if live_out has changed! | |
| 780 BitMap live_in = block->live_in(); | |
| 781 live_in.set_from(block->live_out()); | |
| 782 live_in.set_difference(block->live_kill()); | |
| 783 live_in.set_union(block->live_gen()); | |
| 784 } | |
| 785 | |
| 786 #ifndef PRODUCT | |
| 787 if (TraceLinearScanLevel >= 4) { | |
| 788 char c = ' '; | |
| 789 if (iteration_count == 0 || change_occurred_in_block) { | |
| 790 c = '*'; | |
| 791 } | |
| 792 tty->print("(%d) live_in%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_in()); | |
| 793 tty->print("(%d) live_out%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_out()); | |
| 794 } | |
| 795 #endif | |
| 796 } | |
| 797 iteration_count++; | |
| 798 | |
| 799 if (change_occurred && iteration_count > 50) { | |
| 800 BAILOUT("too many iterations in compute_global_live_sets"); | |
| 801 } | |
| 802 } while (change_occurred); | |
| 803 | |
| 804 | |
| 805 #ifdef ASSERT | |
| 806 // check that fixed intervals are not live at block boundaries | |
| 807 // (live set must be empty at fixed intervals) | |
| 808 for (int i = 0; i < num_blocks; i++) { | |
| 809 BlockBegin* block = block_at(i); | |
| 810 for (int j = 0; j < LIR_OprDesc::vreg_base; j++) { | |
| 811 assert(block->live_in().at(j) == false, "live_in set of fixed register must be empty"); | |
| 812 assert(block->live_out().at(j) == false, "live_out set of fixed register must be empty"); | |
| 813 assert(block->live_gen().at(j) == false, "live_gen set of fixed register must be empty"); | |
| 814 } | |
| 815 } | |
| 816 #endif | |
| 817 | |
| 818 // check that the live_in set of the first block is empty | |
| 819 BitMap live_in_args(ir()->start()->live_in().size()); | |
| 820 live_in_args.clear(); | |
| 821 if (!ir()->start()->live_in().is_same(live_in_args)) { | |
| 822 #ifdef ASSERT | |
| 823 tty->print_cr("Error: live_in set of first block must be empty (when this fails, virtual registers are used before they are defined)"); | |
| 824 tty->print_cr("affected registers:"); | |
| 825 print_bitmap(ir()->start()->live_in()); | |
| 826 | |
| 827 // print some additional information to simplify debugging | |
| 828 for (unsigned int i = 0; i < ir()->start()->live_in().size(); i++) { | |
| 829 if (ir()->start()->live_in().at(i)) { | |
| 830 Instruction* instr = gen()->instruction_for_vreg(i); | |
| 831 tty->print_cr("* vreg %d (HIR instruction %c%d)", i, instr == NULL ? ' ' : instr->type()->tchar(), instr == NULL ? 0 : instr->id()); | |
| 832 | |
| 833 for (int j = 0; j < num_blocks; j++) { | |
| 834 BlockBegin* block = block_at(j); | |
| 835 if (block->live_gen().at(i)) { | |
| 836 tty->print_cr(" used in block B%d", block->block_id()); | |
| 837 } | |
| 838 if (block->live_kill().at(i)) { | |
| 839 tty->print_cr(" defined in block B%d", block->block_id()); | |
| 840 } | |
| 841 } | |
| 842 } | |
| 843 } | |
| 844 | |
| 845 #endif | |
| 846 // when this fails, virtual registers are used before they are defined. | |
| 847 assert(false, "live_in set of first block must be empty"); | |
| 848 // bailout of if this occurs in product mode. | |
| 849 bailout("live_in set of first block not empty"); | |
| 850 } | |
| 851 } | |
| 852 | |
| 853 | |
| 854 // ********** Phase 4: build intervals | |
| 855 // (fills the list _intervals) | |
| 856 | |
| 857 void LinearScan::add_use(Value value, int from, int to, IntervalUseKind use_kind) { | |
| 858 assert(!value->type()->is_illegal(), "if this value is used by the interpreter it shouldn't be of indeterminate type"); | |
| 859 LIR_Opr opr = value->operand(); | |
| 860 Constant* con = value->as_Constant(); | |
| 861 | |
| 862 if ((con == NULL || con->is_pinned()) && opr->is_register()) { | |
| 863 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); | |
| 864 add_use(opr, from, to, use_kind); | |
| 865 } | |
| 866 } | |
| 867 | |
| 868 | |
| 869 void LinearScan::add_def(LIR_Opr opr, int def_pos, IntervalUseKind use_kind) { | |
| 870 TRACE_LINEAR_SCAN(2, tty->print(" def "); opr->print(tty); tty->print_cr(" def_pos %d (%d)", def_pos, use_kind)); | |
| 871 assert(opr->is_register(), "should not be called otherwise"); | |
| 872 | |
| 873 if (opr->is_virtual_register()) { | |
| 874 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); | |
| 875 add_def(opr->vreg_number(), def_pos, use_kind, opr->type_register()); | |
| 876 | |
| 877 } else { | |
| 878 int reg = reg_num(opr); | |
| 879 if (is_processed_reg_num(reg)) { | |
| 880 add_def(reg, def_pos, use_kind, opr->type_register()); | |
| 881 } | |
| 882 reg = reg_numHi(opr); | |
| 883 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { | |
| 884 add_def(reg, def_pos, use_kind, opr->type_register()); | |
| 885 } | |
| 886 } | |
| 887 } | |
| 888 | |
| 889 void LinearScan::add_use(LIR_Opr opr, int from, int to, IntervalUseKind use_kind) { | |
| 890 TRACE_LINEAR_SCAN(2, tty->print(" use "); opr->print(tty); tty->print_cr(" from %d to %d (%d)", from, to, use_kind)); | |
| 891 assert(opr->is_register(), "should not be called otherwise"); | |
| 892 | |
| 893 if (opr->is_virtual_register()) { | |
| 894 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); | |
| 895 add_use(opr->vreg_number(), from, to, use_kind, opr->type_register()); | |
| 896 | |
| 897 } else { | |
| 898 int reg = reg_num(opr); | |
| 899 if (is_processed_reg_num(reg)) { | |
| 900 add_use(reg, from, to, use_kind, opr->type_register()); | |
| 901 } | |
| 902 reg = reg_numHi(opr); | |
| 903 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { | |
| 904 add_use(reg, from, to, use_kind, opr->type_register()); | |
| 905 } | |
| 906 } | |
| 907 } | |
| 908 | |
| 909 void LinearScan::add_temp(LIR_Opr opr, int temp_pos, IntervalUseKind use_kind) { | |
| 910 TRACE_LINEAR_SCAN(2, tty->print(" temp "); opr->print(tty); tty->print_cr(" temp_pos %d (%d)", temp_pos, use_kind)); | |
| 911 assert(opr->is_register(), "should not be called otherwise"); | |
| 912 | |
| 913 if (opr->is_virtual_register()) { | |
| 914 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); | |
| 915 add_temp(opr->vreg_number(), temp_pos, use_kind, opr->type_register()); | |
| 916 | |
| 917 } else { | |
| 918 int reg = reg_num(opr); | |
| 919 if (is_processed_reg_num(reg)) { | |
| 920 add_temp(reg, temp_pos, use_kind, opr->type_register()); | |
| 921 } | |
| 922 reg = reg_numHi(opr); | |
| 923 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { | |
| 924 add_temp(reg, temp_pos, use_kind, opr->type_register()); | |
| 925 } | |
| 926 } | |
| 927 } | |
| 928 | |
| 929 | |
| 930 void LinearScan::add_def(int reg_num, int def_pos, IntervalUseKind use_kind, BasicType type) { | |
| 931 Interval* interval = interval_at(reg_num); | |
| 932 if (interval != NULL) { | |
| 933 assert(interval->reg_num() == reg_num, "wrong interval"); | |
| 934 | |
| 935 if (type != T_ILLEGAL) { | |
| 936 interval->set_type(type); | |
| 937 } | |
| 938 | |
| 939 Range* r = interval->first(); | |
| 940 if (r->from() <= def_pos) { | |
| 941 // Update the starting point (when a range is first created for a use, its | |
| 942 // start is the beginning of the current block until a def is encountered.) | |
| 943 r->set_from(def_pos); | |
| 944 interval->add_use_pos(def_pos, use_kind); | |
| 945 | |
| 946 } else { | |
| 947 // Dead value - make vacuous interval | |
| 948 // also add use_kind for dead intervals | |
| 949 interval->add_range(def_pos, def_pos + 1); | |
| 950 interval->add_use_pos(def_pos, use_kind); | |
| 951 TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: def of reg %d at %d occurs without use", reg_num, def_pos)); | |
| 952 } | |
| 953 | |
| 954 } else { | |
| 955 // Dead value - make vacuous interval | |
| 956 // also add use_kind for dead intervals | |
| 957 interval = create_interval(reg_num); | |
| 958 if (type != T_ILLEGAL) { | |
| 959 interval->set_type(type); | |
| 960 } | |
| 961 | |
| 962 interval->add_range(def_pos, def_pos + 1); | |
| 963 interval->add_use_pos(def_pos, use_kind); | |
| 964 TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: dead value %d at %d in live intervals", reg_num, def_pos)); | |
| 965 } | |
| 966 | |
| 967 change_spill_definition_pos(interval, def_pos); | |
| 968 if (use_kind == noUse && interval->spill_state() <= startInMemory) { | |
| 969 // detection of method-parameters and roundfp-results | |
| 970 // TODO: move this directly to position where use-kind is computed | |
| 971 interval->set_spill_state(startInMemory); | |
| 972 } | |
| 973 } | |
| 974 | |
| 975 void LinearScan::add_use(int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type) { | |
| 976 Interval* interval = interval_at(reg_num); | |
| 977 if (interval == NULL) { | |
| 978 interval = create_interval(reg_num); | |
| 979 } | |
| 980 assert(interval->reg_num() == reg_num, "wrong interval"); | |
| 981 | |
| 982 if (type != T_ILLEGAL) { | |
| 983 interval->set_type(type); | |
| 984 } | |
| 985 | |
| 986 interval->add_range(from, to); | |
| 987 interval->add_use_pos(to, use_kind); | |
| 988 } | |
| 989 | |
| 990 void LinearScan::add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type) { | |
| 991 Interval* interval = interval_at(reg_num); | |
| 992 if (interval == NULL) { | |
| 993 interval = create_interval(reg_num); | |
| 994 } | |
| 995 assert(interval->reg_num() == reg_num, "wrong interval"); | |
| 996 | |
| 997 if (type != T_ILLEGAL) { | |
| 998 interval->set_type(type); | |
| 999 } | |
| 1000 | |
| 1001 interval->add_range(temp_pos, temp_pos + 1); | |
| 1002 interval->add_use_pos(temp_pos, use_kind); | |
| 1003 } | |
| 1004 | |
| 1005 | |
| 1006 // the results of this functions are used for optimizing spilling and reloading | |
| 1007 // if the functions return shouldHaveRegister and the interval is spilled, | |
| 1008 // it is not reloaded to a register. | |
| 1009 IntervalUseKind LinearScan::use_kind_of_output_operand(LIR_Op* op, LIR_Opr opr) { | |
| 1010 if (op->code() == lir_move) { | |
| 1011 assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1"); | |
| 1012 LIR_Op1* move = (LIR_Op1*)op; | |
| 1013 LIR_Opr res = move->result_opr(); | |
| 1014 bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory); | |
| 1015 | |
| 1016 if (result_in_memory) { | |
| 1017 // Begin of an interval with must_start_in_memory set. | |
| 1018 // This interval will always get a stack slot first, so return noUse. | |
| 1019 return noUse; | |
| 1020 | |
| 1021 } else if (move->in_opr()->is_stack()) { | |
| 1022 // method argument (condition must be equal to handle_method_arguments) | |
| 1023 return noUse; | |
| 1024 | |
| 1025 } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) { | |
| 1026 // Move from register to register | |
| 1027 if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) { | |
| 1028 // special handling of phi-function moves inside osr-entry blocks | |
| 1029 // input operand must have a register instead of output operand (leads to better register allocation) | |
| 1030 return shouldHaveRegister; | |
| 1031 } | |
| 1032 } | |
| 1033 } | |
| 1034 | |
| 1035 if (opr->is_virtual() && | |
| 1036 gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::must_start_in_memory)) { | |
| 1037 // result is a stack-slot, so prevent immediate reloading | |
| 1038 return noUse; | |
| 1039 } | |
| 1040 | |
| 1041 // all other operands require a register | |
| 1042 return mustHaveRegister; | |
| 1043 } | |
| 1044 | |
| 1045 IntervalUseKind LinearScan::use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr) { | |
| 1046 if (op->code() == lir_move) { | |
| 1047 assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1"); | |
| 1048 LIR_Op1* move = (LIR_Op1*)op; | |
| 1049 LIR_Opr res = move->result_opr(); | |
| 1050 bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory); | |
| 1051 | |
| 1052 if (result_in_memory) { | |
| 1053 // Move to an interval with must_start_in_memory set. | |
| 1054 // To avoid moves from stack to stack (not allowed) force the input operand to a register | |
| 1055 return mustHaveRegister; | |
| 1056 | |
| 1057 } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) { | |
| 1058 // Move from register to register | |
| 1059 if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) { | |
| 1060 // special handling of phi-function moves inside osr-entry blocks | |
| 1061 // input operand must have a register instead of output operand (leads to better register allocation) | |
| 1062 return mustHaveRegister; | |
| 1063 } | |
| 1064 | |
| 1065 // The input operand is not forced to a register (moves from stack to register are allowed), | |
| 1066 // but it is faster if the input operand is in a register | |
| 1067 return shouldHaveRegister; | |
| 1068 } | |
| 1069 } | |
| 1070 | |
| 1071 | |
| 304 | 1072 #ifdef X86 |
| 0 | 1073 if (op->code() == lir_cmove) { |
| 1074 // conditional moves can handle stack operands | |
| 1075 assert(op->result_opr()->is_register(), "result must always be in a register"); | |
| 1076 return shouldHaveRegister; | |
| 1077 } | |
| 1078 | |
| 1079 // optimizations for second input operand of arithmehtic operations on Intel | |
| 1080 // this operand is allowed to be on the stack in some cases | |
| 1081 BasicType opr_type = opr->type_register(); | |
| 1082 if (opr_type == T_FLOAT || opr_type == T_DOUBLE) { | |
| 1083 if ((UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2) { | |
| 1084 // SSE float instruction (T_DOUBLE only supported with SSE2) | |
| 1085 switch (op->code()) { | |
| 1086 case lir_cmp: | |
| 1087 case lir_add: | |
| 1088 case lir_sub: | |
| 1089 case lir_mul: | |
| 1090 case lir_div: | |
| 1091 { | |
| 1092 assert(op->as_Op2() != NULL, "must be LIR_Op2"); | |
| 1093 LIR_Op2* op2 = (LIR_Op2*)op; | |
| 1094 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) { | |
| 1095 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register"); | |
| 1096 return shouldHaveRegister; | |
| 1097 } | |
| 1098 } | |
| 1099 } | |
| 1100 } else { | |
| 1101 // FPU stack float instruction | |
| 1102 switch (op->code()) { | |
| 1103 case lir_add: | |
| 1104 case lir_sub: | |
| 1105 case lir_mul: | |
| 1106 case lir_div: | |
| 1107 { | |
| 1108 assert(op->as_Op2() != NULL, "must be LIR_Op2"); | |
| 1109 LIR_Op2* op2 = (LIR_Op2*)op; | |
| 1110 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) { | |
| 1111 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register"); | |
| 1112 return shouldHaveRegister; | |
| 1113 } | |
| 1114 } | |
| 1115 } | |
| 1116 } | |
| 1117 | |
| 1118 } else if (opr_type != T_LONG) { | |
| 1119 // integer instruction (note: long operands must always be in register) | |
| 1120 switch (op->code()) { | |
| 1121 case lir_cmp: | |
| 1122 case lir_add: | |
| 1123 case lir_sub: | |
| 1124 case lir_logic_and: | |
| 1125 case lir_logic_or: | |
| 1126 case lir_logic_xor: | |
| 1127 { | |
| 1128 assert(op->as_Op2() != NULL, "must be LIR_Op2"); | |
| 1129 LIR_Op2* op2 = (LIR_Op2*)op; | |
| 1130 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) { | |
| 1131 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register"); | |
| 1132 return shouldHaveRegister; | |
| 1133 } | |
| 1134 } | |
| 1135 } | |
| 1136 } | |
| 304 | 1137 #endif // X86 |
| 0 | 1138 |
| 1139 // all other operands require a register | |
| 1140 return mustHaveRegister; | |
| 1141 } | |
| 1142 | |
| 1143 | |
| 1144 void LinearScan::handle_method_arguments(LIR_Op* op) { | |
| 1145 // special handling for method arguments (moves from stack to virtual register): | |
| 1146 // the interval gets no register assigned, but the stack slot. | |
| 1147 // it is split before the first use by the register allocator. | |
| 1148 | |
| 1149 if (op->code() == lir_move) { | |
| 1150 assert(op->as_Op1() != NULL, "must be LIR_Op1"); | |
| 1151 LIR_Op1* move = (LIR_Op1*)op; | |
| 1152 | |
| 1153 if (move->in_opr()->is_stack()) { | |
| 1154 #ifdef ASSERT | |
| 1155 int arg_size = compilation()->method()->arg_size(); | |
| 1156 LIR_Opr o = move->in_opr(); | |
| 1157 if (o->is_single_stack()) { | |
| 1158 assert(o->single_stack_ix() >= 0 && o->single_stack_ix() < arg_size, "out of range"); | |
| 1159 } else if (o->is_double_stack()) { | |
| 1160 assert(o->double_stack_ix() >= 0 && o->double_stack_ix() < arg_size, "out of range"); | |
| 1161 } else { | |
| 1162 ShouldNotReachHere(); | |
| 1163 } | |
| 1164 | |
| 1165 assert(move->id() > 0, "invalid id"); | |
| 1166 assert(block_of_op_with_id(move->id())->number_of_preds() == 0, "move from stack must be in first block"); | |
| 1167 assert(move->result_opr()->is_virtual(), "result of move must be a virtual register"); | |
| 1168 | |
| 1169 TRACE_LINEAR_SCAN(4, tty->print_cr("found move from stack slot %d to vreg %d", o->is_single_stack() ? o->single_stack_ix() : o->double_stack_ix(), reg_num(move->result_opr()))); | |
| 1170 #endif | |
| 1171 | |
| 1172 Interval* interval = interval_at(reg_num(move->result_opr())); | |
| 1173 | |
| 1174 int stack_slot = LinearScan::nof_regs + (move->in_opr()->is_single_stack() ? move->in_opr()->single_stack_ix() : move->in_opr()->double_stack_ix()); | |
| 1175 interval->set_canonical_spill_slot(stack_slot); | |
| 1176 interval->assign_reg(stack_slot); | |
| 1177 } | |
| 1178 } | |
| 1179 } | |
| 1180 | |
| 1181 void LinearScan::handle_doubleword_moves(LIR_Op* op) { | |
| 1182 // special handling for doubleword move from memory to register: | |
| 1183 // in this case the registers of the input address and the result | |
| 1184 // registers must not overlap -> add a temp range for the input registers | |
| 1185 if (op->code() == lir_move) { | |
| 1186 assert(op->as_Op1() != NULL, "must be LIR_Op1"); | |
| 1187 LIR_Op1* move = (LIR_Op1*)op; | |
| 1188 | |
| 1189 if (move->result_opr()->is_double_cpu() && move->in_opr()->is_pointer()) { | |
| 1190 LIR_Address* address = move->in_opr()->as_address_ptr(); | |
| 1191 if (address != NULL) { | |
| 1192 if (address->base()->is_valid()) { | |
| 1193 add_temp(address->base(), op->id(), noUse); | |
| 1194 } | |
| 1195 if (address->index()->is_valid()) { | |
| 1196 add_temp(address->index(), op->id(), noUse); | |
| 1197 } | |
| 1198 } | |
| 1199 } | |
| 1200 } | |
| 1201 } | |
| 1202 | |
| 1203 void LinearScan::add_register_hints(LIR_Op* op) { | |
| 1204 switch (op->code()) { | |
| 1205 case lir_move: // fall through | |
| 1206 case lir_convert: { | |
| 1207 assert(op->as_Op1() != NULL, "lir_move, lir_convert must be LIR_Op1"); | |
| 1208 LIR_Op1* move = (LIR_Op1*)op; | |
| 1209 | |
| 1210 LIR_Opr move_from = move->in_opr(); | |
| 1211 LIR_Opr move_to = move->result_opr(); | |
| 1212 | |
| 1213 if (move_to->is_register() && move_from->is_register()) { | |
| 1214 Interval* from = interval_at(reg_num(move_from)); | |
| 1215 Interval* to = interval_at(reg_num(move_to)); | |
| 1216 if (from != NULL && to != NULL) { | |
| 1217 to->set_register_hint(from); | |
| 1218 TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", move->id(), from->reg_num(), to->reg_num())); | |
| 1219 } | |
| 1220 } | |
| 1221 break; | |
| 1222 } | |
| 1223 case lir_cmove: { | |
| 1224 assert(op->as_Op2() != NULL, "lir_cmove must be LIR_Op2"); | |
| 1225 LIR_Op2* cmove = (LIR_Op2*)op; | |
| 1226 | |
| 1227 LIR_Opr move_from = cmove->in_opr1(); | |
| 1228 LIR_Opr move_to = cmove->result_opr(); | |
| 1229 | |
| 1230 if (move_to->is_register() && move_from->is_register()) { | |
| 1231 Interval* from = interval_at(reg_num(move_from)); | |
| 1232 Interval* to = interval_at(reg_num(move_to)); | |
| 1233 if (from != NULL && to != NULL) { | |
| 1234 to->set_register_hint(from); | |
| 1235 TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num())); | |
| 1236 } | |
| 1237 } | |
| 1238 break; | |
| 1239 } | |
| 1240 } | |
| 1241 } | |
| 1242 | |
| 1243 | |
| 1244 void LinearScan::build_intervals() { | |
| 1245 TIME_LINEAR_SCAN(timer_build_intervals); | |
| 1246 | |
| 1247 // initialize interval list with expected number of intervals | |
| 1248 // (32 is added to have some space for split children without having to resize the list) | |
| 1249 _intervals = IntervalList(num_virtual_regs() + 32); | |
| 1250 // initialize all slots that are used by build_intervals | |
| 1251 _intervals.at_put_grow(num_virtual_regs() - 1, NULL, NULL); | |
| 1252 | |
| 1253 // create a list with all caller-save registers (cpu, fpu, xmm) | |
| 1254 // when an instruction is a call, a temp range is created for all these registers | |
| 1255 int num_caller_save_registers = 0; | |
| 1256 int caller_save_registers[LinearScan::nof_regs]; | |
| 1257 | |
| 1258 int i; | |
| 1259 for (i = 0; i < FrameMap::nof_caller_save_cpu_regs; i++) { | |
| 1260 LIR_Opr opr = FrameMap::caller_save_cpu_reg_at(i); | |
| 1261 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands"); | |
| 1262 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register"); | |
| 1263 caller_save_registers[num_caller_save_registers++] = reg_num(opr); | |
| 1264 } | |
| 1265 | |
| 1266 // temp ranges for fpu registers are only created when the method has | |
| 1267 // virtual fpu operands. Otherwise no allocation for fpu registers is | |
| 1268 // perfomed and so the temp ranges would be useless | |
| 1269 if (has_fpu_registers()) { | |
| 304 | 1270 #ifdef X86 |
| 0 | 1271 if (UseSSE < 2) { |
| 1272 #endif | |
| 1273 for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) { | |
| 1274 LIR_Opr opr = FrameMap::caller_save_fpu_reg_at(i); | |
| 1275 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands"); | |
| 1276 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register"); | |
| 1277 caller_save_registers[num_caller_save_registers++] = reg_num(opr); | |
| 1278 } | |
| 304 | 1279 #ifdef X86 |
| 0 | 1280 } |
| 1281 if (UseSSE > 0) { | |
| 1282 for (i = 0; i < FrameMap::nof_caller_save_xmm_regs; i++) { | |
| 1283 LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(i); | |
| 1284 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands"); | |
| 1285 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register"); | |
| 1286 caller_save_registers[num_caller_save_registers++] = reg_num(opr); | |
| 1287 } | |
| 1288 } | |
| 1289 #endif | |
| 1290 } | |
| 1291 assert(num_caller_save_registers <= LinearScan::nof_regs, "out of bounds"); | |
| 1292 | |
| 1293 | |
| 1294 LIR_OpVisitState visitor; | |
| 1295 | |
| 1296 // iterate all blocks in reverse order | |
| 1297 for (i = block_count() - 1; i >= 0; i--) { | |
| 1298 BlockBegin* block = block_at(i); | |
| 1299 LIR_OpList* instructions = block->lir()->instructions_list(); | |
| 1300 int block_from = block->first_lir_instruction_id(); | |
| 1301 int block_to = block->last_lir_instruction_id(); | |
| 1302 | |
| 1303 assert(block_from == instructions->at(0)->id(), "must be"); | |
| 1304 assert(block_to == instructions->at(instructions->length() - 1)->id(), "must be"); | |
| 1305 | |
| 1306 // Update intervals for registers live at the end of this block; | |
| 1307 BitMap live = block->live_out(); | |
| 304 | 1308 int size = (int)live.size(); |
| 1309 for (int number = (int)live.get_next_one_offset(0, size); number < size; number = (int)live.get_next_one_offset(number + 1, size)) { | |
| 0 | 1310 assert(live.at(number), "should not stop here otherwise"); |
| 1311 assert(number >= LIR_OprDesc::vreg_base, "fixed intervals must not be live on block bounds"); | |
| 1312 TRACE_LINEAR_SCAN(2, tty->print_cr("live in %d to %d", number, block_to + 2)); | |
| 1313 | |
| 1314 add_use(number, block_from, block_to + 2, noUse, T_ILLEGAL); | |
| 1315 | |
| 1316 // add special use positions for loop-end blocks when the | |
| 1317 // interval is used anywhere inside this loop. It's possible | |
| 1318 // that the block was part of a non-natural loop, so it might | |
| 1319 // have an invalid loop index. | |
| 1320 if (block->is_set(BlockBegin::linear_scan_loop_end_flag) && | |
| 1321 block->loop_index() != -1 && | |
| 1322 is_interval_in_loop(number, block->loop_index())) { | |
| 1323 interval_at(number)->add_use_pos(block_to + 1, loopEndMarker); | |
| 1324 } | |
| 1325 } | |
| 1326 | |
| 1327 // iterate all instructions of the block in reverse order. | |
| 1328 // skip the first instruction because it is always a label | |
| 1329 // definitions of intervals are processed before uses | |
| 1330 assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label"); | |
| 1331 for (int j = instructions->length() - 1; j >= 1; j--) { | |
| 1332 LIR_Op* op = instructions->at(j); | |
| 1333 int op_id = op->id(); | |
| 1334 | |
| 1335 // visit operation to collect all operands | |
| 1336 visitor.visit(op); | |
| 1337 | |
| 1338 // add a temp range for each register if operation destroys caller-save registers | |
| 1339 if (visitor.has_call()) { | |
| 1340 for (int k = 0; k < num_caller_save_registers; k++) { | |
| 1341 add_temp(caller_save_registers[k], op_id, noUse, T_ILLEGAL); | |
| 1342 } | |
| 1343 TRACE_LINEAR_SCAN(4, tty->print_cr("operation destroys all caller-save registers")); | |
| 1344 } | |
| 1345 | |
| 1346 // Add any platform dependent temps | |
| 1347 pd_add_temps(op); | |
| 1348 | |
| 1349 // visit definitions (output and temp operands) | |
| 1350 int k, n; | |
| 1351 n = visitor.opr_count(LIR_OpVisitState::outputMode); | |
| 1352 for (k = 0; k < n; k++) { | |
| 1353 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k); | |
| 1354 assert(opr->is_register(), "visitor should only return register operands"); | |
| 1355 add_def(opr, op_id, use_kind_of_output_operand(op, opr)); | |
| 1356 } | |
| 1357 | |
| 1358 n = visitor.opr_count(LIR_OpVisitState::tempMode); | |
| 1359 for (k = 0; k < n; k++) { | |
| 1360 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k); | |
| 1361 assert(opr->is_register(), "visitor should only return register operands"); | |
| 1362 add_temp(opr, op_id, mustHaveRegister); | |
| 1363 } | |
| 1364 | |
| 1365 // visit uses (input operands) | |
| 1366 n = visitor.opr_count(LIR_OpVisitState::inputMode); | |
| 1367 for (k = 0; k < n; k++) { | |
| 1368 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k); | |
| 1369 assert(opr->is_register(), "visitor should only return register operands"); | |
| 1370 add_use(opr, block_from, op_id, use_kind_of_input_operand(op, opr)); | |
| 1371 } | |
| 1372 | |
| 1373 // Add uses of live locals from interpreter's point of view for proper | |
| 1374 // debug information generation | |
| 1375 // Treat these operands as temp values (if the life range is extended | |
| 1376 // to a call site, the value would be in a register at the call otherwise) | |
| 1377 n = visitor.info_count(); | |
| 1378 for (k = 0; k < n; k++) { | |
| 1379 CodeEmitInfo* info = visitor.info_at(k); | |
| 1380 ValueStack* stack = info->stack(); | |
| 1381 for_each_state_value(stack, value, | |
| 1382 add_use(value, block_from, op_id + 1, noUse); | |
| 1383 ); | |
| 1384 } | |
| 1385 | |
| 1386 // special steps for some instructions (especially moves) | |
| 1387 handle_method_arguments(op); | |
| 1388 handle_doubleword_moves(op); | |
| 1389 add_register_hints(op); | |
| 1390 | |
| 1391 } // end of instruction iteration | |
| 1392 } // end of block iteration | |
| 1393 | |
| 1394 | |
| 1395 // add the range [0, 1[ to all fixed intervals | |
| 1396 // -> the register allocator need not handle unhandled fixed intervals | |
| 1397 for (int n = 0; n < LinearScan::nof_regs; n++) { | |
| 1398 Interval* interval = interval_at(n); | |
| 1399 if (interval != NULL) { | |
| 1400 interval->add_range(0, 1); | |
| 1401 } | |
| 1402 } | |
| 1403 } | |
| 1404 | |
| 1405 | |
| 1406 // ********** Phase 5: actual register allocation | |
| 1407 | |
| 1408 int LinearScan::interval_cmp(Interval** a, Interval** b) { | |
| 1409 if (*a != NULL) { | |
| 1410 if (*b != NULL) { | |
| 1411 return (*a)->from() - (*b)->from(); | |
| 1412 } else { | |
| 1413 return -1; | |
| 1414 } | |
| 1415 } else { | |
| 1416 if (*b != NULL) { | |
| 1417 return 1; | |
| 1418 } else { | |
| 1419 return 0; | |
| 1420 } | |
| 1421 } | |
| 1422 } | |
| 1423 | |
| 1424 #ifndef PRODUCT | |
| 1425 bool LinearScan::is_sorted(IntervalArray* intervals) { | |
| 1426 int from = -1; | |
| 1427 int i, j; | |
| 1428 for (i = 0; i < intervals->length(); i ++) { | |
| 1429 Interval* it = intervals->at(i); | |
| 1430 if (it != NULL) { | |
| 1431 if (from > it->from()) { | |
| 1432 assert(false, ""); | |
| 1433 return false; | |
| 1434 } | |
| 1435 from = it->from(); | |
| 1436 } | |
| 1437 } | |
| 1438 | |
| 1439 // check in both directions if sorted list and unsorted list contain same intervals | |
| 1440 for (i = 0; i < interval_count(); i++) { | |
| 1441 if (interval_at(i) != NULL) { | |
| 1442 int num_found = 0; | |
| 1443 for (j = 0; j < intervals->length(); j++) { | |
| 1444 if (interval_at(i) == intervals->at(j)) { | |
| 1445 num_found++; | |
| 1446 } | |
| 1447 } | |
| 1448 assert(num_found == 1, "lists do not contain same intervals"); | |
| 1449 } | |
| 1450 } | |
| 1451 for (j = 0; j < intervals->length(); j++) { | |
| 1452 int num_found = 0; | |
| 1453 for (i = 0; i < interval_count(); i++) { | |
| 1454 if (interval_at(i) == intervals->at(j)) { | |
| 1455 num_found++; | |
| 1456 } | |
| 1457 } | |
| 1458 assert(num_found == 1, "lists do not contain same intervals"); | |
| 1459 } | |
| 1460 | |
| 1461 return true; | |
| 1462 } | |
| 1463 #endif | |
| 1464 | |
| 1465 void LinearScan::add_to_list(Interval** first, Interval** prev, Interval* interval) { | |
| 1466 if (*prev != NULL) { | |
| 1467 (*prev)->set_next(interval); | |
| 1468 } else { | |
| 1469 *first = interval; | |
| 1470 } | |
| 1471 *prev = interval; | |
| 1472 } | |
| 1473 | |
| 1474 void LinearScan::create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)) { | |
| 1475 assert(is_sorted(_sorted_intervals), "interval list is not sorted"); | |
| 1476 | |
| 1477 *list1 = *list2 = Interval::end(); | |
| 1478 | |
| 1479 Interval* list1_prev = NULL; | |
| 1480 Interval* list2_prev = NULL; | |
| 1481 Interval* v; | |
| 1482 | |
| 1483 const int n = _sorted_intervals->length(); | |
| 1484 for (int i = 0; i < n; i++) { | |
| 1485 v = _sorted_intervals->at(i); | |
| 1486 if (v == NULL) continue; | |
| 1487 | |
| 1488 if (is_list1(v)) { | |
| 1489 add_to_list(list1, &list1_prev, v); | |
| 1490 } else if (is_list2 == NULL || is_list2(v)) { | |
| 1491 add_to_list(list2, &list2_prev, v); | |
| 1492 } | |
| 1493 } | |
| 1494 | |
| 1495 if (list1_prev != NULL) list1_prev->set_next(Interval::end()); | |
| 1496 if (list2_prev != NULL) list2_prev->set_next(Interval::end()); | |
| 1497 | |
| 1498 assert(list1_prev == NULL || list1_prev->next() == Interval::end(), "linear list ends not with sentinel"); | |
| 1499 assert(list2_prev == NULL || list2_prev->next() == Interval::end(), "linear list ends not with sentinel"); | |
| 1500 } | |
| 1501 | |
| 1502 | |
| 1503 void LinearScan::sort_intervals_before_allocation() { | |
| 1504 TIME_LINEAR_SCAN(timer_sort_intervals_before); | |
| 1505 | |
| 1506 IntervalList* unsorted_list = &_intervals; | |
| 1507 int unsorted_len = unsorted_list->length(); | |
| 1508 int sorted_len = 0; | |
| 1509 int unsorted_idx; | |
| 1510 int sorted_idx = 0; | |
| 1511 int sorted_from_max = -1; | |
| 1512 | |
| 1513 // calc number of items for sorted list (sorted list must not contain NULL values) | |
| 1514 for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) { | |
| 1515 if (unsorted_list->at(unsorted_idx) != NULL) { | |
| 1516 sorted_len++; | |
| 1517 } | |
| 1518 } | |
| 1519 IntervalArray* sorted_list = new IntervalArray(sorted_len); | |
| 1520 | |
| 1521 // special sorting algorithm: the original interval-list is almost sorted, | |
| 1522 // only some intervals are swapped. So this is much faster than a complete QuickSort | |
| 1523 for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) { | |
| 1524 Interval* cur_interval = unsorted_list->at(unsorted_idx); | |
| 1525 | |
| 1526 if (cur_interval != NULL) { | |
| 1527 int cur_from = cur_interval->from(); | |
| 1528 | |
| 1529 if (sorted_from_max <= cur_from) { | |
| 1530 sorted_list->at_put(sorted_idx++, cur_interval); | |
| 1531 sorted_from_max = cur_interval->from(); | |
| 1532 } else { | |
| 1533 // the asumption that the intervals are already sorted failed, | |
| 1534 // so this interval must be sorted in manually | |
| 1535 int j; | |
| 1536 for (j = sorted_idx - 1; j >= 0 && cur_from < sorted_list->at(j)->from(); j--) { | |
| 1537 sorted_list->at_put(j + 1, sorted_list->at(j)); | |
| 1538 } | |
| 1539 sorted_list->at_put(j + 1, cur_interval); | |
| 1540 sorted_idx++; | |
| 1541 } | |
| 1542 } | |
| 1543 } | |
| 1544 _sorted_intervals = sorted_list; | |
| 1545 } | |
| 1546 | |
| 1547 void LinearScan::sort_intervals_after_allocation() { | |
| 1548 TIME_LINEAR_SCAN(timer_sort_intervals_after); | |
| 1549 | |
| 1550 IntervalArray* old_list = _sorted_intervals; | |
| 1551 IntervalList* new_list = _new_intervals_from_allocation; | |
| 1552 int old_len = old_list->length(); | |
| 1553 int new_len = new_list->length(); | |
| 1554 | |
| 1555 if (new_len == 0) { | |
| 1556 // no intervals have been added during allocation, so sorted list is already up to date | |
| 1557 return; | |
| 1558 } | |
| 1559 | |
| 1560 // conventional sort-algorithm for new intervals | |
| 1561 new_list->sort(interval_cmp); | |
| 1562 | |
| 1563 // merge old and new list (both already sorted) into one combined list | |
| 1564 IntervalArray* combined_list = new IntervalArray(old_len + new_len); | |
| 1565 int old_idx = 0; | |
| 1566 int new_idx = 0; | |
| 1567 | |
| 1568 while (old_idx + new_idx < old_len + new_len) { | |
| 1569 if (new_idx >= new_len || (old_idx < old_len && old_list->at(old_idx)->from() <= new_list->at(new_idx)->from())) { | |
| 1570 combined_list->at_put(old_idx + new_idx, old_list->at(old_idx)); | |
| 1571 old_idx++; | |
| 1572 } else { | |
| 1573 combined_list->at_put(old_idx + new_idx, new_list->at(new_idx)); | |
| 1574 new_idx++; | |
| 1575 } | |
| 1576 } | |
| 1577 | |
| 1578 _sorted_intervals = combined_list; | |
| 1579 } | |
| 1580 | |
| 1581 | |
| 1582 void LinearScan::allocate_registers() { | |
| 1583 TIME_LINEAR_SCAN(timer_allocate_registers); | |
| 1584 | |
| 1585 Interval* precolored_cpu_intervals, *not_precolored_cpu_intervals; | |
| 1586 Interval* precolored_fpu_intervals, *not_precolored_fpu_intervals; | |
| 1587 | |
| 1588 create_unhandled_lists(&precolored_cpu_intervals, ¬_precolored_cpu_intervals, is_precolored_cpu_interval, is_virtual_cpu_interval); | |
| 1589 if (has_fpu_registers()) { | |
| 1590 create_unhandled_lists(&precolored_fpu_intervals, ¬_precolored_fpu_intervals, is_precolored_fpu_interval, is_virtual_fpu_interval); | |
| 1591 #ifdef ASSERT | |
| 1592 } else { | |
| 1593 // fpu register allocation is omitted because no virtual fpu registers are present | |
| 1594 // just check this again... | |
| 1595 create_unhandled_lists(&precolored_fpu_intervals, ¬_precolored_fpu_intervals, is_precolored_fpu_interval, is_virtual_fpu_interval); | |
| 1596 assert(not_precolored_fpu_intervals == Interval::end(), "missed an uncolored fpu interval"); | |
| 1597 #endif | |
| 1598 } | |
| 1599 | |
| 1600 // allocate cpu registers | |
| 1601 LinearScanWalker cpu_lsw(this, precolored_cpu_intervals, not_precolored_cpu_intervals); | |
| 1602 cpu_lsw.walk(); | |
| 1603 cpu_lsw.finish_allocation(); | |
| 1604 | |
| 1605 if (has_fpu_registers()) { | |
| 1606 // allocate fpu registers | |
| 1607 LinearScanWalker fpu_lsw(this, precolored_fpu_intervals, not_precolored_fpu_intervals); | |
| 1608 fpu_lsw.walk(); | |
| 1609 fpu_lsw.finish_allocation(); | |
| 1610 } | |
| 1611 } | |
| 1612 | |
| 1613 | |
| 1614 // ********** Phase 6: resolve data flow | |
| 1615 // (insert moves at edges between blocks if intervals have been split) | |
| 1616 | |
| 1617 // wrapper for Interval::split_child_at_op_id that performs a bailout in product mode | |
| 1618 // instead of returning NULL | |
| 1619 Interval* LinearScan::split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode) { | |
| 1620 Interval* result = interval->split_child_at_op_id(op_id, mode); | |
| 1621 if (result != NULL) { | |
| 1622 return result; | |
| 1623 } | |
| 1624 | |
| 1625 assert(false, "must find an interval, but do a clean bailout in product mode"); | |
| 1626 result = new Interval(LIR_OprDesc::vreg_base); | |
| 1627 result->assign_reg(0); | |
| 1628 result->set_type(T_INT); | |
| 1629 BAILOUT_("LinearScan: interval is NULL", result); | |
| 1630 } | |
| 1631 | |
| 1632 | |
| 1633 Interval* LinearScan::interval_at_block_begin(BlockBegin* block, int reg_num) { | |
| 1634 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds"); | |
| 1635 assert(interval_at(reg_num) != NULL, "no interval found"); | |
| 1636 | |
| 1637 return split_child_at_op_id(interval_at(reg_num), block->first_lir_instruction_id(), LIR_OpVisitState::outputMode); | |
| 1638 } | |
| 1639 | |
| 1640 Interval* LinearScan::interval_at_block_end(BlockBegin* block, int reg_num) { | |
| 1641 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds"); | |
| 1642 assert(interval_at(reg_num) != NULL, "no interval found"); | |
| 1643 | |
| 1644 return split_child_at_op_id(interval_at(reg_num), block->last_lir_instruction_id() + 1, LIR_OpVisitState::outputMode); | |
| 1645 } | |
| 1646 | |
| 1647 Interval* LinearScan::interval_at_op_id(int reg_num, int op_id) { | |
| 1648 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds"); | |
| 1649 assert(interval_at(reg_num) != NULL, "no interval found"); | |
| 1650 | |
| 1651 return split_child_at_op_id(interval_at(reg_num), op_id, LIR_OpVisitState::inputMode); | |
| 1652 } | |
| 1653 | |
| 1654 | |
| 1655 void LinearScan::resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) { | |
| 1656 DEBUG_ONLY(move_resolver.check_empty()); | |
| 1657 | |
| 1658 const int num_regs = num_virtual_regs(); | |
| 1659 const int size = live_set_size(); | |
| 1660 const BitMap live_at_edge = to_block->live_in(); | |
| 1661 | |
| 1662 // visit all registers where the live_at_edge bit is set | |
| 304 | 1663 for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) { |
| 0 | 1664 assert(r < num_regs, "live information set for not exisiting interval"); |
| 1665 assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge"); | |
| 1666 | |
| 1667 Interval* from_interval = interval_at_block_end(from_block, r); | |
| 1668 Interval* to_interval = interval_at_block_begin(to_block, r); | |
| 1669 | |
| 1670 if (from_interval != to_interval && (from_interval->assigned_reg() != to_interval->assigned_reg() || from_interval->assigned_regHi() != to_interval->assigned_regHi())) { | |
| 1671 // need to insert move instruction | |
| 1672 move_resolver.add_mapping(from_interval, to_interval); | |
| 1673 } | |
| 1674 } | |
| 1675 } | |
| 1676 | |
| 1677 | |
| 1678 void LinearScan::resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) { | |
| 1679 if (from_block->number_of_sux() <= 1) { | |
| 1680 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at end of from_block B%d", from_block->block_id())); | |
| 1681 | |
| 1682 LIR_OpList* instructions = from_block->lir()->instructions_list(); | |
| 1683 LIR_OpBranch* branch = instructions->last()->as_OpBranch(); | |
| 1684 if (branch != NULL) { | |
| 1685 // insert moves before branch | |
| 1686 assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump"); | |
| 1687 move_resolver.set_insert_position(from_block->lir(), instructions->length() - 2); | |
| 1688 } else { | |
| 1689 move_resolver.set_insert_position(from_block->lir(), instructions->length() - 1); | |
| 1690 } | |
| 1691 | |
| 1692 } else { | |
| 1693 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at beginning of to_block B%d", to_block->block_id())); | |
| 1694 #ifdef ASSERT | |
| 1695 assert(from_block->lir()->instructions_list()->at(0)->as_OpLabel() != NULL, "block does not start with a label"); | |
| 1696 | |
| 1697 // because the number of predecessor edges matches the number of | |
| 1698 // successor edges, blocks which are reached by switch statements | |
| 1699 // may have be more than one predecessor but it will be guaranteed | |
| 1700 // that all predecessors will be the same. | |
| 1701 for (int i = 0; i < to_block->number_of_preds(); i++) { | |
| 1702 assert(from_block == to_block->pred_at(i), "all critical edges must be broken"); | |
| 1703 } | |
| 1704 #endif | |
| 1705 | |
| 1706 move_resolver.set_insert_position(to_block->lir(), 0); | |
| 1707 } | |
| 1708 } | |
| 1709 | |
| 1710 | |
| 1711 // insert necessary moves (spilling or reloading) at edges between blocks if interval has been split | |
| 1712 void LinearScan::resolve_data_flow() { | |
| 1713 TIME_LINEAR_SCAN(timer_resolve_data_flow); | |
| 1714 | |
| 1715 int num_blocks = block_count(); | |
| 1716 MoveResolver move_resolver(this); | |
| 1717 BitMap block_completed(num_blocks); block_completed.clear(); | |
| 1718 BitMap already_resolved(num_blocks); already_resolved.clear(); | |
| 1719 | |
| 1720 int i; | |
| 1721 for (i = 0; i < num_blocks; i++) { | |
| 1722 BlockBegin* block = block_at(i); | |
| 1723 | |
| 1724 // check if block has only one predecessor and only one successor | |
| 1725 if (block->number_of_preds() == 1 && block->number_of_sux() == 1 && block->number_of_exception_handlers() == 0) { | |
| 1726 LIR_OpList* instructions = block->lir()->instructions_list(); | |
| 1727 assert(instructions->at(0)->code() == lir_label, "block must start with label"); | |
| 1728 assert(instructions->last()->code() == lir_branch, "block with successors must end with branch"); | |
| 1729 assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block with successor must end with unconditional branch"); | |
| 1730 | |
| 1731 // check if block is empty (only label and branch) | |
| 1732 if (instructions->length() == 2) { | |
| 1733 BlockBegin* pred = block->pred_at(0); | |
| 1734 BlockBegin* sux = block->sux_at(0); | |
| 1735 | |
| 1736 // prevent optimization of two consecutive blocks | |
| 1737 if (!block_completed.at(pred->linear_scan_number()) && !block_completed.at(sux->linear_scan_number())) { | |
| 1738 TRACE_LINEAR_SCAN(3, tty->print_cr("**** optimizing empty block B%d (pred: B%d, sux: B%d)", block->block_id(), pred->block_id(), sux->block_id())); | |
| 1739 block_completed.set_bit(block->linear_scan_number()); | |
| 1740 | |
| 1741 // directly resolve between pred and sux (without looking at the empty block between) | |
| 1742 resolve_collect_mappings(pred, sux, move_resolver); | |
| 1743 if (move_resolver.has_mappings()) { | |
| 1744 move_resolver.set_insert_position(block->lir(), 0); | |
| 1745 move_resolver.resolve_and_append_moves(); | |
| 1746 } | |
| 1747 } | |
| 1748 } | |
| 1749 } | |
| 1750 } | |
| 1751 | |
| 1752 | |
| 1753 for (i = 0; i < num_blocks; i++) { | |
| 1754 if (!block_completed.at(i)) { | |
| 1755 BlockBegin* from_block = block_at(i); | |
| 1756 already_resolved.set_from(block_completed); | |
| 1757 | |
| 1758 int num_sux = from_block->number_of_sux(); | |
| 1759 for (int s = 0; s < num_sux; s++) { | |
| 1760 BlockBegin* to_block = from_block->sux_at(s); | |
| 1761 | |
| 1762 // check for duplicate edges between the same blocks (can happen with switch blocks) | |
| 1763 if (!already_resolved.at(to_block->linear_scan_number())) { | |
| 1764 TRACE_LINEAR_SCAN(3, tty->print_cr("**** processing edge between B%d and B%d", from_block->block_id(), to_block->block_id())); | |
| 1765 already_resolved.set_bit(to_block->linear_scan_number()); | |
| 1766 | |
| 1767 // collect all intervals that have been split between from_block and to_block | |
| 1768 resolve_collect_mappings(from_block, to_block, move_resolver); | |
| 1769 if (move_resolver.has_mappings()) { | |
| 1770 resolve_find_insert_pos(from_block, to_block, move_resolver); | |
| 1771 move_resolver.resolve_and_append_moves(); | |
| 1772 } | |
| 1773 } | |
| 1774 } | |
| 1775 } | |
| 1776 } | |
| 1777 } | |
| 1778 | |
| 1779 | |
| 1780 void LinearScan::resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver) { | |
| 1781 if (interval_at(reg_num) == NULL) { | |
| 1782 // if a phi function is never used, no interval is created -> ignore this | |
| 1783 return; | |
| 1784 } | |
| 1785 | |
| 1786 Interval* interval = interval_at_block_begin(block, reg_num); | |
| 1787 int reg = interval->assigned_reg(); | |
| 1788 int regHi = interval->assigned_regHi(); | |
| 1789 | |
| 1790 if ((reg < nof_regs && interval->always_in_memory()) || | |
| 1791 (use_fpu_stack_allocation() && reg >= pd_first_fpu_reg && reg <= pd_last_fpu_reg)) { | |
| 1792 // the interval is split to get a short range that is located on the stack | |
| 1793 // in the following two cases: | |
| 1794 // * the interval started in memory (e.g. method parameter), but is currently in a register | |
| 1795 // this is an optimization for exception handling that reduces the number of moves that | |
| 1796 // are necessary for resolving the states when an exception uses this exception handler | |
| 1797 // * the interval would be on the fpu stack at the begin of the exception handler | |
| 1798 // this is not allowed because of the complicated fpu stack handling on Intel | |
| 1799 | |
| 1800 // range that will be spilled to memory | |
| 1801 int from_op_id = block->first_lir_instruction_id(); | |
| 1802 int to_op_id = from_op_id + 1; // short live range of length 1 | |
| 1803 assert(interval->from() <= from_op_id && interval->to() >= to_op_id, | |
| 1804 "no split allowed between exception entry and first instruction"); | |
| 1805 | |
| 1806 if (interval->from() != from_op_id) { | |
| 1807 // the part before from_op_id is unchanged | |
| 1808 interval = interval->split(from_op_id); | |
| 1809 interval->assign_reg(reg, regHi); | |
| 1810 append_interval(interval); | |
| 1811 } | |
| 1812 assert(interval->from() == from_op_id, "must be true now"); | |
| 1813 | |
| 1814 Interval* spilled_part = interval; | |
| 1815 if (interval->to() != to_op_id) { | |
| 1816 // the part after to_op_id is unchanged | |
| 1817 spilled_part = interval->split_from_start(to_op_id); | |
| 1818 append_interval(spilled_part); | |
| 1819 move_resolver.add_mapping(spilled_part, interval); | |
| 1820 } | |
| 1821 assign_spill_slot(spilled_part); | |
| 1822 | |
| 1823 assert(spilled_part->from() == from_op_id && spilled_part->to() == to_op_id, "just checking"); | |
| 1824 } | |
| 1825 } | |
| 1826 | |
| 1827 void LinearScan::resolve_exception_entry(BlockBegin* block, MoveResolver &move_resolver) { | |
| 1828 assert(block->is_set(BlockBegin::exception_entry_flag), "should not call otherwise"); | |
| 1829 DEBUG_ONLY(move_resolver.check_empty()); | |
| 1830 | |
| 1831 // visit all registers where the live_in bit is set | |
| 1832 int size = live_set_size(); | |
| 304 | 1833 for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) { |
| 0 | 1834 resolve_exception_entry(block, r, move_resolver); |
| 1835 } | |
| 1836 | |
| 1837 // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately | |
| 1838 for_each_phi_fun(block, phi, | |
| 1839 resolve_exception_entry(block, phi->operand()->vreg_number(), move_resolver) | |
| 1840 ); | |
| 1841 | |
| 1842 if (move_resolver.has_mappings()) { | |
| 1843 // insert moves after first instruction | |
| 1844 move_resolver.set_insert_position(block->lir(), 1); | |
| 1845 move_resolver.resolve_and_append_moves(); | |
| 1846 } | |
| 1847 } | |
| 1848 | |
| 1849 | |
| 1850 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver) { | |
| 1851 if (interval_at(reg_num) == NULL) { | |
| 1852 // if a phi function is never used, no interval is created -> ignore this | |
| 1853 return; | |
| 1854 } | |
| 1855 | |
| 1856 // the computation of to_interval is equal to resolve_collect_mappings, | |
| 1857 // but from_interval is more complicated because of phi functions | |
| 1858 BlockBegin* to_block = handler->entry_block(); | |
| 1859 Interval* to_interval = interval_at_block_begin(to_block, reg_num); | |
| 1860 | |
| 1861 if (phi != NULL) { | |
| 1862 // phi function of the exception entry block | |
| 1863 // no moves are created for this phi function in the LIR_Generator, so the | |
| 1864 // interval at the throwing instruction must be searched using the operands | |
| 1865 // of the phi function | |
| 1866 Value from_value = phi->operand_at(handler->phi_operand()); | |
| 1867 | |
| 1868 // with phi functions it can happen that the same from_value is used in | |
| 1869 // multiple mappings, so notify move-resolver that this is allowed | |
| 1870 move_resolver.set_multiple_reads_allowed(); | |
| 1871 | |
| 1872 Constant* con = from_value->as_Constant(); | |
| 1873 if (con != NULL && !con->is_pinned()) { | |
| 1874 // unpinned constants may have no register, so add mapping from constant to interval | |
| 1875 move_resolver.add_mapping(LIR_OprFact::value_type(con->type()), to_interval); | |
| 1876 } else { | |
| 1877 // search split child at the throwing op_id | |
| 1878 Interval* from_interval = interval_at_op_id(from_value->operand()->vreg_number(), throwing_op_id); | |
| 1879 move_resolver.add_mapping(from_interval, to_interval); | |
| 1880 } | |
| 1881 | |
| 1882 } else { | |
| 1883 // no phi function, so use reg_num also for from_interval | |
| 1884 // search split child at the throwing op_id | |
| 1885 Interval* from_interval = interval_at_op_id(reg_num, throwing_op_id); | |
| 1886 if (from_interval != to_interval) { | |
| 1887 // optimization to reduce number of moves: when to_interval is on stack and | |
| 1888 // the stack slot is known to be always correct, then no move is necessary | |
| 1889 if (!from_interval->always_in_memory() || from_interval->canonical_spill_slot() != to_interval->assigned_reg()) { | |
| 1890 move_resolver.add_mapping(from_interval, to_interval); | |
| 1891 } | |
| 1892 } | |
| 1893 } | |
| 1894 } | |
| 1895 | |
| 1896 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver) { | |
| 1897 TRACE_LINEAR_SCAN(4, tty->print_cr("resolving exception handler B%d: throwing_op_id=%d", handler->entry_block()->block_id(), throwing_op_id)); | |
| 1898 | |
| 1899 DEBUG_ONLY(move_resolver.check_empty()); | |
| 1900 assert(handler->lir_op_id() == -1, "already processed this xhandler"); | |
| 1901 DEBUG_ONLY(handler->set_lir_op_id(throwing_op_id)); | |
| 1902 assert(handler->entry_code() == NULL, "code already present"); | |
| 1903 | |
| 1904 // visit all registers where the live_in bit is set | |
| 1905 BlockBegin* block = handler->entry_block(); | |
| 1906 int size = live_set_size(); | |
| 304 | 1907 for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) { |
| 0 | 1908 resolve_exception_edge(handler, throwing_op_id, r, NULL, move_resolver); |
| 1909 } | |
| 1910 | |
| 1911 // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately | |
| 1912 for_each_phi_fun(block, phi, | |
| 1913 resolve_exception_edge(handler, throwing_op_id, phi->operand()->vreg_number(), phi, move_resolver) | |
| 1914 ); | |
| 1915 | |
| 1916 if (move_resolver.has_mappings()) { | |
| 1917 LIR_List* entry_code = new LIR_List(compilation()); | |
| 1918 move_resolver.set_insert_position(entry_code, 0); | |
| 1919 move_resolver.resolve_and_append_moves(); | |
| 1920 | |
| 1921 entry_code->jump(handler->entry_block()); | |
| 1922 handler->set_entry_code(entry_code); | |
| 1923 } | |
| 1924 } | |
| 1925 | |
| 1926 | |
| 1927 void LinearScan::resolve_exception_handlers() { | |
| 1928 MoveResolver move_resolver(this); | |
| 1929 LIR_OpVisitState visitor; | |
| 1930 int num_blocks = block_count(); | |
| 1931 | |
| 1932 int i; | |
| 1933 for (i = 0; i < num_blocks; i++) { | |
| 1934 BlockBegin* block = block_at(i); | |
| 1935 if (block->is_set(BlockBegin::exception_entry_flag)) { | |
| 1936 resolve_exception_entry(block, move_resolver); | |
| 1937 } | |
| 1938 } | |
| 1939 | |
| 1940 for (i = 0; i < num_blocks; i++) { | |
| 1941 BlockBegin* block = block_at(i); | |
| 1942 LIR_List* ops = block->lir(); | |
| 1943 int num_ops = ops->length(); | |
| 1944 | |
| 1945 // iterate all instructions of the block. skip the first because it is always a label | |
| 1946 assert(visitor.no_operands(ops->at(0)), "first operation must always be a label"); | |
| 1947 for (int j = 1; j < num_ops; j++) { | |
| 1948 LIR_Op* op = ops->at(j); | |
| 1949 int op_id = op->id(); | |
| 1950 | |
| 1951 if (op_id != -1 && has_info(op_id)) { | |
| 1952 // visit operation to collect all operands | |
| 1953 visitor.visit(op); | |
| 1954 assert(visitor.info_count() > 0, "should not visit otherwise"); | |
| 1955 | |
| 1956 XHandlers* xhandlers = visitor.all_xhandler(); | |
| 1957 int n = xhandlers->length(); | |
| 1958 for (int k = 0; k < n; k++) { | |
| 1959 resolve_exception_edge(xhandlers->handler_at(k), op_id, move_resolver); | |
| 1960 } | |
| 1961 | |
| 1962 #ifdef ASSERT | |
| 1963 } else { | |
| 1964 visitor.visit(op); | |
| 1965 assert(visitor.all_xhandler()->length() == 0, "missed exception handler"); | |
| 1966 #endif | |
| 1967 } | |
| 1968 } | |
| 1969 } | |
| 1970 } | |
| 1971 | |
| 1972 | |
| 1973 // ********** Phase 7: assign register numbers back to LIR | |
| 1974 // (includes computation of debug information and oop maps) | |
| 1975 | |
| 1976 VMReg LinearScan::vm_reg_for_interval(Interval* interval) { | |
| 1977 VMReg reg = interval->cached_vm_reg(); | |
| 1978 if (!reg->is_valid() ) { | |
| 1979 reg = vm_reg_for_operand(operand_for_interval(interval)); | |
| 1980 interval->set_cached_vm_reg(reg); | |
| 1981 } | |
| 1982 assert(reg == vm_reg_for_operand(operand_for_interval(interval)), "wrong cached value"); | |
| 1983 return reg; | |
| 1984 } | |
| 1985 | |
| 1986 VMReg LinearScan::vm_reg_for_operand(LIR_Opr opr) { | |
| 1987 assert(opr->is_oop(), "currently only implemented for oop operands"); | |
| 1988 return frame_map()->regname(opr); | |
| 1989 } | |
| 1990 | |
| 1991 | |
| 1992 LIR_Opr LinearScan::operand_for_interval(Interval* interval) { | |
| 1993 LIR_Opr opr = interval->cached_opr(); | |
| 1994 if (opr->is_illegal()) { | |
| 1995 opr = calc_operand_for_interval(interval); | |
| 1996 interval->set_cached_opr(opr); | |
| 1997 } | |
| 1998 | |
| 1999 assert(opr == calc_operand_for_interval(interval), "wrong cached value"); | |
| 2000 return opr; | |
| 2001 } | |
| 2002 | |
| 2003 LIR_Opr LinearScan::calc_operand_for_interval(const Interval* interval) { | |
| 2004 int assigned_reg = interval->assigned_reg(); | |
| 2005 BasicType type = interval->type(); | |
| 2006 | |
| 2007 if (assigned_reg >= nof_regs) { | |
| 2008 // stack slot | |
| 2009 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); | |
| 2010 return LIR_OprFact::stack(assigned_reg - nof_regs, type); | |
| 2011 | |
| 2012 } else { | |
| 2013 // register | |
| 2014 switch (type) { | |
| 2015 case T_OBJECT: { | |
| 2016 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); | |
| 2017 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); | |
| 2018 return LIR_OprFact::single_cpu_oop(assigned_reg); | |
| 2019 } | |
| 2020 | |
|
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2021 #ifdef __SOFTFP__ |
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2022 case T_FLOAT: // fall through |
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2023 #endif // __SOFTFP__ |
| 0 | 2024 case T_INT: { |
| 2025 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); | |
| 2026 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); | |
| 2027 return LIR_OprFact::single_cpu(assigned_reg); | |
| 2028 } | |
| 2029 | |
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2030 #ifdef __SOFTFP__ |
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2031 case T_DOUBLE: // fall through |
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2032 #endif // __SOFTFP__ |
| 0 | 2033 case T_LONG: { |
| 2034 int assigned_regHi = interval->assigned_regHi(); | |
| 2035 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); | |
| 2036 assert(num_physical_regs(T_LONG) == 1 || | |
| 2037 (assigned_regHi >= pd_first_cpu_reg && assigned_regHi <= pd_last_cpu_reg), "no cpu register"); | |
| 2038 | |
| 2039 assert(assigned_reg != assigned_regHi, "invalid allocation"); | |
| 2040 assert(num_physical_regs(T_LONG) == 1 || assigned_reg < assigned_regHi, | |
| 2041 "register numbers must be sorted (ensure that e.g. a move from eax,ebx to ebx,eax can not occur)"); | |
| 2042 assert((assigned_regHi != any_reg) ^ (num_physical_regs(T_LONG) == 1), "must be match"); | |
| 2043 if (requires_adjacent_regs(T_LONG)) { | |
| 2044 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even"); | |
| 2045 } | |
| 2046 | |
| 2047 #ifdef _LP64 | |
| 2048 return LIR_OprFact::double_cpu(assigned_reg, assigned_reg); | |
| 2049 #else | |
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2050 #if defined(SPARC) || defined(PPC) |
| 0 | 2051 return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg); |
| 2052 #else | |
| 2053 return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi); | |
| 304 | 2054 #endif // SPARC |
| 2055 #endif // LP64 | |
| 0 | 2056 } |
| 2057 | |
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2058 #ifndef __SOFTFP__ |
| 0 | 2059 case T_FLOAT: { |
| 304 | 2060 #ifdef X86 |
| 0 | 2061 if (UseSSE >= 1) { |
| 2062 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register"); | |
| 2063 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); | |
| 2064 return LIR_OprFact::single_xmm(assigned_reg - pd_first_xmm_reg); | |
| 2065 } | |
| 2066 #endif | |
| 2067 | |
| 2068 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); | |
| 2069 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); | |
| 2070 return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg); | |
| 2071 } | |
| 2072 | |
| 2073 case T_DOUBLE: { | |
| 304 | 2074 #ifdef X86 |
| 0 | 2075 if (UseSSE >= 2) { |
| 2076 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register"); | |
| 2077 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)"); | |
| 2078 return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg); | |
| 2079 } | |
| 2080 #endif | |
| 2081 | |
| 2082 #ifdef SPARC | |
| 2083 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); | |
| 2084 assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register"); | |
| 2085 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even"); | |
| 2086 LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg); | |
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2087 #elif defined(ARM) |
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2088 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); |
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2089 assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register"); |
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2090 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even"); |
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2091 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg); |
| 0 | 2092 #else |
| 2093 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); | |
| 2094 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)"); | |
| 2095 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg); | |
| 2096 #endif | |
| 2097 return result; | |
| 2098 } | |
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2099 #endif // __SOFTFP__ |
| 0 | 2100 |
| 2101 default: { | |
| 2102 ShouldNotReachHere(); | |
| 2103 return LIR_OprFact::illegalOpr; | |
| 2104 } | |
| 2105 } | |
| 2106 } | |
| 2107 } | |
| 2108 | |
| 2109 LIR_Opr LinearScan::canonical_spill_opr(Interval* interval) { | |
| 2110 assert(interval->canonical_spill_slot() >= nof_regs, "canonical spill slot not set"); | |
| 2111 return LIR_OprFact::stack(interval->canonical_spill_slot() - nof_regs, interval->type()); | |
| 2112 } | |
| 2113 | |
| 2114 LIR_Opr LinearScan::color_lir_opr(LIR_Opr opr, int op_id, LIR_OpVisitState::OprMode mode) { | |
| 2115 assert(opr->is_virtual(), "should not call this otherwise"); | |
| 2116 | |
| 2117 Interval* interval = interval_at(opr->vreg_number()); | |
| 2118 assert(interval != NULL, "interval must exist"); | |
| 2119 | |
| 2120 if (op_id != -1) { | |
| 2121 #ifdef ASSERT | |
| 2122 BlockBegin* block = block_of_op_with_id(op_id); | |
| 2123 if (block->number_of_sux() <= 1 && op_id == block->last_lir_instruction_id()) { | |
| 2124 // check if spill moves could have been appended at the end of this block, but | |
| 2125 // before the branch instruction. So the split child information for this branch would | |
| 2126 // be incorrect. | |
| 2127 LIR_OpBranch* branch = block->lir()->instructions_list()->last()->as_OpBranch(); | |
| 2128 if (branch != NULL) { | |
| 2129 if (block->live_out().at(opr->vreg_number())) { | |
| 2130 assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump"); | |
| 2131 assert(false, "can't get split child for the last branch of a block because the information would be incorrect (moves are inserted before the branch in resolve_data_flow)"); | |
| 2132 } | |
| 2133 } | |
| 2134 } | |
| 2135 #endif | |
| 2136 | |
| 2137 // operands are not changed when an interval is split during allocation, | |
| 2138 // so search the right interval here | |
| 2139 interval = split_child_at_op_id(interval, op_id, mode); | |
| 2140 } | |
| 2141 | |
| 2142 LIR_Opr res = operand_for_interval(interval); | |
| 2143 | |
| 304 | 2144 #ifdef X86 |
| 0 | 2145 // new semantic for is_last_use: not only set on definite end of interval, |
| 2146 // but also before hole | |
| 2147 // This may still miss some cases (e.g. for dead values), but it is not necessary that the | |
| 2148 // last use information is completely correct | |
| 2149 // information is only needed for fpu stack allocation | |
| 2150 if (res->is_fpu_register()) { | |
| 2151 if (opr->is_last_use() || op_id == interval->to() || (op_id != -1 && interval->has_hole_between(op_id, op_id + 1))) { | |
| 2152 assert(op_id == -1 || !is_block_begin(op_id), "holes at begin of block may also result from control flow"); | |
| 2153 res = res->make_last_use(); | |
| 2154 } | |
| 2155 } | |
| 2156 #endif | |
| 2157 | |
| 2158 assert(!gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::callee_saved) || !FrameMap::is_caller_save_register(res), "bad allocation"); | |
| 2159 | |
| 2160 return res; | |
| 2161 } | |
| 2162 | |
| 2163 | |
| 2164 #ifdef ASSERT | |
| 2165 // some methods used to check correctness of debug information | |
| 2166 | |
| 2167 void assert_no_register_values(GrowableArray<ScopeValue*>* values) { | |
| 2168 if (values == NULL) { | |
| 2169 return; | |
| 2170 } | |
| 2171 | |
| 2172 for (int i = 0; i < values->length(); i++) { | |
| 2173 ScopeValue* value = values->at(i); | |
| 2174 | |
| 2175 if (value->is_location()) { | |
| 2176 Location location = ((LocationValue*)value)->location(); | |
| 2177 assert(location.where() == Location::on_stack, "value is in register"); | |
| 2178 } | |
| 2179 } | |
| 2180 } | |
| 2181 | |
| 2182 void assert_no_register_values(GrowableArray<MonitorValue*>* values) { | |
| 2183 if (values == NULL) { | |
| 2184 return; | |
| 2185 } | |
| 2186 | |
| 2187 for (int i = 0; i < values->length(); i++) { | |
| 2188 MonitorValue* value = values->at(i); | |
| 2189 | |
| 2190 if (value->owner()->is_location()) { | |
| 2191 Location location = ((LocationValue*)value->owner())->location(); | |
| 2192 assert(location.where() == Location::on_stack, "owner is in register"); | |
| 2193 } | |
| 2194 assert(value->basic_lock().where() == Location::on_stack, "basic_lock is in register"); | |
| 2195 } | |
| 2196 } | |
| 2197 | |
| 2198 void assert_equal(Location l1, Location l2) { | |
| 2199 assert(l1.where() == l2.where() && l1.type() == l2.type() && l1.offset() == l2.offset(), ""); | |
| 2200 } | |
| 2201 | |
| 2202 void assert_equal(ScopeValue* v1, ScopeValue* v2) { | |
| 2203 if (v1->is_location()) { | |
| 2204 assert(v2->is_location(), ""); | |
| 2205 assert_equal(((LocationValue*)v1)->location(), ((LocationValue*)v2)->location()); | |
| 2206 } else if (v1->is_constant_int()) { | |
| 2207 assert(v2->is_constant_int(), ""); | |
| 2208 assert(((ConstantIntValue*)v1)->value() == ((ConstantIntValue*)v2)->value(), ""); | |
| 2209 } else if (v1->is_constant_double()) { | |
| 2210 assert(v2->is_constant_double(), ""); | |
| 2211 assert(((ConstantDoubleValue*)v1)->value() == ((ConstantDoubleValue*)v2)->value(), ""); | |
| 2212 } else if (v1->is_constant_long()) { | |
| 2213 assert(v2->is_constant_long(), ""); | |
| 2214 assert(((ConstantLongValue*)v1)->value() == ((ConstantLongValue*)v2)->value(), ""); | |
| 2215 } else if (v1->is_constant_oop()) { | |
| 2216 assert(v2->is_constant_oop(), ""); | |
| 2217 assert(((ConstantOopWriteValue*)v1)->value() == ((ConstantOopWriteValue*)v2)->value(), ""); | |
| 2218 } else { | |
| 2219 ShouldNotReachHere(); | |
| 2220 } | |
| 2221 } | |
| 2222 | |
| 2223 void assert_equal(MonitorValue* m1, MonitorValue* m2) { | |
| 2224 assert_equal(m1->owner(), m2->owner()); | |
| 2225 assert_equal(m1->basic_lock(), m2->basic_lock()); | |
| 2226 } | |
| 2227 | |
| 2228 void assert_equal(IRScopeDebugInfo* d1, IRScopeDebugInfo* d2) { | |
| 2229 assert(d1->scope() == d2->scope(), "not equal"); | |
| 2230 assert(d1->bci() == d2->bci(), "not equal"); | |
| 2231 | |
| 2232 if (d1->locals() != NULL) { | |
| 2233 assert(d1->locals() != NULL && d2->locals() != NULL, "not equal"); | |
| 2234 assert(d1->locals()->length() == d2->locals()->length(), "not equal"); | |
| 2235 for (int i = 0; i < d1->locals()->length(); i++) { | |
| 2236 assert_equal(d1->locals()->at(i), d2->locals()->at(i)); | |
| 2237 } | |
| 2238 } else { | |
| 2239 assert(d1->locals() == NULL && d2->locals() == NULL, "not equal"); | |
| 2240 } | |
| 2241 | |
| 2242 if (d1->expressions() != NULL) { | |
| 2243 assert(d1->expressions() != NULL && d2->expressions() != NULL, "not equal"); | |
| 2244 assert(d1->expressions()->length() == d2->expressions()->length(), "not equal"); | |
| 2245 for (int i = 0; i < d1->expressions()->length(); i++) { | |
| 2246 assert_equal(d1->expressions()->at(i), d2->expressions()->at(i)); | |
| 2247 } | |
| 2248 } else { | |
| 2249 assert(d1->expressions() == NULL && d2->expressions() == NULL, "not equal"); | |
| 2250 } | |
| 2251 | |
| 2252 if (d1->monitors() != NULL) { | |
| 2253 assert(d1->monitors() != NULL && d2->monitors() != NULL, "not equal"); | |
| 2254 assert(d1->monitors()->length() == d2->monitors()->length(), "not equal"); | |
| 2255 for (int i = 0; i < d1->monitors()->length(); i++) { | |
| 2256 assert_equal(d1->monitors()->at(i), d2->monitors()->at(i)); | |
| 2257 } | |
| 2258 } else { | |
| 2259 assert(d1->monitors() == NULL && d2->monitors() == NULL, "not equal"); | |
| 2260 } | |
| 2261 | |
| 2262 if (d1->caller() != NULL) { | |
| 2263 assert(d1->caller() != NULL && d2->caller() != NULL, "not equal"); | |
| 2264 assert_equal(d1->caller(), d2->caller()); | |
| 2265 } else { | |
| 2266 assert(d1->caller() == NULL && d2->caller() == NULL, "not equal"); | |
| 2267 } | |
| 2268 } | |
| 2269 | |
| 2270 void check_stack_depth(CodeEmitInfo* info, int stack_end) { | |
| 2271 if (info->bci() != SynchronizationEntryBCI && !info->scope()->method()->is_native()) { | |
| 2272 Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->bci()); | |
| 2273 switch (code) { | |
| 2274 case Bytecodes::_ifnull : // fall through | |
| 2275 case Bytecodes::_ifnonnull : // fall through | |
| 2276 case Bytecodes::_ifeq : // fall through | |
| 2277 case Bytecodes::_ifne : // fall through | |
| 2278 case Bytecodes::_iflt : // fall through | |
| 2279 case Bytecodes::_ifge : // fall through | |
| 2280 case Bytecodes::_ifgt : // fall through | |
| 2281 case Bytecodes::_ifle : // fall through | |
| 2282 case Bytecodes::_if_icmpeq : // fall through | |
| 2283 case Bytecodes::_if_icmpne : // fall through | |
| 2284 case Bytecodes::_if_icmplt : // fall through | |
| 2285 case Bytecodes::_if_icmpge : // fall through | |
| 2286 case Bytecodes::_if_icmpgt : // fall through | |
| 2287 case Bytecodes::_if_icmple : // fall through | |
| 2288 case Bytecodes::_if_acmpeq : // fall through | |
| 2289 case Bytecodes::_if_acmpne : | |
| 2290 assert(stack_end >= -Bytecodes::depth(code), "must have non-empty expression stack at if bytecode"); | |
| 2291 break; | |
| 2292 } | |
| 2293 } | |
| 2294 } | |
| 2295 | |
| 2296 #endif // ASSERT | |
| 2297 | |
| 2298 | |
| 2299 IntervalWalker* LinearScan::init_compute_oop_maps() { | |
| 2300 // setup lists of potential oops for walking | |
| 2301 Interval* oop_intervals; | |
| 2302 Interval* non_oop_intervals; | |
| 2303 | |
| 2304 create_unhandled_lists(&oop_intervals, &non_oop_intervals, is_oop_interval, NULL); | |
| 2305 | |
| 2306 // intervals that have no oops inside need not to be processed | |
| 2307 // to ensure a walking until the last instruction id, add a dummy interval | |
| 2308 // with a high operation id | |
| 2309 non_oop_intervals = new Interval(any_reg); | |
| 2310 non_oop_intervals->add_range(max_jint - 2, max_jint - 1); | |
| 2311 | |
| 2312 return new IntervalWalker(this, oop_intervals, non_oop_intervals); | |
| 2313 } | |
| 2314 | |
| 2315 | |
| 2316 OopMap* LinearScan::compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site) { | |
| 2317 TRACE_LINEAR_SCAN(3, tty->print_cr("creating oop map at op_id %d", op->id())); | |
| 2318 | |
| 2319 // walk before the current operation -> intervals that start at | |
| 2320 // the operation (= output operands of the operation) are not | |
| 2321 // included in the oop map | |
| 2322 iw->walk_before(op->id()); | |
| 2323 | |
| 2324 int frame_size = frame_map()->framesize(); | |
| 2325 int arg_count = frame_map()->oop_map_arg_count(); | |
| 2326 OopMap* map = new OopMap(frame_size, arg_count); | |
| 2327 | |
| 2328 // Check if this is a patch site. | |
| 2329 bool is_patch_info = false; | |
| 2330 if (op->code() == lir_move) { | |
| 2331 assert(!is_call_site, "move must not be a call site"); | |
| 2332 assert(op->as_Op1() != NULL, "move must be LIR_Op1"); | |
| 2333 LIR_Op1* move = (LIR_Op1*)op; | |
| 2334 | |
| 2335 is_patch_info = move->patch_code() != lir_patch_none; | |
| 2336 } | |
| 2337 | |
| 2338 // Iterate through active intervals | |
| 2339 for (Interval* interval = iw->active_first(fixedKind); interval != Interval::end(); interval = interval->next()) { | |
| 2340 int assigned_reg = interval->assigned_reg(); | |
| 2341 | |
| 2342 assert(interval->current_from() <= op->id() && op->id() <= interval->current_to(), "interval should not be active otherwise"); | |
| 2343 assert(interval->assigned_regHi() == any_reg, "oop must be single word"); | |
| 2344 assert(interval->reg_num() >= LIR_OprDesc::vreg_base, "fixed interval found"); | |
| 2345 | |
| 2346 // Check if this range covers the instruction. Intervals that | |
| 2347 // start or end at the current operation are not included in the | |
| 2348 // oop map, except in the case of patching moves. For patching | |
| 2349 // moves, any intervals which end at this instruction are included | |
| 2350 // in the oop map since we may safepoint while doing the patch | |
| 2351 // before we've consumed the inputs. | |
| 2352 if (is_patch_info || op->id() < interval->current_to()) { | |
| 2353 | |
| 2354 // caller-save registers must not be included into oop-maps at calls | |
| 2355 assert(!is_call_site || assigned_reg >= nof_regs || !is_caller_save(assigned_reg), "interval is in a caller-save register at a call -> register will be overwritten"); | |
| 2356 | |
| 2357 VMReg name = vm_reg_for_interval(interval); | |
| 2358 map->set_oop(name); | |
| 2359 | |
| 2360 // Spill optimization: when the stack value is guaranteed to be always correct, | |
| 2361 // then it must be added to the oop map even if the interval is currently in a register | |
| 2362 if (interval->always_in_memory() && | |
| 2363 op->id() > interval->spill_definition_pos() && | |
| 2364 interval->assigned_reg() != interval->canonical_spill_slot()) { | |
| 2365 assert(interval->spill_definition_pos() > 0, "position not set correctly"); | |
| 2366 assert(interval->canonical_spill_slot() >= LinearScan::nof_regs, "no spill slot assigned"); | |
| 2367 assert(interval->assigned_reg() < LinearScan::nof_regs, "interval is on stack, so stack slot is registered twice"); | |
| 2368 | |
| 2369 map->set_oop(frame_map()->slot_regname(interval->canonical_spill_slot() - LinearScan::nof_regs)); | |
| 2370 } | |
| 2371 } | |
| 2372 } | |
| 2373 | |
| 2374 // add oops from lock stack | |
| 2375 assert(info->stack() != NULL, "CodeEmitInfo must always have a stack"); | |
| 2376 int locks_count = info->stack()->locks_size(); | |
| 2377 for (int i = 0; i < locks_count; i++) { | |
| 2378 map->set_oop(frame_map()->monitor_object_regname(i)); | |
| 2379 } | |
| 2380 | |
| 2381 return map; | |
| 2382 } | |
| 2383 | |
| 2384 | |
| 2385 void LinearScan::compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op) { | |
| 2386 assert(visitor.info_count() > 0, "no oop map needed"); | |
| 2387 | |
| 2388 // compute oop_map only for first CodeEmitInfo | |
| 2389 // because it is (in most cases) equal for all other infos of the same operation | |
| 2390 CodeEmitInfo* first_info = visitor.info_at(0); | |
| 2391 OopMap* first_oop_map = compute_oop_map(iw, op, first_info, visitor.has_call()); | |
| 2392 | |
| 2393 for (int i = 0; i < visitor.info_count(); i++) { | |
| 2394 CodeEmitInfo* info = visitor.info_at(i); | |
| 2395 OopMap* oop_map = first_oop_map; | |
| 2396 | |
| 2397 if (info->stack()->locks_size() != first_info->stack()->locks_size()) { | |
| 2398 // this info has a different number of locks then the precomputed oop map | |
| 2399 // (possible for lock and unlock instructions) -> compute oop map with | |
| 2400 // correct lock information | |
| 2401 oop_map = compute_oop_map(iw, op, info, visitor.has_call()); | |
| 2402 } | |
| 2403 | |
| 2404 if (info->_oop_map == NULL) { | |
| 2405 info->_oop_map = oop_map; | |
| 2406 } else { | |
| 2407 // a CodeEmitInfo can not be shared between different LIR-instructions | |
| 2408 // because interval splitting can occur anywhere between two instructions | |
| 2409 // and so the oop maps must be different | |
| 2410 // -> check if the already set oop_map is exactly the one calculated for this operation | |
| 2411 assert(info->_oop_map == oop_map, "same CodeEmitInfo used for multiple LIR instructions"); | |
| 2412 } | |
| 2413 } | |
| 2414 } | |
| 2415 | |
| 2416 | |
| 2417 // frequently used constants | |
| 2418 ConstantOopWriteValue LinearScan::_oop_null_scope_value = ConstantOopWriteValue(NULL); | |
| 2419 ConstantIntValue LinearScan::_int_m1_scope_value = ConstantIntValue(-1); | |
| 2420 ConstantIntValue LinearScan::_int_0_scope_value = ConstantIntValue(0); | |
| 2421 ConstantIntValue LinearScan::_int_1_scope_value = ConstantIntValue(1); | |
| 2422 ConstantIntValue LinearScan::_int_2_scope_value = ConstantIntValue(2); | |
| 2423 LocationValue _illegal_value = LocationValue(Location()); | |
| 2424 | |
| 2425 void LinearScan::init_compute_debug_info() { | |
| 2426 // cache for frequently used scope values | |
| 2427 // (cpu registers and stack slots) | |
| 2428 _scope_value_cache = ScopeValueArray((LinearScan::nof_cpu_regs + frame_map()->argcount() + max_spills()) * 2, NULL); | |
| 2429 } | |
| 2430 | |
| 2431 MonitorValue* LinearScan::location_for_monitor_index(int monitor_index) { | |
| 2432 Location loc; | |
| 2433 if (!frame_map()->location_for_monitor_object(monitor_index, &loc)) { | |
| 2434 bailout("too large frame"); | |
| 2435 } | |
| 2436 ScopeValue* object_scope_value = new LocationValue(loc); | |
| 2437 | |
| 2438 if (!frame_map()->location_for_monitor_lock(monitor_index, &loc)) { | |
| 2439 bailout("too large frame"); | |
| 2440 } | |
| 2441 return new MonitorValue(object_scope_value, loc); | |
| 2442 } | |
| 2443 | |
| 2444 LocationValue* LinearScan::location_for_name(int name, Location::Type loc_type) { | |
| 2445 Location loc; | |
| 2446 if (!frame_map()->locations_for_slot(name, loc_type, &loc)) { | |
| 2447 bailout("too large frame"); | |
| 2448 } | |
| 2449 return new LocationValue(loc); | |
| 2450 } | |
| 2451 | |
| 2452 | |
| 2453 int LinearScan::append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) { | |
| 2454 assert(opr->is_constant(), "should not be called otherwise"); | |
| 2455 | |
| 2456 LIR_Const* c = opr->as_constant_ptr(); | |
| 2457 BasicType t = c->type(); | |
| 2458 switch (t) { | |
| 2459 case T_OBJECT: { | |
| 2460 jobject value = c->as_jobject(); | |
| 2461 if (value == NULL) { | |
| 2462 scope_values->append(&_oop_null_scope_value); | |
| 2463 } else { | |
| 2464 scope_values->append(new ConstantOopWriteValue(c->as_jobject())); | |
| 2465 } | |
| 2466 return 1; | |
| 2467 } | |
| 2468 | |
| 2469 case T_INT: // fall through | |
| 2470 case T_FLOAT: { | |
| 2471 int value = c->as_jint_bits(); | |
| 2472 switch (value) { | |
| 2473 case -1: scope_values->append(&_int_m1_scope_value); break; | |
| 2474 case 0: scope_values->append(&_int_0_scope_value); break; | |
| 2475 case 1: scope_values->append(&_int_1_scope_value); break; | |
| 2476 case 2: scope_values->append(&_int_2_scope_value); break; | |
| 2477 default: scope_values->append(new ConstantIntValue(c->as_jint_bits())); break; | |
| 2478 } | |
| 2479 return 1; | |
| 2480 } | |
| 2481 | |
| 2482 case T_LONG: // fall through | |
| 2483 case T_DOUBLE: { | |
| 1060 | 2484 #ifdef _LP64 |
| 2485 scope_values->append(&_int_0_scope_value); | |
| 2486 scope_values->append(new ConstantLongValue(c->as_jlong_bits())); | |
| 2487 #else | |
| 0 | 2488 if (hi_word_offset_in_bytes > lo_word_offset_in_bytes) { |
| 2489 scope_values->append(new ConstantIntValue(c->as_jint_hi_bits())); | |
| 2490 scope_values->append(new ConstantIntValue(c->as_jint_lo_bits())); | |
| 2491 } else { | |
| 2492 scope_values->append(new ConstantIntValue(c->as_jint_lo_bits())); | |
| 2493 scope_values->append(new ConstantIntValue(c->as_jint_hi_bits())); | |
| 2494 } | |
| 1060 | 2495 #endif |
| 0 | 2496 return 2; |
| 2497 } | |
| 2498 | |
|
1297
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2499 case T_ADDRESS: { |
|
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|
2500 #ifdef _LP64 |
|
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|
2501 scope_values->append(new ConstantLongValue(c->as_jint())); |
|
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|
2502 #else |
|
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|
2503 scope_values->append(new ConstantIntValue(c->as_jint())); |
|
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|
2504 #endif |
|
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|
2505 return 1; |
|
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|
2506 } |
|
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|
2507 |
| 0 | 2508 default: |
| 2509 ShouldNotReachHere(); | |
| 304 | 2510 return -1; |
| 0 | 2511 } |
| 2512 } | |
| 2513 | |
| 2514 int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) { | |
| 2515 if (opr->is_single_stack()) { | |
| 2516 int stack_idx = opr->single_stack_ix(); | |
| 2517 bool is_oop = opr->is_oop_register(); | |
| 2518 int cache_idx = (stack_idx + LinearScan::nof_cpu_regs) * 2 + (is_oop ? 1 : 0); | |
| 2519 | |
| 2520 ScopeValue* sv = _scope_value_cache.at(cache_idx); | |
| 2521 if (sv == NULL) { | |
| 2522 Location::Type loc_type = is_oop ? Location::oop : Location::normal; | |
| 2523 sv = location_for_name(stack_idx, loc_type); | |
| 2524 _scope_value_cache.at_put(cache_idx, sv); | |
| 2525 } | |
| 2526 | |
| 2527 // check if cached value is correct | |
| 2528 DEBUG_ONLY(assert_equal(sv, location_for_name(stack_idx, is_oop ? Location::oop : Location::normal))); | |
| 2529 | |
| 2530 scope_values->append(sv); | |
| 2531 return 1; | |
| 2532 | |
| 2533 } else if (opr->is_single_cpu()) { | |
| 2534 bool is_oop = opr->is_oop_register(); | |
| 2535 int cache_idx = opr->cpu_regnr() * 2 + (is_oop ? 1 : 0); | |
| 1060 | 2536 Location::Type int_loc_type = NOT_LP64(Location::normal) LP64_ONLY(Location::int_in_long); |
| 0 | 2537 |
| 2538 ScopeValue* sv = _scope_value_cache.at(cache_idx); | |
| 2539 if (sv == NULL) { | |
| 1060 | 2540 Location::Type loc_type = is_oop ? Location::oop : int_loc_type; |
| 0 | 2541 VMReg rname = frame_map()->regname(opr); |
| 2542 sv = new LocationValue(Location::new_reg_loc(loc_type, rname)); | |
| 2543 _scope_value_cache.at_put(cache_idx, sv); | |
| 2544 } | |
| 2545 | |
| 2546 // check if cached value is correct | |
| 1060 | 2547 DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : int_loc_type, frame_map()->regname(opr))))); |
| 0 | 2548 |
| 2549 scope_values->append(sv); | |
| 2550 return 1; | |
| 2551 | |
| 304 | 2552 #ifdef X86 |
| 0 | 2553 } else if (opr->is_single_xmm()) { |
| 2554 VMReg rname = opr->as_xmm_float_reg()->as_VMReg(); | |
| 2555 LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname)); | |
| 2556 | |
| 2557 scope_values->append(sv); | |
| 2558 return 1; | |
| 2559 #endif | |
| 2560 | |
| 2561 } else if (opr->is_single_fpu()) { | |
| 304 | 2562 #ifdef X86 |
| 0 | 2563 // the exact location of fpu stack values is only known |
| 2564 // during fpu stack allocation, so the stack allocator object | |
| 2565 // must be present | |
| 2566 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)"); | |
| 2567 assert(_fpu_stack_allocator != NULL, "must be present"); | |
| 2568 opr = _fpu_stack_allocator->to_fpu_stack(opr); | |
| 2569 #endif | |
| 2570 | |
| 2571 Location::Type loc_type = float_saved_as_double ? Location::float_in_dbl : Location::normal; | |
| 2572 VMReg rname = frame_map()->fpu_regname(opr->fpu_regnr()); | |
| 2573 LocationValue* sv = new LocationValue(Location::new_reg_loc(loc_type, rname)); | |
| 2574 | |
| 2575 scope_values->append(sv); | |
| 2576 return 1; | |
| 2577 | |
| 2578 } else { | |
| 2579 // double-size operands | |
| 2580 | |
| 2581 ScopeValue* first; | |
| 2582 ScopeValue* second; | |
| 2583 | |
| 2584 if (opr->is_double_stack()) { | |
| 304 | 2585 #ifdef _LP64 |
| 2586 Location loc1; | |
| 2587 Location::Type loc_type = opr->type() == T_LONG ? Location::lng : Location::dbl; | |
| 2588 if (!frame_map()->locations_for_slot(opr->double_stack_ix(), loc_type, &loc1, NULL)) { | |
| 2589 bailout("too large frame"); | |
| 2590 } | |
| 2591 // Does this reverse on x86 vs. sparc? | |
| 2592 first = new LocationValue(loc1); | |
| 2593 second = &_int_0_scope_value; | |
| 2594 #else | |
| 0 | 2595 Location loc1, loc2; |
| 2596 if (!frame_map()->locations_for_slot(opr->double_stack_ix(), Location::normal, &loc1, &loc2)) { | |
| 2597 bailout("too large frame"); | |
| 2598 } | |
| 2599 first = new LocationValue(loc1); | |
| 2600 second = new LocationValue(loc2); | |
| 304 | 2601 #endif // _LP64 |
| 0 | 2602 |
| 2603 } else if (opr->is_double_cpu()) { | |
| 2604 #ifdef _LP64 | |
| 2605 VMReg rname_first = opr->as_register_lo()->as_VMReg(); | |
| 2606 first = new LocationValue(Location::new_reg_loc(Location::lng, rname_first)); | |
| 2607 second = &_int_0_scope_value; | |
| 2608 #else | |
| 2609 VMReg rname_first = opr->as_register_lo()->as_VMReg(); | |
| 2610 VMReg rname_second = opr->as_register_hi()->as_VMReg(); | |
| 2611 | |
| 2612 if (hi_word_offset_in_bytes < lo_word_offset_in_bytes) { | |
| 2613 // lo/hi and swapped relative to first and second, so swap them | |
| 2614 VMReg tmp = rname_first; | |
| 2615 rname_first = rname_second; | |
| 2616 rname_second = tmp; | |
| 2617 } | |
| 2618 | |
| 2619 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first)); | |
| 2620 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second)); | |
| 304 | 2621 #endif //_LP64 |
| 2622 | |
| 2623 | |
| 2624 #ifdef X86 | |
| 0 | 2625 } else if (opr->is_double_xmm()) { |
| 2626 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation"); | |
| 2627 VMReg rname_first = opr->as_xmm_double_reg()->as_VMReg(); | |
| 1369 | 2628 # ifdef _LP64 |
| 2629 first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first)); | |
| 2630 second = &_int_0_scope_value; | |
| 2631 # else | |
| 0 | 2632 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first)); |
| 2633 // %%% This is probably a waste but we'll keep things as they were for now | |
| 2634 if (true) { | |
| 2635 VMReg rname_second = rname_first->next(); | |
| 2636 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second)); | |
| 2637 } | |
| 1369 | 2638 # endif |
| 0 | 2639 #endif |
| 2640 | |
| 2641 } else if (opr->is_double_fpu()) { | |
| 2642 // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of | |
| 304 | 2643 // the double as float registers in the native ordering. On X86, |
| 0 | 2644 // fpu_regnrLo is a FPU stack slot whose VMReg represents |
| 2645 // the low-order word of the double and fpu_regnrLo + 1 is the | |
| 2646 // name for the other half. *first and *second must represent the | |
| 2647 // least and most significant words, respectively. | |
| 2648 | |
| 304 | 2649 #ifdef X86 |
| 0 | 2650 // the exact location of fpu stack values is only known |
| 2651 // during fpu stack allocation, so the stack allocator object | |
| 2652 // must be present | |
| 2653 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)"); | |
| 2654 assert(_fpu_stack_allocator != NULL, "must be present"); | |
| 2655 opr = _fpu_stack_allocator->to_fpu_stack(opr); | |
| 2656 | |
| 2657 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)"); | |
| 2658 #endif | |
| 2659 #ifdef SPARC | |
| 2660 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)"); | |
| 2661 #endif | |
|
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2662 #ifdef ARM |
|
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2663 assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)"); |
|
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2664 #endif |
|
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2665 #ifdef PPC |
|
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2666 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)"); |
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2667 #endif |
| 0 | 2668 |
| 2669 VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi()); | |
| 1369 | 2670 #ifdef _LP64 |
| 2671 first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first)); | |
| 2672 second = &_int_0_scope_value; | |
| 2673 #else | |
| 0 | 2674 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first)); |
| 2675 // %%% This is probably a waste but we'll keep things as they were for now | |
| 2676 if (true) { | |
| 2677 VMReg rname_second = rname_first->next(); | |
| 2678 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second)); | |
| 2679 } | |
| 1369 | 2680 #endif |
| 0 | 2681 |
| 2682 } else { | |
| 2683 ShouldNotReachHere(); | |
| 2684 first = NULL; | |
| 2685 second = NULL; | |
| 2686 } | |
| 2687 | |
| 2688 assert(first != NULL && second != NULL, "must be set"); | |
| 2689 // The convention the interpreter uses is that the second local | |
| 2690 // holds the first raw word of the native double representation. | |
| 2691 // This is actually reasonable, since locals and stack arrays | |
| 2692 // grow downwards in all implementations. | |
| 2693 // (If, on some machine, the interpreter's Java locals or stack | |
| 2694 // were to grow upwards, the embedded doubles would be word-swapped.) | |
| 2695 scope_values->append(second); | |
| 2696 scope_values->append(first); | |
| 2697 return 2; | |
| 2698 } | |
| 2699 } | |
| 2700 | |
| 2701 | |
| 2702 int LinearScan::append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values) { | |
| 2703 if (value != NULL) { | |
| 2704 LIR_Opr opr = value->operand(); | |
| 2705 Constant* con = value->as_Constant(); | |
| 2706 | |
| 2707 assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands (or illegal if constant is optimized away)"); | |
| 2708 assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands"); | |
| 2709 | |
| 2710 if (con != NULL && !con->is_pinned() && !opr->is_constant()) { | |
| 2711 // Unpinned constants may have a virtual operand for a part of the lifetime | |
| 2712 // or may be illegal when it was optimized away, | |
| 2713 // so always use a constant operand | |
| 2714 opr = LIR_OprFact::value_type(con->type()); | |
| 2715 } | |
| 2716 assert(opr->is_virtual() || opr->is_constant(), "other cases not allowed here"); | |
| 2717 | |
| 2718 if (opr->is_virtual()) { | |
| 2719 LIR_OpVisitState::OprMode mode = LIR_OpVisitState::inputMode; | |
| 2720 | |
| 2721 BlockBegin* block = block_of_op_with_id(op_id); | |
| 2722 if (block->number_of_sux() == 1 && op_id == block->last_lir_instruction_id()) { | |
| 2723 // generating debug information for the last instruction of a block. | |
| 2724 // if this instruction is a branch, spill moves are inserted before this branch | |
| 2725 // and so the wrong operand would be returned (spill moves at block boundaries are not | |
| 2726 // considered in the live ranges of intervals) | |
| 2727 // Solution: use the first op_id of the branch target block instead. | |
| 2728 if (block->lir()->instructions_list()->last()->as_OpBranch() != NULL) { | |
| 2729 if (block->live_out().at(opr->vreg_number())) { | |
| 2730 op_id = block->sux_at(0)->first_lir_instruction_id(); | |
| 2731 mode = LIR_OpVisitState::outputMode; | |
| 2732 } | |
| 2733 } | |
| 2734 } | |
| 2735 | |
| 2736 // Get current location of operand | |
| 2737 // The operand must be live because debug information is considered when building the intervals | |
| 2738 // if the interval is not live, color_lir_opr will cause an assertion failure | |
| 2739 opr = color_lir_opr(opr, op_id, mode); | |
| 2740 assert(!has_call(op_id) || opr->is_stack() || !is_caller_save(reg_num(opr)), "can not have caller-save register operands at calls"); | |
| 2741 | |
| 2742 // Append to ScopeValue array | |
| 2743 return append_scope_value_for_operand(opr, scope_values); | |
| 2744 | |
| 2745 } else { | |
| 2746 assert(value->as_Constant() != NULL, "all other instructions have only virtual operands"); | |
| 2747 assert(opr->is_constant(), "operand must be constant"); | |
| 2748 | |
| 2749 return append_scope_value_for_constant(opr, scope_values); | |
| 2750 } | |
| 2751 } else { | |
| 2752 // append a dummy value because real value not needed | |
| 2753 scope_values->append(&_illegal_value); | |
| 2754 return 1; | |
| 2755 } | |
| 2756 } | |
| 2757 | |
| 2758 | |
| 2759 IRScopeDebugInfo* LinearScan::compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state, int cur_bci, int stack_end, int locks_end) { | |
| 2760 IRScopeDebugInfo* caller_debug_info = NULL; | |
| 2761 int stack_begin, locks_begin; | |
| 2762 | |
| 2763 ValueStack* caller_state = cur_scope->caller_state(); | |
| 2764 if (caller_state != NULL) { | |
| 2765 // process recursively to compute outermost scope first | |
| 2766 stack_begin = caller_state->stack_size(); | |
| 2767 locks_begin = caller_state->locks_size(); | |
| 2768 caller_debug_info = compute_debug_info_for_scope(op_id, cur_scope->caller(), caller_state, innermost_state, cur_scope->caller_bci(), stack_begin, locks_begin); | |
| 2769 } else { | |
| 2770 stack_begin = 0; | |
| 2771 locks_begin = 0; | |
| 2772 } | |
| 2773 | |
| 2774 // initialize these to null. | |
| 2775 // If we don't need deopt info or there are no locals, expressions or monitors, | |
| 2776 // then these get recorded as no information and avoids the allocation of 0 length arrays. | |
| 2777 GrowableArray<ScopeValue*>* locals = NULL; | |
| 2778 GrowableArray<ScopeValue*>* expressions = NULL; | |
| 2779 GrowableArray<MonitorValue*>* monitors = NULL; | |
| 2780 | |
| 2781 // describe local variable values | |
| 2782 int nof_locals = cur_scope->method()->max_locals(); | |
| 2783 if (nof_locals > 0) { | |
| 2784 locals = new GrowableArray<ScopeValue*>(nof_locals); | |
| 2785 | |
| 2786 int pos = 0; | |
| 2787 while (pos < nof_locals) { | |
| 2788 assert(pos < cur_state->locals_size(), "why not?"); | |
| 2789 | |
| 2790 Value local = cur_state->local_at(pos); | |
| 2791 pos += append_scope_value(op_id, local, locals); | |
| 2792 | |
| 2793 assert(locals->length() == pos, "must match"); | |
| 2794 } | |
| 2795 assert(locals->length() == cur_scope->method()->max_locals(), "wrong number of locals"); | |
| 2796 assert(locals->length() == cur_state->locals_size(), "wrong number of locals"); | |
| 2797 } | |
| 2798 | |
| 2799 | |
| 2800 // describe expression stack | |
| 2801 // | |
| 2802 // When we inline methods containing exception handlers, the | |
| 2803 // "lock_stacks" are changed to preserve expression stack values | |
| 2804 // in caller scopes when exception handlers are present. This | |
| 2805 // can cause callee stacks to be smaller than caller stacks. | |
| 2806 if (stack_end > innermost_state->stack_size()) { | |
| 2807 stack_end = innermost_state->stack_size(); | |
| 2808 } | |
| 2809 | |
| 2810 | |
| 2811 | |
| 2812 int nof_stack = stack_end - stack_begin; | |
| 2813 if (nof_stack > 0) { | |
| 2814 expressions = new GrowableArray<ScopeValue*>(nof_stack); | |
| 2815 | |
| 2816 int pos = stack_begin; | |
| 2817 while (pos < stack_end) { | |
| 2818 Value expression = innermost_state->stack_at_inc(pos); | |
| 2819 append_scope_value(op_id, expression, expressions); | |
| 2820 | |
| 2821 assert(expressions->length() + stack_begin == pos, "must match"); | |
| 2822 } | |
| 2823 } | |
| 2824 | |
| 2825 // describe monitors | |
| 2826 assert(locks_begin <= locks_end, "error in scope iteration"); | |
| 2827 int nof_locks = locks_end - locks_begin; | |
| 2828 if (nof_locks > 0) { | |
| 2829 monitors = new GrowableArray<MonitorValue*>(nof_locks); | |
| 2830 for (int i = locks_begin; i < locks_end; i++) { | |
| 2831 monitors->append(location_for_monitor_index(i)); | |
| 2832 } | |
| 2833 } | |
| 2834 | |
| 2835 return new IRScopeDebugInfo(cur_scope, cur_bci, locals, expressions, monitors, caller_debug_info); | |
| 2836 } | |
| 2837 | |
| 2838 | |
| 2839 void LinearScan::compute_debug_info(CodeEmitInfo* info, int op_id) { | |
| 2840 TRACE_LINEAR_SCAN(3, tty->print_cr("creating debug information at op_id %d", op_id)); | |
| 2841 | |
| 2842 IRScope* innermost_scope = info->scope(); | |
| 2843 ValueStack* innermost_state = info->stack(); | |
| 2844 | |
| 2845 assert(innermost_scope != NULL && innermost_state != NULL, "why is it missing?"); | |
| 2846 | |
| 2847 int stack_end = innermost_state->stack_size(); | |
| 2848 int locks_end = innermost_state->locks_size(); | |
| 2849 | |
| 2850 DEBUG_ONLY(check_stack_depth(info, stack_end)); | |
| 2851 | |
| 2852 if (info->_scope_debug_info == NULL) { | |
| 2853 // compute debug information | |
| 2854 info->_scope_debug_info = compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state, info->bci(), stack_end, locks_end); | |
| 2855 } else { | |
| 2856 // debug information already set. Check that it is correct from the current point of view | |
| 2857 DEBUG_ONLY(assert_equal(info->_scope_debug_info, compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state, info->bci(), stack_end, locks_end))); | |
| 2858 } | |
| 2859 } | |
| 2860 | |
| 2861 | |
| 2862 void LinearScan::assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw) { | |
| 2863 LIR_OpVisitState visitor; | |
| 2864 int num_inst = instructions->length(); | |
| 2865 bool has_dead = false; | |
| 2866 | |
| 2867 for (int j = 0; j < num_inst; j++) { | |
| 2868 LIR_Op* op = instructions->at(j); | |
| 2869 if (op == NULL) { // this can happen when spill-moves are removed in eliminate_spill_moves | |
| 2870 has_dead = true; | |
| 2871 continue; | |
| 2872 } | |
| 2873 int op_id = op->id(); | |
| 2874 | |
| 2875 // visit instruction to get list of operands | |
| 2876 visitor.visit(op); | |
| 2877 | |
| 2878 // iterate all modes of the visitor and process all virtual operands | |
| 2879 for_each_visitor_mode(mode) { | |
| 2880 int n = visitor.opr_count(mode); | |
| 2881 for (int k = 0; k < n; k++) { | |
| 2882 LIR_Opr opr = visitor.opr_at(mode, k); | |
| 2883 if (opr->is_virtual_register()) { | |
| 2884 visitor.set_opr_at(mode, k, color_lir_opr(opr, op_id, mode)); | |
| 2885 } | |
| 2886 } | |
| 2887 } | |
| 2888 | |
| 2889 if (visitor.info_count() > 0) { | |
| 2890 // exception handling | |
| 2891 if (compilation()->has_exception_handlers()) { | |
| 2892 XHandlers* xhandlers = visitor.all_xhandler(); | |
| 2893 int n = xhandlers->length(); | |
| 2894 for (int k = 0; k < n; k++) { | |
| 2895 XHandler* handler = xhandlers->handler_at(k); | |
| 2896 if (handler->entry_code() != NULL) { | |
| 2897 assign_reg_num(handler->entry_code()->instructions_list(), NULL); | |
| 2898 } | |
| 2899 } | |
| 2900 } else { | |
| 2901 assert(visitor.all_xhandler()->length() == 0, "missed exception handler"); | |
| 2902 } | |
| 2903 | |
| 2904 // compute oop map | |
| 2905 assert(iw != NULL, "needed for compute_oop_map"); | |
| 2906 compute_oop_map(iw, visitor, op); | |
| 2907 | |
| 2908 // compute debug information | |
| 2909 if (!use_fpu_stack_allocation()) { | |
| 2910 // compute debug information if fpu stack allocation is not needed. | |
| 2911 // when fpu stack allocation is needed, the debug information can not | |
| 2912 // be computed here because the exact location of fpu operands is not known | |
| 2913 // -> debug information is created inside the fpu stack allocator | |
| 2914 int n = visitor.info_count(); | |
| 2915 for (int k = 0; k < n; k++) { | |
| 2916 compute_debug_info(visitor.info_at(k), op_id); | |
| 2917 } | |
| 2918 } | |
| 2919 } | |
| 2920 | |
| 2921 #ifdef ASSERT | |
| 2922 // make sure we haven't made the op invalid. | |
| 2923 op->verify(); | |
| 2924 #endif | |
| 2925 | |
| 2926 // remove useless moves | |
| 2927 if (op->code() == lir_move) { | |
| 2928 assert(op->as_Op1() != NULL, "move must be LIR_Op1"); | |
| 2929 LIR_Op1* move = (LIR_Op1*)op; | |
| 2930 LIR_Opr src = move->in_opr(); | |
| 2931 LIR_Opr dst = move->result_opr(); | |
| 2932 if (dst == src || | |
| 2933 !dst->is_pointer() && !src->is_pointer() && | |
| 2934 src->is_same_register(dst)) { | |
| 2935 instructions->at_put(j, NULL); | |
| 2936 has_dead = true; | |
| 2937 } | |
| 2938 } | |
| 2939 } | |
| 2940 | |
| 2941 if (has_dead) { | |
| 2942 // iterate all instructions of the block and remove all null-values. | |
| 2943 int insert_point = 0; | |
| 2944 for (int j = 0; j < num_inst; j++) { | |
| 2945 LIR_Op* op = instructions->at(j); | |
| 2946 if (op != NULL) { | |
| 2947 if (insert_point != j) { | |
| 2948 instructions->at_put(insert_point, op); | |
| 2949 } | |
| 2950 insert_point++; | |
| 2951 } | |
| 2952 } | |
| 2953 instructions->truncate(insert_point); | |
| 2954 } | |
| 2955 } | |
| 2956 | |
| 2957 void LinearScan::assign_reg_num() { | |
| 2958 TIME_LINEAR_SCAN(timer_assign_reg_num); | |
| 2959 | |
| 2960 init_compute_debug_info(); | |
| 2961 IntervalWalker* iw = init_compute_oop_maps(); | |
| 2962 | |
| 2963 int num_blocks = block_count(); | |
| 2964 for (int i = 0; i < num_blocks; i++) { | |
| 2965 BlockBegin* block = block_at(i); | |
| 2966 assign_reg_num(block->lir()->instructions_list(), iw); | |
| 2967 } | |
| 2968 } | |
| 2969 | |
| 2970 | |
| 2971 void LinearScan::do_linear_scan() { | |
| 2972 NOT_PRODUCT(_total_timer.begin_method()); | |
| 2973 | |
| 2974 number_instructions(); | |
| 2975 | |
| 2976 NOT_PRODUCT(print_lir(1, "Before Register Allocation")); | |
| 2977 | |
| 2978 compute_local_live_sets(); | |
| 2979 compute_global_live_sets(); | |
| 2980 CHECK_BAILOUT(); | |
| 2981 | |
| 2982 build_intervals(); | |
| 2983 CHECK_BAILOUT(); | |
| 2984 sort_intervals_before_allocation(); | |
| 2985 | |
| 2986 NOT_PRODUCT(print_intervals("Before Register Allocation")); | |
| 2987 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_before_alloc)); | |
| 2988 | |
| 2989 allocate_registers(); | |
| 2990 CHECK_BAILOUT(); | |
| 2991 | |
| 2992 resolve_data_flow(); | |
| 2993 if (compilation()->has_exception_handlers()) { | |
| 2994 resolve_exception_handlers(); | |
| 2995 } | |
| 2996 // fill in number of spill slots into frame_map | |
| 2997 propagate_spill_slots(); | |
| 2998 CHECK_BAILOUT(); | |
| 2999 | |
| 3000 NOT_PRODUCT(print_intervals("After Register Allocation")); | |
| 3001 NOT_PRODUCT(print_lir(2, "LIR after register allocation:")); | |
| 3002 | |
| 3003 sort_intervals_after_allocation(); | |
|
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3004 |
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3005 DEBUG_ONLY(verify()); |
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3006 |
| 0 | 3007 eliminate_spill_moves(); |
| 3008 assign_reg_num(); | |
| 3009 CHECK_BAILOUT(); | |
| 3010 | |
| 3011 NOT_PRODUCT(print_lir(2, "LIR after assignment of register numbers:")); | |
| 3012 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_after_asign)); | |
| 3013 | |
| 3014 { TIME_LINEAR_SCAN(timer_allocate_fpu_stack); | |
| 3015 | |
| 3016 if (use_fpu_stack_allocation()) { | |
| 3017 allocate_fpu_stack(); // Only has effect on Intel | |
| 3018 NOT_PRODUCT(print_lir(2, "LIR after FPU stack allocation:")); | |
| 3019 } | |
| 3020 } | |
| 3021 | |
| 3022 { TIME_LINEAR_SCAN(timer_optimize_lir); | |
| 3023 | |
| 3024 EdgeMoveOptimizer::optimize(ir()->code()); | |
| 3025 ControlFlowOptimizer::optimize(ir()->code()); | |
| 3026 // check that cfg is still correct after optimizations | |
| 3027 ir()->verify(); | |
| 3028 } | |
| 3029 | |
| 3030 NOT_PRODUCT(print_lir(1, "Before Code Generation", false)); | |
| 3031 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_final)); | |
| 3032 NOT_PRODUCT(_total_timer.end_method(this)); | |
| 3033 } | |
| 3034 | |
| 3035 | |
| 3036 // ********** Printing functions | |
| 3037 | |
| 3038 #ifndef PRODUCT | |
| 3039 | |
| 3040 void LinearScan::print_timers(double total) { | |
| 3041 _total_timer.print(total); | |
| 3042 } | |
| 3043 | |
| 3044 void LinearScan::print_statistics() { | |
| 3045 _stat_before_alloc.print("before allocation"); | |
| 3046 _stat_after_asign.print("after assignment of register"); | |
| 3047 _stat_final.print("after optimization"); | |
| 3048 } | |
| 3049 | |
| 3050 void LinearScan::print_bitmap(BitMap& b) { | |
| 3051 for (unsigned int i = 0; i < b.size(); i++) { | |
| 3052 if (b.at(i)) tty->print("%d ", i); | |
| 3053 } | |
| 3054 tty->cr(); | |
| 3055 } | |
| 3056 | |
| 3057 void LinearScan::print_intervals(const char* label) { | |
| 3058 if (TraceLinearScanLevel >= 1) { | |
| 3059 int i; | |
| 3060 tty->cr(); | |
| 3061 tty->print_cr("%s", label); | |
| 3062 | |
| 3063 for (i = 0; i < interval_count(); i++) { | |
| 3064 Interval* interval = interval_at(i); | |
| 3065 if (interval != NULL) { | |
| 3066 interval->print(); | |
| 3067 } | |
| 3068 } | |
| 3069 | |
| 3070 tty->cr(); | |
| 3071 tty->print_cr("--- Basic Blocks ---"); | |
| 3072 for (i = 0; i < block_count(); i++) { | |
| 3073 BlockBegin* block = block_at(i); | |
| 3074 tty->print("B%d [%d, %d, %d, %d] ", block->block_id(), block->first_lir_instruction_id(), block->last_lir_instruction_id(), block->loop_index(), block->loop_depth()); | |
| 3075 } | |
| 3076 tty->cr(); | |
| 3077 tty->cr(); | |
| 3078 } | |
| 3079 | |
| 3080 if (PrintCFGToFile) { | |
| 3081 CFGPrinter::print_intervals(&_intervals, label); | |
| 3082 } | |
| 3083 } | |
| 3084 | |
| 3085 void LinearScan::print_lir(int level, const char* label, bool hir_valid) { | |
| 3086 if (TraceLinearScanLevel >= level) { | |
| 3087 tty->cr(); | |
| 3088 tty->print_cr("%s", label); | |
| 3089 print_LIR(ir()->linear_scan_order()); | |
| 3090 tty->cr(); | |
| 3091 } | |
| 3092 | |
| 3093 if (level == 1 && PrintCFGToFile) { | |
| 3094 CFGPrinter::print_cfg(ir()->linear_scan_order(), label, hir_valid, true); | |
| 3095 } | |
| 3096 } | |
| 3097 | |
| 3098 #endif //PRODUCT | |
| 3099 | |
| 3100 | |
| 3101 // ********** verification functions for allocation | |
| 3102 // (check that all intervals have a correct register and that no registers are overwritten) | |
| 3103 #ifdef ASSERT | |
| 3104 | |
| 3105 void LinearScan::verify() { | |
| 3106 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying intervals ******************************************")); | |
| 3107 verify_intervals(); | |
| 3108 | |
| 3109 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that no oops are in fixed intervals ****************")); | |
| 3110 verify_no_oops_in_fixed_intervals(); | |
| 3111 | |
| 3112 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that unpinned constants are not alive across block boundaries")); | |
| 3113 verify_constants(); | |
| 3114 | |
| 3115 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying register allocation ********************************")); | |
| 3116 verify_registers(); | |
| 3117 | |
| 3118 TRACE_LINEAR_SCAN(2, tty->print_cr("********* no errors found **********************************************")); | |
| 3119 } | |
| 3120 | |
| 3121 void LinearScan::verify_intervals() { | |
| 3122 int len = interval_count(); | |
| 3123 bool has_error = false; | |
| 3124 | |
| 3125 for (int i = 0; i < len; i++) { | |
| 3126 Interval* i1 = interval_at(i); | |
| 3127 if (i1 == NULL) continue; | |
| 3128 | |
| 3129 i1->check_split_children(); | |
| 3130 | |
| 3131 if (i1->reg_num() != i) { | |
| 3132 tty->print_cr("Interval %d is on position %d in list", i1->reg_num(), i); i1->print(); tty->cr(); | |
| 3133 has_error = true; | |
| 3134 } | |
| 3135 | |
| 3136 if (i1->reg_num() >= LIR_OprDesc::vreg_base && i1->type() == T_ILLEGAL) { | |
| 3137 tty->print_cr("Interval %d has no type assigned", i1->reg_num()); i1->print(); tty->cr(); | |
| 3138 has_error = true; | |
| 3139 } | |
| 3140 | |
| 3141 if (i1->assigned_reg() == any_reg) { | |
| 3142 tty->print_cr("Interval %d has no register assigned", i1->reg_num()); i1->print(); tty->cr(); | |
| 3143 has_error = true; | |
| 3144 } | |
| 3145 | |
| 3146 if (i1->assigned_reg() == i1->assigned_regHi()) { | |
| 3147 tty->print_cr("Interval %d: low and high register equal", i1->reg_num()); i1->print(); tty->cr(); | |
| 3148 has_error = true; | |
| 3149 } | |
| 3150 | |
| 3151 if (!is_processed_reg_num(i1->assigned_reg())) { | |
| 3152 tty->print_cr("Can not have an Interval for an ignored register"); i1->print(); tty->cr(); | |
| 3153 has_error = true; | |
| 3154 } | |
| 3155 | |
| 3156 if (i1->first() == Range::end()) { | |
| 3157 tty->print_cr("Interval %d has no Range", i1->reg_num()); i1->print(); tty->cr(); | |
| 3158 has_error = true; | |
| 3159 } | |
| 3160 | |
| 3161 for (Range* r = i1->first(); r != Range::end(); r = r->next()) { | |
| 3162 if (r->from() >= r->to()) { | |
| 3163 tty->print_cr("Interval %d has zero length range", i1->reg_num()); i1->print(); tty->cr(); | |
| 3164 has_error = true; | |
| 3165 } | |
| 3166 } | |
| 3167 | |
| 3168 for (int j = i + 1; j < len; j++) { | |
| 3169 Interval* i2 = interval_at(j); | |
| 3170 if (i2 == NULL) continue; | |
| 3171 | |
| 3172 // special intervals that are created in MoveResolver | |
| 3173 // -> ignore them because the range information has no meaning there | |
| 3174 if (i1->from() == 1 && i1->to() == 2) continue; | |
| 3175 if (i2->from() == 1 && i2->to() == 2) continue; | |
| 3176 | |
| 3177 int r1 = i1->assigned_reg(); | |
| 3178 int r1Hi = i1->assigned_regHi(); | |
| 3179 int r2 = i2->assigned_reg(); | |
| 3180 int r2Hi = i2->assigned_regHi(); | |
| 3181 if (i1->intersects(i2) && (r1 == r2 || r1 == r2Hi || (r1Hi != any_reg && (r1Hi == r2 || r1Hi == r2Hi)))) { | |
| 3182 tty->print_cr("Intervals %d and %d overlap and have the same register assigned", i1->reg_num(), i2->reg_num()); | |
| 3183 i1->print(); tty->cr(); | |
| 3184 i2->print(); tty->cr(); | |
| 3185 has_error = true; | |
| 3186 } | |
| 3187 } | |
| 3188 } | |
| 3189 | |
| 3190 assert(has_error == false, "register allocation invalid"); | |
| 3191 } | |
| 3192 | |
| 3193 | |
| 3194 void LinearScan::verify_no_oops_in_fixed_intervals() { | |
|
722
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diff
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|
3195 Interval* fixed_intervals; |
|
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diff
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|
3196 Interval* other_intervals; |
|
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|
3197 create_unhandled_lists(&fixed_intervals, &other_intervals, is_precolored_cpu_interval, NULL); |
|
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|
3198 |
|
a134d9824964
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|
3199 // to ensure a walking until the last instruction id, add a dummy interval |
|
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parents:
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diff
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|
3200 // with a high operation id |
|
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diff
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|
3201 other_intervals = new Interval(any_reg); |
|
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|
3202 other_intervals->add_range(max_jint - 2, max_jint - 1); |
|
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parents:
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|
3203 IntervalWalker* iw = new IntervalWalker(this, fixed_intervals, other_intervals); |
|
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|
3204 |
| 0 | 3205 LIR_OpVisitState visitor; |
| 3206 for (int i = 0; i < block_count(); i++) { | |
| 3207 BlockBegin* block = block_at(i); | |
| 3208 | |
| 3209 LIR_OpList* instructions = block->lir()->instructions_list(); | |
| 3210 | |
| 3211 for (int j = 0; j < instructions->length(); j++) { | |
| 3212 LIR_Op* op = instructions->at(j); | |
| 3213 int op_id = op->id(); | |
| 3214 | |
| 3215 visitor.visit(op); | |
| 3216 | |
|
722
a134d9824964
6828024: verification of fixed interval usage is too weak
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parents:
337
diff
changeset
|
3217 if (visitor.info_count() > 0) { |
|
a134d9824964
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never
parents:
337
diff
changeset
|
3218 iw->walk_before(op->id()); |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
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parents:
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diff
changeset
|
3219 bool check_live = true; |
|
a134d9824964
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parents:
337
diff
changeset
|
3220 if (op->code() == lir_move) { |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
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parents:
337
diff
changeset
|
3221 LIR_Op1* move = (LIR_Op1*)op; |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
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parents:
337
diff
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|
3222 check_live = (move->patch_code() == lir_patch_none); |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
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parents:
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diff
changeset
|
3223 } |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
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parents:
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diff
changeset
|
3224 LIR_OpBranch* branch = op->as_OpBranch(); |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
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parents:
337
diff
changeset
|
3225 if (branch != NULL && branch->stub() != NULL && branch->stub()->is_exception_throw_stub()) { |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
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parents:
337
diff
changeset
|
3226 // Don't bother checking the stub in this case since the |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
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parents:
337
diff
changeset
|
3227 // exception stub will never return to normal control flow. |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
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parents:
337
diff
changeset
|
3228 check_live = false; |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3229 } |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3230 |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3231 // Make sure none of the fixed registers is live across an |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3232 // oopmap since we can't handle that correctly. |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3233 if (check_live) { |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3234 for (Interval* interval = iw->active_first(fixedKind); |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3235 interval != Interval::end(); |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3236 interval = interval->next()) { |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3237 if (interval->current_to() > op->id() + 1) { |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3238 // This interval is live out of this op so make sure |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3239 // that this interval represents some value that's |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3240 // referenced by this op either as an input or output. |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3241 bool ok = false; |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3242 for_each_visitor_mode(mode) { |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3243 int n = visitor.opr_count(mode); |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3244 for (int k = 0; k < n; k++) { |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3245 LIR_Opr opr = visitor.opr_at(mode, k); |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3246 if (opr->is_fixed_cpu()) { |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3247 if (interval_at(reg_num(opr)) == interval) { |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3248 ok = true; |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3249 break; |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3250 } |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3251 int hi = reg_numHi(opr); |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3252 if (hi != -1 && interval_at(hi) == interval) { |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3253 ok = true; |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3254 break; |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3255 } |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3256 } |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3257 } |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3258 } |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3259 assert(ok, "fixed intervals should never be live across an oopmap point"); |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3260 } |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3261 } |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3262 } |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3263 } |
|
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3264 |
| 0 | 3265 // oop-maps at calls do not contain registers, so check is not needed |
| 3266 if (!visitor.has_call()) { | |
| 3267 | |
| 3268 for_each_visitor_mode(mode) { | |
| 3269 int n = visitor.opr_count(mode); | |
| 3270 for (int k = 0; k < n; k++) { | |
| 3271 LIR_Opr opr = visitor.opr_at(mode, k); | |
| 3272 | |
| 3273 if (opr->is_fixed_cpu() && opr->is_oop()) { | |
| 3274 // operand is a non-virtual cpu register and contains an oop | |
| 3275 TRACE_LINEAR_SCAN(4, op->print_on(tty); tty->print("checking operand "); opr->print(); tty->cr()); | |
| 3276 | |
| 3277 Interval* interval = interval_at(reg_num(opr)); | |
| 3278 assert(interval != NULL, "no interval"); | |
| 3279 | |
| 3280 if (mode == LIR_OpVisitState::inputMode) { | |
| 3281 if (interval->to() >= op_id + 1) { | |
| 3282 assert(interval->to() < op_id + 2 || | |
| 3283 interval->has_hole_between(op_id, op_id + 2), | |
| 3284 "oop input operand live after instruction"); | |
| 3285 } | |
| 3286 } else if (mode == LIR_OpVisitState::outputMode) { | |
| 3287 if (interval->from() <= op_id - 1) { | |
| 3288 assert(interval->has_hole_between(op_id - 1, op_id), | |
| 3289 "oop input operand live after instruction"); | |
| 3290 } | |
| 3291 } | |
| 3292 } | |
| 3293 } | |
| 3294 } | |
| 3295 } | |
| 3296 } | |
| 3297 } | |
| 3298 } | |
| 3299 | |
| 3300 | |
| 3301 void LinearScan::verify_constants() { | |
| 3302 int num_regs = num_virtual_regs(); | |
| 3303 int size = live_set_size(); | |
| 3304 int num_blocks = block_count(); | |
| 3305 | |
| 3306 for (int i = 0; i < num_blocks; i++) { | |
| 3307 BlockBegin* block = block_at(i); | |
| 3308 BitMap live_at_edge = block->live_in(); | |
| 3309 | |
| 3310 // visit all registers where the live_at_edge bit is set | |
| 304 | 3311 for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) { |
| 0 | 3312 TRACE_LINEAR_SCAN(4, tty->print("checking interval %d of block B%d", r, block->block_id())); |
| 3313 | |
| 3314 Value value = gen()->instruction_for_vreg(r); | |
| 3315 | |
| 3316 assert(value != NULL, "all intervals live across block boundaries must have Value"); | |
| 3317 assert(value->operand()->is_register() && value->operand()->is_virtual(), "value must have virtual operand"); | |
| 3318 assert(value->operand()->vreg_number() == r, "register number must match"); | |
| 3319 // TKR assert(value->as_Constant() == NULL || value->is_pinned(), "only pinned constants can be alive accross block boundaries"); | |
| 3320 } | |
| 3321 } | |
| 3322 } | |
| 3323 | |
| 3324 | |
| 3325 class RegisterVerifier: public StackObj { | |
| 3326 private: | |
| 3327 LinearScan* _allocator; | |
| 3328 BlockList _work_list; // all blocks that must be processed | |
| 3329 IntervalsList _saved_states; // saved information of previous check | |
| 3330 | |
| 3331 // simplified access to methods of LinearScan | |
| 3332 Compilation* compilation() const { return _allocator->compilation(); } | |
| 3333 Interval* interval_at(int reg_num) const { return _allocator->interval_at(reg_num); } | |
| 3334 int reg_num(LIR_Opr opr) const { return _allocator->reg_num(opr); } | |
| 3335 | |
| 3336 // currently, only registers are processed | |
| 3337 int state_size() { return LinearScan::nof_regs; } | |
| 3338 | |
| 3339 // accessors | |
| 3340 IntervalList* state_for_block(BlockBegin* block) { return _saved_states.at(block->block_id()); } | |
| 3341 void set_state_for_block(BlockBegin* block, IntervalList* saved_state) { _saved_states.at_put(block->block_id(), saved_state); } | |
| 3342 void add_to_work_list(BlockBegin* block) { if (!_work_list.contains(block)) _work_list.append(block); } | |
| 3343 | |
| 3344 // helper functions | |
| 3345 IntervalList* copy(IntervalList* input_state); | |
| 3346 void state_put(IntervalList* input_state, int reg, Interval* interval); | |
| 3347 bool check_state(IntervalList* input_state, int reg, Interval* interval); | |
| 3348 | |
| 3349 void process_block(BlockBegin* block); | |
| 3350 void process_xhandler(XHandler* xhandler, IntervalList* input_state); | |
| 3351 void process_successor(BlockBegin* block, IntervalList* input_state); | |
| 3352 void process_operations(LIR_List* ops, IntervalList* input_state); | |
| 3353 | |
| 3354 public: | |
| 3355 RegisterVerifier(LinearScan* allocator) | |
| 3356 : _allocator(allocator) | |
| 3357 , _work_list(16) | |
| 3358 , _saved_states(BlockBegin::number_of_blocks(), NULL) | |
| 3359 { } | |
| 3360 | |
| 3361 void verify(BlockBegin* start); | |
| 3362 }; | |
| 3363 | |
| 3364 | |
| 3365 // entry function from LinearScan that starts the verification | |
| 3366 void LinearScan::verify_registers() { | |
| 3367 RegisterVerifier verifier(this); | |
| 3368 verifier.verify(block_at(0)); | |
| 3369 } | |
| 3370 | |
| 3371 | |
| 3372 void RegisterVerifier::verify(BlockBegin* start) { | |
| 3373 // setup input registers (method arguments) for first block | |
| 3374 IntervalList* input_state = new IntervalList(state_size(), NULL); | |
| 3375 CallingConvention* args = compilation()->frame_map()->incoming_arguments(); | |
| 3376 for (int n = 0; n < args->length(); n++) { | |
| 3377 LIR_Opr opr = args->at(n); | |
| 3378 if (opr->is_register()) { | |
| 3379 Interval* interval = interval_at(reg_num(opr)); | |
| 3380 | |
| 3381 if (interval->assigned_reg() < state_size()) { | |
| 3382 input_state->at_put(interval->assigned_reg(), interval); | |
| 3383 } | |
| 3384 if (interval->assigned_regHi() != LinearScan::any_reg && interval->assigned_regHi() < state_size()) { | |
| 3385 input_state->at_put(interval->assigned_regHi(), interval); | |
| 3386 } | |
| 3387 } | |
| 3388 } | |
| 3389 | |
| 3390 set_state_for_block(start, input_state); | |
| 3391 add_to_work_list(start); | |
| 3392 | |
| 3393 // main loop for verification | |
| 3394 do { | |
| 3395 BlockBegin* block = _work_list.at(0); | |
| 3396 _work_list.remove_at(0); | |
| 3397 | |
| 3398 process_block(block); | |
| 3399 } while (!_work_list.is_empty()); | |
| 3400 } | |
| 3401 | |
| 3402 void RegisterVerifier::process_block(BlockBegin* block) { | |
| 3403 TRACE_LINEAR_SCAN(2, tty->cr(); tty->print_cr("process_block B%d", block->block_id())); | |
| 3404 | |
| 3405 // must copy state because it is modified | |
| 3406 IntervalList* input_state = copy(state_for_block(block)); | |
| 3407 | |
| 3408 if (TraceLinearScanLevel >= 4) { | |
| 3409 tty->print_cr("Input-State of intervals:"); | |
| 3410 tty->print(" "); | |
| 3411 for (int i = 0; i < state_size(); i++) { | |
| 3412 if (input_state->at(i) != NULL) { | |
| 3413 tty->print(" %4d", input_state->at(i)->reg_num()); | |
| 3414 } else { | |
| 3415 tty->print(" __"); | |
| 3416 } | |
| 3417 } | |
| 3418 tty->cr(); | |
| 3419 tty->cr(); | |
| 3420 } | |
| 3421 | |
| 3422 // process all operations of the block | |
| 3423 process_operations(block->lir(), input_state); | |
| 3424 | |
| 3425 // iterate all successors | |
| 3426 for (int i = 0; i < block->number_of_sux(); i++) { | |
| 3427 process_successor(block->sux_at(i), input_state); | |
| 3428 } | |
| 3429 } | |
| 3430 | |
| 3431 void RegisterVerifier::process_xhandler(XHandler* xhandler, IntervalList* input_state) { | |
| 3432 TRACE_LINEAR_SCAN(2, tty->print_cr("process_xhandler B%d", xhandler->entry_block()->block_id())); | |
| 3433 | |
| 3434 // must copy state because it is modified | |
| 3435 input_state = copy(input_state); | |
| 3436 | |
| 3437 if (xhandler->entry_code() != NULL) { | |
| 3438 process_operations(xhandler->entry_code(), input_state); | |
| 3439 } | |
| 3440 process_successor(xhandler->entry_block(), input_state); | |
| 3441 } | |
| 3442 | |
| 3443 void RegisterVerifier::process_successor(BlockBegin* block, IntervalList* input_state) { | |
| 3444 IntervalList* saved_state = state_for_block(block); | |
| 3445 | |
| 3446 if (saved_state != NULL) { | |
| 3447 // this block was already processed before. | |
| 3448 // check if new input_state is consistent with saved_state | |
| 3449 | |
| 3450 bool saved_state_correct = true; | |
| 3451 for (int i = 0; i < state_size(); i++) { | |
| 3452 if (input_state->at(i) != saved_state->at(i)) { | |
| 3453 // current input_state and previous saved_state assume a different | |
| 3454 // interval in this register -> assume that this register is invalid | |
| 3455 if (saved_state->at(i) != NULL) { | |
| 3456 // invalidate old calculation only if it assumed that | |
| 3457 // register was valid. when the register was already invalid, | |
| 3458 // then the old calculation was correct. | |
| 3459 saved_state_correct = false; | |
| 3460 saved_state->at_put(i, NULL); | |
| 3461 | |
| 3462 TRACE_LINEAR_SCAN(4, tty->print_cr("process_successor B%d: invalidating slot %d", block->block_id(), i)); | |
| 3463 } | |
| 3464 } | |
| 3465 } | |
| 3466 | |
| 3467 if (saved_state_correct) { | |
| 3468 // already processed block with correct input_state | |
| 3469 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: previous visit already correct", block->block_id())); | |
| 3470 } else { | |
| 3471 // must re-visit this block | |
| 3472 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: must re-visit because input state changed", block->block_id())); | |
| 3473 add_to_work_list(block); | |
| 3474 } | |
| 3475 | |
| 3476 } else { | |
| 3477 // block was not processed before, so set initial input_state | |
| 3478 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: initial visit", block->block_id())); | |
| 3479 | |
| 3480 set_state_for_block(block, copy(input_state)); | |
| 3481 add_to_work_list(block); | |
| 3482 } | |
| 3483 } | |
| 3484 | |
| 3485 | |
| 3486 IntervalList* RegisterVerifier::copy(IntervalList* input_state) { | |
| 3487 IntervalList* copy_state = new IntervalList(input_state->length()); | |
| 3488 copy_state->push_all(input_state); | |
| 3489 return copy_state; | |
| 3490 } | |
| 3491 | |
| 3492 void RegisterVerifier::state_put(IntervalList* input_state, int reg, Interval* interval) { | |
| 3493 if (reg != LinearScan::any_reg && reg < state_size()) { | |
| 3494 if (interval != NULL) { | |
| 3495 TRACE_LINEAR_SCAN(4, tty->print_cr(" reg[%d] = %d", reg, interval->reg_num())); | |
| 3496 } else if (input_state->at(reg) != NULL) { | |
| 3497 TRACE_LINEAR_SCAN(4, tty->print_cr(" reg[%d] = NULL", reg)); | |
| 3498 } | |
| 3499 | |
| 3500 input_state->at_put(reg, interval); | |
| 3501 } | |
| 3502 } | |
| 3503 | |
| 3504 bool RegisterVerifier::check_state(IntervalList* input_state, int reg, Interval* interval) { | |
| 3505 if (reg != LinearScan::any_reg && reg < state_size()) { | |
| 3506 if (input_state->at(reg) != interval) { | |
| 3507 tty->print_cr("!! Error in register allocation: register %d does not contain interval %d", reg, interval->reg_num()); | |
| 3508 return true; | |
| 3509 } | |
| 3510 } | |
| 3511 return false; | |
| 3512 } | |
| 3513 | |
| 3514 void RegisterVerifier::process_operations(LIR_List* ops, IntervalList* input_state) { | |
| 3515 // visit all instructions of the block | |
| 3516 LIR_OpVisitState visitor; | |
| 3517 bool has_error = false; | |
| 3518 | |
| 3519 for (int i = 0; i < ops->length(); i++) { | |
| 3520 LIR_Op* op = ops->at(i); | |
| 3521 visitor.visit(op); | |
| 3522 | |
| 3523 TRACE_LINEAR_SCAN(4, op->print_on(tty)); | |
| 3524 | |
| 3525 // check if input operands are correct | |
| 3526 int j; | |
| 3527 int n = visitor.opr_count(LIR_OpVisitState::inputMode); | |
| 3528 for (j = 0; j < n; j++) { | |
| 3529 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, j); | |
| 3530 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) { | |
| 3531 Interval* interval = interval_at(reg_num(opr)); | |
| 3532 if (op->id() != -1) { | |
| 3533 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::inputMode); | |
| 3534 } | |
| 3535 | |
| 3536 has_error |= check_state(input_state, interval->assigned_reg(), interval->split_parent()); | |
| 3537 has_error |= check_state(input_state, interval->assigned_regHi(), interval->split_parent()); | |
| 3538 | |
| 3539 // When an operand is marked with is_last_use, then the fpu stack allocator | |
| 3540 // removes the register from the fpu stack -> the register contains no value | |
| 3541 if (opr->is_last_use()) { | |
| 3542 state_put(input_state, interval->assigned_reg(), NULL); | |
| 3543 state_put(input_state, interval->assigned_regHi(), NULL); | |
| 3544 } | |
| 3545 } | |
| 3546 } | |
| 3547 | |
| 3548 // invalidate all caller save registers at calls | |
| 3549 if (visitor.has_call()) { | |
| 3550 for (j = 0; j < FrameMap::nof_caller_save_cpu_regs; j++) { | |
| 3551 state_put(input_state, reg_num(FrameMap::caller_save_cpu_reg_at(j)), NULL); | |
| 3552 } | |
| 3553 for (j = 0; j < FrameMap::nof_caller_save_fpu_regs; j++) { | |
| 3554 state_put(input_state, reg_num(FrameMap::caller_save_fpu_reg_at(j)), NULL); | |
| 3555 } | |
| 3556 | |
| 304 | 3557 #ifdef X86 |
| 0 | 3558 for (j = 0; j < FrameMap::nof_caller_save_xmm_regs; j++) { |
| 3559 state_put(input_state, reg_num(FrameMap::caller_save_xmm_reg_at(j)), NULL); | |
| 3560 } | |
| 3561 #endif | |
| 3562 } | |
| 3563 | |
| 3564 // process xhandler before output and temp operands | |
| 3565 XHandlers* xhandlers = visitor.all_xhandler(); | |
| 3566 n = xhandlers->length(); | |
| 3567 for (int k = 0; k < n; k++) { | |
| 3568 process_xhandler(xhandlers->handler_at(k), input_state); | |
| 3569 } | |
| 3570 | |
| 3571 // set temp operands (some operations use temp operands also as output operands, so can't set them NULL) | |
| 3572 n = visitor.opr_count(LIR_OpVisitState::tempMode); | |
| 3573 for (j = 0; j < n; j++) { | |
| 3574 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, j); | |
| 3575 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) { | |
| 3576 Interval* interval = interval_at(reg_num(opr)); | |
| 3577 if (op->id() != -1) { | |
| 3578 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::tempMode); | |
| 3579 } | |
| 3580 | |
| 3581 state_put(input_state, interval->assigned_reg(), interval->split_parent()); | |
| 3582 state_put(input_state, interval->assigned_regHi(), interval->split_parent()); | |
| 3583 } | |
| 3584 } | |
| 3585 | |
| 3586 // set output operands | |
| 3587 n = visitor.opr_count(LIR_OpVisitState::outputMode); | |
| 3588 for (j = 0; j < n; j++) { | |
| 3589 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, j); | |
| 3590 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) { | |
| 3591 Interval* interval = interval_at(reg_num(opr)); | |
| 3592 if (op->id() != -1) { | |
| 3593 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::outputMode); | |
| 3594 } | |
| 3595 | |
| 3596 state_put(input_state, interval->assigned_reg(), interval->split_parent()); | |
| 3597 state_put(input_state, interval->assigned_regHi(), interval->split_parent()); | |
| 3598 } | |
| 3599 } | |
| 3600 } | |
| 3601 assert(has_error == false, "Error in register allocation"); | |
| 3602 } | |
| 3603 | |
| 3604 #endif // ASSERT | |
| 3605 | |
| 3606 | |
| 3607 | |
| 3608 // **** Implementation of MoveResolver ****************************** | |
| 3609 | |
| 3610 MoveResolver::MoveResolver(LinearScan* allocator) : | |
| 3611 _allocator(allocator), | |
| 3612 _multiple_reads_allowed(false), | |
| 3613 _mapping_from(8), | |
| 3614 _mapping_from_opr(8), | |
| 3615 _mapping_to(8), | |
| 3616 _insert_list(NULL), | |
| 3617 _insert_idx(-1), | |
| 3618 _insertion_buffer() | |
| 3619 { | |
| 3620 for (int i = 0; i < LinearScan::nof_regs; i++) { | |
| 3621 _register_blocked[i] = 0; | |
| 3622 } | |
| 3623 DEBUG_ONLY(check_empty()); | |
| 3624 } | |
| 3625 | |
| 3626 | |
| 3627 #ifdef ASSERT | |
| 3628 | |
| 3629 void MoveResolver::check_empty() { | |
| 3630 assert(_mapping_from.length() == 0 && _mapping_from_opr.length() == 0 && _mapping_to.length() == 0, "list must be empty before and after processing"); | |
| 3631 for (int i = 0; i < LinearScan::nof_regs; i++) { | |
| 3632 assert(register_blocked(i) == 0, "register map must be empty before and after processing"); | |
| 3633 } | |
| 3634 assert(_multiple_reads_allowed == false, "must have default value"); | |
| 3635 } | |
| 3636 | |
| 3637 void MoveResolver::verify_before_resolve() { | |
| 3638 assert(_mapping_from.length() == _mapping_from_opr.length(), "length must be equal"); | |
| 3639 assert(_mapping_from.length() == _mapping_to.length(), "length must be equal"); | |
| 3640 assert(_insert_list != NULL && _insert_idx != -1, "insert position not set"); | |
| 3641 | |
| 3642 int i, j; | |
| 3643 if (!_multiple_reads_allowed) { | |
| 3644 for (i = 0; i < _mapping_from.length(); i++) { | |
| 3645 for (j = i + 1; j < _mapping_from.length(); j++) { | |
| 3646 assert(_mapping_from.at(i) == NULL || _mapping_from.at(i) != _mapping_from.at(j), "cannot read from same interval twice"); | |
| 3647 } | |
| 3648 } | |
| 3649 } | |
| 3650 | |
| 3651 for (i = 0; i < _mapping_to.length(); i++) { | |
| 3652 for (j = i + 1; j < _mapping_to.length(); j++) { | |
| 3653 assert(_mapping_to.at(i) != _mapping_to.at(j), "cannot write to same interval twice"); | |
| 3654 } | |
| 3655 } | |
| 3656 | |
| 3657 | |
| 3658 BitMap used_regs(LinearScan::nof_regs + allocator()->frame_map()->argcount() + allocator()->max_spills()); | |
| 3659 used_regs.clear(); | |
| 3660 if (!_multiple_reads_allowed) { | |
| 3661 for (i = 0; i < _mapping_from.length(); i++) { | |
| 3662 Interval* it = _mapping_from.at(i); | |
| 3663 if (it != NULL) { | |
| 3664 assert(!used_regs.at(it->assigned_reg()), "cannot read from same register twice"); | |
| 3665 used_regs.set_bit(it->assigned_reg()); | |
| 3666 | |
| 3667 if (it->assigned_regHi() != LinearScan::any_reg) { | |
| 3668 assert(!used_regs.at(it->assigned_regHi()), "cannot read from same register twice"); | |
| 3669 used_regs.set_bit(it->assigned_regHi()); | |
| 3670 } | |
| 3671 } | |
| 3672 } | |
| 3673 } | |
| 3674 | |
| 3675 used_regs.clear(); | |
| 3676 for (i = 0; i < _mapping_to.length(); i++) { | |
| 3677 Interval* it = _mapping_to.at(i); | |
| 3678 assert(!used_regs.at(it->assigned_reg()), "cannot write to same register twice"); | |
| 3679 used_regs.set_bit(it->assigned_reg()); | |
| 3680 | |
| 3681 if (it->assigned_regHi() != LinearScan::any_reg) { | |
| 3682 assert(!used_regs.at(it->assigned_regHi()), "cannot write to same register twice"); | |
| 3683 used_regs.set_bit(it->assigned_regHi()); | |
| 3684 } | |
| 3685 } | |
| 3686 | |
| 3687 used_regs.clear(); | |
| 3688 for (i = 0; i < _mapping_from.length(); i++) { | |
| 3689 Interval* it = _mapping_from.at(i); | |
| 3690 if (it != NULL && it->assigned_reg() >= LinearScan::nof_regs) { | |
| 3691 used_regs.set_bit(it->assigned_reg()); | |
| 3692 } | |
| 3693 } | |
| 3694 for (i = 0; i < _mapping_to.length(); i++) { | |
| 3695 Interval* it = _mapping_to.at(i); | |
| 3696 assert(!used_regs.at(it->assigned_reg()) || it->assigned_reg() == _mapping_from.at(i)->assigned_reg(), "stack slots used in _mapping_from must be disjoint to _mapping_to"); | |
| 3697 } | |
| 3698 } | |
| 3699 | |
| 3700 #endif // ASSERT | |
| 3701 | |
| 3702 | |
| 3703 // mark assigned_reg and assigned_regHi of the interval as blocked | |
| 3704 void MoveResolver::block_registers(Interval* it) { | |
| 3705 int reg = it->assigned_reg(); | |
| 3706 if (reg < LinearScan::nof_regs) { | |
| 3707 assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used"); | |
| 3708 set_register_blocked(reg, 1); | |
| 3709 } | |
| 3710 reg = it->assigned_regHi(); | |
| 3711 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) { | |
| 3712 assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used"); | |
| 3713 set_register_blocked(reg, 1); | |
| 3714 } | |
| 3715 } | |
| 3716 | |
| 3717 // mark assigned_reg and assigned_regHi of the interval as unblocked | |
| 3718 void MoveResolver::unblock_registers(Interval* it) { | |
| 3719 int reg = it->assigned_reg(); | |
| 3720 if (reg < LinearScan::nof_regs) { | |
| 3721 assert(register_blocked(reg) > 0, "register already marked as unused"); | |
| 3722 set_register_blocked(reg, -1); | |
| 3723 } | |
| 3724 reg = it->assigned_regHi(); | |
| 3725 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) { | |
| 3726 assert(register_blocked(reg) > 0, "register already marked as unused"); | |
| 3727 set_register_blocked(reg, -1); | |
| 3728 } | |
| 3729 } | |
| 3730 | |
| 3731 // check if assigned_reg and assigned_regHi of the to-interval are not blocked (or only blocked by from) | |
| 3732 bool MoveResolver::save_to_process_move(Interval* from, Interval* to) { | |
| 3733 int from_reg = -1; | |
| 3734 int from_regHi = -1; | |
| 3735 if (from != NULL) { | |
| 3736 from_reg = from->assigned_reg(); | |
| 3737 from_regHi = from->assigned_regHi(); | |
| 3738 } | |
| 3739 | |
| 3740 int reg = to->assigned_reg(); | |
| 3741 if (reg < LinearScan::nof_regs) { | |
| 3742 if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) { | |
| 3743 return false; | |
| 3744 } | |
| 3745 } | |
| 3746 reg = to->assigned_regHi(); | |
| 3747 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) { | |
| 3748 if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) { | |
| 3749 return false; | |
| 3750 } | |
| 3751 } | |
| 3752 | |
| 3753 return true; | |
| 3754 } | |
| 3755 | |
| 3756 | |
| 3757 void MoveResolver::create_insertion_buffer(LIR_List* list) { | |
| 3758 assert(!_insertion_buffer.initialized(), "overwriting existing buffer"); | |
| 3759 _insertion_buffer.init(list); | |
| 3760 } | |
| 3761 | |
| 3762 void MoveResolver::append_insertion_buffer() { | |
| 3763 if (_insertion_buffer.initialized()) { | |
| 3764 _insertion_buffer.lir_list()->append(&_insertion_buffer); | |
| 3765 } | |
| 3766 assert(!_insertion_buffer.initialized(), "must be uninitialized now"); | |
| 3767 | |
| 3768 _insert_list = NULL; | |
| 3769 _insert_idx = -1; | |
| 3770 } | |
| 3771 | |
| 3772 void MoveResolver::insert_move(Interval* from_interval, Interval* to_interval) { | |
| 3773 assert(from_interval->reg_num() != to_interval->reg_num(), "from and to interval equal"); | |
| 3774 assert(from_interval->type() == to_interval->type(), "move between different types"); | |
| 3775 assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first"); | |
| 3776 assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer"); | |
| 3777 | |
| 3778 LIR_Opr from_opr = LIR_OprFact::virtual_register(from_interval->reg_num(), from_interval->type()); | |
| 3779 LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type()); | |
| 3780 | |
| 3781 if (!_multiple_reads_allowed) { | |
| 3782 // the last_use flag is an optimization for FPU stack allocation. When the same | |
| 3783 // input interval is used in more than one move, then it is too difficult to determine | |
| 3784 // if this move is really the last use. | |
| 3785 from_opr = from_opr->make_last_use(); | |
| 3786 } | |
| 3787 _insertion_buffer.move(_insert_idx, from_opr, to_opr); | |
| 3788 | |
| 3789 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: inserted move from register %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi())); | |
| 3790 } | |
| 3791 | |
| 3792 void MoveResolver::insert_move(LIR_Opr from_opr, Interval* to_interval) { | |
| 3793 assert(from_opr->type() == to_interval->type(), "move between different types"); | |
| 3794 assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first"); | |
| 3795 assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer"); | |
| 3796 | |
| 3797 LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type()); | |
| 3798 _insertion_buffer.move(_insert_idx, from_opr, to_opr); | |
| 3799 | |
| 3800 TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: inserted move from constant "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi())); | |
| 3801 } | |
| 3802 | |
| 3803 | |
| 3804 void MoveResolver::resolve_mappings() { | |
| 3805 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: resolving mappings for Block B%d, index %d", _insert_list->block() != NULL ? _insert_list->block()->block_id() : -1, _insert_idx)); | |
| 3806 DEBUG_ONLY(verify_before_resolve()); | |
| 3807 | |
| 3808 // Block all registers that are used as input operands of a move. | |
| 3809 // When a register is blocked, no move to this register is emitted. | |
| 3810 // This is necessary for detecting cycles in moves. | |
| 3811 int i; | |
| 3812 for (i = _mapping_from.length() - 1; i >= 0; i--) { | |
| 3813 Interval* from_interval = _mapping_from.at(i); | |
| 3814 if (from_interval != NULL) { | |
| 3815 block_registers(from_interval); | |
| 3816 } | |
| 3817 } | |
| 3818 | |
| 3819 int spill_candidate = -1; | |
| 3820 while (_mapping_from.length() > 0) { | |
| 3821 bool processed_interval = false; | |
| 3822 | |
| 3823 for (i = _mapping_from.length() - 1; i >= 0; i--) { | |
| 3824 Interval* from_interval = _mapping_from.at(i); | |
| 3825 Interval* to_interval = _mapping_to.at(i); | |
| 3826 | |
| 3827 if (save_to_process_move(from_interval, to_interval)) { | |
| 3828 // this inverval can be processed because target is free | |
| 3829 if (from_interval != NULL) { | |
| 3830 insert_move(from_interval, to_interval); | |
| 3831 unblock_registers(from_interval); | |
| 3832 } else { | |
| 3833 insert_move(_mapping_from_opr.at(i), to_interval); | |
| 3834 } | |
| 3835 _mapping_from.remove_at(i); | |
| 3836 _mapping_from_opr.remove_at(i); | |
| 3837 _mapping_to.remove_at(i); | |
| 3838 | |
| 3839 processed_interval = true; | |
| 3840 } else if (from_interval != NULL && from_interval->assigned_reg() < LinearScan::nof_regs) { | |
| 3841 // this interval cannot be processed now because target is not free | |
| 3842 // it starts in a register, so it is a possible candidate for spilling | |
| 3843 spill_candidate = i; | |
| 3844 } | |
| 3845 } | |
| 3846 | |
| 3847 if (!processed_interval) { | |
| 3848 // no move could be processed because there is a cycle in the move list | |
| 3849 // (e.g. r1 -> r2, r2 -> r1), so one interval must be spilled to memory | |
| 3850 assert(spill_candidate != -1, "no interval in register for spilling found"); | |
| 3851 | |
| 3852 // create a new spill interval and assign a stack slot to it | |
| 3853 Interval* from_interval = _mapping_from.at(spill_candidate); | |
| 3854 Interval* spill_interval = new Interval(-1); | |
| 3855 spill_interval->set_type(from_interval->type()); | |
| 3856 | |
| 3857 // add a dummy range because real position is difficult to calculate | |
| 3858 // Note: this range is a special case when the integrity of the allocation is checked | |
| 3859 spill_interval->add_range(1, 2); | |
| 3860 | |
| 3861 // do not allocate a new spill slot for temporary interval, but | |
| 3862 // use spill slot assigned to from_interval. Otherwise moves from | |
| 3863 // one stack slot to another can happen (not allowed by LIR_Assembler | |
| 3864 int spill_slot = from_interval->canonical_spill_slot(); | |
| 3865 if (spill_slot < 0) { | |
| 3866 spill_slot = allocator()->allocate_spill_slot(type2spill_size[spill_interval->type()] == 2); | |
| 3867 from_interval->set_canonical_spill_slot(spill_slot); | |
| 3868 } | |
| 3869 spill_interval->assign_reg(spill_slot); | |
| 3870 allocator()->append_interval(spill_interval); | |
| 3871 | |
| 3872 TRACE_LINEAR_SCAN(4, tty->print_cr("created new Interval %d for spilling", spill_interval->reg_num())); | |
| 3873 | |
| 3874 // insert a move from register to stack and update the mapping | |
| 3875 insert_move(from_interval, spill_interval); | |
| 3876 _mapping_from.at_put(spill_candidate, spill_interval); | |
| 3877 unblock_registers(from_interval); | |
| 3878 } | |
| 3879 } | |
| 3880 | |
| 3881 // reset to default value | |
| 3882 _multiple_reads_allowed = false; | |
| 3883 | |
| 3884 // check that all intervals have been processed | |
| 3885 DEBUG_ONLY(check_empty()); | |
| 3886 } | |
| 3887 | |
| 3888 | |
| 3889 void MoveResolver::set_insert_position(LIR_List* insert_list, int insert_idx) { | |
| 3890 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: setting insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx)); | |
| 3891 assert(_insert_list == NULL && _insert_idx == -1, "use move_insert_position instead of set_insert_position when data already set"); | |
| 3892 | |
| 3893 create_insertion_buffer(insert_list); | |
| 3894 _insert_list = insert_list; | |
| 3895 _insert_idx = insert_idx; | |
| 3896 } | |
| 3897 | |
| 3898 void MoveResolver::move_insert_position(LIR_List* insert_list, int insert_idx) { | |
| 3899 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: moving insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx)); | |
| 3900 | |
| 3901 if (_insert_list != NULL && (insert_list != _insert_list || insert_idx != _insert_idx)) { | |
| 3902 // insert position changed -> resolve current mappings | |
| 3903 resolve_mappings(); | |
| 3904 } | |
| 3905 | |
| 3906 if (insert_list != _insert_list) { | |
| 3907 // block changed -> append insertion_buffer because it is | |
| 3908 // bound to a specific block and create a new insertion_buffer | |
| 3909 append_insertion_buffer(); | |
| 3910 create_insertion_buffer(insert_list); | |
| 3911 } | |
| 3912 | |
| 3913 _insert_list = insert_list; | |
| 3914 _insert_idx = insert_idx; | |
| 3915 } | |
| 3916 | |
| 3917 void MoveResolver::add_mapping(Interval* from_interval, Interval* to_interval) { | |
| 3918 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: adding mapping from %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi())); | |
| 3919 | |
| 3920 _mapping_from.append(from_interval); | |
| 3921 _mapping_from_opr.append(LIR_OprFact::illegalOpr); | |
| 3922 _mapping_to.append(to_interval); | |
| 3923 } | |
| 3924 | |
| 3925 | |
| 3926 void MoveResolver::add_mapping(LIR_Opr from_opr, Interval* to_interval) { | |
| 3927 TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: adding mapping from "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi())); | |
| 3928 assert(from_opr->is_constant(), "only for constants"); | |
| 3929 | |
| 3930 _mapping_from.append(NULL); | |
| 3931 _mapping_from_opr.append(from_opr); | |
| 3932 _mapping_to.append(to_interval); | |
| 3933 } | |
| 3934 | |
| 3935 void MoveResolver::resolve_and_append_moves() { | |
| 3936 if (has_mappings()) { | |
| 3937 resolve_mappings(); | |
| 3938 } | |
| 3939 append_insertion_buffer(); | |
| 3940 } | |
| 3941 | |
| 3942 | |
| 3943 | |
| 3944 // **** Implementation of Range ************************************* | |
| 3945 | |
| 3946 Range::Range(int from, int to, Range* next) : | |
| 3947 _from(from), | |
| 3948 _to(to), | |
| 3949 _next(next) | |
| 3950 { | |
| 3951 } | |
| 3952 | |
| 3953 // initialize sentinel | |
| 3954 Range* Range::_end = NULL; | |
| 1584 | 3955 void Range::initialize(Arena* arena) { |
| 3956 _end = new (arena) Range(max_jint, max_jint, NULL); | |
| 0 | 3957 } |
| 3958 | |
| 3959 int Range::intersects_at(Range* r2) const { | |
| 3960 const Range* r1 = this; | |
| 3961 | |
| 3962 assert(r1 != NULL && r2 != NULL, "null ranges not allowed"); | |
| 3963 assert(r1 != _end && r2 != _end, "empty ranges not allowed"); | |
| 3964 | |
| 3965 do { | |
| 3966 if (r1->from() < r2->from()) { | |
| 3967 if (r1->to() <= r2->from()) { | |
| 3968 r1 = r1->next(); if (r1 == _end) return -1; | |
| 3969 } else { | |
| 3970 return r2->from(); | |
| 3971 } | |
| 3972 } else if (r2->from() < r1->from()) { | |
| 3973 if (r2->to() <= r1->from()) { | |
| 3974 r2 = r2->next(); if (r2 == _end) return -1; | |
| 3975 } else { | |
| 3976 return r1->from(); | |
| 3977 } | |
| 3978 } else { // r1->from() == r2->from() | |
| 3979 if (r1->from() == r1->to()) { | |
| 3980 r1 = r1->next(); if (r1 == _end) return -1; | |
| 3981 } else if (r2->from() == r2->to()) { | |
| 3982 r2 = r2->next(); if (r2 == _end) return -1; | |
| 3983 } else { | |
| 3984 return r1->from(); | |
| 3985 } | |
| 3986 } | |
| 3987 } while (true); | |
| 3988 } | |
| 3989 | |
| 3990 #ifndef PRODUCT | |
| 3991 void Range::print(outputStream* out) const { | |
| 3992 out->print("[%d, %d[ ", _from, _to); | |
| 3993 } | |
| 3994 #endif | |
| 3995 | |
| 3996 | |
| 3997 | |
| 3998 // **** Implementation of Interval ********************************** | |
| 3999 | |
| 4000 // initialize sentinel | |
| 4001 Interval* Interval::_end = NULL; | |
| 1584 | 4002 void Interval::initialize(Arena* arena) { |
| 4003 Range::initialize(arena); | |
| 4004 _end = new (arena) Interval(-1); | |
| 0 | 4005 } |
| 4006 | |
| 4007 Interval::Interval(int reg_num) : | |
| 4008 _reg_num(reg_num), | |
| 4009 _type(T_ILLEGAL), | |
| 4010 _first(Range::end()), | |
| 4011 _use_pos_and_kinds(12), | |
| 4012 _current(Range::end()), | |
| 4013 _next(_end), | |
| 4014 _state(invalidState), | |
| 4015 _assigned_reg(LinearScan::any_reg), | |
| 4016 _assigned_regHi(LinearScan::any_reg), | |
| 4017 _cached_to(-1), | |
| 4018 _cached_opr(LIR_OprFact::illegalOpr), | |
| 4019 _cached_vm_reg(VMRegImpl::Bad()), | |
| 4020 _split_children(0), | |
| 4021 _canonical_spill_slot(-1), | |
| 4022 _insert_move_when_activated(false), | |
| 4023 _register_hint(NULL), | |
| 4024 _spill_state(noDefinitionFound), | |
| 4025 _spill_definition_pos(-1) | |
| 4026 { | |
| 4027 _split_parent = this; | |
| 4028 _current_split_child = this; | |
| 4029 } | |
| 4030 | |
| 4031 int Interval::calc_to() { | |
| 4032 assert(_first != Range::end(), "interval has no range"); | |
| 4033 | |
| 4034 Range* r = _first; | |
| 4035 while (r->next() != Range::end()) { | |
| 4036 r = r->next(); | |
| 4037 } | |
| 4038 return r->to(); | |
| 4039 } | |
| 4040 | |
| 4041 | |
| 4042 #ifdef ASSERT | |
| 4043 // consistency check of split-children | |
| 4044 void Interval::check_split_children() { | |
| 4045 if (_split_children.length() > 0) { | |
| 4046 assert(is_split_parent(), "only split parents can have children"); | |
| 4047 | |
| 4048 for (int i = 0; i < _split_children.length(); i++) { | |
| 4049 Interval* i1 = _split_children.at(i); | |
| 4050 | |
| 4051 assert(i1->split_parent() == this, "not a split child of this interval"); | |
| 4052 assert(i1->type() == type(), "must be equal for all split children"); | |
| 4053 assert(i1->canonical_spill_slot() == canonical_spill_slot(), "must be equal for all split children"); | |
| 4054 | |
| 4055 for (int j = i + 1; j < _split_children.length(); j++) { | |
| 4056 Interval* i2 = _split_children.at(j); | |
| 4057 | |
| 4058 assert(i1->reg_num() != i2->reg_num(), "same register number"); | |
| 4059 | |
| 4060 if (i1->from() < i2->from()) { | |
| 4061 assert(i1->to() <= i2->from() && i1->to() < i2->to(), "intervals overlapping"); | |
| 4062 } else { | |
| 4063 assert(i2->from() < i1->from(), "intervals start at same op_id"); | |
| 4064 assert(i2->to() <= i1->from() && i2->to() < i1->to(), "intervals overlapping"); | |
| 4065 } | |
| 4066 } | |
| 4067 } | |
| 4068 } | |
| 4069 } | |
| 4070 #endif // ASSERT | |
| 4071 | |
| 4072 Interval* Interval::register_hint(bool search_split_child) const { | |
| 4073 if (!search_split_child) { | |
| 4074 return _register_hint; | |
| 4075 } | |
| 4076 | |
| 4077 if (_register_hint != NULL) { | |
| 4078 assert(_register_hint->is_split_parent(), "ony split parents are valid hint registers"); | |
| 4079 | |
| 4080 if (_register_hint->assigned_reg() >= 0 && _register_hint->assigned_reg() < LinearScan::nof_regs) { | |
| 4081 return _register_hint; | |
| 4082 | |
| 4083 } else if (_register_hint->_split_children.length() > 0) { | |
| 4084 // search the first split child that has a register assigned | |
| 4085 int len = _register_hint->_split_children.length(); | |
| 4086 for (int i = 0; i < len; i++) { | |
| 4087 Interval* cur = _register_hint->_split_children.at(i); | |
| 4088 | |
| 4089 if (cur->assigned_reg() >= 0 && cur->assigned_reg() < LinearScan::nof_regs) { | |
| 4090 return cur; | |
| 4091 } | |
| 4092 } | |
| 4093 } | |
| 4094 } | |
| 4095 | |
| 4096 // no hint interval found that has a register assigned | |
| 4097 return NULL; | |
| 4098 } | |
| 4099 | |
| 4100 | |
| 4101 Interval* Interval::split_child_at_op_id(int op_id, LIR_OpVisitState::OprMode mode) { | |
| 4102 assert(is_split_parent(), "can only be called for split parents"); | |
| 4103 assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)"); | |
| 4104 | |
| 4105 Interval* result; | |
| 4106 if (_split_children.length() == 0) { | |
| 4107 result = this; | |
| 4108 } else { | |
| 4109 result = NULL; | |
| 4110 int len = _split_children.length(); | |
| 4111 | |
| 4112 // in outputMode, the end of the interval (op_id == cur->to()) is not valid | |
| 4113 int to_offset = (mode == LIR_OpVisitState::outputMode ? 0 : 1); | |
| 4114 | |
| 4115 int i; | |
| 4116 for (i = 0; i < len; i++) { | |
| 4117 Interval* cur = _split_children.at(i); | |
| 4118 if (cur->from() <= op_id && op_id < cur->to() + to_offset) { | |
| 4119 if (i > 0) { | |
| 4120 // exchange current split child to start of list (faster access for next call) | |
| 4121 _split_children.at_put(i, _split_children.at(0)); | |
| 4122 _split_children.at_put(0, cur); | |
| 4123 } | |
| 4124 | |
| 4125 // interval found | |
| 4126 result = cur; | |
| 4127 break; | |
| 4128 } | |
| 4129 } | |
| 4130 | |
| 4131 #ifdef ASSERT | |
| 4132 for (i = 0; i < len; i++) { | |
| 4133 Interval* tmp = _split_children.at(i); | |
| 4134 if (tmp != result && tmp->from() <= op_id && op_id < tmp->to() + to_offset) { | |
| 4135 tty->print_cr("two valid result intervals found for op_id %d: %d and %d", op_id, result->reg_num(), tmp->reg_num()); | |
| 4136 result->print(); | |
| 4137 tmp->print(); | |
| 4138 assert(false, "two valid result intervals found"); | |
| 4139 } | |
| 4140 } | |
| 4141 #endif | |
| 4142 } | |
| 4143 | |
| 4144 assert(result != NULL, "no matching interval found"); | |
| 4145 assert(result->covers(op_id, mode), "op_id not covered by interval"); | |
| 4146 | |
| 4147 return result; | |
| 4148 } | |
| 4149 | |
| 4150 | |
| 4151 // returns the last split child that ends before the given op_id | |
| 4152 Interval* Interval::split_child_before_op_id(int op_id) { | |
| 4153 assert(op_id >= 0, "invalid op_id"); | |
| 4154 | |
| 4155 Interval* parent = split_parent(); | |
| 4156 Interval* result = NULL; | |
| 4157 | |
| 4158 int len = parent->_split_children.length(); | |
| 4159 assert(len > 0, "no split children available"); | |
| 4160 | |
| 4161 for (int i = len - 1; i >= 0; i--) { | |
| 4162 Interval* cur = parent->_split_children.at(i); | |
| 4163 if (cur->to() <= op_id && (result == NULL || result->to() < cur->to())) { | |
| 4164 result = cur; | |
| 4165 } | |
| 4166 } | |
| 4167 | |
| 4168 assert(result != NULL, "no split child found"); | |
| 4169 return result; | |
| 4170 } | |
| 4171 | |
| 4172 | |
| 4173 // checks if op_id is covered by any split child | |
| 4174 bool Interval::split_child_covers(int op_id, LIR_OpVisitState::OprMode mode) { | |
| 4175 assert(is_split_parent(), "can only be called for split parents"); | |
| 4176 assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)"); | |
| 4177 | |
| 4178 if (_split_children.length() == 0) { | |
| 4179 // simple case if interval was not split | |
| 4180 return covers(op_id, mode); | |
| 4181 | |
| 4182 } else { | |
| 4183 // extended case: check all split children | |
| 4184 int len = _split_children.length(); | |
| 4185 for (int i = 0; i < len; i++) { | |
| 4186 Interval* cur = _split_children.at(i); | |
| 4187 if (cur->covers(op_id, mode)) { | |
| 4188 return true; | |
| 4189 } | |
| 4190 } | |
| 4191 return false; | |
| 4192 } | |
| 4193 } | |
| 4194 | |
| 4195 | |
| 4196 // Note: use positions are sorted descending -> first use has highest index | |
| 4197 int Interval::first_usage(IntervalUseKind min_use_kind) const { | |
| 4198 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals"); | |
| 4199 | |
| 4200 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { | |
| 4201 if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) { | |
| 4202 return _use_pos_and_kinds.at(i); | |
| 4203 } | |
| 4204 } | |
| 4205 return max_jint; | |
| 4206 } | |
| 4207 | |
| 4208 int Interval::next_usage(IntervalUseKind min_use_kind, int from) const { | |
| 4209 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals"); | |
| 4210 | |
| 4211 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { | |
| 4212 if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) >= min_use_kind) { | |
| 4213 return _use_pos_and_kinds.at(i); | |
| 4214 } | |
| 4215 } | |
| 4216 return max_jint; | |
| 4217 } | |
| 4218 | |
| 4219 int Interval::next_usage_exact(IntervalUseKind exact_use_kind, int from) const { | |
| 4220 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals"); | |
| 4221 | |
| 4222 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { | |
| 4223 if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) == exact_use_kind) { | |
| 4224 return _use_pos_and_kinds.at(i); | |
| 4225 } | |
| 4226 } | |
| 4227 return max_jint; | |
| 4228 } | |
| 4229 | |
| 4230 int Interval::previous_usage(IntervalUseKind min_use_kind, int from) const { | |
| 4231 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals"); | |
| 4232 | |
| 4233 int prev = 0; | |
| 4234 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { | |
| 4235 if (_use_pos_and_kinds.at(i) > from) { | |
| 4236 return prev; | |
| 4237 } | |
| 4238 if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) { | |
| 4239 prev = _use_pos_and_kinds.at(i); | |
| 4240 } | |
| 4241 } | |
| 4242 return prev; | |
| 4243 } | |
| 4244 | |
| 4245 void Interval::add_use_pos(int pos, IntervalUseKind use_kind) { | |
| 4246 assert(covers(pos, LIR_OpVisitState::inputMode), "use position not covered by live range"); | |
| 4247 | |
| 4248 // do not add use positions for precolored intervals because | |
| 4249 // they are never used | |
| 4250 if (use_kind != noUse && reg_num() >= LIR_OprDesc::vreg_base) { | |
| 4251 #ifdef ASSERT | |
| 4252 assert(_use_pos_and_kinds.length() % 2 == 0, "must be"); | |
| 4253 for (int i = 0; i < _use_pos_and_kinds.length(); i += 2) { | |
| 4254 assert(pos <= _use_pos_and_kinds.at(i), "already added a use-position with lower position"); | |
| 4255 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind"); | |
| 4256 if (i > 0) { | |
| 4257 assert(_use_pos_and_kinds.at(i) < _use_pos_and_kinds.at(i - 2), "not sorted descending"); | |
| 4258 } | |
| 4259 } | |
| 4260 #endif | |
| 4261 | |
| 4262 // Note: add_use is called in descending order, so list gets sorted | |
| 4263 // automatically by just appending new use positions | |
| 4264 int len = _use_pos_and_kinds.length(); | |
| 4265 if (len == 0 || _use_pos_and_kinds.at(len - 2) > pos) { | |
| 4266 _use_pos_and_kinds.append(pos); | |
| 4267 _use_pos_and_kinds.append(use_kind); | |
| 4268 } else if (_use_pos_and_kinds.at(len - 1) < use_kind) { | |
| 4269 assert(_use_pos_and_kinds.at(len - 2) == pos, "list not sorted correctly"); | |
| 4270 _use_pos_and_kinds.at_put(len - 1, use_kind); | |
| 4271 } | |
| 4272 } | |
| 4273 } | |
| 4274 | |
| 4275 void Interval::add_range(int from, int to) { | |
| 4276 assert(from < to, "invalid range"); | |
| 4277 assert(first() == Range::end() || to < first()->next()->from(), "not inserting at begin of interval"); | |
| 4278 assert(from <= first()->to(), "not inserting at begin of interval"); | |
| 4279 | |
| 4280 if (first()->from() <= to) { | |
| 4281 // join intersecting ranges | |
| 4282 first()->set_from(MIN2(from, first()->from())); | |
| 4283 first()->set_to (MAX2(to, first()->to())); | |
| 4284 } else { | |
| 4285 // insert new range | |
| 4286 _first = new Range(from, to, first()); | |
| 4287 } | |
| 4288 } | |
| 4289 | |
| 4290 Interval* Interval::new_split_child() { | |
| 4291 // allocate new interval | |
| 4292 Interval* result = new Interval(-1); | |
| 4293 result->set_type(type()); | |
| 4294 | |
| 4295 Interval* parent = split_parent(); | |
| 4296 result->_split_parent = parent; | |
| 4297 result->set_register_hint(parent); | |
| 4298 | |
| 4299 // insert new interval in children-list of parent | |
| 4300 if (parent->_split_children.length() == 0) { | |
| 4301 assert(is_split_parent(), "list must be initialized at first split"); | |
| 4302 | |
| 4303 parent->_split_children = IntervalList(4); | |
| 4304 parent->_split_children.append(this); | |
| 4305 } | |
| 4306 parent->_split_children.append(result); | |
| 4307 | |
| 4308 return result; | |
| 4309 } | |
| 4310 | |
| 4311 // split this interval at the specified position and return | |
| 4312 // the remainder as a new interval. | |
| 4313 // | |
| 4314 // when an interval is split, a bi-directional link is established between the original interval | |
| 4315 // (the split parent) and the intervals that are split off this interval (the split children) | |
| 4316 // When a split child is split again, the new created interval is also a direct child | |
| 4317 // of the original parent (there is no tree of split children stored, but a flat list) | |
| 4318 // All split children are spilled to the same stack slot (stored in _canonical_spill_slot) | |
| 4319 // | |
| 4320 // Note: The new interval has no valid reg_num | |
| 4321 Interval* Interval::split(int split_pos) { | |
| 4322 assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals"); | |
| 4323 | |
| 4324 // allocate new interval | |
| 4325 Interval* result = new_split_child(); | |
| 4326 | |
| 4327 // split the ranges | |
| 4328 Range* prev = NULL; | |
| 4329 Range* cur = _first; | |
| 4330 while (cur != Range::end() && cur->to() <= split_pos) { | |
| 4331 prev = cur; | |
| 4332 cur = cur->next(); | |
| 4333 } | |
| 4334 assert(cur != Range::end(), "split interval after end of last range"); | |
| 4335 | |
| 4336 if (cur->from() < split_pos) { | |
| 4337 result->_first = new Range(split_pos, cur->to(), cur->next()); | |
| 4338 cur->set_to(split_pos); | |
| 4339 cur->set_next(Range::end()); | |
| 4340 | |
| 4341 } else { | |
| 4342 assert(prev != NULL, "split before start of first range"); | |
| 4343 result->_first = cur; | |
| 4344 prev->set_next(Range::end()); | |
| 4345 } | |
| 4346 result->_current = result->_first; | |
| 4347 _cached_to = -1; // clear cached value | |
| 4348 | |
| 4349 // split list of use positions | |
| 4350 int total_len = _use_pos_and_kinds.length(); | |
| 4351 int start_idx = total_len - 2; | |
| 4352 while (start_idx >= 0 && _use_pos_and_kinds.at(start_idx) < split_pos) { | |
| 4353 start_idx -= 2; | |
| 4354 } | |
| 4355 | |
| 4356 intStack new_use_pos_and_kinds(total_len - start_idx); | |
| 4357 int i; | |
| 4358 for (i = start_idx + 2; i < total_len; i++) { | |
| 4359 new_use_pos_and_kinds.append(_use_pos_and_kinds.at(i)); | |
| 4360 } | |
| 4361 | |
| 4362 _use_pos_and_kinds.truncate(start_idx + 2); | |
| 4363 result->_use_pos_and_kinds = _use_pos_and_kinds; | |
| 4364 _use_pos_and_kinds = new_use_pos_and_kinds; | |
| 4365 | |
| 4366 #ifdef ASSERT | |
| 4367 assert(_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos"); | |
| 4368 assert(result->_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos"); | |
| 4369 assert(_use_pos_and_kinds.length() + result->_use_pos_and_kinds.length() == total_len, "missed some entries"); | |
| 4370 | |
| 4371 for (i = 0; i < _use_pos_and_kinds.length(); i += 2) { | |
| 4372 assert(_use_pos_and_kinds.at(i) < split_pos, "must be"); | |
| 4373 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind"); | |
| 4374 } | |
| 4375 for (i = 0; i < result->_use_pos_and_kinds.length(); i += 2) { | |
| 4376 assert(result->_use_pos_and_kinds.at(i) >= split_pos, "must be"); | |
| 4377 assert(result->_use_pos_and_kinds.at(i + 1) >= firstValidKind && result->_use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind"); | |
| 4378 } | |
| 4379 #endif | |
| 4380 | |
| 4381 return result; | |
| 4382 } | |
| 4383 | |
| 4384 // split this interval at the specified position and return | |
| 4385 // the head as a new interval (the original interval is the tail) | |
| 4386 // | |
| 4387 // Currently, only the first range can be split, and the new interval | |
| 4388 // must not have split positions | |
| 4389 Interval* Interval::split_from_start(int split_pos) { | |
| 4390 assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals"); | |
| 4391 assert(split_pos > from() && split_pos < to(), "can only split inside interval"); | |
| 4392 assert(split_pos > _first->from() && split_pos <= _first->to(), "can only split inside first range"); | |
| 4393 assert(first_usage(noUse) > split_pos, "can not split when use positions are present"); | |
| 4394 | |
| 4395 // allocate new interval | |
| 4396 Interval* result = new_split_child(); | |
| 4397 | |
| 4398 // the new created interval has only one range (checked by assertion above), | |
| 4399 // so the splitting of the ranges is very simple | |
| 4400 result->add_range(_first->from(), split_pos); | |
| 4401 | |
| 4402 if (split_pos == _first->to()) { | |
| 4403 assert(_first->next() != Range::end(), "must not be at end"); | |
| 4404 _first = _first->next(); | |
| 4405 } else { | |
| 4406 _first->set_from(split_pos); | |
| 4407 } | |
| 4408 | |
| 4409 return result; | |
| 4410 } | |
| 4411 | |
| 4412 | |
| 4413 // returns true if the op_id is inside the interval | |
| 4414 bool Interval::covers(int op_id, LIR_OpVisitState::OprMode mode) const { | |
| 4415 Range* cur = _first; | |
| 4416 | |
| 4417 while (cur != Range::end() && cur->to() < op_id) { | |
| 4418 cur = cur->next(); | |
| 4419 } | |
| 4420 if (cur != Range::end()) { | |
| 4421 assert(cur->to() != cur->next()->from(), "ranges not separated"); | |
| 4422 | |
| 4423 if (mode == LIR_OpVisitState::outputMode) { | |
| 4424 return cur->from() <= op_id && op_id < cur->to(); | |
| 4425 } else { | |
| 4426 return cur->from() <= op_id && op_id <= cur->to(); | |
| 4427 } | |
| 4428 } | |
| 4429 return false; | |
| 4430 } | |
| 4431 | |
| 4432 // returns true if the interval has any hole between hole_from and hole_to | |
| 4433 // (even if the hole has only the length 1) | |
| 4434 bool Interval::has_hole_between(int hole_from, int hole_to) { | |
| 4435 assert(hole_from < hole_to, "check"); | |
| 4436 assert(from() <= hole_from && hole_to <= to(), "index out of interval"); | |
| 4437 | |
| 4438 Range* cur = _first; | |
| 4439 while (cur != Range::end()) { | |
| 4440 assert(cur->to() < cur->next()->from(), "no space between ranges"); | |
| 4441 | |
| 4442 // hole-range starts before this range -> hole | |
| 4443 if (hole_from < cur->from()) { | |
| 4444 return true; | |
| 4445 | |
| 4446 // hole-range completely inside this range -> no hole | |
| 4447 } else if (hole_to <= cur->to()) { | |
| 4448 return false; | |
| 4449 | |
| 4450 // overlapping of hole-range with this range -> hole | |
| 4451 } else if (hole_from <= cur->to()) { | |
| 4452 return true; | |
| 4453 } | |
| 4454 | |
| 4455 cur = cur->next(); | |
| 4456 } | |
| 4457 | |
| 4458 return false; | |
| 4459 } | |
| 4460 | |
| 4461 | |
| 4462 #ifndef PRODUCT | |
| 4463 void Interval::print(outputStream* out) const { | |
| 4464 const char* SpillState2Name[] = { "no definition", "no spill store", "one spill store", "store at definition", "start in memory", "no optimization" }; | |
| 4465 const char* UseKind2Name[] = { "N", "L", "S", "M" }; | |
| 4466 | |
| 4467 const char* type_name; | |
| 4468 LIR_Opr opr = LIR_OprFact::illegal(); | |
| 4469 if (reg_num() < LIR_OprDesc::vreg_base) { | |
| 4470 type_name = "fixed"; | |
| 4471 // need a temporary operand for fixed intervals because type() cannot be called | |
| 4472 if (assigned_reg() >= pd_first_cpu_reg && assigned_reg() <= pd_last_cpu_reg) { | |
| 4473 opr = LIR_OprFact::single_cpu(assigned_reg()); | |
| 4474 } else if (assigned_reg() >= pd_first_fpu_reg && assigned_reg() <= pd_last_fpu_reg) { | |
| 4475 opr = LIR_OprFact::single_fpu(assigned_reg() - pd_first_fpu_reg); | |
| 304 | 4476 #ifdef X86 |
| 0 | 4477 } else if (assigned_reg() >= pd_first_xmm_reg && assigned_reg() <= pd_last_xmm_reg) { |
| 4478 opr = LIR_OprFact::single_xmm(assigned_reg() - pd_first_xmm_reg); | |
| 4479 #endif | |
| 4480 } else { | |
| 4481 ShouldNotReachHere(); | |
| 4482 } | |
| 4483 } else { | |
| 4484 type_name = type2name(type()); | |
| 4485 if (assigned_reg() != -1) { | |
| 4486 opr = LinearScan::calc_operand_for_interval(this); | |
| 4487 } | |
| 4488 } | |
| 4489 | |
| 4490 out->print("%d %s ", reg_num(), type_name); | |
| 4491 if (opr->is_valid()) { | |
| 4492 out->print("\""); | |
| 4493 opr->print(out); | |
| 4494 out->print("\" "); | |
| 4495 } | |
| 4496 out->print("%d %d ", split_parent()->reg_num(), (register_hint(false) != NULL ? register_hint(false)->reg_num() : -1)); | |
| 4497 | |
| 4498 // print ranges | |
| 4499 Range* cur = _first; | |
| 4500 while (cur != Range::end()) { | |
| 4501 cur->print(out); | |
| 4502 cur = cur->next(); | |
| 4503 assert(cur != NULL, "range list not closed with range sentinel"); | |
| 4504 } | |
| 4505 | |
| 4506 // print use positions | |
| 4507 int prev = 0; | |
| 4508 assert(_use_pos_and_kinds.length() % 2 == 0, "must be"); | |
| 4509 for (int i =_use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { | |
| 4510 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind"); | |
| 4511 assert(prev < _use_pos_and_kinds.at(i), "use positions not sorted"); | |
| 4512 | |
| 4513 out->print("%d %s ", _use_pos_and_kinds.at(i), UseKind2Name[_use_pos_and_kinds.at(i + 1)]); | |
| 4514 prev = _use_pos_and_kinds.at(i); | |
| 4515 } | |
| 4516 | |
| 4517 out->print(" \"%s\"", SpillState2Name[spill_state()]); | |
| 4518 out->cr(); | |
| 4519 } | |
| 4520 #endif | |
| 4521 | |
| 4522 | |
| 4523 | |
| 4524 // **** Implementation of IntervalWalker **************************** | |
| 4525 | |
| 4526 IntervalWalker::IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first) | |
| 4527 : _compilation(allocator->compilation()) | |
| 4528 , _allocator(allocator) | |
| 4529 { | |
| 4530 _unhandled_first[fixedKind] = unhandled_fixed_first; | |
| 4531 _unhandled_first[anyKind] = unhandled_any_first; | |
| 4532 _active_first[fixedKind] = Interval::end(); | |
| 4533 _inactive_first[fixedKind] = Interval::end(); | |
| 4534 _active_first[anyKind] = Interval::end(); | |
| 4535 _inactive_first[anyKind] = Interval::end(); | |
| 4536 _current_position = -1; | |
| 4537 _current = NULL; | |
| 4538 next_interval(); | |
| 4539 } | |
| 4540 | |
| 4541 | |
| 4542 // append interval at top of list | |
| 4543 void IntervalWalker::append_unsorted(Interval** list, Interval* interval) { | |
| 4544 interval->set_next(*list); *list = interval; | |
| 4545 } | |
| 4546 | |
| 4547 | |
| 4548 // append interval in order of current range from() | |
| 4549 void IntervalWalker::append_sorted(Interval** list, Interval* interval) { | |
| 4550 Interval* prev = NULL; | |
| 4551 Interval* cur = *list; | |
| 4552 while (cur->current_from() < interval->current_from()) { | |
| 4553 prev = cur; cur = cur->next(); | |
| 4554 } | |
| 4555 if (prev == NULL) { | |
| 4556 *list = interval; | |
| 4557 } else { | |
| 4558 prev->set_next(interval); | |
| 4559 } | |
| 4560 interval->set_next(cur); | |
| 4561 } | |
| 4562 | |
| 4563 void IntervalWalker::append_to_unhandled(Interval** list, Interval* interval) { | |
| 4564 assert(interval->from() >= current()->current_from(), "cannot append new interval before current walk position"); | |
| 4565 | |
| 4566 Interval* prev = NULL; | |
| 4567 Interval* cur = *list; | |
| 4568 while (cur->from() < interval->from() || (cur->from() == interval->from() && cur->first_usage(noUse) < interval->first_usage(noUse))) { | |
| 4569 prev = cur; cur = cur->next(); | |
| 4570 } | |
| 4571 if (prev == NULL) { | |
| 4572 *list = interval; | |
| 4573 } else { | |
| 4574 prev->set_next(interval); | |
| 4575 } | |
| 4576 interval->set_next(cur); | |
| 4577 } | |
| 4578 | |
| 4579 | |
| 4580 inline bool IntervalWalker::remove_from_list(Interval** list, Interval* i) { | |
| 4581 while (*list != Interval::end() && *list != i) { | |
| 4582 list = (*list)->next_addr(); | |
| 4583 } | |
| 4584 if (*list != Interval::end()) { | |
| 4585 assert(*list == i, "check"); | |
| 4586 *list = (*list)->next(); | |
| 4587 return true; | |
| 4588 } else { | |
| 4589 return false; | |
| 4590 } | |
| 4591 } | |
| 4592 | |
| 4593 void IntervalWalker::remove_from_list(Interval* i) { | |
| 4594 bool deleted; | |
| 4595 | |
| 4596 if (i->state() == activeState) { | |
| 4597 deleted = remove_from_list(active_first_addr(anyKind), i); | |
| 4598 } else { | |
| 4599 assert(i->state() == inactiveState, "invalid state"); | |
| 4600 deleted = remove_from_list(inactive_first_addr(anyKind), i); | |
| 4601 } | |
| 4602 | |
| 4603 assert(deleted, "interval has not been found in list"); | |
| 4604 } | |
| 4605 | |
| 4606 | |
| 4607 void IntervalWalker::walk_to(IntervalState state, int from) { | |
| 4608 assert (state == activeState || state == inactiveState, "wrong state"); | |
| 4609 for_each_interval_kind(kind) { | |
| 4610 Interval** prev = state == activeState ? active_first_addr(kind) : inactive_first_addr(kind); | |
| 4611 Interval* next = *prev; | |
| 4612 while (next->current_from() <= from) { | |
| 4613 Interval* cur = next; | |
| 4614 next = cur->next(); | |
| 4615 | |
| 4616 bool range_has_changed = false; | |
| 4617 while (cur->current_to() <= from) { | |
| 4618 cur->next_range(); | |
| 4619 range_has_changed = true; | |
| 4620 } | |
| 4621 | |
| 4622 // also handle move from inactive list to active list | |
| 4623 range_has_changed = range_has_changed || (state == inactiveState && cur->current_from() <= from); | |
| 4624 | |
| 4625 if (range_has_changed) { | |
| 4626 // remove cur from list | |
| 4627 *prev = next; | |
| 4628 if (cur->current_at_end()) { | |
| 4629 // move to handled state (not maintained as a list) | |
| 4630 cur->set_state(handledState); | |
| 4631 interval_moved(cur, kind, state, handledState); | |
| 4632 } else if (cur->current_from() <= from){ | |
| 4633 // sort into active list | |
| 4634 append_sorted(active_first_addr(kind), cur); | |
| 4635 cur->set_state(activeState); | |
| 4636 if (*prev == cur) { | |
| 4637 assert(state == activeState, "check"); | |
| 4638 prev = cur->next_addr(); | |
| 4639 } | |
| 4640 interval_moved(cur, kind, state, activeState); | |
| 4641 } else { | |
| 4642 // sort into inactive list | |
| 4643 append_sorted(inactive_first_addr(kind), cur); | |
| 4644 cur->set_state(inactiveState); | |
| 4645 if (*prev == cur) { | |
| 4646 assert(state == inactiveState, "check"); | |
| 4647 prev = cur->next_addr(); | |
| 4648 } | |
| 4649 interval_moved(cur, kind, state, inactiveState); | |
| 4650 } | |
| 4651 } else { | |
| 4652 prev = cur->next_addr(); | |
| 4653 continue; | |
| 4654 } | |
| 4655 } | |
| 4656 } | |
| 4657 } | |
| 4658 | |
| 4659 | |
| 4660 void IntervalWalker::next_interval() { | |
| 4661 IntervalKind kind; | |
| 4662 Interval* any = _unhandled_first[anyKind]; | |
| 4663 Interval* fixed = _unhandled_first[fixedKind]; | |
| 4664 | |
| 4665 if (any != Interval::end()) { | |
| 4666 // intervals may start at same position -> prefer fixed interval | |
| 4667 kind = fixed != Interval::end() && fixed->from() <= any->from() ? fixedKind : anyKind; | |
| 4668 | |
| 4669 assert (kind == fixedKind && fixed->from() <= any->from() || | |
| 4670 kind == anyKind && any->from() <= fixed->from(), "wrong interval!!!"); | |
| 4671 assert(any == Interval::end() || fixed == Interval::end() || any->from() != fixed->from() || kind == fixedKind, "if fixed and any-Interval start at same position, fixed must be processed first"); | |
| 4672 | |
| 4673 } else if (fixed != Interval::end()) { | |
| 4674 kind = fixedKind; | |
| 4675 } else { | |
| 4676 _current = NULL; return; | |
| 4677 } | |
| 4678 _current_kind = kind; | |
| 4679 _current = _unhandled_first[kind]; | |
| 4680 _unhandled_first[kind] = _current->next(); | |
| 4681 _current->set_next(Interval::end()); | |
| 4682 _current->rewind_range(); | |
| 4683 } | |
| 4684 | |
| 4685 | |
| 4686 void IntervalWalker::walk_to(int lir_op_id) { | |
| 4687 assert(_current_position <= lir_op_id, "can not walk backwards"); | |
| 4688 while (current() != NULL) { | |
| 4689 bool is_active = current()->from() <= lir_op_id; | |
| 4690 int id = is_active ? current()->from() : lir_op_id; | |
| 4691 | |
| 4692 TRACE_LINEAR_SCAN(2, if (_current_position < id) { tty->cr(); tty->print_cr("walk_to(%d) **************************************************************", id); }) | |
| 4693 | |
| 4694 // set _current_position prior to call of walk_to | |
| 4695 _current_position = id; | |
| 4696 | |
| 4697 // call walk_to even if _current_position == id | |
| 4698 walk_to(activeState, id); | |
| 4699 walk_to(inactiveState, id); | |
| 4700 | |
| 4701 if (is_active) { | |
| 4702 current()->set_state(activeState); | |
| 4703 if (activate_current()) { | |
| 4704 append_sorted(active_first_addr(current_kind()), current()); | |
| 4705 interval_moved(current(), current_kind(), unhandledState, activeState); | |
| 4706 } | |
| 4707 | |
| 4708 next_interval(); | |
| 4709 } else { | |
| 4710 return; | |
| 4711 } | |
| 4712 } | |
| 4713 } | |
| 4714 | |
| 4715 void IntervalWalker::interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to) { | |
| 4716 #ifndef PRODUCT | |
| 4717 if (TraceLinearScanLevel >= 4) { | |
| 4718 #define print_state(state) \ | |
| 4719 switch(state) {\ | |
| 4720 case unhandledState: tty->print("unhandled"); break;\ | |
| 4721 case activeState: tty->print("active"); break;\ | |
| 4722 case inactiveState: tty->print("inactive"); break;\ | |
| 4723 case handledState: tty->print("handled"); break;\ | |
| 4724 default: ShouldNotReachHere(); \ | |
| 4725 } | |
| 4726 | |
| 4727 print_state(from); tty->print(" to "); print_state(to); | |
| 4728 tty->fill_to(23); | |
| 4729 interval->print(); | |
| 4730 | |
| 4731 #undef print_state | |
| 4732 } | |
| 4733 #endif | |
| 4734 } | |
| 4735 | |
| 4736 | |
| 4737 | |
| 4738 // **** Implementation of LinearScanWalker ************************** | |
| 4739 | |
| 4740 LinearScanWalker::LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first) | |
| 4741 : IntervalWalker(allocator, unhandled_fixed_first, unhandled_any_first) | |
| 4742 , _move_resolver(allocator) | |
| 4743 { | |
| 4744 for (int i = 0; i < LinearScan::nof_regs; i++) { | |
| 4745 _spill_intervals[i] = new IntervalList(2); | |
| 4746 } | |
| 4747 } | |
| 4748 | |
| 4749 | |
| 4750 inline void LinearScanWalker::init_use_lists(bool only_process_use_pos) { | |
| 4751 for (int i = _first_reg; i <= _last_reg; i++) { | |
| 4752 _use_pos[i] = max_jint; | |
| 4753 | |
| 4754 if (!only_process_use_pos) { | |
| 4755 _block_pos[i] = max_jint; | |
| 4756 _spill_intervals[i]->clear(); | |
| 4757 } | |
| 4758 } | |
| 4759 } | |
| 4760 | |
| 4761 inline void LinearScanWalker::exclude_from_use(int reg) { | |
| 4762 assert(reg < LinearScan::nof_regs, "interval must have a register assigned (stack slots not allowed)"); | |
| 4763 if (reg >= _first_reg && reg <= _last_reg) { | |
| 4764 _use_pos[reg] = 0; | |
| 4765 } | |
| 4766 } | |
| 4767 inline void LinearScanWalker::exclude_from_use(Interval* i) { | |
| 4768 assert(i->assigned_reg() != any_reg, "interval has no register assigned"); | |
| 4769 | |
| 4770 exclude_from_use(i->assigned_reg()); | |
| 4771 exclude_from_use(i->assigned_regHi()); | |
| 4772 } | |
| 4773 | |
| 4774 inline void LinearScanWalker::set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos) { | |
| 4775 assert(use_pos != 0, "must use exclude_from_use to set use_pos to 0"); | |
| 4776 | |
| 4777 if (reg >= _first_reg && reg <= _last_reg) { | |
| 4778 if (_use_pos[reg] > use_pos) { | |
| 4779 _use_pos[reg] = use_pos; | |
| 4780 } | |
| 4781 if (!only_process_use_pos) { | |
| 4782 _spill_intervals[reg]->append(i); | |
| 4783 } | |
| 4784 } | |
| 4785 } | |
| 4786 inline void LinearScanWalker::set_use_pos(Interval* i, int use_pos, bool only_process_use_pos) { | |
| 4787 assert(i->assigned_reg() != any_reg, "interval has no register assigned"); | |
| 4788 if (use_pos != -1) { | |
| 4789 set_use_pos(i->assigned_reg(), i, use_pos, only_process_use_pos); | |
| 4790 set_use_pos(i->assigned_regHi(), i, use_pos, only_process_use_pos); | |
| 4791 } | |
| 4792 } | |
| 4793 | |
| 4794 inline void LinearScanWalker::set_block_pos(int reg, Interval* i, int block_pos) { | |
| 4795 if (reg >= _first_reg && reg <= _last_reg) { | |
| 4796 if (_block_pos[reg] > block_pos) { | |
| 4797 _block_pos[reg] = block_pos; | |
| 4798 } | |
| 4799 if (_use_pos[reg] > block_pos) { | |
| 4800 _use_pos[reg] = block_pos; | |
| 4801 } | |
| 4802 } | |
| 4803 } | |
| 4804 inline void LinearScanWalker::set_block_pos(Interval* i, int block_pos) { | |
| 4805 assert(i->assigned_reg() != any_reg, "interval has no register assigned"); | |
| 4806 if (block_pos != -1) { | |
| 4807 set_block_pos(i->assigned_reg(), i, block_pos); | |
| 4808 set_block_pos(i->assigned_regHi(), i, block_pos); | |
| 4809 } | |
| 4810 } | |
| 4811 | |
| 4812 | |
| 4813 void LinearScanWalker::free_exclude_active_fixed() { | |
| 4814 Interval* list = active_first(fixedKind); | |
| 4815 while (list != Interval::end()) { | |
| 4816 assert(list->assigned_reg() < LinearScan::nof_regs, "active interval must have a register assigned"); | |
| 4817 exclude_from_use(list); | |
| 4818 list = list->next(); | |
| 4819 } | |
| 4820 } | |
| 4821 | |
| 4822 void LinearScanWalker::free_exclude_active_any() { | |
| 4823 Interval* list = active_first(anyKind); | |
| 4824 while (list != Interval::end()) { | |
| 4825 exclude_from_use(list); | |
| 4826 list = list->next(); | |
| 4827 } | |
| 4828 } | |
| 4829 | |
| 4830 void LinearScanWalker::free_collect_inactive_fixed(Interval* cur) { | |
| 4831 Interval* list = inactive_first(fixedKind); | |
| 4832 while (list != Interval::end()) { | |
| 4833 if (cur->to() <= list->current_from()) { | |
| 4834 assert(list->current_intersects_at(cur) == -1, "must not intersect"); | |
| 4835 set_use_pos(list, list->current_from(), true); | |
| 4836 } else { | |
| 4837 set_use_pos(list, list->current_intersects_at(cur), true); | |
| 4838 } | |
| 4839 list = list->next(); | |
| 4840 } | |
| 4841 } | |
| 4842 | |
| 4843 void LinearScanWalker::free_collect_inactive_any(Interval* cur) { | |
| 4844 Interval* list = inactive_first(anyKind); | |
| 4845 while (list != Interval::end()) { | |
| 4846 set_use_pos(list, list->current_intersects_at(cur), true); | |
| 4847 list = list->next(); | |
| 4848 } | |
| 4849 } | |
| 4850 | |
| 4851 void LinearScanWalker::free_collect_unhandled(IntervalKind kind, Interval* cur) { | |
| 4852 Interval* list = unhandled_first(kind); | |
| 4853 while (list != Interval::end()) { | |
| 4854 set_use_pos(list, list->intersects_at(cur), true); | |
| 4855 if (kind == fixedKind && cur->to() <= list->from()) { | |
| 4856 set_use_pos(list, list->from(), true); | |
| 4857 } | |
| 4858 list = list->next(); | |
| 4859 } | |
| 4860 } | |
| 4861 | |
| 4862 void LinearScanWalker::spill_exclude_active_fixed() { | |
| 4863 Interval* list = active_first(fixedKind); | |
| 4864 while (list != Interval::end()) { | |
| 4865 exclude_from_use(list); | |
| 4866 list = list->next(); | |
| 4867 } | |
| 4868 } | |
| 4869 | |
| 4870 void LinearScanWalker::spill_block_unhandled_fixed(Interval* cur) { | |
| 4871 Interval* list = unhandled_first(fixedKind); | |
| 4872 while (list != Interval::end()) { | |
| 4873 set_block_pos(list, list->intersects_at(cur)); | |
| 4874 list = list->next(); | |
| 4875 } | |
| 4876 } | |
| 4877 | |
| 4878 void LinearScanWalker::spill_block_inactive_fixed(Interval* cur) { | |
| 4879 Interval* list = inactive_first(fixedKind); | |
| 4880 while (list != Interval::end()) { | |
| 4881 if (cur->to() > list->current_from()) { | |
| 4882 set_block_pos(list, list->current_intersects_at(cur)); | |
| 4883 } else { | |
| 4884 assert(list->current_intersects_at(cur) == -1, "invalid optimization: intervals intersect"); | |
| 4885 } | |
| 4886 | |
| 4887 list = list->next(); | |
| 4888 } | |
| 4889 } | |
| 4890 | |
| 4891 void LinearScanWalker::spill_collect_active_any() { | |
| 4892 Interval* list = active_first(anyKind); | |
| 4893 while (list != Interval::end()) { | |
| 4894 set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false); | |
| 4895 list = list->next(); | |
| 4896 } | |
| 4897 } | |
| 4898 | |
| 4899 void LinearScanWalker::spill_collect_inactive_any(Interval* cur) { | |
| 4900 Interval* list = inactive_first(anyKind); | |
| 4901 while (list != Interval::end()) { | |
| 4902 if (list->current_intersects(cur)) { | |
| 4903 set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false); | |
| 4904 } | |
| 4905 list = list->next(); | |
| 4906 } | |
| 4907 } | |
| 4908 | |
| 4909 | |
| 4910 void LinearScanWalker::insert_move(int op_id, Interval* src_it, Interval* dst_it) { | |
| 4911 // output all moves here. When source and target are equal, the move is | |
| 4912 // optimized away later in assign_reg_nums | |
| 4913 | |
| 4914 op_id = (op_id + 1) & ~1; | |
| 4915 BlockBegin* op_block = allocator()->block_of_op_with_id(op_id); | |
| 4916 assert(op_id > 0 && allocator()->block_of_op_with_id(op_id - 2) == op_block, "cannot insert move at block boundary"); | |
| 4917 | |
| 4918 // calculate index of instruction inside instruction list of current block | |
| 4919 // the minimal index (for a block with no spill moves) can be calculated because the | |
| 4920 // numbering of instructions is known. | |
| 4921 // When the block already contains spill moves, the index must be increased until the | |
| 4922 // correct index is reached. | |
| 4923 LIR_OpList* list = op_block->lir()->instructions_list(); | |
| 4924 int index = (op_id - list->at(0)->id()) / 2; | |
| 4925 assert(list->at(index)->id() <= op_id, "error in calculation"); | |
| 4926 | |
| 4927 while (list->at(index)->id() != op_id) { | |
| 4928 index++; | |
| 4929 assert(0 <= index && index < list->length(), "index out of bounds"); | |
| 4930 } | |
| 4931 assert(1 <= index && index < list->length(), "index out of bounds"); | |
| 4932 assert(list->at(index)->id() == op_id, "error in calculation"); | |
| 4933 | |
| 4934 // insert new instruction before instruction at position index | |
| 4935 _move_resolver.move_insert_position(op_block->lir(), index - 1); | |
| 4936 _move_resolver.add_mapping(src_it, dst_it); | |
| 4937 } | |
| 4938 | |
| 4939 | |
| 4940 int LinearScanWalker::find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos) { | |
| 4941 int from_block_nr = min_block->linear_scan_number(); | |
| 4942 int to_block_nr = max_block->linear_scan_number(); | |
| 4943 | |
| 4944 assert(0 <= from_block_nr && from_block_nr < block_count(), "out of range"); | |
| 4945 assert(0 <= to_block_nr && to_block_nr < block_count(), "out of range"); | |
| 4946 assert(from_block_nr < to_block_nr, "must cross block boundary"); | |
| 4947 | |
| 4948 // Try to split at end of max_block. If this would be after | |
| 4949 // max_split_pos, then use the begin of max_block | |
| 4950 int optimal_split_pos = max_block->last_lir_instruction_id() + 2; | |
| 4951 if (optimal_split_pos > max_split_pos) { | |
| 4952 optimal_split_pos = max_block->first_lir_instruction_id(); | |
| 4953 } | |
| 4954 | |
| 4955 int min_loop_depth = max_block->loop_depth(); | |
| 4956 for (int i = to_block_nr - 1; i >= from_block_nr; i--) { | |
| 4957 BlockBegin* cur = block_at(i); | |
| 4958 | |
| 4959 if (cur->loop_depth() < min_loop_depth) { | |
| 4960 // block with lower loop-depth found -> split at the end of this block | |
| 4961 min_loop_depth = cur->loop_depth(); | |
| 4962 optimal_split_pos = cur->last_lir_instruction_id() + 2; | |
| 4963 } | |
| 4964 } | |
| 4965 assert(optimal_split_pos > allocator()->max_lir_op_id() || allocator()->is_block_begin(optimal_split_pos), "algorithm must move split pos to block boundary"); | |
| 4966 | |
| 4967 return optimal_split_pos; | |
| 4968 } | |
| 4969 | |
| 4970 | |
| 4971 int LinearScanWalker::find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization) { | |
| 4972 int optimal_split_pos = -1; | |
| 4973 if (min_split_pos == max_split_pos) { | |
| 4974 // trivial case, no optimization of split position possible | |
| 4975 TRACE_LINEAR_SCAN(4, tty->print_cr(" min-pos and max-pos are equal, no optimization possible")); | |
| 4976 optimal_split_pos = min_split_pos; | |
| 4977 | |
| 4978 } else { | |
| 4979 assert(min_split_pos < max_split_pos, "must be true then"); | |
| 4980 assert(min_split_pos > 0, "cannot access min_split_pos - 1 otherwise"); | |
| 4981 | |
| 4982 // reason for using min_split_pos - 1: when the minimal split pos is exactly at the | |
| 4983 // beginning of a block, then min_split_pos is also a possible split position. | |
| 4984 // Use the block before as min_block, because then min_block->last_lir_instruction_id() + 2 == min_split_pos | |
| 4985 BlockBegin* min_block = allocator()->block_of_op_with_id(min_split_pos - 1); | |
| 4986 | |
| 4987 // reason for using max_split_pos - 1: otherwise there would be an assertion failure | |
| 4988 // when an interval ends at the end of the last block of the method | |
| 4989 // (in this case, max_split_pos == allocator()->max_lir_op_id() + 2, and there is no | |
| 4990 // block at this op_id) | |
| 4991 BlockBegin* max_block = allocator()->block_of_op_with_id(max_split_pos - 1); | |
| 4992 | |
| 4993 assert(min_block->linear_scan_number() <= max_block->linear_scan_number(), "invalid order"); | |
| 4994 if (min_block == max_block) { | |
| 4995 // split position cannot be moved to block boundary, so split as late as possible | |
| 4996 TRACE_LINEAR_SCAN(4, tty->print_cr(" cannot move split pos to block boundary because min_pos and max_pos are in same block")); | |
| 4997 optimal_split_pos = max_split_pos; | |
| 4998 | |
| 4999 } else if (it->has_hole_between(max_split_pos - 1, max_split_pos) && !allocator()->is_block_begin(max_split_pos)) { | |
| 5000 // Do not move split position if the interval has a hole before max_split_pos. | |
| 5001 // Intervals resulting from Phi-Functions have more than one definition (marked | |
| 5002 // as mustHaveRegister) with a hole before each definition. When the register is needed | |
| 5003 // for the second definition, an earlier reloading is unnecessary. | |
| 5004 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has hole just before max_split_pos, so splitting at max_split_pos")); | |
| 5005 optimal_split_pos = max_split_pos; | |
| 5006 | |
| 5007 } else { | |
| 5008 // seach optimal block boundary between min_split_pos and max_split_pos | |
| 5009 TRACE_LINEAR_SCAN(4, tty->print_cr(" moving split pos to optimal block boundary between block B%d and B%d", min_block->block_id(), max_block->block_id())); | |
| 5010 | |
| 5011 if (do_loop_optimization) { | |
| 5012 // Loop optimization: if a loop-end marker is found between min- and max-position, | |
| 5013 // then split before this loop | |
| 5014 int loop_end_pos = it->next_usage_exact(loopEndMarker, min_block->last_lir_instruction_id() + 2); | |
| 5015 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization: loop end found at pos %d", loop_end_pos)); | |
| 5016 | |
| 5017 assert(loop_end_pos > min_split_pos, "invalid order"); | |
| 5018 if (loop_end_pos < max_split_pos) { | |
| 5019 // loop-end marker found between min- and max-position | |
| 5020 // if it is not the end marker for the same loop as the min-position, then move | |
| 5021 // the max-position to this loop block. | |
| 5022 // Desired result: uses tagged as shouldHaveRegister inside a loop cause a reloading | |
| 5023 // of the interval (normally, only mustHaveRegister causes a reloading) | |
| 5024 BlockBegin* loop_block = allocator()->block_of_op_with_id(loop_end_pos); | |
| 5025 | |
| 5026 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval is used in loop that ends in block B%d, so trying to move max_block back from B%d to B%d", loop_block->block_id(), max_block->block_id(), loop_block->block_id())); | |
| 5027 assert(loop_block != min_block, "loop_block and min_block must be different because block boundary is needed between"); | |
| 5028 | |
| 5029 optimal_split_pos = find_optimal_split_pos(min_block, loop_block, loop_block->last_lir_instruction_id() + 2); | |
| 5030 if (optimal_split_pos == loop_block->last_lir_instruction_id() + 2) { | |
| 5031 optimal_split_pos = -1; | |
| 5032 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization not necessary")); | |
| 5033 } else { | |
| 5034 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization successful")); | |
| 5035 } | |
| 5036 } | |
| 5037 } | |
| 5038 | |
| 5039 if (optimal_split_pos == -1) { | |
| 5040 // not calculated by loop optimization | |
| 5041 optimal_split_pos = find_optimal_split_pos(min_block, max_block, max_split_pos); | |
| 5042 } | |
| 5043 } | |
| 5044 } | |
| 5045 TRACE_LINEAR_SCAN(4, tty->print_cr(" optimal split position: %d", optimal_split_pos)); | |
| 5046 | |
| 5047 return optimal_split_pos; | |
| 5048 } | |
| 5049 | |
| 5050 | |
| 5051 /* | |
| 5052 split an interval at the optimal position between min_split_pos and | |
| 5053 max_split_pos in two parts: | |
| 5054 1) the left part has already a location assigned | |
| 5055 2) the right part is sorted into to the unhandled-list | |
| 5056 */ | |
| 5057 void LinearScanWalker::split_before_usage(Interval* it, int min_split_pos, int max_split_pos) { | |
| 5058 TRACE_LINEAR_SCAN(2, tty->print ("----- splitting interval: "); it->print()); | |
| 5059 TRACE_LINEAR_SCAN(2, tty->print_cr(" between %d and %d", min_split_pos, max_split_pos)); | |
| 5060 | |
| 5061 assert(it->from() < min_split_pos, "cannot split at start of interval"); | |
| 5062 assert(current_position() < min_split_pos, "cannot split before current position"); | |
| 5063 assert(min_split_pos <= max_split_pos, "invalid order"); | |
| 5064 assert(max_split_pos <= it->to(), "cannot split after end of interval"); | |
| 5065 | |
| 5066 int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, true); | |
| 5067 | |
| 5068 assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range"); | |
| 5069 assert(optimal_split_pos <= it->to(), "cannot split after end of interval"); | |
| 5070 assert(optimal_split_pos > it->from(), "cannot split at start of interval"); | |
| 5071 | |
| 5072 if (optimal_split_pos == it->to() && it->next_usage(mustHaveRegister, min_split_pos) == max_jint) { | |
| 5073 // the split position would be just before the end of the interval | |
| 5074 // -> no split at all necessary | |
| 5075 TRACE_LINEAR_SCAN(4, tty->print_cr(" no split necessary because optimal split position is at end of interval")); | |
| 5076 return; | |
| 5077 } | |
| 5078 | |
| 5079 // must calculate this before the actual split is performed and before split position is moved to odd op_id | |
| 5080 bool move_necessary = !allocator()->is_block_begin(optimal_split_pos) && !it->has_hole_between(optimal_split_pos - 1, optimal_split_pos); | |
| 5081 | |
| 5082 if (!allocator()->is_block_begin(optimal_split_pos)) { | |
| 5083 // move position before actual instruction (odd op_id) | |
| 5084 optimal_split_pos = (optimal_split_pos - 1) | 1; | |
| 5085 } | |
| 5086 | |
| 5087 TRACE_LINEAR_SCAN(4, tty->print_cr(" splitting at position %d", optimal_split_pos)); | |
| 5088 assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary"); | |
| 5089 assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary"); | |
| 5090 | |
| 5091 Interval* split_part = it->split(optimal_split_pos); | |
| 5092 | |
| 5093 allocator()->append_interval(split_part); | |
| 5094 allocator()->copy_register_flags(it, split_part); | |
| 5095 split_part->set_insert_move_when_activated(move_necessary); | |
| 5096 append_to_unhandled(unhandled_first_addr(anyKind), split_part); | |
| 5097 | |
| 5098 TRACE_LINEAR_SCAN(2, tty->print_cr(" split interval in two parts (insert_move_when_activated: %d)", move_necessary)); | |
| 5099 TRACE_LINEAR_SCAN(2, tty->print (" "); it->print()); | |
| 5100 TRACE_LINEAR_SCAN(2, tty->print (" "); split_part->print()); | |
| 5101 } | |
| 5102 | |
| 5103 /* | |
| 5104 split an interval at the optimal position between min_split_pos and | |
| 5105 max_split_pos in two parts: | |
| 5106 1) the left part has already a location assigned | |
| 5107 2) the right part is always on the stack and therefore ignored in further processing | |
| 5108 */ | |
| 5109 void LinearScanWalker::split_for_spilling(Interval* it) { | |
| 5110 // calculate allowed range of splitting position | |
| 5111 int max_split_pos = current_position(); | |
| 5112 int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, max_split_pos) + 1, it->from()); | |
| 5113 | |
| 5114 TRACE_LINEAR_SCAN(2, tty->print ("----- splitting and spilling interval: "); it->print()); | |
| 5115 TRACE_LINEAR_SCAN(2, tty->print_cr(" between %d and %d", min_split_pos, max_split_pos)); | |
| 5116 | |
| 5117 assert(it->state() == activeState, "why spill interval that is not active?"); | |
| 5118 assert(it->from() <= min_split_pos, "cannot split before start of interval"); | |
| 5119 assert(min_split_pos <= max_split_pos, "invalid order"); | |
| 5120 assert(max_split_pos < it->to(), "cannot split at end end of interval"); | |
| 5121 assert(current_position() < it->to(), "interval must not end before current position"); | |
| 5122 | |
| 5123 if (min_split_pos == it->from()) { | |
| 5124 // the whole interval is never used, so spill it entirely to memory | |
| 5125 TRACE_LINEAR_SCAN(2, tty->print_cr(" spilling entire interval because split pos is at beginning of interval")); | |
| 5126 assert(it->first_usage(shouldHaveRegister) > current_position(), "interval must not have use position before current_position"); | |
| 5127 | |
| 5128 allocator()->assign_spill_slot(it); | |
| 5129 allocator()->change_spill_state(it, min_split_pos); | |
| 5130 | |
| 5131 // Also kick parent intervals out of register to memory when they have no use | |
| 5132 // position. This avoids short interval in register surrounded by intervals in | |
| 5133 // memory -> avoid useless moves from memory to register and back | |
| 5134 Interval* parent = it; | |
| 5135 while (parent != NULL && parent->is_split_child()) { | |
| 5136 parent = parent->split_child_before_op_id(parent->from()); | |
| 5137 | |
| 5138 if (parent->assigned_reg() < LinearScan::nof_regs) { | |
| 5139 if (parent->first_usage(shouldHaveRegister) == max_jint) { | |
| 5140 // parent is never used, so kick it out of its assigned register | |
| 5141 TRACE_LINEAR_SCAN(4, tty->print_cr(" kicking out interval %d out of its register because it is never used", parent->reg_num())); | |
| 5142 allocator()->assign_spill_slot(parent); | |
| 5143 } else { | |
| 5144 // do not go further back because the register is actually used by the interval | |
| 5145 parent = NULL; | |
| 5146 } | |
| 5147 } | |
| 5148 } | |
| 5149 | |
| 5150 } else { | |
| 5151 // search optimal split pos, split interval and spill only the right hand part | |
| 5152 int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, false); | |
| 5153 | |
| 5154 assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range"); | |
| 5155 assert(optimal_split_pos < it->to(), "cannot split at end of interval"); | |
| 5156 assert(optimal_split_pos >= it->from(), "cannot split before start of interval"); | |
| 5157 | |
| 5158 if (!allocator()->is_block_begin(optimal_split_pos)) { | |
| 5159 // move position before actual instruction (odd op_id) | |
| 5160 optimal_split_pos = (optimal_split_pos - 1) | 1; | |
| 5161 } | |
| 5162 | |
| 5163 TRACE_LINEAR_SCAN(4, tty->print_cr(" splitting at position %d", optimal_split_pos)); | |
| 5164 assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary"); | |
| 5165 assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary"); | |
| 5166 | |
| 5167 Interval* spilled_part = it->split(optimal_split_pos); | |
| 5168 allocator()->append_interval(spilled_part); | |
| 5169 allocator()->assign_spill_slot(spilled_part); | |
| 5170 allocator()->change_spill_state(spilled_part, optimal_split_pos); | |
| 5171 | |
| 5172 if (!allocator()->is_block_begin(optimal_split_pos)) { | |
| 5173 TRACE_LINEAR_SCAN(4, tty->print_cr(" inserting move from interval %d to %d", it->reg_num(), spilled_part->reg_num())); | |
| 5174 insert_move(optimal_split_pos, it, spilled_part); | |
| 5175 } | |
| 5176 | |
| 5177 // the current_split_child is needed later when moves are inserted for reloading | |
| 5178 assert(spilled_part->current_split_child() == it, "overwriting wrong current_split_child"); | |
| 5179 spilled_part->make_current_split_child(); | |
| 5180 | |
| 5181 TRACE_LINEAR_SCAN(2, tty->print_cr(" split interval in two parts")); | |
| 5182 TRACE_LINEAR_SCAN(2, tty->print (" "); it->print()); | |
| 5183 TRACE_LINEAR_SCAN(2, tty->print (" "); spilled_part->print()); | |
| 5184 } | |
| 5185 } | |
| 5186 | |
| 5187 | |
| 5188 void LinearScanWalker::split_stack_interval(Interval* it) { | |
| 5189 int min_split_pos = current_position() + 1; | |
| 5190 int max_split_pos = MIN2(it->first_usage(shouldHaveRegister), it->to()); | |
| 5191 | |
| 5192 split_before_usage(it, min_split_pos, max_split_pos); | |
| 5193 } | |
| 5194 | |
| 5195 void LinearScanWalker::split_when_partial_register_available(Interval* it, int register_available_until) { | |
| 5196 int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, register_available_until), it->from() + 1); | |
| 5197 int max_split_pos = register_available_until; | |
| 5198 | |
| 5199 split_before_usage(it, min_split_pos, max_split_pos); | |
| 5200 } | |
| 5201 | |
| 5202 void LinearScanWalker::split_and_spill_interval(Interval* it) { | |
| 5203 assert(it->state() == activeState || it->state() == inactiveState, "other states not allowed"); | |
| 5204 | |
| 5205 int current_pos = current_position(); | |
| 5206 if (it->state() == inactiveState) { | |
| 5207 // the interval is currently inactive, so no spill slot is needed for now. | |
| 5208 // when the split part is activated, the interval has a new chance to get a register, | |
| 5209 // so in the best case no stack slot is necessary | |
| 5210 assert(it->has_hole_between(current_pos - 1, current_pos + 1), "interval can not be inactive otherwise"); | |
| 5211 split_before_usage(it, current_pos + 1, current_pos + 1); | |
| 5212 | |
| 5213 } else { | |
| 5214 // search the position where the interval must have a register and split | |
| 5215 // at the optimal position before. | |
| 5216 // The new created part is added to the unhandled list and will get a register | |
| 5217 // when it is activated | |
| 5218 int min_split_pos = current_pos + 1; | |
| 5219 int max_split_pos = MIN2(it->next_usage(mustHaveRegister, min_split_pos), it->to()); | |
| 5220 | |
| 5221 split_before_usage(it, min_split_pos, max_split_pos); | |
| 5222 | |
| 5223 assert(it->next_usage(mustHaveRegister, current_pos) == max_jint, "the remaining part is spilled to stack and therefore has no register"); | |
| 5224 split_for_spilling(it); | |
| 5225 } | |
| 5226 } | |
| 5227 | |
| 5228 | |
| 5229 int LinearScanWalker::find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) { | |
| 5230 int min_full_reg = any_reg; | |
| 5231 int max_partial_reg = any_reg; | |
| 5232 | |
| 5233 for (int i = _first_reg; i <= _last_reg; i++) { | |
| 5234 if (i == ignore_reg) { | |
| 5235 // this register must be ignored | |
| 5236 | |
| 5237 } else if (_use_pos[i] >= interval_to) { | |
| 5238 // this register is free for the full interval | |
| 5239 if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) { | |
| 5240 min_full_reg = i; | |
| 5241 } | |
| 5242 } else if (_use_pos[i] > reg_needed_until) { | |
| 5243 // this register is at least free until reg_needed_until | |
| 5244 if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) { | |
| 5245 max_partial_reg = i; | |
| 5246 } | |
| 5247 } | |
| 5248 } | |
| 5249 | |
| 5250 if (min_full_reg != any_reg) { | |
| 5251 return min_full_reg; | |
| 5252 } else if (max_partial_reg != any_reg) { | |
| 5253 *need_split = true; | |
| 5254 return max_partial_reg; | |
| 5255 } else { | |
| 5256 return any_reg; | |
| 5257 } | |
| 5258 } | |
| 5259 | |
| 5260 int LinearScanWalker::find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) { | |
| 5261 assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm"); | |
| 5262 | |
| 5263 int min_full_reg = any_reg; | |
| 5264 int max_partial_reg = any_reg; | |
| 5265 | |
| 5266 for (int i = _first_reg; i < _last_reg; i+=2) { | |
| 5267 if (_use_pos[i] >= interval_to && _use_pos[i + 1] >= interval_to) { | |
| 5268 // this register is free for the full interval | |
| 5269 if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) { | |
| 5270 min_full_reg = i; | |
| 5271 } | |
| 5272 } else if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) { | |
| 5273 // this register is at least free until reg_needed_until | |
| 5274 if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) { | |
| 5275 max_partial_reg = i; | |
| 5276 } | |
| 5277 } | |
| 5278 } | |
| 5279 | |
| 5280 if (min_full_reg != any_reg) { | |
| 5281 return min_full_reg; | |
| 5282 } else if (max_partial_reg != any_reg) { | |
| 5283 *need_split = true; | |
| 5284 return max_partial_reg; | |
| 5285 } else { | |
| 5286 return any_reg; | |
| 5287 } | |
| 5288 } | |
| 5289 | |
| 5290 | |
| 5291 bool LinearScanWalker::alloc_free_reg(Interval* cur) { | |
| 5292 TRACE_LINEAR_SCAN(2, tty->print("trying to find free register for "); cur->print()); | |
| 5293 | |
| 5294 init_use_lists(true); | |
| 5295 free_exclude_active_fixed(); | |
| 5296 free_exclude_active_any(); | |
| 5297 free_collect_inactive_fixed(cur); | |
| 5298 free_collect_inactive_any(cur); | |
| 5299 // free_collect_unhandled(fixedKind, cur); | |
| 5300 assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0"); | |
| 5301 | |
| 5302 // _use_pos contains the start of the next interval that has this register assigned | |
| 5303 // (either as a fixed register or a normal allocated register in the past) | |
| 5304 // only intervals overlapping with cur are processed, non-overlapping invervals can be ignored safely | |
| 5305 TRACE_LINEAR_SCAN(4, tty->print_cr(" state of registers:")); | |
| 5306 TRACE_LINEAR_SCAN(4, for (int i = _first_reg; i <= _last_reg; i++) tty->print_cr(" reg %d: use_pos: %d", i, _use_pos[i])); | |
| 5307 | |
| 5308 int hint_reg, hint_regHi; | |
| 5309 Interval* register_hint = cur->register_hint(); | |
| 5310 if (register_hint != NULL) { | |
| 5311 hint_reg = register_hint->assigned_reg(); | |
| 5312 hint_regHi = register_hint->assigned_regHi(); | |
| 5313 | |
| 5314 if (allocator()->is_precolored_cpu_interval(register_hint)) { | |
| 5315 assert(hint_reg != any_reg && hint_regHi == any_reg, "must be for fixed intervals"); | |
| 5316 hint_regHi = hint_reg + 1; // connect e.g. eax-edx | |
| 5317 } | |
| 5318 TRACE_LINEAR_SCAN(4, tty->print(" hint registers %d, %d from interval ", hint_reg, hint_regHi); register_hint->print()); | |
| 5319 | |
| 5320 } else { | |
| 5321 hint_reg = any_reg; | |
| 5322 hint_regHi = any_reg; | |
| 5323 } | |
| 5324 assert(hint_reg == any_reg || hint_reg != hint_regHi, "hint reg and regHi equal"); | |
| 5325 assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned to interval"); | |
| 5326 | |
| 5327 // the register must be free at least until this position | |
| 5328 int reg_needed_until = cur->from() + 1; | |
| 5329 int interval_to = cur->to(); | |
| 5330 | |
| 5331 bool need_split = false; | |
| 5332 int split_pos = -1; | |
| 5333 int reg = any_reg; | |
| 5334 int regHi = any_reg; | |
| 5335 | |
| 5336 if (_adjacent_regs) { | |
| 5337 reg = find_free_double_reg(reg_needed_until, interval_to, hint_reg, &need_split); | |
| 5338 regHi = reg + 1; | |
| 5339 if (reg == any_reg) { | |
| 5340 return false; | |
| 5341 } | |
| 5342 split_pos = MIN2(_use_pos[reg], _use_pos[regHi]); | |
| 5343 | |
| 5344 } else { | |
| 5345 reg = find_free_reg(reg_needed_until, interval_to, hint_reg, any_reg, &need_split); | |
| 5346 if (reg == any_reg) { | |
| 5347 return false; | |
| 5348 } | |
| 5349 split_pos = _use_pos[reg]; | |
| 5350 | |
| 5351 if (_num_phys_regs == 2) { | |
| 5352 regHi = find_free_reg(reg_needed_until, interval_to, hint_regHi, reg, &need_split); | |
| 5353 | |
| 5354 if (_use_pos[reg] < interval_to && regHi == any_reg) { | |
| 5355 // do not split interval if only one register can be assigned until the split pos | |
| 5356 // (when one register is found for the whole interval, split&spill is only | |
| 5357 // performed for the hi register) | |
| 5358 return false; | |
| 5359 | |
| 5360 } else if (regHi != any_reg) { | |
| 5361 split_pos = MIN2(split_pos, _use_pos[regHi]); | |
| 5362 | |
| 5363 // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax | |
| 5364 if (reg > regHi) { | |
| 5365 int temp = reg; | |
| 5366 reg = regHi; | |
| 5367 regHi = temp; | |
| 5368 } | |
| 5369 } | |
| 5370 } | |
| 5371 } | |
| 5372 | |
| 5373 cur->assign_reg(reg, regHi); | |
| 5374 TRACE_LINEAR_SCAN(2, tty->print_cr("selected register %d, %d", reg, regHi)); | |
| 5375 | |
| 5376 assert(split_pos > 0, "invalid split_pos"); | |
| 5377 if (need_split) { | |
| 5378 // register not available for full interval, so split it | |
| 5379 split_when_partial_register_available(cur, split_pos); | |
| 5380 } | |
| 5381 | |
| 5382 // only return true if interval is completely assigned | |
| 5383 return _num_phys_regs == 1 || regHi != any_reg; | |
| 5384 } | |
| 5385 | |
| 5386 | |
| 5387 int LinearScanWalker::find_locked_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) { | |
| 5388 int max_reg = any_reg; | |
| 5389 | |
| 5390 for (int i = _first_reg; i <= _last_reg; i++) { | |
| 5391 if (i == ignore_reg) { | |
| 5392 // this register must be ignored | |
| 5393 | |
| 5394 } else if (_use_pos[i] > reg_needed_until) { | |
| 5395 if (max_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_reg] && max_reg != hint_reg)) { | |
| 5396 max_reg = i; | |
| 5397 } | |
| 5398 } | |
| 5399 } | |
| 5400 | |
| 5401 if (max_reg != any_reg && _block_pos[max_reg] <= interval_to) { | |
| 5402 *need_split = true; | |
| 5403 } | |
| 5404 | |
| 5405 return max_reg; | |
| 5406 } | |
| 5407 | |
| 5408 int LinearScanWalker::find_locked_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) { | |
| 5409 assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm"); | |
| 5410 | |
| 5411 int max_reg = any_reg; | |
| 5412 | |
| 5413 for (int i = _first_reg; i < _last_reg; i+=2) { | |
| 5414 if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) { | |
| 5415 if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) { | |
| 5416 max_reg = i; | |
| 5417 } | |
| 5418 } | |
| 5419 } | |
| 5420 | |
| 5421 if (_block_pos[max_reg] <= interval_to || _block_pos[max_reg + 1] <= interval_to) { | |
| 5422 *need_split = true; | |
| 5423 } | |
| 5424 | |
| 5425 return max_reg; | |
| 5426 } | |
| 5427 | |
| 5428 void LinearScanWalker::split_and_spill_intersecting_intervals(int reg, int regHi) { | |
| 5429 assert(reg != any_reg, "no register assigned"); | |
| 5430 | |
| 5431 for (int i = 0; i < _spill_intervals[reg]->length(); i++) { | |
| 5432 Interval* it = _spill_intervals[reg]->at(i); | |
| 5433 remove_from_list(it); | |
| 5434 split_and_spill_interval(it); | |
| 5435 } | |
| 5436 | |
| 5437 if (regHi != any_reg) { | |
| 5438 IntervalList* processed = _spill_intervals[reg]; | |
| 5439 for (int i = 0; i < _spill_intervals[regHi]->length(); i++) { | |
| 5440 Interval* it = _spill_intervals[regHi]->at(i); | |
| 5441 if (processed->index_of(it) == -1) { | |
| 5442 remove_from_list(it); | |
| 5443 split_and_spill_interval(it); | |
| 5444 } | |
| 5445 } | |
| 5446 } | |
| 5447 } | |
| 5448 | |
| 5449 | |
| 5450 // Split an Interval and spill it to memory so that cur can be placed in a register | |
| 5451 void LinearScanWalker::alloc_locked_reg(Interval* cur) { | |
| 5452 TRACE_LINEAR_SCAN(2, tty->print("need to split and spill to get register for "); cur->print()); | |
| 5453 | |
| 5454 // collect current usage of registers | |
| 5455 init_use_lists(false); | |
| 5456 spill_exclude_active_fixed(); | |
| 5457 // spill_block_unhandled_fixed(cur); | |
| 5458 assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0"); | |
| 5459 spill_block_inactive_fixed(cur); | |
| 5460 spill_collect_active_any(); | |
| 5461 spill_collect_inactive_any(cur); | |
| 5462 | |
| 5463 #ifndef PRODUCT | |
| 5464 if (TraceLinearScanLevel >= 4) { | |
| 5465 tty->print_cr(" state of registers:"); | |
| 5466 for (int i = _first_reg; i <= _last_reg; i++) { | |
| 5467 tty->print(" reg %d: use_pos: %d, block_pos: %d, intervals: ", i, _use_pos[i], _block_pos[i]); | |
| 5468 for (int j = 0; j < _spill_intervals[i]->length(); j++) { | |
| 5469 tty->print("%d ", _spill_intervals[i]->at(j)->reg_num()); | |
| 5470 } | |
| 5471 tty->cr(); | |
| 5472 } | |
| 5473 } | |
| 5474 #endif | |
| 5475 | |
| 5476 // the register must be free at least until this position | |
| 5477 int reg_needed_until = MIN2(cur->first_usage(mustHaveRegister), cur->from() + 1); | |
| 5478 int interval_to = cur->to(); | |
| 5479 assert (reg_needed_until > 0 && reg_needed_until < max_jint, "interval has no use"); | |
| 5480 | |
| 5481 int split_pos = 0; | |
| 5482 int use_pos = 0; | |
| 5483 bool need_split = false; | |
| 5484 int reg, regHi; | |
| 5485 | |
| 5486 if (_adjacent_regs) { | |
| 5487 reg = find_locked_double_reg(reg_needed_until, interval_to, any_reg, &need_split); | |
| 5488 regHi = reg + 1; | |
| 5489 | |
| 5490 if (reg != any_reg) { | |
| 5491 use_pos = MIN2(_use_pos[reg], _use_pos[regHi]); | |
| 5492 split_pos = MIN2(_block_pos[reg], _block_pos[regHi]); | |
| 5493 } | |
| 5494 } else { | |
| 5495 reg = find_locked_reg(reg_needed_until, interval_to, any_reg, cur->assigned_reg(), &need_split); | |
| 5496 regHi = any_reg; | |
| 5497 | |
| 5498 if (reg != any_reg) { | |
| 5499 use_pos = _use_pos[reg]; | |
| 5500 split_pos = _block_pos[reg]; | |
| 5501 | |
| 5502 if (_num_phys_regs == 2) { | |
| 5503 if (cur->assigned_reg() != any_reg) { | |
| 5504 regHi = reg; | |
| 5505 reg = cur->assigned_reg(); | |
| 5506 } else { | |
| 5507 regHi = find_locked_reg(reg_needed_until, interval_to, any_reg, reg, &need_split); | |
| 5508 if (regHi != any_reg) { | |
| 5509 use_pos = MIN2(use_pos, _use_pos[regHi]); | |
| 5510 split_pos = MIN2(split_pos, _block_pos[regHi]); | |
| 5511 } | |
| 5512 } | |
| 5513 | |
| 5514 if (regHi != any_reg && reg > regHi) { | |
| 5515 // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax | |
| 5516 int temp = reg; | |
| 5517 reg = regHi; | |
| 5518 regHi = temp; | |
| 5519 } | |
| 5520 } | |
| 5521 } | |
| 5522 } | |
| 5523 | |
| 5524 if (reg == any_reg || (_num_phys_regs == 2 && regHi == any_reg) || use_pos <= cur->first_usage(mustHaveRegister)) { | |
| 5525 // the first use of cur is later than the spilling position -> spill cur | |
| 5526 TRACE_LINEAR_SCAN(4, tty->print_cr("able to spill current interval. first_usage(register): %d, use_pos: %d", cur->first_usage(mustHaveRegister), use_pos)); | |
| 5527 | |
| 5528 if (cur->first_usage(mustHaveRegister) <= cur->from() + 1) { | |
| 5529 assert(false, "cannot spill interval that is used in first instruction (possible reason: no register found)"); | |
| 5530 // assign a reasonable register and do a bailout in product mode to avoid errors | |
| 5531 allocator()->assign_spill_slot(cur); | |
| 5532 BAILOUT("LinearScan: no register found"); | |
| 5533 } | |
| 5534 | |
| 5535 split_and_spill_interval(cur); | |
| 5536 } else { | |
| 5537 TRACE_LINEAR_SCAN(4, tty->print_cr("decided to use register %d, %d", reg, regHi)); | |
| 5538 assert(reg != any_reg && (_num_phys_regs == 1 || regHi != any_reg), "no register found"); | |
| 5539 assert(split_pos > 0, "invalid split_pos"); | |
| 5540 assert(need_split == false || split_pos > cur->from(), "splitting interval at from"); | |
| 5541 | |
| 5542 cur->assign_reg(reg, regHi); | |
| 5543 if (need_split) { | |
| 5544 // register not available for full interval, so split it | |
| 5545 split_when_partial_register_available(cur, split_pos); | |
| 5546 } | |
| 5547 | |
| 5548 // perform splitting and spilling for all affected intervalls | |
| 5549 split_and_spill_intersecting_intervals(reg, regHi); | |
| 5550 } | |
| 5551 } | |
| 5552 | |
| 5553 bool LinearScanWalker::no_allocation_possible(Interval* cur) { | |
| 304 | 5554 #ifdef X86 |
| 0 | 5555 // fast calculation of intervals that can never get a register because the |
| 5556 // the next instruction is a call that blocks all registers | |
| 5557 // Note: this does not work if callee-saved registers are available (e.g. on Sparc) | |
| 5558 | |
| 5559 // check if this interval is the result of a split operation | |
| 5560 // (an interval got a register until this position) | |
| 5561 int pos = cur->from(); | |
| 5562 if ((pos & 1) == 1) { | |
| 5563 // the current instruction is a call that blocks all registers | |
| 5564 if (pos < allocator()->max_lir_op_id() && allocator()->has_call(pos + 1)) { | |
| 5565 TRACE_LINEAR_SCAN(4, tty->print_cr(" free register cannot be available because all registers blocked by following call")); | |
| 5566 | |
| 5567 // safety check that there is really no register available | |
| 5568 assert(alloc_free_reg(cur) == false, "found a register for this interval"); | |
| 5569 return true; | |
| 5570 } | |
| 5571 | |
| 5572 } | |
| 5573 #endif | |
| 5574 return false; | |
| 5575 } | |
| 5576 | |
| 5577 void LinearScanWalker::init_vars_for_alloc(Interval* cur) { | |
| 5578 BasicType type = cur->type(); | |
| 5579 _num_phys_regs = LinearScan::num_physical_regs(type); | |
| 5580 _adjacent_regs = LinearScan::requires_adjacent_regs(type); | |
| 5581 | |
| 5582 if (pd_init_regs_for_alloc(cur)) { | |
| 5583 // the appropriate register range was selected. | |
| 5584 } else if (type == T_FLOAT || type == T_DOUBLE) { | |
| 5585 _first_reg = pd_first_fpu_reg; | |
| 5586 _last_reg = pd_last_fpu_reg; | |
| 5587 } else { | |
| 5588 _first_reg = pd_first_cpu_reg; | |
| 5589 _last_reg = pd_last_cpu_reg; | |
| 5590 } | |
| 5591 | |
| 5592 assert(0 <= _first_reg && _first_reg < LinearScan::nof_regs, "out of range"); | |
| 5593 assert(0 <= _last_reg && _last_reg < LinearScan::nof_regs, "out of range"); | |
| 5594 } | |
| 5595 | |
| 5596 | |
| 5597 bool LinearScanWalker::is_move(LIR_Op* op, Interval* from, Interval* to) { | |
| 5598 if (op->code() != lir_move) { | |
| 5599 return false; | |
| 5600 } | |
| 5601 assert(op->as_Op1() != NULL, "move must be LIR_Op1"); | |
| 5602 | |
| 5603 LIR_Opr in = ((LIR_Op1*)op)->in_opr(); | |
| 5604 LIR_Opr res = ((LIR_Op1*)op)->result_opr(); | |
| 5605 return in->is_virtual() && res->is_virtual() && in->vreg_number() == from->reg_num() && res->vreg_number() == to->reg_num(); | |
| 5606 } | |
| 5607 | |
| 5608 // optimization (especially for phi functions of nested loops): | |
| 5609 // assign same spill slot to non-intersecting intervals | |
| 5610 void LinearScanWalker::combine_spilled_intervals(Interval* cur) { | |
| 5611 if (cur->is_split_child()) { | |
| 5612 // optimization is only suitable for split parents | |
| 5613 return; | |
| 5614 } | |
| 5615 | |
| 5616 Interval* register_hint = cur->register_hint(false); | |
| 5617 if (register_hint == NULL) { | |
| 5618 // cur is not the target of a move, otherwise register_hint would be set | |
| 5619 return; | |
| 5620 } | |
| 5621 assert(register_hint->is_split_parent(), "register hint must be split parent"); | |
| 5622 | |
| 5623 if (cur->spill_state() != noOptimization || register_hint->spill_state() != noOptimization) { | |
| 5624 // combining the stack slots for intervals where spill move optimization is applied | |
| 5625 // is not benefitial and would cause problems | |
| 5626 return; | |
| 5627 } | |
| 5628 | |
| 5629 int begin_pos = cur->from(); | |
| 5630 int end_pos = cur->to(); | |
| 5631 if (end_pos > allocator()->max_lir_op_id() || (begin_pos & 1) != 0 || (end_pos & 1) != 0) { | |
| 5632 // safety check that lir_op_with_id is allowed | |
| 5633 return; | |
| 5634 } | |
| 5635 | |
| 5636 if (!is_move(allocator()->lir_op_with_id(begin_pos), register_hint, cur) || !is_move(allocator()->lir_op_with_id(end_pos), cur, register_hint)) { | |
| 5637 // cur and register_hint are not connected with two moves | |
| 5638 return; | |
| 5639 } | |
| 5640 | |
| 5641 Interval* begin_hint = register_hint->split_child_at_op_id(begin_pos, LIR_OpVisitState::inputMode); | |
| 5642 Interval* end_hint = register_hint->split_child_at_op_id(end_pos, LIR_OpVisitState::outputMode); | |
| 5643 if (begin_hint == end_hint || begin_hint->to() != begin_pos || end_hint->from() != end_pos) { | |
| 5644 // register_hint must be split, otherwise the re-writing of use positions does not work | |
| 5645 return; | |
| 5646 } | |
| 5647 | |
| 5648 assert(begin_hint->assigned_reg() != any_reg, "must have register assigned"); | |
| 5649 assert(end_hint->assigned_reg() == any_reg, "must not have register assigned"); | |
| 5650 assert(cur->first_usage(mustHaveRegister) == begin_pos, "must have use position at begin of interval because of move"); | |
| 5651 assert(end_hint->first_usage(mustHaveRegister) == end_pos, "must have use position at begin of interval because of move"); | |
| 5652 | |
| 5653 if (begin_hint->assigned_reg() < LinearScan::nof_regs) { | |
| 5654 // register_hint is not spilled at begin_pos, so it would not be benefitial to immediately spill cur | |
| 5655 return; | |
| 5656 } | |
| 5657 assert(register_hint->canonical_spill_slot() != -1, "must be set when part of interval was spilled"); | |
| 5658 | |
| 5659 // modify intervals such that cur gets the same stack slot as register_hint | |
| 5660 // delete use positions to prevent the intervals to get a register at beginning | |
| 5661 cur->set_canonical_spill_slot(register_hint->canonical_spill_slot()); | |
| 5662 cur->remove_first_use_pos(); | |
| 5663 end_hint->remove_first_use_pos(); | |
| 5664 } | |
| 5665 | |
| 5666 | |
| 5667 // allocate a physical register or memory location to an interval | |
| 5668 bool LinearScanWalker::activate_current() { | |
| 5669 Interval* cur = current(); | |
| 5670 bool result = true; | |
| 5671 | |
| 5672 TRACE_LINEAR_SCAN(2, tty->print ("+++++ activating interval "); cur->print()); | |
| 5673 TRACE_LINEAR_SCAN(4, tty->print_cr(" split_parent: %d, insert_move_when_activated: %d", cur->split_parent()->reg_num(), cur->insert_move_when_activated())); | |
| 5674 | |
| 5675 if (cur->assigned_reg() >= LinearScan::nof_regs) { | |
| 5676 // activating an interval that has a stack slot assigned -> split it at first use position | |
| 5677 // used for method parameters | |
| 5678 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has spill slot assigned (method parameter) -> split it before first use")); | |
| 5679 | |
| 5680 split_stack_interval(cur); | |
| 5681 result = false; | |
| 5682 | |
| 5683 } else if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::must_start_in_memory)) { | |
| 5684 // activating an interval that must start in a stack slot, but may get a register later | |
| 5685 // used for lir_roundfp: rounding is done by store to stack and reload later | |
| 5686 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval must start in stack slot -> split it before first use")); | |
| 5687 assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned"); | |
| 5688 | |
| 5689 allocator()->assign_spill_slot(cur); | |
| 5690 split_stack_interval(cur); | |
| 5691 result = false; | |
| 5692 | |
| 5693 } else if (cur->assigned_reg() == any_reg) { | |
| 5694 // interval has not assigned register -> normal allocation | |
| 5695 // (this is the normal case for most intervals) | |
| 5696 TRACE_LINEAR_SCAN(4, tty->print_cr(" normal allocation of register")); | |
| 5697 | |
| 5698 // assign same spill slot to non-intersecting intervals | |
| 5699 combine_spilled_intervals(cur); | |
| 5700 | |
| 5701 init_vars_for_alloc(cur); | |
| 5702 if (no_allocation_possible(cur) || !alloc_free_reg(cur)) { | |
| 5703 // no empty register available. | |
| 5704 // split and spill another interval so that this interval gets a register | |
| 5705 alloc_locked_reg(cur); | |
| 5706 } | |
| 5707 | |
| 5708 // spilled intervals need not be move to active-list | |
| 5709 if (cur->assigned_reg() >= LinearScan::nof_regs) { | |
| 5710 result = false; | |
| 5711 } | |
| 5712 } | |
| 5713 | |
| 5714 // load spilled values that become active from stack slot to register | |
| 5715 if (cur->insert_move_when_activated()) { | |
| 5716 assert(cur->is_split_child(), "must be"); | |
| 5717 assert(cur->current_split_child() != NULL, "must be"); | |
| 5718 assert(cur->current_split_child()->reg_num() != cur->reg_num(), "cannot insert move between same interval"); | |
| 5719 TRACE_LINEAR_SCAN(4, tty->print_cr("Inserting move from interval %d to %d because insert_move_when_activated is set", cur->current_split_child()->reg_num(), cur->reg_num())); | |
| 5720 | |
| 5721 insert_move(cur->from(), cur->current_split_child(), cur); | |
| 5722 } | |
| 5723 cur->make_current_split_child(); | |
| 5724 | |
| 5725 return result; // true = interval is moved to active list | |
| 5726 } | |
| 5727 | |
| 5728 | |
| 5729 // Implementation of EdgeMoveOptimizer | |
| 5730 | |
| 5731 EdgeMoveOptimizer::EdgeMoveOptimizer() : | |
| 5732 _edge_instructions(4), | |
| 5733 _edge_instructions_idx(4) | |
| 5734 { | |
| 5735 } | |
| 5736 | |
| 5737 void EdgeMoveOptimizer::optimize(BlockList* code) { | |
| 5738 EdgeMoveOptimizer optimizer = EdgeMoveOptimizer(); | |
| 5739 | |
| 5740 // ignore the first block in the list (index 0 is not processed) | |
| 5741 for (int i = code->length() - 1; i >= 1; i--) { | |
| 5742 BlockBegin* block = code->at(i); | |
| 5743 | |
| 5744 if (block->number_of_preds() > 1 && !block->is_set(BlockBegin::exception_entry_flag)) { | |
| 5745 optimizer.optimize_moves_at_block_end(block); | |
| 5746 } | |
| 5747 if (block->number_of_sux() == 2) { | |
| 5748 optimizer.optimize_moves_at_block_begin(block); | |
| 5749 } | |
| 5750 } | |
| 5751 } | |
| 5752 | |
| 5753 | |
| 5754 // clear all internal data structures | |
| 5755 void EdgeMoveOptimizer::init_instructions() { | |
| 5756 _edge_instructions.clear(); | |
| 5757 _edge_instructions_idx.clear(); | |
| 5758 } | |
| 5759 | |
| 5760 // append a lir-instruction-list and the index of the current operation in to the list | |
| 5761 void EdgeMoveOptimizer::append_instructions(LIR_OpList* instructions, int instructions_idx) { | |
| 5762 _edge_instructions.append(instructions); | |
| 5763 _edge_instructions_idx.append(instructions_idx); | |
| 5764 } | |
| 5765 | |
| 5766 // return the current operation of the given edge (predecessor or successor) | |
| 5767 LIR_Op* EdgeMoveOptimizer::instruction_at(int edge) { | |
| 5768 LIR_OpList* instructions = _edge_instructions.at(edge); | |
| 5769 int idx = _edge_instructions_idx.at(edge); | |
| 5770 | |
| 5771 if (idx < instructions->length()) { | |
| 5772 return instructions->at(idx); | |
| 5773 } else { | |
| 5774 return NULL; | |
| 5775 } | |
| 5776 } | |
| 5777 | |
| 5778 // removes the current operation of the given edge (predecessor or successor) | |
| 5779 void EdgeMoveOptimizer::remove_cur_instruction(int edge, bool decrement_index) { | |
| 5780 LIR_OpList* instructions = _edge_instructions.at(edge); | |
| 5781 int idx = _edge_instructions_idx.at(edge); | |
| 5782 instructions->remove_at(idx); | |
| 5783 | |
| 5784 if (decrement_index) { | |
| 5785 _edge_instructions_idx.at_put(edge, idx - 1); | |
| 5786 } | |
| 5787 } | |
| 5788 | |
| 5789 | |
| 5790 bool EdgeMoveOptimizer::operations_different(LIR_Op* op1, LIR_Op* op2) { | |
| 5791 if (op1 == NULL || op2 == NULL) { | |
| 5792 // at least one block is already empty -> no optimization possible | |
| 5793 return true; | |
| 5794 } | |
| 5795 | |
| 5796 if (op1->code() == lir_move && op2->code() == lir_move) { | |
| 5797 assert(op1->as_Op1() != NULL, "move must be LIR_Op1"); | |
| 5798 assert(op2->as_Op1() != NULL, "move must be LIR_Op1"); | |
| 5799 LIR_Op1* move1 = (LIR_Op1*)op1; | |
| 5800 LIR_Op1* move2 = (LIR_Op1*)op2; | |
| 5801 if (move1->info() == move2->info() && move1->in_opr() == move2->in_opr() && move1->result_opr() == move2->result_opr()) { | |
| 5802 // these moves are exactly equal and can be optimized | |
| 5803 return false; | |
| 5804 } | |
| 5805 | |
| 5806 } else if (op1->code() == lir_fxch && op2->code() == lir_fxch) { | |
| 5807 assert(op1->as_Op1() != NULL, "fxch must be LIR_Op1"); | |
| 5808 assert(op2->as_Op1() != NULL, "fxch must be LIR_Op1"); | |
| 5809 LIR_Op1* fxch1 = (LIR_Op1*)op1; | |
| 5810 LIR_Op1* fxch2 = (LIR_Op1*)op2; | |
| 5811 if (fxch1->in_opr()->as_jint() == fxch2->in_opr()->as_jint()) { | |
| 5812 // equal FPU stack operations can be optimized | |
| 5813 return false; | |
| 5814 } | |
| 5815 | |
| 5816 } else if (op1->code() == lir_fpop_raw && op2->code() == lir_fpop_raw) { | |
| 5817 // equal FPU stack operations can be optimized | |
| 5818 return false; | |
| 5819 } | |
| 5820 | |
| 5821 // no optimization possible | |
| 5822 return true; | |
| 5823 } | |
| 5824 | |
| 5825 void EdgeMoveOptimizer::optimize_moves_at_block_end(BlockBegin* block) { | |
| 5826 TRACE_LINEAR_SCAN(4, tty->print_cr("optimizing moves at end of block B%d", block->block_id())); | |
| 5827 | |
| 5828 if (block->is_predecessor(block)) { | |
| 5829 // currently we can't handle this correctly. | |
| 5830 return; | |
| 5831 } | |
| 5832 | |
| 5833 init_instructions(); | |
| 5834 int num_preds = block->number_of_preds(); | |
| 5835 assert(num_preds > 1, "do not call otherwise"); | |
| 5836 assert(!block->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed"); | |
| 5837 | |
| 5838 // setup a list with the lir-instructions of all predecessors | |
| 5839 int i; | |
| 5840 for (i = 0; i < num_preds; i++) { | |
| 5841 BlockBegin* pred = block->pred_at(i); | |
| 5842 LIR_OpList* pred_instructions = pred->lir()->instructions_list(); | |
| 5843 | |
| 5844 if (pred->number_of_sux() != 1) { | |
| 5845 // this can happen with switch-statements where multiple edges are between | |
| 5846 // the same blocks. | |
| 5847 return; | |
| 5848 } | |
| 5849 | |
| 5850 assert(pred->number_of_sux() == 1, "can handle only one successor"); | |
| 5851 assert(pred->sux_at(0) == block, "invalid control flow"); | |
| 5852 assert(pred_instructions->last()->code() == lir_branch, "block with successor must end with branch"); | |
| 5853 assert(pred_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch"); | |
| 5854 assert(pred_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch"); | |
| 5855 | |
| 5856 if (pred_instructions->last()->info() != NULL) { | |
| 5857 // can not optimize instructions when debug info is needed | |
| 5858 return; | |
| 5859 } | |
| 5860 | |
| 5861 // ignore the unconditional branch at the end of the block | |
| 5862 append_instructions(pred_instructions, pred_instructions->length() - 2); | |
| 5863 } | |
| 5864 | |
| 5865 | |
| 5866 // process lir-instructions while all predecessors end with the same instruction | |
| 5867 while (true) { | |
| 5868 LIR_Op* op = instruction_at(0); | |
| 5869 for (i = 1; i < num_preds; i++) { | |
| 5870 if (operations_different(op, instruction_at(i))) { | |
| 5871 // these instructions are different and cannot be optimized -> | |
| 5872 // no further optimization possible | |
| 5873 return; | |
| 5874 } | |
| 5875 } | |
| 5876 | |
| 5877 TRACE_LINEAR_SCAN(4, tty->print("found instruction that is equal in all %d predecessors: ", num_preds); op->print()); | |
| 5878 | |
| 5879 // insert the instruction at the beginning of the current block | |
| 5880 block->lir()->insert_before(1, op); | |
| 5881 | |
| 5882 // delete the instruction at the end of all predecessors | |
| 5883 for (i = 0; i < num_preds; i++) { | |
| 5884 remove_cur_instruction(i, true); | |
| 5885 } | |
| 5886 } | |
| 5887 } | |
| 5888 | |
| 5889 | |
| 5890 void EdgeMoveOptimizer::optimize_moves_at_block_begin(BlockBegin* block) { | |
| 5891 TRACE_LINEAR_SCAN(4, tty->print_cr("optimization moves at begin of block B%d", block->block_id())); | |
| 5892 | |
| 5893 init_instructions(); | |
| 5894 int num_sux = block->number_of_sux(); | |
| 5895 | |
| 5896 LIR_OpList* cur_instructions = block->lir()->instructions_list(); | |
| 5897 | |
| 5898 assert(num_sux == 2, "method should not be called otherwise"); | |
| 5899 assert(cur_instructions->last()->code() == lir_branch, "block with successor must end with branch"); | |
| 5900 assert(cur_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch"); | |
| 5901 assert(cur_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch"); | |
| 5902 | |
| 5903 if (cur_instructions->last()->info() != NULL) { | |
| 5904 // can no optimize instructions when debug info is needed | |
| 5905 return; | |
| 5906 } | |
| 5907 | |
| 5908 LIR_Op* branch = cur_instructions->at(cur_instructions->length() - 2); | |
| 5909 if (branch->info() != NULL || (branch->code() != lir_branch && branch->code() != lir_cond_float_branch)) { | |
| 5910 // not a valid case for optimization | |
| 5911 // currently, only blocks that end with two branches (conditional branch followed | |
| 5912 // by unconditional branch) are optimized | |
| 5913 return; | |
| 5914 } | |
| 5915 | |
| 5916 // now it is guaranteed that the block ends with two branch instructions. | |
| 5917 // the instructions are inserted at the end of the block before these two branches | |
| 5918 int insert_idx = cur_instructions->length() - 2; | |
| 5919 | |
| 5920 int i; | |
| 5921 #ifdef ASSERT | |
| 5922 for (i = insert_idx - 1; i >= 0; i--) { | |
| 5923 LIR_Op* op = cur_instructions->at(i); | |
| 5924 if ((op->code() == lir_branch || op->code() == lir_cond_float_branch) && ((LIR_OpBranch*)op)->block() != NULL) { | |
| 5925 assert(false, "block with two successors can have only two branch instructions"); | |
| 5926 } | |
| 5927 } | |
| 5928 #endif | |
| 5929 | |
| 5930 // setup a list with the lir-instructions of all successors | |
| 5931 for (i = 0; i < num_sux; i++) { | |
| 5932 BlockBegin* sux = block->sux_at(i); | |
| 5933 LIR_OpList* sux_instructions = sux->lir()->instructions_list(); | |
| 5934 | |
| 5935 assert(sux_instructions->at(0)->code() == lir_label, "block must start with label"); | |
| 5936 | |
| 5937 if (sux->number_of_preds() != 1) { | |
| 5938 // this can happen with switch-statements where multiple edges are between | |
| 5939 // the same blocks. | |
| 5940 return; | |
| 5941 } | |
| 5942 assert(sux->pred_at(0) == block, "invalid control flow"); | |
| 5943 assert(!sux->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed"); | |
| 5944 | |
| 5945 // ignore the label at the beginning of the block | |
| 5946 append_instructions(sux_instructions, 1); | |
| 5947 } | |
| 5948 | |
| 5949 // process lir-instructions while all successors begin with the same instruction | |
| 5950 while (true) { | |
| 5951 LIR_Op* op = instruction_at(0); | |
| 5952 for (i = 1; i < num_sux; i++) { | |
| 5953 if (operations_different(op, instruction_at(i))) { | |
| 5954 // these instructions are different and cannot be optimized -> | |
| 5955 // no further optimization possible | |
| 5956 return; | |
| 5957 } | |
| 5958 } | |
| 5959 | |
| 5960 TRACE_LINEAR_SCAN(4, tty->print("----- found instruction that is equal in all %d successors: ", num_sux); op->print()); | |
| 5961 | |
| 5962 // insert instruction at end of current block | |
| 5963 block->lir()->insert_before(insert_idx, op); | |
| 5964 insert_idx++; | |
| 5965 | |
| 5966 // delete the instructions at the beginning of all successors | |
| 5967 for (i = 0; i < num_sux; i++) { | |
| 5968 remove_cur_instruction(i, false); | |
| 5969 } | |
| 5970 } | |
| 5971 } | |
| 5972 | |
| 5973 | |
| 5974 // Implementation of ControlFlowOptimizer | |
| 5975 | |
| 5976 ControlFlowOptimizer::ControlFlowOptimizer() : | |
| 5977 _original_preds(4) | |
| 5978 { | |
| 5979 } | |
| 5980 | |
| 5981 void ControlFlowOptimizer::optimize(BlockList* code) { | |
| 5982 ControlFlowOptimizer optimizer = ControlFlowOptimizer(); | |
| 5983 | |
| 5984 // push the OSR entry block to the end so that we're not jumping over it. | |
| 5985 BlockBegin* osr_entry = code->at(0)->end()->as_Base()->osr_entry(); | |
| 5986 if (osr_entry) { | |
| 5987 int index = osr_entry->linear_scan_number(); | |
| 5988 assert(code->at(index) == osr_entry, "wrong index"); | |
| 5989 code->remove_at(index); | |
| 5990 code->append(osr_entry); | |
| 5991 } | |
| 5992 | |
| 5993 optimizer.reorder_short_loops(code); | |
| 5994 optimizer.delete_empty_blocks(code); | |
| 5995 optimizer.delete_unnecessary_jumps(code); | |
| 5996 optimizer.delete_jumps_to_return(code); | |
| 5997 } | |
| 5998 | |
| 5999 void ControlFlowOptimizer::reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx) { | |
| 6000 int i = header_idx + 1; | |
| 6001 int max_end = MIN2(header_idx + ShortLoopSize, code->length()); | |
| 6002 while (i < max_end && code->at(i)->loop_depth() >= header_block->loop_depth()) { | |
| 6003 i++; | |
| 6004 } | |
| 6005 | |
| 6006 if (i == code->length() || code->at(i)->loop_depth() < header_block->loop_depth()) { | |
| 6007 int end_idx = i - 1; | |
| 6008 BlockBegin* end_block = code->at(end_idx); | |
| 6009 | |
| 6010 if (end_block->number_of_sux() == 1 && end_block->sux_at(0) == header_block) { | |
| 6011 // short loop from header_idx to end_idx found -> reorder blocks such that | |
| 6012 // the header_block is the last block instead of the first block of the loop | |
| 6013 TRACE_LINEAR_SCAN(1, tty->print_cr("Reordering short loop: length %d, header B%d, end B%d", | |
| 6014 end_idx - header_idx + 1, | |
| 6015 header_block->block_id(), end_block->block_id())); | |
| 6016 | |
| 6017 for (int j = header_idx; j < end_idx; j++) { | |
| 6018 code->at_put(j, code->at(j + 1)); | |
| 6019 } | |
| 6020 code->at_put(end_idx, header_block); | |
| 6021 | |
| 6022 // correct the flags so that any loop alignment occurs in the right place. | |
| 6023 assert(code->at(end_idx)->is_set(BlockBegin::backward_branch_target_flag), "must be backward branch target"); | |
| 6024 code->at(end_idx)->clear(BlockBegin::backward_branch_target_flag); | |
| 6025 code->at(header_idx)->set(BlockBegin::backward_branch_target_flag); | |
| 6026 } | |
| 6027 } | |
| 6028 } | |
| 6029 | |
| 6030 void ControlFlowOptimizer::reorder_short_loops(BlockList* code) { | |
| 6031 for (int i = code->length() - 1; i >= 0; i--) { | |
| 6032 BlockBegin* block = code->at(i); | |
| 6033 | |
| 6034 if (block->is_set(BlockBegin::linear_scan_loop_header_flag)) { | |
| 6035 reorder_short_loop(code, block, i); | |
| 6036 } | |
| 6037 } | |
| 6038 | |
| 6039 DEBUG_ONLY(verify(code)); | |
| 6040 } | |
| 6041 | |
| 6042 // only blocks with exactly one successor can be deleted. Such blocks | |
| 6043 // must always end with an unconditional branch to this successor | |
| 6044 bool ControlFlowOptimizer::can_delete_block(BlockBegin* block) { | |
| 6045 if (block->number_of_sux() != 1 || block->number_of_exception_handlers() != 0 || block->is_entry_block()) { | |
| 6046 return false; | |
| 6047 } | |
| 6048 | |
| 6049 LIR_OpList* instructions = block->lir()->instructions_list(); | |
| 6050 | |
| 6051 assert(instructions->length() >= 2, "block must have label and branch"); | |
| 6052 assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label"); | |
| 6053 assert(instructions->last()->as_OpBranch() != NULL, "last instrcution must always be a branch"); | |
| 6054 assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "branch must be unconditional"); | |
| 6055 assert(instructions->last()->as_OpBranch()->block() == block->sux_at(0), "branch target must be the successor"); | |
| 6056 | |
| 6057 // block must have exactly one successor | |
| 6058 | |
| 6059 if (instructions->length() == 2 && instructions->last()->info() == NULL) { | |
| 6060 return true; | |
| 6061 } | |
| 6062 return false; | |
| 6063 } | |
| 6064 | |
| 6065 // substitute branch targets in all branch-instructions of this blocks | |
| 6066 void ControlFlowOptimizer::substitute_branch_target(BlockBegin* block, BlockBegin* target_from, BlockBegin* target_to) { | |
| 6067 TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting empty block: substituting from B%d to B%d inside B%d", target_from->block_id(), target_to->block_id(), block->block_id())); | |
| 6068 | |
| 6069 LIR_OpList* instructions = block->lir()->instructions_list(); | |
| 6070 | |
| 6071 assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label"); | |
| 6072 for (int i = instructions->length() - 1; i >= 1; i--) { | |
| 6073 LIR_Op* op = instructions->at(i); | |
| 6074 | |
| 6075 if (op->code() == lir_branch || op->code() == lir_cond_float_branch) { | |
| 6076 assert(op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch"); | |
| 6077 LIR_OpBranch* branch = (LIR_OpBranch*)op; | |
| 6078 | |
| 6079 if (branch->block() == target_from) { | |
| 6080 branch->change_block(target_to); | |
| 6081 } | |
| 6082 if (branch->ublock() == target_from) { | |
| 6083 branch->change_ublock(target_to); | |
| 6084 } | |
| 6085 } | |
| 6086 } | |
| 6087 } | |
| 6088 | |
| 6089 void ControlFlowOptimizer::delete_empty_blocks(BlockList* code) { | |
| 6090 int old_pos = 0; | |
| 6091 int new_pos = 0; | |
| 6092 int num_blocks = code->length(); | |
| 6093 | |
| 6094 while (old_pos < num_blocks) { | |
| 6095 BlockBegin* block = code->at(old_pos); | |
| 6096 | |
| 6097 if (can_delete_block(block)) { | |
| 6098 BlockBegin* new_target = block->sux_at(0); | |
| 6099 | |
| 6100 // propagate backward branch target flag for correct code alignment | |
| 6101 if (block->is_set(BlockBegin::backward_branch_target_flag)) { | |
| 6102 new_target->set(BlockBegin::backward_branch_target_flag); | |
| 6103 } | |
| 6104 | |
| 6105 // collect a list with all predecessors that contains each predecessor only once | |
| 6106 // the predecessors of cur are changed during the substitution, so a copy of the | |
| 6107 // predecessor list is necessary | |
| 6108 int j; | |
| 6109 _original_preds.clear(); | |
| 6110 for (j = block->number_of_preds() - 1; j >= 0; j--) { | |
| 6111 BlockBegin* pred = block->pred_at(j); | |
| 6112 if (_original_preds.index_of(pred) == -1) { | |
| 6113 _original_preds.append(pred); | |
| 6114 } | |
| 6115 } | |
| 6116 | |
| 6117 for (j = _original_preds.length() - 1; j >= 0; j--) { | |
| 6118 BlockBegin* pred = _original_preds.at(j); | |
| 6119 substitute_branch_target(pred, block, new_target); | |
| 6120 pred->substitute_sux(block, new_target); | |
| 6121 } | |
| 6122 } else { | |
| 6123 // adjust position of this block in the block list if blocks before | |
| 6124 // have been deleted | |
| 6125 if (new_pos != old_pos) { | |
| 6126 code->at_put(new_pos, code->at(old_pos)); | |
| 6127 } | |
| 6128 new_pos++; | |
| 6129 } | |
| 6130 old_pos++; | |
| 6131 } | |
| 6132 code->truncate(new_pos); | |
| 6133 | |
| 6134 DEBUG_ONLY(verify(code)); | |
| 6135 } | |
| 6136 | |
| 6137 void ControlFlowOptimizer::delete_unnecessary_jumps(BlockList* code) { | |
| 6138 // skip the last block because there a branch is always necessary | |
| 6139 for (int i = code->length() - 2; i >= 0; i--) { | |
| 6140 BlockBegin* block = code->at(i); | |
| 6141 LIR_OpList* instructions = block->lir()->instructions_list(); | |
| 6142 | |
| 6143 LIR_Op* last_op = instructions->last(); | |
| 6144 if (last_op->code() == lir_branch) { | |
| 6145 assert(last_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch"); | |
| 6146 LIR_OpBranch* last_branch = (LIR_OpBranch*)last_op; | |
| 6147 | |
| 6148 assert(last_branch->block() != NULL, "last branch must always have a block as target"); | |
| 6149 assert(last_branch->label() == last_branch->block()->label(), "must be equal"); | |
| 6150 | |
| 6151 if (last_branch->info() == NULL) { | |
| 6152 if (last_branch->block() == code->at(i + 1)) { | |
| 6153 | |
| 6154 TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting unconditional branch at end of block B%d", block->block_id())); | |
| 6155 | |
| 6156 // delete last branch instruction | |
| 6157 instructions->truncate(instructions->length() - 1); | |
| 6158 | |
| 6159 } else { | |
| 6160 LIR_Op* prev_op = instructions->at(instructions->length() - 2); | |
| 6161 if (prev_op->code() == lir_branch || prev_op->code() == lir_cond_float_branch) { | |
| 6162 assert(prev_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch"); | |
| 6163 LIR_OpBranch* prev_branch = (LIR_OpBranch*)prev_op; | |
| 6164 | |
|
1681
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6165 LIR_Op2* prev_cmp = NULL; |
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126ea7725993
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6166 |
|
126ea7725993
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parents:
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diff
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|
6167 for(int j = instructions->length() - 3; j >= 0 && prev_cmp == NULL; j--) { |
|
126ea7725993
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6168 prev_op = instructions->at(j); |
|
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6169 if(prev_op->code() == lir_cmp) { |
|
126ea7725993
6953477: Increase portability and flexibility of building Hotspot
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parents:
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6170 assert(prev_op->as_Op2() != NULL, "branch must be of type LIR_Op2"); |
|
126ea7725993
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|
6171 prev_cmp = (LIR_Op2*)prev_op; |
|
126ea7725993
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6172 assert(prev_branch->cond() == prev_cmp->condition(), "should be the same"); |
|
126ea7725993
6953477: Increase portability and flexibility of building Hotspot
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6173 } |
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6174 } |
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6175 assert(prev_cmp != NULL, "should have found comp instruction for branch"); |
| 0 | 6176 if (prev_branch->block() == code->at(i + 1) && prev_branch->info() == NULL) { |
| 6177 | |
| 6178 TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id())); | |
| 6179 | |
| 6180 // eliminate a conditional branch to the immediate successor | |
| 6181 prev_branch->change_block(last_branch->block()); | |
| 6182 prev_branch->negate_cond(); | |
|
1681
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6183 prev_cmp->set_condition(prev_branch->cond()); |
| 0 | 6184 instructions->truncate(instructions->length() - 1); |
| 6185 } | |
| 6186 } | |
| 6187 } | |
| 6188 } | |
| 6189 } | |
| 6190 } | |
| 6191 | |
| 6192 DEBUG_ONLY(verify(code)); | |
| 6193 } | |
| 6194 | |
| 6195 void ControlFlowOptimizer::delete_jumps_to_return(BlockList* code) { | |
| 6196 #ifdef ASSERT | |
| 6197 BitMap return_converted(BlockBegin::number_of_blocks()); | |
| 6198 return_converted.clear(); | |
| 6199 #endif | |
| 6200 | |
| 6201 for (int i = code->length() - 1; i >= 0; i--) { | |
| 6202 BlockBegin* block = code->at(i); | |
| 6203 LIR_OpList* cur_instructions = block->lir()->instructions_list(); | |
| 6204 LIR_Op* cur_last_op = cur_instructions->last(); | |
| 6205 | |
| 6206 assert(cur_instructions->at(0)->code() == lir_label, "first instruction must always be a label"); | |
| 6207 if (cur_instructions->length() == 2 && cur_last_op->code() == lir_return) { | |
| 6208 // the block contains only a label and a return | |
| 6209 // if a predecessor ends with an unconditional jump to this block, then the jump | |
| 6210 // can be replaced with a return instruction | |
| 6211 // | |
| 6212 // Note: the original block with only a return statement cannot be deleted completely | |
| 6213 // because the predecessors might have other (conditional) jumps to this block | |
| 6214 // -> this may lead to unnecesary return instructions in the final code | |
| 6215 | |
| 6216 assert(cur_last_op->info() == NULL, "return instructions do not have debug information"); | |
| 6217 assert(block->number_of_sux() == 0 || | |
| 6218 (return_converted.at(block->block_id()) && block->number_of_sux() == 1), | |
| 6219 "blocks that end with return must not have successors"); | |
| 6220 | |
| 6221 assert(cur_last_op->as_Op1() != NULL, "return must be LIR_Op1"); | |
| 6222 LIR_Opr return_opr = ((LIR_Op1*)cur_last_op)->in_opr(); | |
| 6223 | |
| 6224 for (int j = block->number_of_preds() - 1; j >= 0; j--) { | |
| 6225 BlockBegin* pred = block->pred_at(j); | |
| 6226 LIR_OpList* pred_instructions = pred->lir()->instructions_list(); | |
| 6227 LIR_Op* pred_last_op = pred_instructions->last(); | |
| 6228 | |
| 6229 if (pred_last_op->code() == lir_branch) { | |
| 6230 assert(pred_last_op->as_OpBranch() != NULL, "branch must be LIR_OpBranch"); | |
| 6231 LIR_OpBranch* pred_last_branch = (LIR_OpBranch*)pred_last_op; | |
| 6232 | |
| 6233 if (pred_last_branch->block() == block && pred_last_branch->cond() == lir_cond_always && pred_last_branch->info() == NULL) { | |
| 6234 // replace the jump to a return with a direct return | |
| 6235 // Note: currently the edge between the blocks is not deleted | |
| 6236 pred_instructions->at_put(pred_instructions->length() - 1, new LIR_Op1(lir_return, return_opr)); | |
| 6237 #ifdef ASSERT | |
| 6238 return_converted.set_bit(pred->block_id()); | |
| 6239 #endif | |
| 6240 } | |
| 6241 } | |
| 6242 } | |
| 6243 } | |
| 6244 } | |
| 6245 } | |
| 6246 | |
| 6247 | |
| 6248 #ifdef ASSERT | |
| 6249 void ControlFlowOptimizer::verify(BlockList* code) { | |
| 6250 for (int i = 0; i < code->length(); i++) { | |
| 6251 BlockBegin* block = code->at(i); | |
| 6252 LIR_OpList* instructions = block->lir()->instructions_list(); | |
| 6253 | |
| 6254 int j; | |
| 6255 for (j = 0; j < instructions->length(); j++) { | |
| 6256 LIR_OpBranch* op_branch = instructions->at(j)->as_OpBranch(); | |
| 6257 | |
| 6258 if (op_branch != NULL) { | |
| 6259 assert(op_branch->block() == NULL || code->index_of(op_branch->block()) != -1, "branch target not valid"); | |
| 6260 assert(op_branch->ublock() == NULL || code->index_of(op_branch->ublock()) != -1, "branch target not valid"); | |
| 6261 } | |
| 6262 } | |
| 6263 | |
| 6264 for (j = 0; j < block->number_of_sux() - 1; j++) { | |
| 6265 BlockBegin* sux = block->sux_at(j); | |
| 6266 assert(code->index_of(sux) != -1, "successor not valid"); | |
| 6267 } | |
| 6268 | |
| 6269 for (j = 0; j < block->number_of_preds() - 1; j++) { | |
| 6270 BlockBegin* pred = block->pred_at(j); | |
| 6271 assert(code->index_of(pred) != -1, "successor not valid"); | |
| 6272 } | |
| 6273 } | |
| 6274 } | |
| 6275 #endif | |
| 6276 | |
| 6277 | |
| 6278 #ifndef PRODUCT | |
| 6279 | |
| 6280 // Implementation of LinearStatistic | |
| 6281 | |
| 6282 const char* LinearScanStatistic::counter_name(int counter_idx) { | |
| 6283 switch (counter_idx) { | |
| 6284 case counter_method: return "compiled methods"; | |
| 6285 case counter_fpu_method: return "methods using fpu"; | |
| 6286 case counter_loop_method: return "methods with loops"; | |
| 6287 case counter_exception_method:return "methods with xhandler"; | |
| 6288 | |
| 6289 case counter_loop: return "loops"; | |
| 6290 case counter_block: return "blocks"; | |
| 6291 case counter_loop_block: return "blocks inside loop"; | |
| 6292 case counter_exception_block: return "exception handler entries"; | |
| 6293 case counter_interval: return "intervals"; | |
| 6294 case counter_fixed_interval: return "fixed intervals"; | |
| 6295 case counter_range: return "ranges"; | |
| 6296 case counter_fixed_range: return "fixed ranges"; | |
| 6297 case counter_use_pos: return "use positions"; | |
| 6298 case counter_fixed_use_pos: return "fixed use positions"; | |
| 6299 case counter_spill_slots: return "spill slots"; | |
| 6300 | |
| 6301 // counter for classes of lir instructions | |
| 6302 case counter_instruction: return "total instructions"; | |
| 6303 case counter_label: return "labels"; | |
| 6304 case counter_entry: return "method entries"; | |
| 6305 case counter_return: return "method returns"; | |
| 6306 case counter_call: return "method calls"; | |
| 6307 case counter_move: return "moves"; | |
| 6308 case counter_cmp: return "compare"; | |
| 6309 case counter_cond_branch: return "conditional branches"; | |
| 6310 case counter_uncond_branch: return "unconditional branches"; | |
| 6311 case counter_stub_branch: return "branches to stub"; | |
| 6312 case counter_alu: return "artithmetic + logic"; | |
| 6313 case counter_alloc: return "allocations"; | |
| 6314 case counter_sync: return "synchronisation"; | |
| 6315 case counter_throw: return "throw"; | |
| 6316 case counter_unwind: return "unwind"; | |
| 6317 case counter_typecheck: return "type+null-checks"; | |
| 6318 case counter_fpu_stack: return "fpu-stack"; | |
| 6319 case counter_misc_inst: return "other instructions"; | |
| 6320 case counter_other_inst: return "misc. instructions"; | |
| 6321 | |
| 6322 // counter for different types of moves | |
| 6323 case counter_move_total: return "total moves"; | |
| 6324 case counter_move_reg_reg: return "register->register"; | |
| 6325 case counter_move_reg_stack: return "register->stack"; | |
| 6326 case counter_move_stack_reg: return "stack->register"; | |
| 6327 case counter_move_stack_stack:return "stack->stack"; | |
| 6328 case counter_move_reg_mem: return "register->memory"; | |
| 6329 case counter_move_mem_reg: return "memory->register"; | |
| 6330 case counter_move_const_any: return "constant->any"; | |
| 6331 | |
| 6332 case blank_line_1: return ""; | |
| 6333 case blank_line_2: return ""; | |
| 6334 | |
| 6335 default: ShouldNotReachHere(); return ""; | |
| 6336 } | |
| 6337 } | |
| 6338 | |
| 6339 LinearScanStatistic::Counter LinearScanStatistic::base_counter(int counter_idx) { | |
| 6340 if (counter_idx == counter_fpu_method || counter_idx == counter_loop_method || counter_idx == counter_exception_method) { | |
| 6341 return counter_method; | |
| 6342 } else if (counter_idx == counter_loop_block || counter_idx == counter_exception_block) { | |
| 6343 return counter_block; | |
| 6344 } else if (counter_idx >= counter_instruction && counter_idx <= counter_other_inst) { | |
| 6345 return counter_instruction; | |
| 6346 } else if (counter_idx >= counter_move_total && counter_idx <= counter_move_const_any) { | |
| 6347 return counter_move_total; | |
| 6348 } | |
| 6349 return invalid_counter; | |
| 6350 } | |
| 6351 | |
| 6352 LinearScanStatistic::LinearScanStatistic() { | |
| 6353 for (int i = 0; i < number_of_counters; i++) { | |
| 6354 _counters_sum[i] = 0; | |
| 6355 _counters_max[i] = -1; | |
| 6356 } | |
| 6357 | |
| 6358 } | |
| 6359 | |
| 6360 // add the method-local numbers to the total sum | |
| 6361 void LinearScanStatistic::sum_up(LinearScanStatistic &method_statistic) { | |
| 6362 for (int i = 0; i < number_of_counters; i++) { | |
| 6363 _counters_sum[i] += method_statistic._counters_sum[i]; | |
| 6364 _counters_max[i] = MAX2(_counters_max[i], method_statistic._counters_sum[i]); | |
| 6365 } | |
| 6366 } | |
| 6367 | |
| 6368 void LinearScanStatistic::print(const char* title) { | |
| 6369 if (CountLinearScan || TraceLinearScanLevel > 0) { | |
| 6370 tty->cr(); | |
| 6371 tty->print_cr("***** LinearScan statistic - %s *****", title); | |
| 6372 | |
| 6373 for (int i = 0; i < number_of_counters; i++) { | |
| 6374 if (_counters_sum[i] > 0 || _counters_max[i] >= 0) { | |
| 6375 tty->print("%25s: %8d", counter_name(i), _counters_sum[i]); | |
| 6376 | |
| 6377 if (base_counter(i) != invalid_counter) { | |
| 6378 tty->print(" (%5.1f%%) ", _counters_sum[i] * 100.0 / _counters_sum[base_counter(i)]); | |
| 6379 } else { | |
| 6380 tty->print(" "); | |
| 6381 } | |
| 6382 | |
| 6383 if (_counters_max[i] >= 0) { | |
| 6384 tty->print("%8d", _counters_max[i]); | |
| 6385 } | |
| 6386 } | |
| 6387 tty->cr(); | |
| 6388 } | |
| 6389 } | |
| 6390 } | |
| 6391 | |
| 6392 void LinearScanStatistic::collect(LinearScan* allocator) { | |
| 6393 inc_counter(counter_method); | |
| 6394 if (allocator->has_fpu_registers()) { | |
| 6395 inc_counter(counter_fpu_method); | |
| 6396 } | |
| 6397 if (allocator->num_loops() > 0) { | |
| 6398 inc_counter(counter_loop_method); | |
| 6399 } | |
| 6400 inc_counter(counter_loop, allocator->num_loops()); | |
| 6401 inc_counter(counter_spill_slots, allocator->max_spills()); | |
| 6402 | |
| 6403 int i; | |
| 6404 for (i = 0; i < allocator->interval_count(); i++) { | |
| 6405 Interval* cur = allocator->interval_at(i); | |
| 6406 | |
| 6407 if (cur != NULL) { | |
| 6408 inc_counter(counter_interval); | |
| 6409 inc_counter(counter_use_pos, cur->num_use_positions()); | |
| 6410 if (LinearScan::is_precolored_interval(cur)) { | |
| 6411 inc_counter(counter_fixed_interval); | |
| 6412 inc_counter(counter_fixed_use_pos, cur->num_use_positions()); | |
| 6413 } | |
| 6414 | |
| 6415 Range* range = cur->first(); | |
| 6416 while (range != Range::end()) { | |
| 6417 inc_counter(counter_range); | |
| 6418 if (LinearScan::is_precolored_interval(cur)) { | |
| 6419 inc_counter(counter_fixed_range); | |
| 6420 } | |
| 6421 range = range->next(); | |
| 6422 } | |
| 6423 } | |
| 6424 } | |
| 6425 | |
| 6426 bool has_xhandlers = false; | |
| 6427 // Note: only count blocks that are in code-emit order | |
| 6428 for (i = 0; i < allocator->ir()->code()->length(); i++) { | |
| 6429 BlockBegin* cur = allocator->ir()->code()->at(i); | |
| 6430 | |
| 6431 inc_counter(counter_block); | |
| 6432 if (cur->loop_depth() > 0) { | |
| 6433 inc_counter(counter_loop_block); | |
| 6434 } | |
| 6435 if (cur->is_set(BlockBegin::exception_entry_flag)) { | |
| 6436 inc_counter(counter_exception_block); | |
| 6437 has_xhandlers = true; | |
| 6438 } | |
| 6439 | |
| 6440 LIR_OpList* instructions = cur->lir()->instructions_list(); | |
| 6441 for (int j = 0; j < instructions->length(); j++) { | |
| 6442 LIR_Op* op = instructions->at(j); | |
| 6443 | |
| 6444 inc_counter(counter_instruction); | |
| 6445 | |
| 6446 switch (op->code()) { | |
| 6447 case lir_label: inc_counter(counter_label); break; | |
| 6448 case lir_std_entry: | |
| 6449 case lir_osr_entry: inc_counter(counter_entry); break; | |
| 6450 case lir_return: inc_counter(counter_return); break; | |
| 6451 | |
| 6452 case lir_rtcall: | |
| 6453 case lir_static_call: | |
| 6454 case lir_optvirtual_call: | |
| 6455 case lir_virtual_call: inc_counter(counter_call); break; | |
| 6456 | |
| 6457 case lir_move: { | |
| 6458 inc_counter(counter_move); | |
| 6459 inc_counter(counter_move_total); | |
| 6460 | |
| 6461 LIR_Opr in = op->as_Op1()->in_opr(); | |
| 6462 LIR_Opr res = op->as_Op1()->result_opr(); | |
| 6463 if (in->is_register()) { | |
| 6464 if (res->is_register()) { | |
| 6465 inc_counter(counter_move_reg_reg); | |
| 6466 } else if (res->is_stack()) { | |
| 6467 inc_counter(counter_move_reg_stack); | |
| 6468 } else if (res->is_address()) { | |
| 6469 inc_counter(counter_move_reg_mem); | |
| 6470 } else { | |
| 6471 ShouldNotReachHere(); | |
| 6472 } | |
| 6473 } else if (in->is_stack()) { | |
| 6474 if (res->is_register()) { | |
| 6475 inc_counter(counter_move_stack_reg); | |
| 6476 } else { | |
| 6477 inc_counter(counter_move_stack_stack); | |
| 6478 } | |
| 6479 } else if (in->is_address()) { | |
| 6480 assert(res->is_register(), "must be"); | |
| 6481 inc_counter(counter_move_mem_reg); | |
| 6482 } else if (in->is_constant()) { | |
| 6483 inc_counter(counter_move_const_any); | |
| 6484 } else { | |
| 6485 ShouldNotReachHere(); | |
| 6486 } | |
| 6487 break; | |
| 6488 } | |
| 6489 | |
| 6490 case lir_cmp: inc_counter(counter_cmp); break; | |
| 6491 | |
| 6492 case lir_branch: | |
| 6493 case lir_cond_float_branch: { | |
| 6494 LIR_OpBranch* branch = op->as_OpBranch(); | |
| 6495 if (branch->block() == NULL) { | |
| 6496 inc_counter(counter_stub_branch); | |
| 6497 } else if (branch->cond() == lir_cond_always) { | |
| 6498 inc_counter(counter_uncond_branch); | |
| 6499 } else { | |
| 6500 inc_counter(counter_cond_branch); | |
| 6501 } | |
| 6502 break; | |
| 6503 } | |
| 6504 | |
| 6505 case lir_neg: | |
| 6506 case lir_add: | |
| 6507 case lir_sub: | |
| 6508 case lir_mul: | |
| 6509 case lir_mul_strictfp: | |
| 6510 case lir_div: | |
| 6511 case lir_div_strictfp: | |
| 6512 case lir_rem: | |
| 6513 case lir_sqrt: | |
| 6514 case lir_sin: | |
| 6515 case lir_cos: | |
| 6516 case lir_abs: | |
| 6517 case lir_log10: | |
| 6518 case lir_log: | |
| 6519 case lir_logic_and: | |
| 6520 case lir_logic_or: | |
| 6521 case lir_logic_xor: | |
| 6522 case lir_shl: | |
| 6523 case lir_shr: | |
| 6524 case lir_ushr: inc_counter(counter_alu); break; | |
| 6525 | |
| 6526 case lir_alloc_object: | |
| 6527 case lir_alloc_array: inc_counter(counter_alloc); break; | |
| 6528 | |
| 6529 case lir_monaddr: | |
| 6530 case lir_lock: | |
| 6531 case lir_unlock: inc_counter(counter_sync); break; | |
| 6532 | |
| 6533 case lir_throw: inc_counter(counter_throw); break; | |
| 6534 | |
| 6535 case lir_unwind: inc_counter(counter_unwind); break; | |
| 6536 | |
| 6537 case lir_null_check: | |
| 6538 case lir_leal: | |
| 6539 case lir_instanceof: | |
| 6540 case lir_checkcast: | |
| 6541 case lir_store_check: inc_counter(counter_typecheck); break; | |
| 6542 | |
| 6543 case lir_fpop_raw: | |
| 6544 case lir_fxch: | |
| 6545 case lir_fld: inc_counter(counter_fpu_stack); break; | |
| 6546 | |
| 6547 case lir_nop: | |
| 6548 case lir_push: | |
| 6549 case lir_pop: | |
| 6550 case lir_convert: | |
| 6551 case lir_roundfp: | |
| 6552 case lir_cmove: inc_counter(counter_misc_inst); break; | |
| 6553 | |
| 6554 default: inc_counter(counter_other_inst); break; | |
| 6555 } | |
| 6556 } | |
| 6557 } | |
| 6558 | |
| 6559 if (has_xhandlers) { | |
| 6560 inc_counter(counter_exception_method); | |
| 6561 } | |
| 6562 } | |
| 6563 | |
| 6564 void LinearScanStatistic::compute(LinearScan* allocator, LinearScanStatistic &global_statistic) { | |
| 6565 if (CountLinearScan || TraceLinearScanLevel > 0) { | |
| 6566 | |
| 6567 LinearScanStatistic local_statistic = LinearScanStatistic(); | |
| 6568 | |
| 6569 local_statistic.collect(allocator); | |
| 6570 global_statistic.sum_up(local_statistic); | |
| 6571 | |
| 6572 if (TraceLinearScanLevel > 2) { | |
| 6573 local_statistic.print("current local statistic"); | |
| 6574 } | |
| 6575 } | |
| 6576 } | |
| 6577 | |
| 6578 | |
| 6579 // Implementation of LinearTimers | |
| 6580 | |
| 6581 LinearScanTimers::LinearScanTimers() { | |
| 6582 for (int i = 0; i < number_of_timers; i++) { | |
| 6583 timer(i)->reset(); | |
| 6584 } | |
| 6585 } | |
| 6586 | |
| 6587 const char* LinearScanTimers::timer_name(int idx) { | |
| 6588 switch (idx) { | |
| 6589 case timer_do_nothing: return "Nothing (Time Check)"; | |
| 6590 case timer_number_instructions: return "Number Instructions"; | |
| 6591 case timer_compute_local_live_sets: return "Local Live Sets"; | |
| 6592 case timer_compute_global_live_sets: return "Global Live Sets"; | |
| 6593 case timer_build_intervals: return "Build Intervals"; | |
| 6594 case timer_sort_intervals_before: return "Sort Intervals Before"; | |
| 6595 case timer_allocate_registers: return "Allocate Registers"; | |
| 6596 case timer_resolve_data_flow: return "Resolve Data Flow"; | |
| 6597 case timer_sort_intervals_after: return "Sort Intervals After"; | |
| 6598 case timer_eliminate_spill_moves: return "Spill optimization"; | |
| 6599 case timer_assign_reg_num: return "Assign Reg Num"; | |
| 6600 case timer_allocate_fpu_stack: return "Allocate FPU Stack"; | |
| 6601 case timer_optimize_lir: return "Optimize LIR"; | |
| 6602 default: ShouldNotReachHere(); return ""; | |
| 6603 } | |
| 6604 } | |
| 6605 | |
| 6606 void LinearScanTimers::begin_method() { | |
| 6607 if (TimeEachLinearScan) { | |
| 6608 // reset all timers to measure only current method | |
| 6609 for (int i = 0; i < number_of_timers; i++) { | |
| 6610 timer(i)->reset(); | |
| 6611 } | |
| 6612 } | |
| 6613 } | |
| 6614 | |
| 6615 void LinearScanTimers::end_method(LinearScan* allocator) { | |
| 6616 if (TimeEachLinearScan) { | |
| 6617 | |
| 6618 double c = timer(timer_do_nothing)->seconds(); | |
| 6619 double total = 0; | |
| 6620 for (int i = 1; i < number_of_timers; i++) { | |
| 6621 total += timer(i)->seconds() - c; | |
| 6622 } | |
| 6623 | |
| 6624 if (total >= 0.0005) { | |
| 6625 // print all information in one line for automatic processing | |
| 6626 tty->print("@"); allocator->compilation()->method()->print_name(); | |
| 6627 | |
| 6628 tty->print("@ %d ", allocator->compilation()->method()->code_size()); | |
| 6629 tty->print("@ %d ", allocator->block_at(allocator->block_count() - 1)->last_lir_instruction_id() / 2); | |
| 6630 tty->print("@ %d ", allocator->block_count()); | |
| 6631 tty->print("@ %d ", allocator->num_virtual_regs()); | |
| 6632 tty->print("@ %d ", allocator->interval_count()); | |
| 6633 tty->print("@ %d ", allocator->_num_calls); | |
| 6634 tty->print("@ %d ", allocator->num_loops()); | |
| 6635 | |
| 6636 tty->print("@ %6.6f ", total); | |
| 6637 for (int i = 1; i < number_of_timers; i++) { | |
| 6638 tty->print("@ %4.1f ", ((timer(i)->seconds() - c) / total) * 100); | |
| 6639 } | |
| 6640 tty->cr(); | |
| 6641 } | |
| 6642 } | |
| 6643 } | |
| 6644 | |
| 6645 void LinearScanTimers::print(double total_time) { | |
| 6646 if (TimeLinearScan) { | |
| 6647 // correction value: sum of dummy-timer that only measures the time that | |
| 6648 // is necesary to start and stop itself | |
| 6649 double c = timer(timer_do_nothing)->seconds(); | |
| 6650 | |
| 6651 for (int i = 0; i < number_of_timers; i++) { | |
| 6652 double t = timer(i)->seconds(); | |
| 6653 tty->print_cr(" %25s: %6.3f s (%4.1f%%) corrected: %6.3f s (%4.1f%%)", timer_name(i), t, (t / total_time) * 100.0, t - c, (t - c) / (total_time - 2 * number_of_timers * c) * 100); | |
| 6654 } | |
| 6655 } | |
| 6656 } | |
| 6657 | |
| 6658 #endif // #ifndef PRODUCT |