Mercurial > hg > truffle
annotate src/share/vm/opto/matcher.hpp @ 4710:41406797186b
7113012: G1: rename not-fully-young GCs as "mixed"
Summary: Renamed partially-young GCs as mixed and fully-young GCs as young. Change all external output that includes those terms (GC log and GC ergo log) as well as any comments, fields, methods, etc. The changeset also includes very minor code tidying up (added some curly brackets).
Reviewed-by: johnc, brutisso
| author | tonyp |
|---|---|
| date | Fri, 16 Dec 2011 02:14:27 -0500 |
| parents | db2e64ca2d5a |
| children | 8c92982cbbc4 |
| rev | line source |
|---|---|
| 0 | 1 /* |
|
2426
1d1603768966
7010070: Update all 2010 Oracle-changed OpenJDK files to have the proper copyright dates - second pass
trims
parents:
2401
diff
changeset
|
2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1274
diff
changeset
|
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1274
diff
changeset
|
20 * or visit www.oracle.com if you need additional information or have any |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1274
diff
changeset
|
21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #ifndef SHARE_VM_OPTO_MATCHER_HPP |
| 26 #define SHARE_VM_OPTO_MATCHER_HPP | |
| 27 | |
| 28 #include "libadt/vectset.hpp" | |
| 29 #include "memory/resourceArea.hpp" | |
| 30 #include "opto/node.hpp" | |
| 31 #include "opto/phaseX.hpp" | |
| 32 #include "opto/regmask.hpp" | |
| 33 | |
| 0 | 34 class Compile; |
| 35 class Node; | |
| 36 class MachNode; | |
| 37 class MachTypeNode; | |
| 38 class MachOper; | |
| 39 | |
| 40 //---------------------------Matcher------------------------------------------- | |
| 41 class Matcher : public PhaseTransform { | |
| 42 friend class VMStructs; | |
| 43 // Private arena of State objects | |
| 44 ResourceArea _states_arena; | |
| 45 | |
| 46 VectorSet _visited; // Visit bits | |
| 47 | |
| 48 // Used to control the Label pass | |
| 49 VectorSet _shared; // Shared Ideal Node | |
| 50 VectorSet _dontcare; // Nothing the matcher cares about | |
| 51 | |
| 52 // Private methods which perform the actual matching and reduction | |
| 53 // Walks the label tree, generating machine nodes | |
| 54 MachNode *ReduceInst( State *s, int rule, Node *&mem); | |
| 55 void ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach); | |
| 56 uint ReduceInst_Interior(State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds); | |
| 57 void ReduceOper( State *s, int newrule, Node *&mem, MachNode *mach ); | |
| 58 | |
| 59 // If this node already matched using "rule", return the MachNode for it. | |
|
168
7793bd37a336
6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents:
0
diff
changeset
|
60 MachNode* find_shared_node(Node* n, uint rule); |
| 0 | 61 |
| 62 // Convert a dense opcode number to an expanded rule number | |
| 63 const int *_reduceOp; | |
| 64 const int *_leftOp; | |
| 65 const int *_rightOp; | |
| 66 | |
| 67 // Map dense opcode number to info on when rule is swallowed constant. | |
| 68 const bool *_swallowed; | |
| 69 | |
| 70 // Map dense rule number to determine if this is an instruction chain rule | |
| 71 const uint _begin_inst_chain_rule; | |
| 72 const uint _end_inst_chain_rule; | |
| 73 | |
| 74 // We want to clone constants and possible CmpI-variants. | |
| 75 // If we do not clone CmpI, then we can have many instances of | |
| 76 // condition codes alive at once. This is OK on some chips and | |
| 77 // bad on others. Hence the machine-dependent table lookup. | |
| 78 const char *_must_clone; | |
| 79 | |
| 80 // Find shared Nodes, or Nodes that otherwise are Matcher roots | |
| 81 void find_shared( Node *n ); | |
| 82 | |
| 83 // Debug and profile information for nodes in old space: | |
| 84 GrowableArray<Node_Notes*>* _old_node_note_array; | |
| 85 | |
| 86 // Node labeling iterator for instruction selection | |
| 87 Node *Label_Root( const Node *n, State *svec, Node *control, const Node *mem ); | |
| 88 | |
| 89 Node *transform( Node *dummy ); | |
| 90 | |
| 91 Node_List &_proj_list; // For Machine nodes killing many values | |
| 92 | |
|
168
7793bd37a336
6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents:
0
diff
changeset
|
93 Node_Array _shared_nodes; |
| 0 | 94 |
| 95 debug_only(Node_Array _old2new_map;) // Map roots of ideal-trees to machine-roots | |
| 222 | 96 debug_only(Node_Array _new2old_map;) // Maps machine nodes back to ideal |
| 0 | 97 |
| 98 // Accessors for the inherited field PhaseTransform::_nodes: | |
| 99 void grow_new_node_array(uint idx_limit) { | |
| 100 _nodes.map(idx_limit-1, NULL); | |
| 101 } | |
| 102 bool has_new_node(const Node* n) const { | |
| 103 return _nodes.at(n->_idx) != NULL; | |
| 104 } | |
| 105 Node* new_node(const Node* n) const { | |
| 106 assert(has_new_node(n), "set before get"); | |
| 107 return _nodes.at(n->_idx); | |
| 108 } | |
| 109 void set_new_node(const Node* n, Node *nn) { | |
| 110 assert(!has_new_node(n), "set only once"); | |
| 111 _nodes.map(n->_idx, nn); | |
| 112 } | |
| 113 | |
| 114 #ifdef ASSERT | |
| 115 // Make sure only new nodes are reachable from this node | |
| 116 void verify_new_nodes_only(Node* root); | |
|
216
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
168
diff
changeset
|
117 |
|
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
168
diff
changeset
|
118 Node* _mem_node; // Ideal memory node consumed by mach node |
| 0 | 119 #endif |
| 120 | |
|
729
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
415
diff
changeset
|
121 // Mach node for ConP #NULL |
|
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
415
diff
changeset
|
122 MachNode* _mach_null; |
|
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
415
diff
changeset
|
123 |
| 0 | 124 public: |
| 125 int LabelRootDepth; | |
| 126 static const int base2reg[]; // Map Types to machine register types | |
| 127 // Convert ideal machine register to a register mask for spill-loads | |
| 128 static const RegMask *idealreg2regmask[]; | |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
844
diff
changeset
|
129 RegMask *idealreg2spillmask [_last_machine_leaf]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
844
diff
changeset
|
130 RegMask *idealreg2debugmask [_last_machine_leaf]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
844
diff
changeset
|
131 RegMask *idealreg2mhdebugmask[_last_machine_leaf]; |
| 0 | 132 void init_spill_mask( Node *ret ); |
| 133 // Convert machine register number to register mask | |
| 134 static uint mreg2regmask_max; | |
| 135 static RegMask mreg2regmask[]; | |
| 136 static RegMask STACK_ONLY_mask; | |
| 137 | |
|
729
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
415
diff
changeset
|
138 MachNode* mach_null() const { return _mach_null; } |
|
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
415
diff
changeset
|
139 |
| 0 | 140 bool is_shared( Node *n ) { return _shared.test(n->_idx) != 0; } |
| 141 void set_shared( Node *n ) { _shared.set(n->_idx); } | |
| 142 bool is_visited( Node *n ) { return _visited.test(n->_idx) != 0; } | |
| 143 void set_visited( Node *n ) { _visited.set(n->_idx); } | |
| 144 bool is_dontcare( Node *n ) { return _dontcare.test(n->_idx) != 0; } | |
| 145 void set_dontcare( Node *n ) { _dontcare.set(n->_idx); } | |
| 146 | |
| 147 // Mode bit to tell DFA and expand rules whether we are running after | |
| 148 // (or during) register selection. Usually, the matcher runs before, | |
| 149 // but it will also get called to generate post-allocation spill code. | |
| 150 // In this situation, it is a deadly error to attempt to allocate more | |
| 151 // temporary registers. | |
| 152 bool _allocation_started; | |
| 153 | |
| 154 // Machine register names | |
| 155 static const char *regName[]; | |
| 156 // Machine register encodings | |
| 157 static const unsigned char _regEncode[]; | |
| 158 // Machine Node names | |
| 159 const char **_ruleName; | |
| 160 // Rules that are cheaper to rematerialize than to spill | |
| 161 static const uint _begin_rematerialize; | |
| 162 static const uint _end_rematerialize; | |
| 163 | |
| 164 // An array of chars, from 0 to _last_Mach_Reg. | |
| 165 // No Save = 'N' (for register windows) | |
| 166 // Save on Entry = 'E' | |
| 167 // Save on Call = 'C' | |
| 168 // Always Save = 'A' (same as SOE + SOC) | |
| 169 const char *_register_save_policy; | |
| 170 const char *_c_reg_save_policy; | |
| 171 // Convert a machine register to a machine register type, so-as to | |
| 172 // properly match spill code. | |
| 173 const int *_register_save_type; | |
| 174 // Maps from machine register to boolean; true if machine register can | |
| 175 // be holding a call argument in some signature. | |
| 176 static bool can_be_java_arg( int reg ); | |
| 177 // Maps from machine register to boolean; true if machine register holds | |
| 178 // a spillable argument. | |
| 179 static bool is_spillable_arg( int reg ); | |
| 180 | |
| 181 // List of IfFalse or IfTrue Nodes that indicate a taken null test. | |
| 182 // List is valid in the post-matching space. | |
| 183 Node_List _null_check_tests; | |
|
368
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
235
diff
changeset
|
184 void collect_null_checks( Node *proj, Node *orig_proj ); |
| 0 | 185 void validate_null_checks( ); |
| 186 | |
| 187 Matcher( Node_List &proj_list ); | |
| 188 | |
| 189 // Select instructions for entire method | |
| 190 void match( ); | |
| 191 // Helper for match | |
| 192 OptoReg::Name warp_incoming_stk_arg( VMReg reg ); | |
| 193 | |
| 194 // Transform, then walk. Does implicit DCE while walking. | |
| 195 // Name changed from "transform" to avoid it being virtual. | |
| 196 Node *xform( Node *old_space_node, int Nodes ); | |
| 197 | |
| 198 // Match a single Ideal Node - turn it into a 1-Node tree; Label & Reduce. | |
| 199 MachNode *match_tree( const Node *n ); | |
| 200 MachNode *match_sfpt( SafePointNode *sfpt ); | |
| 201 // Helper for match_sfpt | |
| 202 OptoReg::Name warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ); | |
| 203 | |
| 204 // Initialize first stack mask and related masks. | |
| 205 void init_first_stack_mask(); | |
| 206 | |
| 207 // If we should save-on-entry this register | |
| 208 bool is_save_on_entry( int reg ); | |
| 209 | |
| 210 // Fixup the save-on-entry registers | |
| 211 void Fixup_Save_On_Entry( ); | |
| 212 | |
| 213 // --- Frame handling --- | |
| 214 | |
| 215 // Register number of the stack slot corresponding to the incoming SP. | |
| 216 // Per the Big Picture in the AD file, it is: | |
| 217 // SharedInfo::stack0 + locks + in_preserve_stack_slots + pad2. | |
| 218 OptoReg::Name _old_SP; | |
| 219 | |
| 220 // Register number of the stack slot corresponding to the highest incoming | |
| 221 // argument on the stack. Per the Big Picture in the AD file, it is: | |
| 222 // _old_SP + out_preserve_stack_slots + incoming argument size. | |
| 223 OptoReg::Name _in_arg_limit; | |
| 224 | |
| 225 // Register number of the stack slot corresponding to the new SP. | |
| 226 // Per the Big Picture in the AD file, it is: | |
| 227 // _in_arg_limit + pad0 | |
| 228 OptoReg::Name _new_SP; | |
| 229 | |
| 230 // Register number of the stack slot corresponding to the highest outgoing | |
| 231 // argument on the stack. Per the Big Picture in the AD file, it is: | |
| 232 // _new_SP + max outgoing arguments of all calls | |
| 233 OptoReg::Name _out_arg_limit; | |
| 234 | |
| 235 OptoRegPair *_parm_regs; // Array of machine registers per argument | |
| 236 RegMask *_calling_convention_mask; // Array of RegMasks per argument | |
| 237 | |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
729
diff
changeset
|
238 // Does matcher have a match rule for this ideal node? |
| 0 | 239 static const bool has_match_rule(int opcode); |
| 240 static const bool _hasMatchRule[_last_opcode]; | |
| 241 | |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
729
diff
changeset
|
242 // Does matcher have a match rule for this ideal node and is the |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
729
diff
changeset
|
243 // predicate (if there is one) true? |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
729
diff
changeset
|
244 // NOTE: If this function is used more commonly in the future, ADLC |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
729
diff
changeset
|
245 // should generate this one. |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
729
diff
changeset
|
246 static const bool match_rule_supported(int opcode); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
729
diff
changeset
|
247 |
| 0 | 248 // Used to determine if we have fast l2f conversion |
| 249 // USII has it, USIII doesn't | |
| 250 static const bool convL2FSupported(void); | |
| 251 | |
| 252 // Vector width in bytes | |
| 253 static const uint vector_width_in_bytes(void); | |
| 254 | |
| 255 // Vector ideal reg | |
| 256 static const uint vector_ideal_reg(void); | |
| 257 | |
| 258 // Used to determine a "low complexity" 64-bit constant. (Zero is simple.) | |
| 259 // The standard of comparison is one (StoreL ConL) vs. two (StoreI ConI). | |
| 260 // Depends on the details of 64-bit constant generation on the CPU. | |
| 261 static const bool isSimpleConstant64(jlong con); | |
| 262 | |
| 263 // These calls are all generated by the ADLC | |
| 264 | |
| 265 // TRUE - grows up, FALSE - grows down (Intel) | |
| 266 virtual bool stack_direction() const; | |
| 267 | |
| 268 // Java-Java calling convention | |
| 269 // (what you use when Java calls Java) | |
| 270 | |
| 271 // Alignment of stack in bytes, standard Intel word alignment is 4. | |
| 272 // Sparc probably wants at least double-word (8). | |
| 273 static uint stack_alignment_in_bytes(); | |
| 274 // Alignment of stack, measured in stack slots. | |
| 275 // The size of stack slots is defined by VMRegImpl::stack_slot_size. | |
| 276 static uint stack_alignment_in_slots() { | |
| 277 return stack_alignment_in_bytes() / (VMRegImpl::stack_slot_size); | |
| 278 } | |
| 279 | |
| 280 // Array mapping arguments to registers. Argument 0 is usually the 'this' | |
| 281 // pointer. Registers can include stack-slots and regular registers. | |
| 282 static void calling_convention( BasicType *, VMRegPair *, uint len, bool is_outgoing ); | |
| 283 | |
| 284 // Convert a sig into a calling convention register layout | |
| 285 // and find interesting things about it. | |
| 286 static OptoReg::Name find_receiver( bool is_outgoing ); | |
| 287 // Return address register. On Intel it is a stack-slot. On PowerPC | |
| 288 // it is the Link register. On Sparc it is r31? | |
| 289 virtual OptoReg::Name return_addr() const; | |
| 290 RegMask _return_addr_mask; | |
| 291 // Return value register. On Intel it is EAX. On Sparc i0/o0. | |
| 292 static OptoRegPair return_value(int ideal_reg, bool is_outgoing); | |
| 293 static OptoRegPair c_return_value(int ideal_reg, bool is_outgoing); | |
| 294 RegMask _return_value_mask; | |
| 295 // Inline Cache Register | |
| 296 static OptoReg::Name inline_cache_reg(); | |
| 297 static int inline_cache_reg_encode(); | |
| 298 | |
| 299 // Register for DIVI projection of divmodI | |
| 300 static RegMask divI_proj_mask(); | |
| 301 // Register for MODI projection of divmodI | |
| 302 static RegMask modI_proj_mask(); | |
| 303 | |
| 304 // Register for DIVL projection of divmodL | |
| 305 static RegMask divL_proj_mask(); | |
| 306 // Register for MODL projection of divmodL | |
| 307 static RegMask modL_proj_mask(); | |
| 308 | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1579
diff
changeset
|
309 // Use hardware DIV instruction when it is faster than |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1579
diff
changeset
|
310 // a code which use multiply for division by constant. |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1579
diff
changeset
|
311 static bool use_asm_for_ldiv_by_con( jlong divisor ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1579
diff
changeset
|
312 |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
844
diff
changeset
|
313 static const RegMask method_handle_invoke_SP_save_mask(); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
844
diff
changeset
|
314 |
| 0 | 315 // Java-Interpreter calling convention |
| 316 // (what you use when calling between compiled-Java and Interpreted-Java | |
| 317 | |
| 318 // Number of callee-save + always-save registers | |
| 319 // Ignores frame pointer and "special" registers | |
| 320 static int number_of_saved_registers(); | |
| 321 | |
| 322 // The Method-klass-holder may be passed in the inline_cache_reg | |
| 323 // and then expanded into the inline_cache_reg and a method_oop register | |
| 324 | |
| 325 static OptoReg::Name interpreter_method_oop_reg(); | |
| 326 static int interpreter_method_oop_reg_encode(); | |
| 327 | |
| 328 static OptoReg::Name compiler_method_oop_reg(); | |
| 329 static const RegMask &compiler_method_oop_reg_mask(); | |
| 330 static int compiler_method_oop_reg_encode(); | |
| 331 | |
| 332 // Interpreter's Frame Pointer Register | |
| 333 static OptoReg::Name interpreter_frame_pointer_reg(); | |
| 334 | |
| 335 // Java-Native calling convention | |
| 336 // (what you use when intercalling between Java and C++ code) | |
| 337 | |
| 338 // Array mapping arguments to registers. Argument 0 is usually the 'this' | |
| 339 // pointer. Registers can include stack-slots and regular registers. | |
| 340 static void c_calling_convention( BasicType*, VMRegPair *, uint ); | |
| 341 // Frame pointer. The frame pointer is kept at the base of the stack | |
| 342 // and so is probably the stack pointer for most machines. On Intel | |
| 343 // it is ESP. On the PowerPC it is R1. On Sparc it is SP. | |
| 344 OptoReg::Name c_frame_pointer() const; | |
| 345 static RegMask c_frame_ptr_mask; | |
| 346 | |
| 347 // !!!!! Special stuff for building ScopeDescs | |
| 348 virtual int regnum_to_fpu_offset(int regnum); | |
| 349 | |
| 350 // Is this branch offset small enough to be addressed by a short branch? | |
| 3851 | 351 bool is_short_branch_offset(int rule, int br_size, int offset); |
| 0 | 352 |
| 353 // Optional scaling for the parameter to the ClearArray/CopyArray node. | |
| 354 static const bool init_array_count_is_in_bytes; | |
| 355 | |
| 356 // Threshold small size (in bytes) for a ClearArray/CopyArray node. | |
| 357 // Anything this size or smaller may get converted to discrete scalar stores. | |
| 358 static const int init_array_short_size; | |
| 359 | |
| 4047 | 360 // Some hardware needs 2 CMOV's for longs. |
| 361 static const int long_cmove_cost(); | |
| 362 | |
| 363 // Some hardware have expensive CMOV for float and double. | |
| 364 static const int float_cmove_cost(); | |
| 365 | |
| 0 | 366 // Should the Matcher clone shifts on addressing modes, expecting them to |
| 367 // be subsumed into complex addressing expressions or compute them into | |
| 368 // registers? True for Intel but false for most RISCs | |
| 369 static const bool clone_shift_expressions; | |
| 370 | |
|
1575
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
371 static bool narrow_oop_use_complex_address(); |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
372 |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
373 // Generate implicit null check for narrow oops if it can fold |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
374 // into address expression (x64). |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
375 // |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
376 // [R12 + narrow_oop_reg<<3 + offset] // fold into address expression |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
377 // NullCheck narrow_oop_reg |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
378 // |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
379 // When narrow oops can't fold into address expression (Sparc) and |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
380 // base is not null use decode_not_null and normal implicit null check. |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
381 // Note, decode_not_null node can be used here since it is referenced |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
382 // only on non null path but it requires special handling, see |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
383 // collect_null_checks(): |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
384 // |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
385 // decode_not_null narrow_oop_reg, oop_reg // 'shift' and 'add base' |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
386 // [oop_reg + offset] |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
387 // NullCheck oop_reg |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
388 // |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
389 // With Zero base and when narrow oops can not fold into address |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
390 // expression use normal implicit null check since only shift |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
391 // is needed to decode narrow oop. |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
392 // |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
393 // decode narrow_oop_reg, oop_reg // only 'shift' |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
394 // [oop_reg + offset] |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
395 // NullCheck oop_reg |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
396 // |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
397 inline static bool gen_narrow_oop_implicit_null_checks() { |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
398 return Universe::narrow_oop_use_implicit_null_checks() && |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
399 (narrow_oop_use_complex_address() || |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
400 Universe::narrow_oop_base() != NULL); |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
401 } |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1274
diff
changeset
|
402 |
| 0 | 403 // Is it better to copy float constants, or load them directly from memory? |
| 404 // Intel can load a float constant from a direct address, requiring no | |
| 405 // extra registers. Most RISCs will have to materialize an address into a | |
| 406 // register first, so they may as well materialize the constant immediately. | |
| 407 static const bool rematerialize_float_constants; | |
| 408 | |
| 409 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
| 410 // needed. Else we split the double into 2 integer pieces and move it | |
| 411 // piece-by-piece. Only happens when passing doubles into C code or when | |
| 412 // calling i2c adapters as the Java calling convention forces doubles to be | |
| 413 // aligned. | |
| 414 static const bool misaligned_doubles_ok; | |
| 415 | |
| 416 // Perform a platform dependent implicit null fixup. This is needed | |
| 417 // on windows95 to take care of some unusual register constraints. | |
| 418 void pd_implicit_null_fixup(MachNode *load, uint idx); | |
| 419 | |
| 420 // Advertise here if the CPU requires explicit rounding operations | |
| 421 // to implement the UseStrictFP mode. | |
| 422 static const bool strict_fp_requires_explicit_rounding; | |
| 423 | |
|
1274
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
1137
diff
changeset
|
424 // Are floats conerted to double when stored to stack during deoptimization? |
|
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
1137
diff
changeset
|
425 static bool float_in_double(); |
| 0 | 426 // Do ints take an entire long register or just half? |
| 427 static const bool int_in_long; | |
| 428 | |
|
2401
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
2008
diff
changeset
|
429 // Do the processor's shift instructions only use the low 5/6 bits |
|
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
2008
diff
changeset
|
430 // of the count for 32/64 bit ints? If not we need to do the masking |
|
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
2008
diff
changeset
|
431 // ourselves. |
|
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
2008
diff
changeset
|
432 static const bool need_masked_shift_count; |
|
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
2008
diff
changeset
|
433 |
| 0 | 434 // This routine is run whenever a graph fails to match. |
| 435 // If it returns, the compiler should bailout to interpreter without error. | |
| 436 // In non-product mode, SoftMatchFailure is false to detect non-canonical | |
| 437 // graphs. Print a message and exit. | |
| 438 static void soft_match_failure() { | |
| 439 if( SoftMatchFailure ) return; | |
| 440 else { fatal("SoftMatchFailure is not allowed except in product"); } | |
| 441 } | |
| 442 | |
| 443 // Check for a following volatile memory barrier without an | |
| 444 // intervening load and thus we don't need a barrier here. We | |
| 445 // retain the Node to act as a compiler ordering barrier. | |
| 446 static bool post_store_load_barrier(const Node* mb); | |
| 447 | |
| 448 | |
| 449 #ifdef ASSERT | |
| 450 void dump_old2new_map(); // machine-independent to machine-dependent | |
| 222 | 451 |
| 452 Node* find_old_node(Node* new_node) { | |
| 453 return _new2old_map[new_node->_idx]; | |
| 454 } | |
| 0 | 455 #endif |
| 456 }; | |
| 1972 | 457 |
| 458 #endif // SHARE_VM_OPTO_MATCHER_HPP |