7204
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1 /*
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2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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20 * or visit www.oracle.com if you need additional information or have any
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21 * questions.
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22 *
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23 */
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24
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25 #include "precompiled.hpp"
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26 #include "asm/assembler.inline.hpp"
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27 #include "compiler/disassembler.hpp"
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28 #include "gc_interface/collectedHeap.inline.hpp"
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29 #include "interpreter/interpreter.hpp"
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30 #include "memory/cardTableModRefBS.hpp"
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31 #include "memory/resourceArea.hpp"
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32 #include "prims/methodHandles.hpp"
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33 #include "runtime/biasedLocking.hpp"
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34 #include "runtime/interfaceSupport.hpp"
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35 #include "runtime/objectMonitor.hpp"
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36 #include "runtime/os.hpp"
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37 #include "runtime/sharedRuntime.hpp"
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38 #include "runtime/stubRoutines.hpp"
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39 #ifndef SERIALGC
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40 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
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41 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
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42 #include "gc_implementation/g1/heapRegion.hpp"
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43 #endif
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44
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45 #ifdef PRODUCT
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46 #define BLOCK_COMMENT(str) /* nothing */
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47 #define STOP(error) stop(error)
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48 #else
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49 #define BLOCK_COMMENT(str) block_comment(str)
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50 #define STOP(error) block_comment(error); stop(error)
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51 #endif
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52
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53 // Convert the raw encoding form into the form expected by the
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54 // constructor for Address.
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55 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
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56 assert(scale == 0, "not supported");
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57 RelocationHolder rspec;
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58 if (disp_reloc != relocInfo::none) {
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59 rspec = Relocation::spec_simple(disp_reloc);
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60 }
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61
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62 Register rindex = as_Register(index);
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63 if (rindex != G0) {
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64 Address madr(as_Register(base), rindex);
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65 madr._rspec = rspec;
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66 return madr;
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67 } else {
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68 Address madr(as_Register(base), disp);
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69 madr._rspec = rspec;
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70 return madr;
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71 }
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72 }
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73
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74 Address Argument::address_in_frame() const {
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75 // Warning: In LP64 mode disp will occupy more than 10 bits, but
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76 // op codes such as ld or ldx, only access disp() to get
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77 // their simm13 argument.
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78 int disp = ((_number - Argument::n_register_parameters + frame::memory_parameter_word_sp_offset) * BytesPerWord) + STACK_BIAS;
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79 if (is_in())
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80 return Address(FP, disp); // In argument.
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81 else
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82 return Address(SP, disp); // Out argument.
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83 }
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84
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85 static const char* argumentNames[][2] = {
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86 {"A0","P0"}, {"A1","P1"}, {"A2","P2"}, {"A3","P3"}, {"A4","P4"},
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87 {"A5","P5"}, {"A6","P6"}, {"A7","P7"}, {"A8","P8"}, {"A9","P9"},
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88 {"A(n>9)","P(n>9)"}
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89 };
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90
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91 const char* Argument::name() const {
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92 int nofArgs = sizeof argumentNames / sizeof argumentNames[0];
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93 int num = number();
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94 if (num >= nofArgs) num = nofArgs - 1;
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95 return argumentNames[num][is_in() ? 1 : 0];
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96 }
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97
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98 #ifdef ASSERT
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99 // On RISC, there's no benefit to verifying instruction boundaries.
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100 bool AbstractAssembler::pd_check_instruction_mark() { return false; }
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101 #endif
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102
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103
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104 void MacroAssembler::print_instruction(int inst) {
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105 const char* s;
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106 switch (inv_op(inst)) {
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107 default: s = "????"; break;
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108 case call_op: s = "call"; break;
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109 case branch_op:
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110 switch (inv_op2(inst)) {
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111 case fb_op2: s = "fb"; break;
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112 case fbp_op2: s = "fbp"; break;
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113 case br_op2: s = "br"; break;
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114 case bp_op2: s = "bp"; break;
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115 case cb_op2: s = "cb"; break;
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116 case bpr_op2: {
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117 if (is_cbcond(inst)) {
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118 s = is_cxb(inst) ? "cxb" : "cwb";
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119 } else {
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120 s = "bpr";
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121 }
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122 break;
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123 }
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124 default: s = "????"; break;
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125 }
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126 }
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127 ::tty->print("%s", s);
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128 }
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129
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130
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131 // Patch instruction inst at offset inst_pos to refer to dest_pos
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132 // and return the resulting instruction.
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133 // We should have pcs, not offsets, but since all is relative, it will work out
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134 // OK.
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135 int MacroAssembler::patched_branch(int dest_pos, int inst, int inst_pos) {
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136 int m; // mask for displacement field
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137 int v; // new value for displacement field
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138 const int word_aligned_ones = -4;
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139 switch (inv_op(inst)) {
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140 default: ShouldNotReachHere();
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141 case call_op: m = wdisp(word_aligned_ones, 0, 30); v = wdisp(dest_pos, inst_pos, 30); break;
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142 case branch_op:
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143 switch (inv_op2(inst)) {
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144 case fbp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break;
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145 case bp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break;
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146 case fb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break;
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147 case br_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break;
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148 case cb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break;
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149 case bpr_op2: {
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150 if (is_cbcond(inst)) {
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151 m = wdisp10(word_aligned_ones, 0);
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152 v = wdisp10(dest_pos, inst_pos);
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153 } else {
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154 m = wdisp16(word_aligned_ones, 0);
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155 v = wdisp16(dest_pos, inst_pos);
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156 }
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157 break;
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158 }
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159 default: ShouldNotReachHere();
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160 }
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161 }
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162 return inst & ~m | v;
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163 }
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164
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165 // Return the offset of the branch destionation of instruction inst
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166 // at offset pos.
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167 // Should have pcs, but since all is relative, it works out.
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168 int MacroAssembler::branch_destination(int inst, int pos) {
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169 int r;
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170 switch (inv_op(inst)) {
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171 default: ShouldNotReachHere();
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172 case call_op: r = inv_wdisp(inst, pos, 30); break;
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173 case branch_op:
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174 switch (inv_op2(inst)) {
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175 case fbp_op2: r = inv_wdisp( inst, pos, 19); break;
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176 case bp_op2: r = inv_wdisp( inst, pos, 19); break;
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177 case fb_op2: r = inv_wdisp( inst, pos, 22); break;
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178 case br_op2: r = inv_wdisp( inst, pos, 22); break;
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179 case cb_op2: r = inv_wdisp( inst, pos, 22); break;
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180 case bpr_op2: {
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181 if (is_cbcond(inst)) {
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182 r = inv_wdisp10(inst, pos);
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183 } else {
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184 r = inv_wdisp16(inst, pos);
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185 }
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186 break;
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187 }
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188 default: ShouldNotReachHere();
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189 }
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190 }
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191 return r;
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192 }
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193
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194 void MacroAssembler::null_check(Register reg, int offset) {
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195 if (needs_explicit_null_check((intptr_t)offset)) {
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196 // provoke OS NULL exception if reg = NULL by
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197 // accessing M[reg] w/o changing any registers
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198 ld_ptr(reg, 0, G0);
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199 }
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200 else {
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201 // nothing to do, (later) access of M[reg + offset]
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202 // will provoke OS NULL exception if reg = NULL
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203 }
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204 }
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205
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206 // Ring buffer jumps
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207
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208 #ifndef PRODUCT
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209 void MacroAssembler::ret( bool trace ) { if (trace) {
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210 mov(I7, O7); // traceable register
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211 JMP(O7, 2 * BytesPerInstWord);
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212 } else {
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213 jmpl( I7, 2 * BytesPerInstWord, G0 );
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214 }
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215 }
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216
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217 void MacroAssembler::retl( bool trace ) { if (trace) JMP(O7, 2 * BytesPerInstWord);
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218 else jmpl( O7, 2 * BytesPerInstWord, G0 ); }
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219 #endif /* PRODUCT */
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220
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221
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222 void MacroAssembler::jmp2(Register r1, Register r2, const char* file, int line ) {
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223 assert_not_delayed();
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224 // This can only be traceable if r1 & r2 are visible after a window save
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225 if (TraceJumps) {
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226 #ifndef PRODUCT
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227 save_frame(0);
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228 verify_thread();
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229 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0);
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230 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1);
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231 sll(O0, exact_log2(4*sizeof(intptr_t)), O2);
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232 add(O2, O1, O1);
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233
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234 add(r1->after_save(), r2->after_save(), O2);
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235 set((intptr_t)file, O3);
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236 set(line, O4);
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237 Label L;
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238 // get nearby pc, store jmp target
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239 call(L, relocInfo::none); // No relocation for call to pc+0x8
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240 delayed()->st(O2, O1, 0);
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241 bind(L);
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242
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243 // store nearby pc
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244 st(O7, O1, sizeof(intptr_t));
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245 // store file
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246 st(O3, O1, 2*sizeof(intptr_t));
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247 // store line
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248 st(O4, O1, 3*sizeof(intptr_t));
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249 add(O0, 1, O0);
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250 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0);
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251 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()));
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252 restore();
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253 #endif /* PRODUCT */
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254 }
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255 jmpl(r1, r2, G0);
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256 }
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257 void MacroAssembler::jmp(Register r1, int offset, const char* file, int line ) {
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258 assert_not_delayed();
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259 // This can only be traceable if r1 is visible after a window save
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260 if (TraceJumps) {
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261 #ifndef PRODUCT
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262 save_frame(0);
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263 verify_thread();
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264 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0);
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265 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1);
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266 sll(O0, exact_log2(4*sizeof(intptr_t)), O2);
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267 add(O2, O1, O1);
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268
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269 add(r1->after_save(), offset, O2);
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270 set((intptr_t)file, O3);
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271 set(line, O4);
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272 Label L;
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273 // get nearby pc, store jmp target
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274 call(L, relocInfo::none); // No relocation for call to pc+0x8
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275 delayed()->st(O2, O1, 0);
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276 bind(L);
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277
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278 // store nearby pc
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279 st(O7, O1, sizeof(intptr_t));
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280 // store file
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281 st(O3, O1, 2*sizeof(intptr_t));
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282 // store line
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283 st(O4, O1, 3*sizeof(intptr_t));
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284 add(O0, 1, O0);
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285 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0);
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286 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()));
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287 restore();
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288 #endif /* PRODUCT */
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289 }
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290 jmp(r1, offset);
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291 }
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292
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293 // This code sequence is relocatable to any address, even on LP64.
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294 void MacroAssembler::jumpl(const AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line) {
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295 assert_not_delayed();
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296 // Force fixed length sethi because NativeJump and NativeFarCall don't handle
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297 // variable length instruction streams.
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298 patchable_sethi(addrlit, temp);
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299 Address a(temp, addrlit.low10() + offset); // Add the offset to the displacement.
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300 if (TraceJumps) {
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301 #ifndef PRODUCT
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302 // Must do the add here so relocation can find the remainder of the
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303 // value to be relocated.
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304 add(a.base(), a.disp(), a.base(), addrlit.rspec(offset));
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305 save_frame(0);
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306 verify_thread();
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307 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0);
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308 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1);
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309 sll(O0, exact_log2(4*sizeof(intptr_t)), O2);
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310 add(O2, O1, O1);
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311
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312 set((intptr_t)file, O3);
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313 set(line, O4);
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314 Label L;
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315
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316 // get nearby pc, store jmp target
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317 call(L, relocInfo::none); // No relocation for call to pc+0x8
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318 delayed()->st(a.base()->after_save(), O1, 0);
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319 bind(L);
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320
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321 // store nearby pc
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322 st(O7, O1, sizeof(intptr_t));
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323 // store file
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324 st(O3, O1, 2*sizeof(intptr_t));
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325 // store line
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326 st(O4, O1, 3*sizeof(intptr_t));
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327 add(O0, 1, O0);
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328 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0);
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329 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()));
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330 restore();
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331 jmpl(a.base(), G0, d);
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332 #else
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333 jmpl(a.base(), a.disp(), d);
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334 #endif /* PRODUCT */
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335 } else {
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336 jmpl(a.base(), a.disp(), d);
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337 }
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338 }
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339
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340 void MacroAssembler::jump(const AddressLiteral& addrlit, Register temp, int offset, const char* file, int line) {
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341 jumpl(addrlit, temp, G0, offset, file, line);
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342 }
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343
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344
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345 // Conditional breakpoint (for assertion checks in assembly code)
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346 void MacroAssembler::breakpoint_trap(Condition c, CC cc) {
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347 trap(c, cc, G0, ST_RESERVED_FOR_USER_0);
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348 }
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349
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350 // We want to use ST_BREAKPOINT here, but the debugger is confused by it.
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351 void MacroAssembler::breakpoint_trap() {
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352 trap(ST_RESERVED_FOR_USER_0);
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353 }
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354
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355 // flush windows (except current) using flushw instruction if avail.
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356 void MacroAssembler::flush_windows() {
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357 if (VM_Version::v9_instructions_work()) flushw();
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358 else flush_windows_trap();
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359 }
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360
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361 // Write serialization page so VM thread can do a pseudo remote membar
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362 // We use the current thread pointer to calculate a thread specific
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363 // offset to write to within the page. This minimizes bus traffic
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364 // due to cache line collision.
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365 void MacroAssembler::serialize_memory(Register thread, Register tmp1, Register tmp2) {
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366 srl(thread, os::get_serialize_page_shift_count(), tmp2);
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367 if (Assembler::is_simm13(os::vm_page_size())) {
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368 and3(tmp2, (os::vm_page_size() - sizeof(int)), tmp2);
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369 }
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370 else {
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371 set((os::vm_page_size() - sizeof(int)), tmp1);
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372 and3(tmp2, tmp1, tmp2);
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373 }
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374 set(os::get_memory_serialize_page(), tmp1);
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375 st(G0, tmp1, tmp2);
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376 }
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377
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378
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379
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380 void MacroAssembler::enter() {
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381 Unimplemented();
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382 }
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383
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384 void MacroAssembler::leave() {
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385 Unimplemented();
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386 }
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387
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388 void MacroAssembler::mult(Register s1, Register s2, Register d) {
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389 if(VM_Version::v9_instructions_work()) {
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390 mulx (s1, s2, d);
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391 } else {
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392 smul (s1, s2, d);
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393 }
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394 }
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395
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396 void MacroAssembler::mult(Register s1, int simm13a, Register d) {
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397 if(VM_Version::v9_instructions_work()) {
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398 mulx (s1, simm13a, d);
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399 } else {
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400 smul (s1, simm13a, d);
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401 }
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402 }
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403
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404
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405 #ifdef ASSERT
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406 void MacroAssembler::read_ccr_v8_assert(Register ccr_save) {
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407 const Register s1 = G3_scratch;
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408 const Register s2 = G4_scratch;
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409 Label get_psr_test;
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410 // Get the condition codes the V8 way.
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411 read_ccr_trap(s1);
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412 mov(ccr_save, s2);
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413 // This is a test of V8 which has icc but not xcc
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414 // so mask off the xcc bits
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415 and3(s2, 0xf, s2);
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416 // Compare condition codes from the V8 and V9 ways.
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417 subcc(s2, s1, G0);
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418 br(Assembler::notEqual, true, Assembler::pt, get_psr_test);
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419 delayed()->breakpoint_trap();
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420 bind(get_psr_test);
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421 }
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422
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423 void MacroAssembler::write_ccr_v8_assert(Register ccr_save) {
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424 const Register s1 = G3_scratch;
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425 const Register s2 = G4_scratch;
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426 Label set_psr_test;
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427 // Write out the saved condition codes the V8 way
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428 write_ccr_trap(ccr_save, s1, s2);
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429 // Read back the condition codes using the V9 instruction
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430 rdccr(s1);
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431 mov(ccr_save, s2);
|
|
432 // This is a test of V8 which has icc but not xcc
|
|
433 // so mask off the xcc bits
|
|
434 and3(s2, 0xf, s2);
|
|
435 and3(s1, 0xf, s1);
|
|
436 // Compare the V8 way with the V9 way.
|
|
437 subcc(s2, s1, G0);
|
|
438 br(Assembler::notEqual, true, Assembler::pt, set_psr_test);
|
|
439 delayed()->breakpoint_trap();
|
|
440 bind(set_psr_test);
|
|
441 }
|
|
442 #else
|
|
443 #define read_ccr_v8_assert(x)
|
|
444 #define write_ccr_v8_assert(x)
|
|
445 #endif // ASSERT
|
|
446
|
|
447 void MacroAssembler::read_ccr(Register ccr_save) {
|
|
448 if (VM_Version::v9_instructions_work()) {
|
|
449 rdccr(ccr_save);
|
|
450 // Test code sequence used on V8. Do not move above rdccr.
|
|
451 read_ccr_v8_assert(ccr_save);
|
|
452 } else {
|
|
453 read_ccr_trap(ccr_save);
|
|
454 }
|
|
455 }
|
|
456
|
|
457 void MacroAssembler::write_ccr(Register ccr_save) {
|
|
458 if (VM_Version::v9_instructions_work()) {
|
|
459 // Test code sequence used on V8. Do not move below wrccr.
|
|
460 write_ccr_v8_assert(ccr_save);
|
|
461 wrccr(ccr_save);
|
|
462 } else {
|
|
463 const Register temp_reg1 = G3_scratch;
|
|
464 const Register temp_reg2 = G4_scratch;
|
|
465 write_ccr_trap(ccr_save, temp_reg1, temp_reg2);
|
|
466 }
|
|
467 }
|
|
468
|
|
469
|
|
470 // Calls to C land
|
|
471
|
|
472 #ifdef ASSERT
|
|
473 // a hook for debugging
|
|
474 static Thread* reinitialize_thread() {
|
|
475 return ThreadLocalStorage::thread();
|
|
476 }
|
|
477 #else
|
|
478 #define reinitialize_thread ThreadLocalStorage::thread
|
|
479 #endif
|
|
480
|
|
481 #ifdef ASSERT
|
|
482 address last_get_thread = NULL;
|
|
483 #endif
|
|
484
|
|
485 // call this when G2_thread is not known to be valid
|
|
486 void MacroAssembler::get_thread() {
|
|
487 save_frame(0); // to avoid clobbering O0
|
|
488 mov(G1, L0); // avoid clobbering G1
|
|
489 mov(G5_method, L1); // avoid clobbering G5
|
|
490 mov(G3, L2); // avoid clobbering G3 also
|
|
491 mov(G4, L5); // avoid clobbering G4
|
|
492 #ifdef ASSERT
|
|
493 AddressLiteral last_get_thread_addrlit(&last_get_thread);
|
|
494 set(last_get_thread_addrlit, L3);
|
|
495 inc(L4, get_pc(L4) + 2 * BytesPerInstWord); // skip getpc() code + inc + st_ptr to point L4 at call
|
|
496 st_ptr(L4, L3, 0);
|
|
497 #endif
|
|
498 call(CAST_FROM_FN_PTR(address, reinitialize_thread), relocInfo::runtime_call_type);
|
|
499 delayed()->nop();
|
|
500 mov(L0, G1);
|
|
501 mov(L1, G5_method);
|
|
502 mov(L2, G3);
|
|
503 mov(L5, G4);
|
|
504 restore(O0, 0, G2_thread);
|
|
505 }
|
|
506
|
|
507 static Thread* verify_thread_subroutine(Thread* gthread_value) {
|
|
508 Thread* correct_value = ThreadLocalStorage::thread();
|
|
509 guarantee(gthread_value == correct_value, "G2_thread value must be the thread");
|
|
510 return correct_value;
|
|
511 }
|
|
512
|
|
513 void MacroAssembler::verify_thread() {
|
|
514 if (VerifyThread) {
|
|
515 // NOTE: this chops off the heads of the 64-bit O registers.
|
|
516 #ifdef CC_INTERP
|
|
517 save_frame(0);
|
|
518 #else
|
|
519 // make sure G2_thread contains the right value
|
|
520 save_frame_and_mov(0, Lmethod, Lmethod); // to avoid clobbering O0 (and propagate Lmethod for -Xprof)
|
|
521 mov(G1, L1); // avoid clobbering G1
|
|
522 // G2 saved below
|
|
523 mov(G3, L3); // avoid clobbering G3
|
|
524 mov(G4, L4); // avoid clobbering G4
|
|
525 mov(G5_method, L5); // avoid clobbering G5_method
|
|
526 #endif /* CC_INTERP */
|
|
527 #if defined(COMPILER2) && !defined(_LP64)
|
|
528 // Save & restore possible 64-bit Long arguments in G-regs
|
|
529 srlx(G1,32,L0);
|
|
530 srlx(G4,32,L6);
|
|
531 #endif
|
|
532 call(CAST_FROM_FN_PTR(address,verify_thread_subroutine), relocInfo::runtime_call_type);
|
|
533 delayed()->mov(G2_thread, O0);
|
|
534
|
|
535 mov(L1, G1); // Restore G1
|
|
536 // G2 restored below
|
|
537 mov(L3, G3); // restore G3
|
|
538 mov(L4, G4); // restore G4
|
|
539 mov(L5, G5_method); // restore G5_method
|
|
540 #if defined(COMPILER2) && !defined(_LP64)
|
|
541 // Save & restore possible 64-bit Long arguments in G-regs
|
|
542 sllx(L0,32,G2); // Move old high G1 bits high in G2
|
|
543 srl(G1, 0,G1); // Clear current high G1 bits
|
|
544 or3 (G1,G2,G1); // Recover 64-bit G1
|
|
545 sllx(L6,32,G2); // Move old high G4 bits high in G2
|
|
546 srl(G4, 0,G4); // Clear current high G4 bits
|
|
547 or3 (G4,G2,G4); // Recover 64-bit G4
|
|
548 #endif
|
|
549 restore(O0, 0, G2_thread);
|
|
550 }
|
|
551 }
|
|
552
|
|
553
|
|
554 void MacroAssembler::save_thread(const Register thread_cache) {
|
|
555 verify_thread();
|
|
556 if (thread_cache->is_valid()) {
|
|
557 assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile");
|
|
558 mov(G2_thread, thread_cache);
|
|
559 }
|
|
560 if (VerifyThread) {
|
|
561 // smash G2_thread, as if the VM were about to anyway
|
|
562 set(0x67676767, G2_thread);
|
|
563 }
|
|
564 }
|
|
565
|
|
566
|
|
567 void MacroAssembler::restore_thread(const Register thread_cache) {
|
|
568 if (thread_cache->is_valid()) {
|
|
569 assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile");
|
|
570 mov(thread_cache, G2_thread);
|
|
571 verify_thread();
|
|
572 } else {
|
|
573 // do it the slow way
|
|
574 get_thread();
|
|
575 }
|
|
576 }
|
|
577
|
|
578
|
|
579 // %%% maybe get rid of [re]set_last_Java_frame
|
|
580 void MacroAssembler::set_last_Java_frame(Register last_java_sp, Register last_Java_pc) {
|
|
581 assert_not_delayed();
|
|
582 Address flags(G2_thread, JavaThread::frame_anchor_offset() +
|
|
583 JavaFrameAnchor::flags_offset());
|
|
584 Address pc_addr(G2_thread, JavaThread::last_Java_pc_offset());
|
|
585
|
|
586 // Always set last_Java_pc and flags first because once last_Java_sp is visible
|
|
587 // has_last_Java_frame is true and users will look at the rest of the fields.
|
|
588 // (Note: flags should always be zero before we get here so doesn't need to be set.)
|
|
589
|
|
590 #ifdef ASSERT
|
|
591 // Verify that flags was zeroed on return to Java
|
|
592 Label PcOk;
|
|
593 save_frame(0); // to avoid clobbering O0
|
|
594 ld_ptr(pc_addr, L0);
|
|
595 br_null_short(L0, Assembler::pt, PcOk);
|
|
596 STOP("last_Java_pc not zeroed before leaving Java");
|
|
597 bind(PcOk);
|
|
598
|
|
599 // Verify that flags was zeroed on return to Java
|
|
600 Label FlagsOk;
|
|
601 ld(flags, L0);
|
|
602 tst(L0);
|
|
603 br(Assembler::zero, false, Assembler::pt, FlagsOk);
|
|
604 delayed() -> restore();
|
|
605 STOP("flags not zeroed before leaving Java");
|
|
606 bind(FlagsOk);
|
|
607 #endif /* ASSERT */
|
|
608 //
|
|
609 // When returning from calling out from Java mode the frame anchor's last_Java_pc
|
|
610 // will always be set to NULL. It is set here so that if we are doing a call to
|
|
611 // native (not VM) that we capture the known pc and don't have to rely on the
|
|
612 // native call having a standard frame linkage where we can find the pc.
|
|
613
|
|
614 if (last_Java_pc->is_valid()) {
|
|
615 st_ptr(last_Java_pc, pc_addr);
|
|
616 }
|
|
617
|
|
618 #ifdef _LP64
|
|
619 #ifdef ASSERT
|
|
620 // Make sure that we have an odd stack
|
|
621 Label StackOk;
|
|
622 andcc(last_java_sp, 0x01, G0);
|
|
623 br(Assembler::notZero, false, Assembler::pt, StackOk);
|
|
624 delayed()->nop();
|
|
625 STOP("Stack Not Biased in set_last_Java_frame");
|
|
626 bind(StackOk);
|
|
627 #endif // ASSERT
|
|
628 assert( last_java_sp != G4_scratch, "bad register usage in set_last_Java_frame");
|
|
629 add( last_java_sp, STACK_BIAS, G4_scratch );
|
|
630 st_ptr(G4_scratch, G2_thread, JavaThread::last_Java_sp_offset());
|
|
631 #else
|
|
632 st_ptr(last_java_sp, G2_thread, JavaThread::last_Java_sp_offset());
|
|
633 #endif // _LP64
|
|
634 }
|
|
635
|
|
636 void MacroAssembler::reset_last_Java_frame(void) {
|
|
637 assert_not_delayed();
|
|
638
|
|
639 Address sp_addr(G2_thread, JavaThread::last_Java_sp_offset());
|
|
640 Address pc_addr(G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
|
|
641 Address flags (G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset());
|
|
642
|
|
643 #ifdef ASSERT
|
|
644 // check that it WAS previously set
|
|
645 #ifdef CC_INTERP
|
|
646 save_frame(0);
|
|
647 #else
|
|
648 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod to helper frame for -Xprof
|
|
649 #endif /* CC_INTERP */
|
|
650 ld_ptr(sp_addr, L0);
|
|
651 tst(L0);
|
|
652 breakpoint_trap(Assembler::zero, Assembler::ptr_cc);
|
|
653 restore();
|
|
654 #endif // ASSERT
|
|
655
|
|
656 st_ptr(G0, sp_addr);
|
|
657 // Always return last_Java_pc to zero
|
|
658 st_ptr(G0, pc_addr);
|
|
659 // Always null flags after return to Java
|
|
660 st(G0, flags);
|
|
661 }
|
|
662
|
|
663
|
|
664 void MacroAssembler::call_VM_base(
|
|
665 Register oop_result,
|
|
666 Register thread_cache,
|
|
667 Register last_java_sp,
|
|
668 address entry_point,
|
|
669 int number_of_arguments,
|
|
670 bool check_exceptions)
|
|
671 {
|
|
672 assert_not_delayed();
|
|
673
|
|
674 // determine last_java_sp register
|
|
675 if (!last_java_sp->is_valid()) {
|
|
676 last_java_sp = SP;
|
|
677 }
|
|
678 // debugging support
|
|
679 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
|
|
680
|
|
681 // 64-bit last_java_sp is biased!
|
|
682 set_last_Java_frame(last_java_sp, noreg);
|
|
683 if (VerifyThread) mov(G2_thread, O0); // about to be smashed; pass early
|
|
684 save_thread(thread_cache);
|
|
685 // do the call
|
|
686 call(entry_point, relocInfo::runtime_call_type);
|
|
687 if (!VerifyThread)
|
|
688 delayed()->mov(G2_thread, O0); // pass thread as first argument
|
|
689 else
|
|
690 delayed()->nop(); // (thread already passed)
|
|
691 restore_thread(thread_cache);
|
|
692 reset_last_Java_frame();
|
|
693
|
|
694 // check for pending exceptions. use Gtemp as scratch register.
|
|
695 if (check_exceptions) {
|
|
696 check_and_forward_exception(Gtemp);
|
|
697 }
|
|
698
|
|
699 #ifdef ASSERT
|
|
700 set(badHeapWordVal, G3);
|
|
701 set(badHeapWordVal, G4);
|
|
702 set(badHeapWordVal, G5);
|
|
703 #endif
|
|
704
|
|
705 // get oop result if there is one and reset the value in the thread
|
|
706 if (oop_result->is_valid()) {
|
|
707 get_vm_result(oop_result);
|
|
708 }
|
|
709 }
|
|
710
|
|
711 void MacroAssembler::check_and_forward_exception(Register scratch_reg)
|
|
712 {
|
|
713 Label L;
|
|
714
|
|
715 check_and_handle_popframe(scratch_reg);
|
|
716 check_and_handle_earlyret(scratch_reg);
|
|
717
|
|
718 Address exception_addr(G2_thread, Thread::pending_exception_offset());
|
|
719 ld_ptr(exception_addr, scratch_reg);
|
|
720 br_null_short(scratch_reg, pt, L);
|
|
721 // we use O7 linkage so that forward_exception_entry has the issuing PC
|
|
722 call(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type);
|
|
723 delayed()->nop();
|
|
724 bind(L);
|
|
725 }
|
|
726
|
|
727
|
|
728 void MacroAssembler::check_and_handle_popframe(Register scratch_reg) {
|
|
729 }
|
|
730
|
|
731
|
|
732 void MacroAssembler::check_and_handle_earlyret(Register scratch_reg) {
|
|
733 }
|
|
734
|
|
735
|
|
736 void MacroAssembler::call_VM(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
|
|
737 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions);
|
|
738 }
|
|
739
|
|
740
|
|
741 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions) {
|
|
742 // O0 is reserved for the thread
|
|
743 mov(arg_1, O1);
|
|
744 call_VM(oop_result, entry_point, 1, check_exceptions);
|
|
745 }
|
|
746
|
|
747
|
|
748 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {
|
|
749 // O0 is reserved for the thread
|
|
750 mov(arg_1, O1);
|
|
751 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
|
|
752 call_VM(oop_result, entry_point, 2, check_exceptions);
|
|
753 }
|
|
754
|
|
755
|
|
756 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) {
|
|
757 // O0 is reserved for the thread
|
|
758 mov(arg_1, O1);
|
|
759 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
|
|
760 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument");
|
|
761 call_VM(oop_result, entry_point, 3, check_exceptions);
|
|
762 }
|
|
763
|
|
764
|
|
765
|
|
766 // Note: The following call_VM overloadings are useful when a "save"
|
|
767 // has already been performed by a stub, and the last Java frame is
|
|
768 // the previous one. In that case, last_java_sp must be passed as FP
|
|
769 // instead of SP.
|
|
770
|
|
771
|
|
772 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments, bool check_exceptions) {
|
|
773 call_VM_base(oop_result, noreg, last_java_sp, entry_point, number_of_arguments, check_exceptions);
|
|
774 }
|
|
775
|
|
776
|
|
777 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions) {
|
|
778 // O0 is reserved for the thread
|
|
779 mov(arg_1, O1);
|
|
780 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
|
|
781 }
|
|
782
|
|
783
|
|
784 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {
|
|
785 // O0 is reserved for the thread
|
|
786 mov(arg_1, O1);
|
|
787 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
|
|
788 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
|
|
789 }
|
|
790
|
|
791
|
|
792 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) {
|
|
793 // O0 is reserved for the thread
|
|
794 mov(arg_1, O1);
|
|
795 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
|
|
796 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument");
|
|
797 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
|
|
798 }
|
|
799
|
|
800
|
|
801
|
|
802 void MacroAssembler::call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments) {
|
|
803 assert_not_delayed();
|
|
804 save_thread(thread_cache);
|
|
805 // do the call
|
|
806 call(entry_point, relocInfo::runtime_call_type);
|
|
807 delayed()->nop();
|
|
808 restore_thread(thread_cache);
|
|
809 #ifdef ASSERT
|
|
810 set(badHeapWordVal, G3);
|
|
811 set(badHeapWordVal, G4);
|
|
812 set(badHeapWordVal, G5);
|
|
813 #endif
|
|
814 }
|
|
815
|
|
816
|
|
817 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments) {
|
|
818 call_VM_leaf_base(thread_cache, entry_point, number_of_arguments);
|
|
819 }
|
|
820
|
|
821
|
|
822 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1) {
|
|
823 mov(arg_1, O0);
|
|
824 call_VM_leaf(thread_cache, entry_point, 1);
|
|
825 }
|
|
826
|
|
827
|
|
828 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2) {
|
|
829 mov(arg_1, O0);
|
|
830 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument");
|
|
831 call_VM_leaf(thread_cache, entry_point, 2);
|
|
832 }
|
|
833
|
|
834
|
|
835 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3) {
|
|
836 mov(arg_1, O0);
|
|
837 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument");
|
|
838 mov(arg_3, O2); assert(arg_3 != O0 && arg_3 != O1, "smashed argument");
|
|
839 call_VM_leaf(thread_cache, entry_point, 3);
|
|
840 }
|
|
841
|
|
842
|
|
843 void MacroAssembler::get_vm_result(Register oop_result) {
|
|
844 verify_thread();
|
|
845 Address vm_result_addr(G2_thread, JavaThread::vm_result_offset());
|
|
846 ld_ptr( vm_result_addr, oop_result);
|
|
847 st_ptr(G0, vm_result_addr);
|
|
848 verify_oop(oop_result);
|
|
849 }
|
|
850
|
|
851
|
|
852 void MacroAssembler::get_vm_result_2(Register metadata_result) {
|
|
853 verify_thread();
|
|
854 Address vm_result_addr_2(G2_thread, JavaThread::vm_result_2_offset());
|
|
855 ld_ptr(vm_result_addr_2, metadata_result);
|
|
856 st_ptr(G0, vm_result_addr_2);
|
|
857 }
|
|
858
|
|
859
|
|
860 // We require that C code which does not return a value in vm_result will
|
|
861 // leave it undisturbed.
|
|
862 void MacroAssembler::set_vm_result(Register oop_result) {
|
|
863 verify_thread();
|
|
864 Address vm_result_addr(G2_thread, JavaThread::vm_result_offset());
|
|
865 verify_oop(oop_result);
|
|
866
|
|
867 # ifdef ASSERT
|
|
868 // Check that we are not overwriting any other oop.
|
|
869 #ifdef CC_INTERP
|
|
870 save_frame(0);
|
|
871 #else
|
|
872 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod for -Xprof
|
|
873 #endif /* CC_INTERP */
|
|
874 ld_ptr(vm_result_addr, L0);
|
|
875 tst(L0);
|
|
876 restore();
|
|
877 breakpoint_trap(notZero, Assembler::ptr_cc);
|
|
878 // }
|
|
879 # endif
|
|
880
|
|
881 st_ptr(oop_result, vm_result_addr);
|
|
882 }
|
|
883
|
|
884
|
|
885 void MacroAssembler::ic_call(address entry, bool emit_delay) {
|
|
886 RelocationHolder rspec = virtual_call_Relocation::spec(pc());
|
|
887 patchable_set((intptr_t)Universe::non_oop_word(), G5_inline_cache_reg);
|
|
888 relocate(rspec);
|
|
889 call(entry, relocInfo::none);
|
|
890 if (emit_delay) {
|
|
891 delayed()->nop();
|
|
892 }
|
|
893 }
|
|
894
|
|
895
|
|
896 void MacroAssembler::card_table_write(jbyte* byte_map_base,
|
|
897 Register tmp, Register obj) {
|
|
898 #ifdef _LP64
|
|
899 srlx(obj, CardTableModRefBS::card_shift, obj);
|
|
900 #else
|
|
901 srl(obj, CardTableModRefBS::card_shift, obj);
|
|
902 #endif
|
|
903 assert(tmp != obj, "need separate temp reg");
|
|
904 set((address) byte_map_base, tmp);
|
|
905 stb(G0, tmp, obj);
|
|
906 }
|
|
907
|
|
908
|
|
909 void MacroAssembler::internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) {
|
|
910 address save_pc;
|
|
911 int shiftcnt;
|
|
912 #ifdef _LP64
|
|
913 # ifdef CHECK_DELAY
|
|
914 assert_not_delayed((char*) "cannot put two instructions in delay slot");
|
|
915 # endif
|
|
916 v9_dep();
|
|
917 save_pc = pc();
|
|
918
|
|
919 int msb32 = (int) (addrlit.value() >> 32);
|
|
920 int lsb32 = (int) (addrlit.value());
|
|
921
|
|
922 if (msb32 == 0 && lsb32 >= 0) {
|
|
923 Assembler::sethi(lsb32, d, addrlit.rspec());
|
|
924 }
|
|
925 else if (msb32 == -1) {
|
|
926 Assembler::sethi(~lsb32, d, addrlit.rspec());
|
|
927 xor3(d, ~low10(~0), d);
|
|
928 }
|
|
929 else {
|
|
930 Assembler::sethi(msb32, d, addrlit.rspec()); // msb 22-bits
|
|
931 if (msb32 & 0x3ff) // Any bits?
|
|
932 or3(d, msb32 & 0x3ff, d); // msb 32-bits are now in lsb 32
|
|
933 if (lsb32 & 0xFFFFFC00) { // done?
|
|
934 if ((lsb32 >> 20) & 0xfff) { // Any bits set?
|
|
935 sllx(d, 12, d); // Make room for next 12 bits
|
|
936 or3(d, (lsb32 >> 20) & 0xfff, d); // Or in next 12
|
|
937 shiftcnt = 0; // We already shifted
|
|
938 }
|
|
939 else
|
|
940 shiftcnt = 12;
|
|
941 if ((lsb32 >> 10) & 0x3ff) {
|
|
942 sllx(d, shiftcnt + 10, d); // Make room for last 10 bits
|
|
943 or3(d, (lsb32 >> 10) & 0x3ff, d); // Or in next 10
|
|
944 shiftcnt = 0;
|
|
945 }
|
|
946 else
|
|
947 shiftcnt = 10;
|
|
948 sllx(d, shiftcnt + 10, d); // Shift leaving disp field 0'd
|
|
949 }
|
|
950 else
|
|
951 sllx(d, 32, d);
|
|
952 }
|
|
953 // Pad out the instruction sequence so it can be patched later.
|
|
954 if (ForceRelocatable || (addrlit.rtype() != relocInfo::none &&
|
|
955 addrlit.rtype() != relocInfo::runtime_call_type)) {
|
|
956 while (pc() < (save_pc + (7 * BytesPerInstWord)))
|
|
957 nop();
|
|
958 }
|
|
959 #else
|
|
960 Assembler::sethi(addrlit.value(), d, addrlit.rspec());
|
|
961 #endif
|
|
962 }
|
|
963
|
|
964
|
|
965 void MacroAssembler::sethi(const AddressLiteral& addrlit, Register d) {
|
|
966 internal_sethi(addrlit, d, false);
|
|
967 }
|
|
968
|
|
969
|
|
970 void MacroAssembler::patchable_sethi(const AddressLiteral& addrlit, Register d) {
|
|
971 internal_sethi(addrlit, d, true);
|
|
972 }
|
|
973
|
|
974
|
|
975 int MacroAssembler::insts_for_sethi(address a, bool worst_case) {
|
|
976 #ifdef _LP64
|
|
977 if (worst_case) return 7;
|
|
978 intptr_t iaddr = (intptr_t) a;
|
|
979 int msb32 = (int) (iaddr >> 32);
|
|
980 int lsb32 = (int) (iaddr);
|
|
981 int count;
|
|
982 if (msb32 == 0 && lsb32 >= 0)
|
|
983 count = 1;
|
|
984 else if (msb32 == -1)
|
|
985 count = 2;
|
|
986 else {
|
|
987 count = 2;
|
|
988 if (msb32 & 0x3ff)
|
|
989 count++;
|
|
990 if (lsb32 & 0xFFFFFC00 ) {
|
|
991 if ((lsb32 >> 20) & 0xfff) count += 2;
|
|
992 if ((lsb32 >> 10) & 0x3ff) count += 2;
|
|
993 }
|
|
994 }
|
|
995 return count;
|
|
996 #else
|
|
997 return 1;
|
|
998 #endif
|
|
999 }
|
|
1000
|
|
1001 int MacroAssembler::worst_case_insts_for_set() {
|
|
1002 return insts_for_sethi(NULL, true) + 1;
|
|
1003 }
|
|
1004
|
|
1005
|
|
1006 // Keep in sync with MacroAssembler::insts_for_internal_set
|
|
1007 void MacroAssembler::internal_set(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) {
|
|
1008 intptr_t value = addrlit.value();
|
|
1009
|
|
1010 if (!ForceRelocatable && addrlit.rspec().type() == relocInfo::none) {
|
|
1011 // can optimize
|
|
1012 if (-4096 <= value && value <= 4095) {
|
|
1013 or3(G0, value, d); // setsw (this leaves upper 32 bits sign-extended)
|
|
1014 return;
|
|
1015 }
|
|
1016 if (inv_hi22(hi22(value)) == value) {
|
|
1017 sethi(addrlit, d);
|
|
1018 return;
|
|
1019 }
|
|
1020 }
|
|
1021 assert_not_delayed((char*) "cannot put two instructions in delay slot");
|
|
1022 internal_sethi(addrlit, d, ForceRelocatable);
|
|
1023 if (ForceRelocatable || addrlit.rspec().type() != relocInfo::none || addrlit.low10() != 0) {
|
|
1024 add(d, addrlit.low10(), d, addrlit.rspec());
|
|
1025 }
|
|
1026 }
|
|
1027
|
|
1028 // Keep in sync with MacroAssembler::internal_set
|
|
1029 int MacroAssembler::insts_for_internal_set(intptr_t value) {
|
|
1030 // can optimize
|
|
1031 if (-4096 <= value && value <= 4095) {
|
|
1032 return 1;
|
|
1033 }
|
|
1034 if (inv_hi22(hi22(value)) == value) {
|
|
1035 return insts_for_sethi((address) value);
|
|
1036 }
|
|
1037 int count = insts_for_sethi((address) value);
|
|
1038 AddressLiteral al(value);
|
|
1039 if (al.low10() != 0) {
|
|
1040 count++;
|
|
1041 }
|
|
1042 return count;
|
|
1043 }
|
|
1044
|
|
1045 void MacroAssembler::set(const AddressLiteral& al, Register d) {
|
|
1046 internal_set(al, d, false);
|
|
1047 }
|
|
1048
|
|
1049 void MacroAssembler::set(intptr_t value, Register d) {
|
|
1050 AddressLiteral al(value);
|
|
1051 internal_set(al, d, false);
|
|
1052 }
|
|
1053
|
|
1054 void MacroAssembler::set(address addr, Register d, RelocationHolder const& rspec) {
|
|
1055 AddressLiteral al(addr, rspec);
|
|
1056 internal_set(al, d, false);
|
|
1057 }
|
|
1058
|
|
1059 void MacroAssembler::patchable_set(const AddressLiteral& al, Register d) {
|
|
1060 internal_set(al, d, true);
|
|
1061 }
|
|
1062
|
|
1063 void MacroAssembler::patchable_set(intptr_t value, Register d) {
|
|
1064 AddressLiteral al(value);
|
|
1065 internal_set(al, d, true);
|
|
1066 }
|
|
1067
|
|
1068
|
|
1069 void MacroAssembler::set64(jlong value, Register d, Register tmp) {
|
|
1070 assert_not_delayed();
|
|
1071 v9_dep();
|
|
1072
|
|
1073 int hi = (int)(value >> 32);
|
|
1074 int lo = (int)(value & ~0);
|
|
1075 // (Matcher::isSimpleConstant64 knows about the following optimizations.)
|
|
1076 if (Assembler::is_simm13(lo) && value == lo) {
|
|
1077 or3(G0, lo, d);
|
|
1078 } else if (hi == 0) {
|
|
1079 Assembler::sethi(lo, d); // hardware version zero-extends to upper 32
|
|
1080 if (low10(lo) != 0)
|
|
1081 or3(d, low10(lo), d);
|
|
1082 }
|
|
1083 else if (hi == -1) {
|
|
1084 Assembler::sethi(~lo, d); // hardware version zero-extends to upper 32
|
|
1085 xor3(d, low10(lo) ^ ~low10(~0), d);
|
|
1086 }
|
|
1087 else if (lo == 0) {
|
|
1088 if (Assembler::is_simm13(hi)) {
|
|
1089 or3(G0, hi, d);
|
|
1090 } else {
|
|
1091 Assembler::sethi(hi, d); // hardware version zero-extends to upper 32
|
|
1092 if (low10(hi) != 0)
|
|
1093 or3(d, low10(hi), d);
|
|
1094 }
|
|
1095 sllx(d, 32, d);
|
|
1096 }
|
|
1097 else {
|
|
1098 Assembler::sethi(hi, tmp);
|
|
1099 Assembler::sethi(lo, d); // macro assembler version sign-extends
|
|
1100 if (low10(hi) != 0)
|
|
1101 or3 (tmp, low10(hi), tmp);
|
|
1102 if (low10(lo) != 0)
|
|
1103 or3 ( d, low10(lo), d);
|
|
1104 sllx(tmp, 32, tmp);
|
|
1105 or3 (d, tmp, d);
|
|
1106 }
|
|
1107 }
|
|
1108
|
|
1109 int MacroAssembler::insts_for_set64(jlong value) {
|
|
1110 v9_dep();
|
|
1111
|
|
1112 int hi = (int) (value >> 32);
|
|
1113 int lo = (int) (value & ~0);
|
|
1114 int count = 0;
|
|
1115
|
|
1116 // (Matcher::isSimpleConstant64 knows about the following optimizations.)
|
|
1117 if (Assembler::is_simm13(lo) && value == lo) {
|
|
1118 count++;
|
|
1119 } else if (hi == 0) {
|
|
1120 count++;
|
|
1121 if (low10(lo) != 0)
|
|
1122 count++;
|
|
1123 }
|
|
1124 else if (hi == -1) {
|
|
1125 count += 2;
|
|
1126 }
|
|
1127 else if (lo == 0) {
|
|
1128 if (Assembler::is_simm13(hi)) {
|
|
1129 count++;
|
|
1130 } else {
|
|
1131 count++;
|
|
1132 if (low10(hi) != 0)
|
|
1133 count++;
|
|
1134 }
|
|
1135 count++;
|
|
1136 }
|
|
1137 else {
|
|
1138 count += 2;
|
|
1139 if (low10(hi) != 0)
|
|
1140 count++;
|
|
1141 if (low10(lo) != 0)
|
|
1142 count++;
|
|
1143 count += 2;
|
|
1144 }
|
|
1145 return count;
|
|
1146 }
|
|
1147
|
|
1148 // compute size in bytes of sparc frame, given
|
|
1149 // number of extraWords
|
|
1150 int MacroAssembler::total_frame_size_in_bytes(int extraWords) {
|
|
1151
|
|
1152 int nWords = frame::memory_parameter_word_sp_offset;
|
|
1153
|
|
1154 nWords += extraWords;
|
|
1155
|
|
1156 if (nWords & 1) ++nWords; // round up to double-word
|
|
1157
|
|
1158 return nWords * BytesPerWord;
|
|
1159 }
|
|
1160
|
|
1161
|
|
1162 // save_frame: given number of "extra" words in frame,
|
|
1163 // issue approp. save instruction (p 200, v8 manual)
|
|
1164
|
|
1165 void MacroAssembler::save_frame(int extraWords) {
|
|
1166 int delta = -total_frame_size_in_bytes(extraWords);
|
|
1167 if (is_simm13(delta)) {
|
|
1168 save(SP, delta, SP);
|
|
1169 } else {
|
|
1170 set(delta, G3_scratch);
|
|
1171 save(SP, G3_scratch, SP);
|
|
1172 }
|
|
1173 }
|
|
1174
|
|
1175
|
|
1176 void MacroAssembler::save_frame_c1(int size_in_bytes) {
|
|
1177 if (is_simm13(-size_in_bytes)) {
|
|
1178 save(SP, -size_in_bytes, SP);
|
|
1179 } else {
|
|
1180 set(-size_in_bytes, G3_scratch);
|
|
1181 save(SP, G3_scratch, SP);
|
|
1182 }
|
|
1183 }
|
|
1184
|
|
1185
|
|
1186 void MacroAssembler::save_frame_and_mov(int extraWords,
|
|
1187 Register s1, Register d1,
|
|
1188 Register s2, Register d2) {
|
|
1189 assert_not_delayed();
|
|
1190
|
|
1191 // The trick here is to use precisely the same memory word
|
|
1192 // that trap handlers also use to save the register.
|
|
1193 // This word cannot be used for any other purpose, but
|
|
1194 // it works fine to save the register's value, whether or not
|
|
1195 // an interrupt flushes register windows at any given moment!
|
|
1196 Address s1_addr;
|
|
1197 if (s1->is_valid() && (s1->is_in() || s1->is_local())) {
|
|
1198 s1_addr = s1->address_in_saved_window();
|
|
1199 st_ptr(s1, s1_addr);
|
|
1200 }
|
|
1201
|
|
1202 Address s2_addr;
|
|
1203 if (s2->is_valid() && (s2->is_in() || s2->is_local())) {
|
|
1204 s2_addr = s2->address_in_saved_window();
|
|
1205 st_ptr(s2, s2_addr);
|
|
1206 }
|
|
1207
|
|
1208 save_frame(extraWords);
|
|
1209
|
|
1210 if (s1_addr.base() == SP) {
|
|
1211 ld_ptr(s1_addr.after_save(), d1);
|
|
1212 } else if (s1->is_valid()) {
|
|
1213 mov(s1->after_save(), d1);
|
|
1214 }
|
|
1215
|
|
1216 if (s2_addr.base() == SP) {
|
|
1217 ld_ptr(s2_addr.after_save(), d2);
|
|
1218 } else if (s2->is_valid()) {
|
|
1219 mov(s2->after_save(), d2);
|
|
1220 }
|
|
1221 }
|
|
1222
|
|
1223
|
|
1224 AddressLiteral MacroAssembler::allocate_metadata_address(Metadata* obj) {
|
|
1225 assert(oop_recorder() != NULL, "this assembler needs a Recorder");
|
|
1226 int index = oop_recorder()->allocate_metadata_index(obj);
|
|
1227 RelocationHolder rspec = metadata_Relocation::spec(index);
|
|
1228 return AddressLiteral((address)obj, rspec);
|
|
1229 }
|
|
1230
|
|
1231 AddressLiteral MacroAssembler::constant_metadata_address(Metadata* obj) {
|
|
1232 assert(oop_recorder() != NULL, "this assembler needs a Recorder");
|
|
1233 int index = oop_recorder()->find_index(obj);
|
|
1234 RelocationHolder rspec = metadata_Relocation::spec(index);
|
|
1235 return AddressLiteral((address)obj, rspec);
|
|
1236 }
|
|
1237
|
|
1238
|
|
1239 AddressLiteral MacroAssembler::constant_oop_address(jobject obj) {
|
|
1240 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
|
|
1241 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "not an oop");
|
|
1242 int oop_index = oop_recorder()->find_index(obj);
|
|
1243 return AddressLiteral(obj, oop_Relocation::spec(oop_index));
|
|
1244 }
|
|
1245
|
|
1246 void MacroAssembler::set_narrow_oop(jobject obj, Register d) {
|
|
1247 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
|
|
1248 int oop_index = oop_recorder()->find_index(obj);
|
|
1249 RelocationHolder rspec = oop_Relocation::spec(oop_index);
|
|
1250
|
|
1251 assert_not_delayed();
|
|
1252 // Relocation with special format (see relocInfo_sparc.hpp).
|
|
1253 relocate(rspec, 1);
|
|
1254 // Assembler::sethi(0x3fffff, d);
|
|
1255 emit_long( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(0x3fffff) );
|
|
1256 // Don't add relocation for 'add'. Do patching during 'sethi' processing.
|
|
1257 add(d, 0x3ff, d);
|
|
1258
|
|
1259 }
|
|
1260
|
|
1261 void MacroAssembler::set_narrow_klass(Klass* k, Register d) {
|
|
1262 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
|
|
1263 int klass_index = oop_recorder()->find_index(k);
|
|
1264 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
|
|
1265 narrowOop encoded_k = oopDesc::encode_klass(k);
|
|
1266
|
|
1267 assert_not_delayed();
|
|
1268 // Relocation with special format (see relocInfo_sparc.hpp).
|
|
1269 relocate(rspec, 1);
|
|
1270 // Assembler::sethi(encoded_k, d);
|
|
1271 emit_long( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(encoded_k) );
|
|
1272 // Don't add relocation for 'add'. Do patching during 'sethi' processing.
|
|
1273 add(d, low10(encoded_k), d);
|
|
1274
|
|
1275 }
|
|
1276
|
|
1277 void MacroAssembler::align(int modulus) {
|
|
1278 while (offset() % modulus != 0) nop();
|
|
1279 }
|
|
1280
|
|
1281
|
|
1282 void MacroAssembler::safepoint() {
|
|
1283 relocate(breakpoint_Relocation::spec(breakpoint_Relocation::safepoint));
|
|
1284 }
|
|
1285
|
|
1286
|
|
1287 void RegistersForDebugging::print(outputStream* s) {
|
|
1288 FlagSetting fs(Debugging, true);
|
|
1289 int j;
|
|
1290 for (j = 0; j < 8; ++j) {
|
|
1291 if (j != 6) { s->print("i%d = ", j); os::print_location(s, i[j]); }
|
|
1292 else { s->print( "fp = " ); os::print_location(s, i[j]); }
|
|
1293 }
|
|
1294 s->cr();
|
|
1295
|
|
1296 for (j = 0; j < 8; ++j) {
|
|
1297 s->print("l%d = ", j); os::print_location(s, l[j]);
|
|
1298 }
|
|
1299 s->cr();
|
|
1300
|
|
1301 for (j = 0; j < 8; ++j) {
|
|
1302 if (j != 6) { s->print("o%d = ", j); os::print_location(s, o[j]); }
|
|
1303 else { s->print( "sp = " ); os::print_location(s, o[j]); }
|
|
1304 }
|
|
1305 s->cr();
|
|
1306
|
|
1307 for (j = 0; j < 8; ++j) {
|
|
1308 s->print("g%d = ", j); os::print_location(s, g[j]);
|
|
1309 }
|
|
1310 s->cr();
|
|
1311
|
|
1312 // print out floats with compression
|
|
1313 for (j = 0; j < 32; ) {
|
|
1314 jfloat val = f[j];
|
|
1315 int last = j;
|
|
1316 for ( ; last+1 < 32; ++last ) {
|
|
1317 char b1[1024], b2[1024];
|
|
1318 sprintf(b1, "%f", val);
|
|
1319 sprintf(b2, "%f", f[last+1]);
|
|
1320 if (strcmp(b1, b2))
|
|
1321 break;
|
|
1322 }
|
|
1323 s->print("f%d", j);
|
|
1324 if ( j != last ) s->print(" - f%d", last);
|
|
1325 s->print(" = %f", val);
|
|
1326 s->fill_to(25);
|
|
1327 s->print_cr(" (0x%x)", val);
|
|
1328 j = last + 1;
|
|
1329 }
|
|
1330 s->cr();
|
|
1331
|
|
1332 // and doubles (evens only)
|
|
1333 for (j = 0; j < 32; ) {
|
|
1334 jdouble val = d[j];
|
|
1335 int last = j;
|
|
1336 for ( ; last+1 < 32; ++last ) {
|
|
1337 char b1[1024], b2[1024];
|
|
1338 sprintf(b1, "%f", val);
|
|
1339 sprintf(b2, "%f", d[last+1]);
|
|
1340 if (strcmp(b1, b2))
|
|
1341 break;
|
|
1342 }
|
|
1343 s->print("d%d", 2 * j);
|
|
1344 if ( j != last ) s->print(" - d%d", last);
|
|
1345 s->print(" = %f", val);
|
|
1346 s->fill_to(30);
|
|
1347 s->print("(0x%x)", *(int*)&val);
|
|
1348 s->fill_to(42);
|
|
1349 s->print_cr("(0x%x)", *(1 + (int*)&val));
|
|
1350 j = last + 1;
|
|
1351 }
|
|
1352 s->cr();
|
|
1353 }
|
|
1354
|
|
1355 void RegistersForDebugging::save_registers(MacroAssembler* a) {
|
|
1356 a->sub(FP, round_to(sizeof(RegistersForDebugging), sizeof(jdouble)) - STACK_BIAS, O0);
|
|
1357 a->flush_windows();
|
|
1358 int i;
|
|
1359 for (i = 0; i < 8; ++i) {
|
|
1360 a->ld_ptr(as_iRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, i_offset(i));
|
|
1361 a->ld_ptr(as_lRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, l_offset(i));
|
|
1362 a->st_ptr(as_oRegister(i)->after_save(), O0, o_offset(i));
|
|
1363 a->st_ptr(as_gRegister(i)->after_save(), O0, g_offset(i));
|
|
1364 }
|
|
1365 for (i = 0; i < 32; ++i) {
|
|
1366 a->stf(FloatRegisterImpl::S, as_FloatRegister(i), O0, f_offset(i));
|
|
1367 }
|
|
1368 for (i = 0; i < (VM_Version::v9_instructions_work() ? 64 : 32); i += 2) {
|
|
1369 a->stf(FloatRegisterImpl::D, as_FloatRegister(i), O0, d_offset(i));
|
|
1370 }
|
|
1371 }
|
|
1372
|
|
1373 void RegistersForDebugging::restore_registers(MacroAssembler* a, Register r) {
|
|
1374 for (int i = 1; i < 8; ++i) {
|
|
1375 a->ld_ptr(r, g_offset(i), as_gRegister(i));
|
|
1376 }
|
|
1377 for (int j = 0; j < 32; ++j) {
|
|
1378 a->ldf(FloatRegisterImpl::S, O0, f_offset(j), as_FloatRegister(j));
|
|
1379 }
|
|
1380 for (int k = 0; k < (VM_Version::v9_instructions_work() ? 64 : 32); k += 2) {
|
|
1381 a->ldf(FloatRegisterImpl::D, O0, d_offset(k), as_FloatRegister(k));
|
|
1382 }
|
|
1383 }
|
|
1384
|
|
1385
|
|
1386 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
|
|
1387 void MacroAssembler::push_fTOS() {
|
|
1388 // %%%%%% need to implement this
|
|
1389 }
|
|
1390
|
|
1391 // pops double TOS element from CPU stack and pushes on FPU stack
|
|
1392 void MacroAssembler::pop_fTOS() {
|
|
1393 // %%%%%% need to implement this
|
|
1394 }
|
|
1395
|
|
1396 void MacroAssembler::empty_FPU_stack() {
|
|
1397 // %%%%%% need to implement this
|
|
1398 }
|
|
1399
|
|
1400 void MacroAssembler::_verify_oop(Register reg, const char* msg, const char * file, int line) {
|
|
1401 // plausibility check for oops
|
|
1402 if (!VerifyOops) return;
|
|
1403
|
|
1404 if (reg == G0) return; // always NULL, which is always an oop
|
|
1405
|
|
1406 BLOCK_COMMENT("verify_oop {");
|
|
1407 char buffer[64];
|
|
1408 #ifdef COMPILER1
|
|
1409 if (CommentedAssembly) {
|
|
1410 snprintf(buffer, sizeof(buffer), "verify_oop at %d", offset());
|
|
1411 block_comment(buffer);
|
|
1412 }
|
|
1413 #endif
|
|
1414
|
|
1415 int len = strlen(file) + strlen(msg) + 1 + 4;
|
|
1416 sprintf(buffer, "%d", line);
|
|
1417 len += strlen(buffer);
|
|
1418 sprintf(buffer, " at offset %d ", offset());
|
|
1419 len += strlen(buffer);
|
|
1420 char * real_msg = new char[len];
|
|
1421 sprintf(real_msg, "%s%s(%s:%d)", msg, buffer, file, line);
|
|
1422
|
|
1423 // Call indirectly to solve generation ordering problem
|
|
1424 AddressLiteral a(StubRoutines::verify_oop_subroutine_entry_address());
|
|
1425
|
|
1426 // Make some space on stack above the current register window.
|
|
1427 // Enough to hold 8 64-bit registers.
|
|
1428 add(SP,-8*8,SP);
|
|
1429
|
|
1430 // Save some 64-bit registers; a normal 'save' chops the heads off
|
|
1431 // of 64-bit longs in the 32-bit build.
|
|
1432 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8);
|
|
1433 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8);
|
|
1434 mov(reg,O0); // Move arg into O0; arg might be in O7 which is about to be crushed
|
|
1435 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8);
|
|
1436
|
|
1437 // Size of set() should stay the same
|
|
1438 patchable_set((intptr_t)real_msg, O1);
|
|
1439 // Load address to call to into O7
|
|
1440 load_ptr_contents(a, O7);
|
|
1441 // Register call to verify_oop_subroutine
|
|
1442 callr(O7, G0);
|
|
1443 delayed()->nop();
|
|
1444 // recover frame size
|
|
1445 add(SP, 8*8,SP);
|
|
1446 BLOCK_COMMENT("} verify_oop");
|
|
1447 }
|
|
1448
|
|
1449 void MacroAssembler::_verify_oop_addr(Address addr, const char* msg, const char * file, int line) {
|
|
1450 // plausibility check for oops
|
|
1451 if (!VerifyOops) return;
|
|
1452
|
|
1453 char buffer[64];
|
|
1454 sprintf(buffer, "%d", line);
|
|
1455 int len = strlen(file) + strlen(msg) + 1 + 4 + strlen(buffer);
|
|
1456 sprintf(buffer, " at SP+%d ", addr.disp());
|
|
1457 len += strlen(buffer);
|
|
1458 char * real_msg = new char[len];
|
|
1459 sprintf(real_msg, "%s at SP+%d (%s:%d)", msg, addr.disp(), file, line);
|
|
1460
|
|
1461 // Call indirectly to solve generation ordering problem
|
|
1462 AddressLiteral a(StubRoutines::verify_oop_subroutine_entry_address());
|
|
1463
|
|
1464 // Make some space on stack above the current register window.
|
|
1465 // Enough to hold 8 64-bit registers.
|
|
1466 add(SP,-8*8,SP);
|
|
1467
|
|
1468 // Save some 64-bit registers; a normal 'save' chops the heads off
|
|
1469 // of 64-bit longs in the 32-bit build.
|
|
1470 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8);
|
|
1471 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8);
|
|
1472 ld_ptr(addr.base(), addr.disp() + 8*8, O0); // Load arg into O0; arg might be in O7 which is about to be crushed
|
|
1473 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8);
|
|
1474
|
|
1475 // Size of set() should stay the same
|
|
1476 patchable_set((intptr_t)real_msg, O1);
|
|
1477 // Load address to call to into O7
|
|
1478 load_ptr_contents(a, O7);
|
|
1479 // Register call to verify_oop_subroutine
|
|
1480 callr(O7, G0);
|
|
1481 delayed()->nop();
|
|
1482 // recover frame size
|
|
1483 add(SP, 8*8,SP);
|
|
1484 }
|
|
1485
|
|
1486 // side-door communication with signalHandler in os_solaris.cpp
|
|
1487 address MacroAssembler::_verify_oop_implicit_branch[3] = { NULL };
|
|
1488
|
|
1489 // This macro is expanded just once; it creates shared code. Contract:
|
|
1490 // receives an oop in O0. Must restore O0 & O7 from TLS. Must not smash ANY
|
|
1491 // registers, including flags. May not use a register 'save', as this blows
|
|
1492 // the high bits of the O-regs if they contain Long values. Acts as a 'leaf'
|
|
1493 // call.
|
|
1494 void MacroAssembler::verify_oop_subroutine() {
|
|
1495 assert( VM_Version::v9_instructions_work(), "VerifyOops not supported for V8" );
|
|
1496
|
|
1497 // Leaf call; no frame.
|
|
1498 Label succeed, fail, null_or_fail;
|
|
1499
|
|
1500 // O0 and O7 were saved already (O0 in O0's TLS home, O7 in O5's TLS home).
|
|
1501 // O0 is now the oop to be checked. O7 is the return address.
|
|
1502 Register O0_obj = O0;
|
|
1503
|
|
1504 // Save some more registers for temps.
|
|
1505 stx(O2,SP,frame::register_save_words*wordSize+STACK_BIAS+2*8);
|
|
1506 stx(O3,SP,frame::register_save_words*wordSize+STACK_BIAS+3*8);
|
|
1507 stx(O4,SP,frame::register_save_words*wordSize+STACK_BIAS+4*8);
|
|
1508 stx(O5,SP,frame::register_save_words*wordSize+STACK_BIAS+5*8);
|
|
1509
|
|
1510 // Save flags
|
|
1511 Register O5_save_flags = O5;
|
|
1512 rdccr( O5_save_flags );
|
|
1513
|
|
1514 { // count number of verifies
|
|
1515 Register O2_adr = O2;
|
|
1516 Register O3_accum = O3;
|
|
1517 inc_counter(StubRoutines::verify_oop_count_addr(), O2_adr, O3_accum);
|
|
1518 }
|
|
1519
|
|
1520 Register O2_mask = O2;
|
|
1521 Register O3_bits = O3;
|
|
1522 Register O4_temp = O4;
|
|
1523
|
|
1524 // mark lower end of faulting range
|
|
1525 assert(_verify_oop_implicit_branch[0] == NULL, "set once");
|
|
1526 _verify_oop_implicit_branch[0] = pc();
|
|
1527
|
|
1528 // We can't check the mark oop because it could be in the process of
|
|
1529 // locking or unlocking while this is running.
|
|
1530 set(Universe::verify_oop_mask (), O2_mask);
|
|
1531 set(Universe::verify_oop_bits (), O3_bits);
|
|
1532
|
|
1533 // assert((obj & oop_mask) == oop_bits);
|
|
1534 and3(O0_obj, O2_mask, O4_temp);
|
|
1535 cmp_and_brx_short(O4_temp, O3_bits, notEqual, pn, null_or_fail);
|
|
1536
|
|
1537 if ((NULL_WORD & Universe::verify_oop_mask()) == Universe::verify_oop_bits()) {
|
|
1538 // the null_or_fail case is useless; must test for null separately
|
|
1539 br_null_short(O0_obj, pn, succeed);
|
|
1540 }
|
|
1541
|
|
1542 // Check the Klass* of this object for being in the right area of memory.
|
|
1543 // Cannot do the load in the delay above slot in case O0 is null
|
|
1544 load_klass(O0_obj, O0_obj);
|
|
1545 // assert((klass != NULL)
|
|
1546 br_null_short(O0_obj, pn, fail);
|
|
1547 // TODO: Future assert that klass is lower 4g memory for UseCompressedKlassPointers
|
|
1548
|
|
1549 wrccr( O5_save_flags ); // Restore CCR's
|
|
1550
|
|
1551 // mark upper end of faulting range
|
|
1552 _verify_oop_implicit_branch[1] = pc();
|
|
1553
|
|
1554 //-----------------------
|
|
1555 // all tests pass
|
|
1556 bind(succeed);
|
|
1557
|
|
1558 // Restore prior 64-bit registers
|
|
1559 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+0*8,O0);
|
|
1560 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+1*8,O1);
|
|
1561 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+2*8,O2);
|
|
1562 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+3*8,O3);
|
|
1563 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+4*8,O4);
|
|
1564 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+5*8,O5);
|
|
1565
|
|
1566 retl(); // Leaf return; restore prior O7 in delay slot
|
|
1567 delayed()->ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+7*8,O7);
|
|
1568
|
|
1569 //-----------------------
|
|
1570 bind(null_or_fail); // nulls are less common but OK
|
|
1571 br_null(O0_obj, false, pt, succeed);
|
|
1572 delayed()->wrccr( O5_save_flags ); // Restore CCR's
|
|
1573
|
|
1574 //-----------------------
|
|
1575 // report failure:
|
|
1576 bind(fail);
|
|
1577 _verify_oop_implicit_branch[2] = pc();
|
|
1578
|
|
1579 wrccr( O5_save_flags ); // Restore CCR's
|
|
1580
|
|
1581 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2));
|
|
1582
|
|
1583 // stop_subroutine expects message pointer in I1.
|
|
1584 mov(I1, O1);
|
|
1585
|
|
1586 // Restore prior 64-bit registers
|
|
1587 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+0*8,I0);
|
|
1588 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+1*8,I1);
|
|
1589 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+2*8,I2);
|
|
1590 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+3*8,I3);
|
|
1591 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+4*8,I4);
|
|
1592 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+5*8,I5);
|
|
1593
|
|
1594 // factor long stop-sequence into subroutine to save space
|
|
1595 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet");
|
|
1596
|
|
1597 // call indirectly to solve generation ordering problem
|
|
1598 AddressLiteral al(StubRoutines::Sparc::stop_subroutine_entry_address());
|
|
1599 load_ptr_contents(al, O5);
|
|
1600 jmpl(O5, 0, O7);
|
|
1601 delayed()->nop();
|
|
1602 }
|
|
1603
|
|
1604
|
|
1605 void MacroAssembler::stop(const char* msg) {
|
|
1606 // save frame first to get O7 for return address
|
|
1607 // add one word to size in case struct is odd number of words long
|
|
1608 // It must be doubleword-aligned for storing doubles into it.
|
|
1609
|
|
1610 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2));
|
|
1611
|
|
1612 // stop_subroutine expects message pointer in I1.
|
|
1613 // Size of set() should stay the same
|
|
1614 patchable_set((intptr_t)msg, O1);
|
|
1615
|
|
1616 // factor long stop-sequence into subroutine to save space
|
|
1617 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet");
|
|
1618
|
|
1619 // call indirectly to solve generation ordering problem
|
|
1620 AddressLiteral a(StubRoutines::Sparc::stop_subroutine_entry_address());
|
|
1621 load_ptr_contents(a, O5);
|
|
1622 jmpl(O5, 0, O7);
|
|
1623 delayed()->nop();
|
|
1624
|
|
1625 breakpoint_trap(); // make stop actually stop rather than writing
|
|
1626 // unnoticeable results in the output files.
|
|
1627
|
|
1628 // restore(); done in callee to save space!
|
|
1629 }
|
|
1630
|
|
1631
|
|
1632 void MacroAssembler::warn(const char* msg) {
|
|
1633 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2));
|
|
1634 RegistersForDebugging::save_registers(this);
|
|
1635 mov(O0, L0);
|
|
1636 // Size of set() should stay the same
|
|
1637 patchable_set((intptr_t)msg, O0);
|
|
1638 call( CAST_FROM_FN_PTR(address, warning) );
|
|
1639 delayed()->nop();
|
|
1640 // ret();
|
|
1641 // delayed()->restore();
|
|
1642 RegistersForDebugging::restore_registers(this, L0);
|
|
1643 restore();
|
|
1644 }
|
|
1645
|
|
1646
|
|
1647 void MacroAssembler::untested(const char* what) {
|
|
1648 // We must be able to turn interactive prompting off
|
|
1649 // in order to run automated test scripts on the VM
|
|
1650 // Use the flag ShowMessageBoxOnError
|
|
1651
|
|
1652 char* b = new char[1024];
|
|
1653 sprintf(b, "untested: %s", what);
|
|
1654
|
|
1655 if (ShowMessageBoxOnError) { STOP(b); }
|
|
1656 else { warn(b); }
|
|
1657 }
|
|
1658
|
|
1659
|
|
1660 void MacroAssembler::stop_subroutine() {
|
|
1661 RegistersForDebugging::save_registers(this);
|
|
1662
|
|
1663 // for the sake of the debugger, stick a PC on the current frame
|
|
1664 // (this assumes that the caller has performed an extra "save")
|
|
1665 mov(I7, L7);
|
|
1666 add(O7, -7 * BytesPerInt, I7);
|
|
1667
|
|
1668 save_frame(); // one more save to free up another O7 register
|
|
1669 mov(I0, O1); // addr of reg save area
|
|
1670
|
|
1671 // We expect pointer to message in I1. Caller must set it up in O1
|
|
1672 mov(I1, O0); // get msg
|
|
1673 call (CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type);
|
|
1674 delayed()->nop();
|
|
1675
|
|
1676 restore();
|
|
1677
|
|
1678 RegistersForDebugging::restore_registers(this, O0);
|
|
1679
|
|
1680 save_frame(0);
|
|
1681 call(CAST_FROM_FN_PTR(address,breakpoint));
|
|
1682 delayed()->nop();
|
|
1683 restore();
|
|
1684
|
|
1685 mov(L7, I7);
|
|
1686 retl();
|
|
1687 delayed()->restore(); // see stop above
|
|
1688 }
|
|
1689
|
|
1690
|
|
1691 void MacroAssembler::debug(char* msg, RegistersForDebugging* regs) {
|
|
1692 if ( ShowMessageBoxOnError ) {
|
|
1693 JavaThread* thread = JavaThread::current();
|
|
1694 JavaThreadState saved_state = thread->thread_state();
|
|
1695 thread->set_thread_state(_thread_in_vm);
|
|
1696 {
|
|
1697 // In order to get locks work, we need to fake a in_VM state
|
|
1698 ttyLocker ttyl;
|
|
1699 ::tty->print_cr("EXECUTION STOPPED: %s\n", msg);
|
|
1700 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
|
|
1701 BytecodeCounter::print();
|
|
1702 }
|
|
1703 if (os::message_box(msg, "Execution stopped, print registers?"))
|
|
1704 regs->print(::tty);
|
|
1705 }
|
|
1706 BREAKPOINT;
|
|
1707 ThreadStateTransition::transition(JavaThread::current(), _thread_in_vm, saved_state);
|
|
1708 }
|
|
1709 else {
|
|
1710 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
|
|
1711 }
|
|
1712 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
|
|
1713 }
|
|
1714
|
|
1715
|
|
1716 void MacroAssembler::calc_mem_param_words(Register Rparam_words, Register Rresult) {
|
|
1717 subcc( Rparam_words, Argument::n_register_parameters, Rresult); // how many mem words?
|
|
1718 Label no_extras;
|
|
1719 br( negative, true, pt, no_extras ); // if neg, clear reg
|
|
1720 delayed()->set(0, Rresult); // annuled, so only if taken
|
|
1721 bind( no_extras );
|
|
1722 }
|
|
1723
|
|
1724
|
|
1725 void MacroAssembler::calc_frame_size(Register Rextra_words, Register Rresult) {
|
|
1726 #ifdef _LP64
|
|
1727 add(Rextra_words, frame::memory_parameter_word_sp_offset, Rresult);
|
|
1728 #else
|
|
1729 add(Rextra_words, frame::memory_parameter_word_sp_offset + 1, Rresult);
|
|
1730 #endif
|
|
1731 bclr(1, Rresult);
|
|
1732 sll(Rresult, LogBytesPerWord, Rresult); // Rresult has total frame bytes
|
|
1733 }
|
|
1734
|
|
1735
|
|
1736 void MacroAssembler::calc_frame_size_and_save(Register Rextra_words, Register Rresult) {
|
|
1737 calc_frame_size(Rextra_words, Rresult);
|
|
1738 neg(Rresult);
|
|
1739 save(SP, Rresult, SP);
|
|
1740 }
|
|
1741
|
|
1742
|
|
1743 // ---------------------------------------------------------
|
|
1744 Assembler::RCondition cond2rcond(Assembler::Condition c) {
|
|
1745 switch (c) {
|
|
1746 /*case zero: */
|
|
1747 case Assembler::equal: return Assembler::rc_z;
|
|
1748 case Assembler::lessEqual: return Assembler::rc_lez;
|
|
1749 case Assembler::less: return Assembler::rc_lz;
|
|
1750 /*case notZero:*/
|
|
1751 case Assembler::notEqual: return Assembler::rc_nz;
|
|
1752 case Assembler::greater: return Assembler::rc_gz;
|
|
1753 case Assembler::greaterEqual: return Assembler::rc_gez;
|
|
1754 }
|
|
1755 ShouldNotReachHere();
|
|
1756 return Assembler::rc_z;
|
|
1757 }
|
|
1758
|
|
1759 // compares (32 bit) register with zero and branches. NOT FOR USE WITH 64-bit POINTERS
|
|
1760 void MacroAssembler::cmp_zero_and_br(Condition c, Register s1, Label& L, bool a, Predict p) {
|
|
1761 tst(s1);
|
|
1762 br (c, a, p, L);
|
|
1763 }
|
|
1764
|
|
1765 // Compares a pointer register with zero and branches on null.
|
|
1766 // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
|
|
1767 void MacroAssembler::br_null( Register s1, bool a, Predict p, Label& L ) {
|
|
1768 assert_not_delayed();
|
|
1769 #ifdef _LP64
|
|
1770 bpr( rc_z, a, p, s1, L );
|
|
1771 #else
|
|
1772 tst(s1);
|
|
1773 br ( zero, a, p, L );
|
|
1774 #endif
|
|
1775 }
|
|
1776
|
|
1777 void MacroAssembler::br_notnull( Register s1, bool a, Predict p, Label& L ) {
|
|
1778 assert_not_delayed();
|
|
1779 #ifdef _LP64
|
|
1780 bpr( rc_nz, a, p, s1, L );
|
|
1781 #else
|
|
1782 tst(s1);
|
|
1783 br ( notZero, a, p, L );
|
|
1784 #endif
|
|
1785 }
|
|
1786
|
|
1787 // Compare registers and branch with nop in delay slot or cbcond without delay slot.
|
|
1788
|
|
1789 // Compare integer (32 bit) values (icc only).
|
|
1790 void MacroAssembler::cmp_and_br_short(Register s1, Register s2, Condition c,
|
|
1791 Predict p, Label& L) {
|
|
1792 assert_not_delayed();
|
|
1793 if (use_cbcond(L)) {
|
|
1794 Assembler::cbcond(c, icc, s1, s2, L);
|
|
1795 } else {
|
|
1796 cmp(s1, s2);
|
|
1797 br(c, false, p, L);
|
|
1798 delayed()->nop();
|
|
1799 }
|
|
1800 }
|
|
1801
|
|
1802 // Compare integer (32 bit) values (icc only).
|
|
1803 void MacroAssembler::cmp_and_br_short(Register s1, int simm13a, Condition c,
|
|
1804 Predict p, Label& L) {
|
|
1805 assert_not_delayed();
|
|
1806 if (is_simm(simm13a,5) && use_cbcond(L)) {
|
|
1807 Assembler::cbcond(c, icc, s1, simm13a, L);
|
|
1808 } else {
|
|
1809 cmp(s1, simm13a);
|
|
1810 br(c, false, p, L);
|
|
1811 delayed()->nop();
|
|
1812 }
|
|
1813 }
|
|
1814
|
|
1815 // Branch that tests xcc in LP64 and icc in !LP64
|
|
1816 void MacroAssembler::cmp_and_brx_short(Register s1, Register s2, Condition c,
|
|
1817 Predict p, Label& L) {
|
|
1818 assert_not_delayed();
|
|
1819 if (use_cbcond(L)) {
|
|
1820 Assembler::cbcond(c, ptr_cc, s1, s2, L);
|
|
1821 } else {
|
|
1822 cmp(s1, s2);
|
|
1823 brx(c, false, p, L);
|
|
1824 delayed()->nop();
|
|
1825 }
|
|
1826 }
|
|
1827
|
|
1828 // Branch that tests xcc in LP64 and icc in !LP64
|
|
1829 void MacroAssembler::cmp_and_brx_short(Register s1, int simm13a, Condition c,
|
|
1830 Predict p, Label& L) {
|
|
1831 assert_not_delayed();
|
|
1832 if (is_simm(simm13a,5) && use_cbcond(L)) {
|
|
1833 Assembler::cbcond(c, ptr_cc, s1, simm13a, L);
|
|
1834 } else {
|
|
1835 cmp(s1, simm13a);
|
|
1836 brx(c, false, p, L);
|
|
1837 delayed()->nop();
|
|
1838 }
|
|
1839 }
|
|
1840
|
|
1841 // Short branch version for compares a pointer with zero.
|
|
1842
|
|
1843 void MacroAssembler::br_null_short(Register s1, Predict p, Label& L) {
|
|
1844 assert_not_delayed();
|
|
1845 if (use_cbcond(L)) {
|
|
1846 Assembler::cbcond(zero, ptr_cc, s1, 0, L);
|
|
1847 return;
|
|
1848 }
|
|
1849 br_null(s1, false, p, L);
|
|
1850 delayed()->nop();
|
|
1851 }
|
|
1852
|
|
1853 void MacroAssembler::br_notnull_short(Register s1, Predict p, Label& L) {
|
|
1854 assert_not_delayed();
|
|
1855 if (use_cbcond(L)) {
|
|
1856 Assembler::cbcond(notZero, ptr_cc, s1, 0, L);
|
|
1857 return;
|
|
1858 }
|
|
1859 br_notnull(s1, false, p, L);
|
|
1860 delayed()->nop();
|
|
1861 }
|
|
1862
|
|
1863 // Unconditional short branch
|
|
1864 void MacroAssembler::ba_short(Label& L) {
|
|
1865 if (use_cbcond(L)) {
|
|
1866 Assembler::cbcond(equal, icc, G0, G0, L);
|
|
1867 return;
|
|
1868 }
|
|
1869 br(always, false, pt, L);
|
|
1870 delayed()->nop();
|
|
1871 }
|
|
1872
|
|
1873 // instruction sequences factored across compiler & interpreter
|
|
1874
|
|
1875
|
|
1876 void MacroAssembler::lcmp( Register Ra_hi, Register Ra_low,
|
|
1877 Register Rb_hi, Register Rb_low,
|
|
1878 Register Rresult) {
|
|
1879
|
|
1880 Label check_low_parts, done;
|
|
1881
|
|
1882 cmp(Ra_hi, Rb_hi ); // compare hi parts
|
|
1883 br(equal, true, pt, check_low_parts);
|
|
1884 delayed()->cmp(Ra_low, Rb_low); // test low parts
|
|
1885
|
|
1886 // And, with an unsigned comparison, it does not matter if the numbers
|
|
1887 // are negative or not.
|
|
1888 // E.g., -2 cmp -1: the low parts are 0xfffffffe and 0xffffffff.
|
|
1889 // The second one is bigger (unsignedly).
|
|
1890
|
|
1891 // Other notes: The first move in each triplet can be unconditional
|
|
1892 // (and therefore probably prefetchable).
|
|
1893 // And the equals case for the high part does not need testing,
|
|
1894 // since that triplet is reached only after finding the high halves differ.
|
|
1895
|
|
1896 if (VM_Version::v9_instructions_work()) {
|
|
1897 mov(-1, Rresult);
|
|
1898 ba(done); delayed()-> movcc(greater, false, icc, 1, Rresult);
|
|
1899 } else {
|
|
1900 br(less, true, pt, done); delayed()-> set(-1, Rresult);
|
|
1901 br(greater, true, pt, done); delayed()-> set( 1, Rresult);
|
|
1902 }
|
|
1903
|
|
1904 bind( check_low_parts );
|
|
1905
|
|
1906 if (VM_Version::v9_instructions_work()) {
|
|
1907 mov( -1, Rresult);
|
|
1908 movcc(equal, false, icc, 0, Rresult);
|
|
1909 movcc(greaterUnsigned, false, icc, 1, Rresult);
|
|
1910 } else {
|
|
1911 set(-1, Rresult);
|
|
1912 br(equal, true, pt, done); delayed()->set( 0, Rresult);
|
|
1913 br(greaterUnsigned, true, pt, done); delayed()->set( 1, Rresult);
|
|
1914 }
|
|
1915 bind( done );
|
|
1916 }
|
|
1917
|
|
1918 void MacroAssembler::lneg( Register Rhi, Register Rlow ) {
|
|
1919 subcc( G0, Rlow, Rlow );
|
|
1920 subc( G0, Rhi, Rhi );
|
|
1921 }
|
|
1922
|
|
1923 void MacroAssembler::lshl( Register Rin_high, Register Rin_low,
|
|
1924 Register Rcount,
|
|
1925 Register Rout_high, Register Rout_low,
|
|
1926 Register Rtemp ) {
|
|
1927
|
|
1928
|
|
1929 Register Ralt_count = Rtemp;
|
|
1930 Register Rxfer_bits = Rtemp;
|
|
1931
|
|
1932 assert( Ralt_count != Rin_high
|
|
1933 && Ralt_count != Rin_low
|
|
1934 && Ralt_count != Rcount
|
|
1935 && Rxfer_bits != Rin_low
|
|
1936 && Rxfer_bits != Rin_high
|
|
1937 && Rxfer_bits != Rcount
|
|
1938 && Rxfer_bits != Rout_low
|
|
1939 && Rout_low != Rin_high,
|
|
1940 "register alias checks");
|
|
1941
|
|
1942 Label big_shift, done;
|
|
1943
|
|
1944 // This code can be optimized to use the 64 bit shifts in V9.
|
|
1945 // Here we use the 32 bit shifts.
|
|
1946
|
|
1947 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits
|
|
1948 subcc(Rcount, 31, Ralt_count);
|
|
1949 br(greater, true, pn, big_shift);
|
|
1950 delayed()->dec(Ralt_count);
|
|
1951
|
|
1952 // shift < 32 bits, Ralt_count = Rcount-31
|
|
1953
|
|
1954 // We get the transfer bits by shifting right by 32-count the low
|
|
1955 // register. This is done by shifting right by 31-count and then by one
|
|
1956 // more to take care of the special (rare) case where count is zero
|
|
1957 // (shifting by 32 would not work).
|
|
1958
|
|
1959 neg(Ralt_count);
|
|
1960
|
|
1961 // The order of the next two instructions is critical in the case where
|
|
1962 // Rin and Rout are the same and should not be reversed.
|
|
1963
|
|
1964 srl(Rin_low, Ralt_count, Rxfer_bits); // shift right by 31-count
|
|
1965 if (Rcount != Rout_low) {
|
|
1966 sll(Rin_low, Rcount, Rout_low); // low half
|
|
1967 }
|
|
1968 sll(Rin_high, Rcount, Rout_high);
|
|
1969 if (Rcount == Rout_low) {
|
|
1970 sll(Rin_low, Rcount, Rout_low); // low half
|
|
1971 }
|
|
1972 srl(Rxfer_bits, 1, Rxfer_bits ); // shift right by one more
|
|
1973 ba(done);
|
|
1974 delayed()->or3(Rout_high, Rxfer_bits, Rout_high); // new hi value: or in shifted old hi part and xfer from low
|
|
1975
|
|
1976 // shift >= 32 bits, Ralt_count = Rcount-32
|
|
1977 bind(big_shift);
|
|
1978 sll(Rin_low, Ralt_count, Rout_high );
|
|
1979 clr(Rout_low);
|
|
1980
|
|
1981 bind(done);
|
|
1982 }
|
|
1983
|
|
1984
|
|
1985 void MacroAssembler::lshr( Register Rin_high, Register Rin_low,
|
|
1986 Register Rcount,
|
|
1987 Register Rout_high, Register Rout_low,
|
|
1988 Register Rtemp ) {
|
|
1989
|
|
1990 Register Ralt_count = Rtemp;
|
|
1991 Register Rxfer_bits = Rtemp;
|
|
1992
|
|
1993 assert( Ralt_count != Rin_high
|
|
1994 && Ralt_count != Rin_low
|
|
1995 && Ralt_count != Rcount
|
|
1996 && Rxfer_bits != Rin_low
|
|
1997 && Rxfer_bits != Rin_high
|
|
1998 && Rxfer_bits != Rcount
|
|
1999 && Rxfer_bits != Rout_high
|
|
2000 && Rout_high != Rin_low,
|
|
2001 "register alias checks");
|
|
2002
|
|
2003 Label big_shift, done;
|
|
2004
|
|
2005 // This code can be optimized to use the 64 bit shifts in V9.
|
|
2006 // Here we use the 32 bit shifts.
|
|
2007
|
|
2008 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits
|
|
2009 subcc(Rcount, 31, Ralt_count);
|
|
2010 br(greater, true, pn, big_shift);
|
|
2011 delayed()->dec(Ralt_count);
|
|
2012
|
|
2013 // shift < 32 bits, Ralt_count = Rcount-31
|
|
2014
|
|
2015 // We get the transfer bits by shifting left by 32-count the high
|
|
2016 // register. This is done by shifting left by 31-count and then by one
|
|
2017 // more to take care of the special (rare) case where count is zero
|
|
2018 // (shifting by 32 would not work).
|
|
2019
|
|
2020 neg(Ralt_count);
|
|
2021 if (Rcount != Rout_low) {
|
|
2022 srl(Rin_low, Rcount, Rout_low);
|
|
2023 }
|
|
2024
|
|
2025 // The order of the next two instructions is critical in the case where
|
|
2026 // Rin and Rout are the same and should not be reversed.
|
|
2027
|
|
2028 sll(Rin_high, Ralt_count, Rxfer_bits); // shift left by 31-count
|
|
2029 sra(Rin_high, Rcount, Rout_high ); // high half
|
|
2030 sll(Rxfer_bits, 1, Rxfer_bits); // shift left by one more
|
|
2031 if (Rcount == Rout_low) {
|
|
2032 srl(Rin_low, Rcount, Rout_low);
|
|
2033 }
|
|
2034 ba(done);
|
|
2035 delayed()->or3(Rout_low, Rxfer_bits, Rout_low); // new low value: or shifted old low part and xfer from high
|
|
2036
|
|
2037 // shift >= 32 bits, Ralt_count = Rcount-32
|
|
2038 bind(big_shift);
|
|
2039
|
|
2040 sra(Rin_high, Ralt_count, Rout_low);
|
|
2041 sra(Rin_high, 31, Rout_high); // sign into hi
|
|
2042
|
|
2043 bind( done );
|
|
2044 }
|
|
2045
|
|
2046
|
|
2047
|
|
2048 void MacroAssembler::lushr( Register Rin_high, Register Rin_low,
|
|
2049 Register Rcount,
|
|
2050 Register Rout_high, Register Rout_low,
|
|
2051 Register Rtemp ) {
|
|
2052
|
|
2053 Register Ralt_count = Rtemp;
|
|
2054 Register Rxfer_bits = Rtemp;
|
|
2055
|
|
2056 assert( Ralt_count != Rin_high
|
|
2057 && Ralt_count != Rin_low
|
|
2058 && Ralt_count != Rcount
|
|
2059 && Rxfer_bits != Rin_low
|
|
2060 && Rxfer_bits != Rin_high
|
|
2061 && Rxfer_bits != Rcount
|
|
2062 && Rxfer_bits != Rout_high
|
|
2063 && Rout_high != Rin_low,
|
|
2064 "register alias checks");
|
|
2065
|
|
2066 Label big_shift, done;
|
|
2067
|
|
2068 // This code can be optimized to use the 64 bit shifts in V9.
|
|
2069 // Here we use the 32 bit shifts.
|
|
2070
|
|
2071 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits
|
|
2072 subcc(Rcount, 31, Ralt_count);
|
|
2073 br(greater, true, pn, big_shift);
|
|
2074 delayed()->dec(Ralt_count);
|
|
2075
|
|
2076 // shift < 32 bits, Ralt_count = Rcount-31
|
|
2077
|
|
2078 // We get the transfer bits by shifting left by 32-count the high
|
|
2079 // register. This is done by shifting left by 31-count and then by one
|
|
2080 // more to take care of the special (rare) case where count is zero
|
|
2081 // (shifting by 32 would not work).
|
|
2082
|
|
2083 neg(Ralt_count);
|
|
2084 if (Rcount != Rout_low) {
|
|
2085 srl(Rin_low, Rcount, Rout_low);
|
|
2086 }
|
|
2087
|
|
2088 // The order of the next two instructions is critical in the case where
|
|
2089 // Rin and Rout are the same and should not be reversed.
|
|
2090
|
|
2091 sll(Rin_high, Ralt_count, Rxfer_bits); // shift left by 31-count
|
|
2092 srl(Rin_high, Rcount, Rout_high ); // high half
|
|
2093 sll(Rxfer_bits, 1, Rxfer_bits); // shift left by one more
|
|
2094 if (Rcount == Rout_low) {
|
|
2095 srl(Rin_low, Rcount, Rout_low);
|
|
2096 }
|
|
2097 ba(done);
|
|
2098 delayed()->or3(Rout_low, Rxfer_bits, Rout_low); // new low value: or shifted old low part and xfer from high
|
|
2099
|
|
2100 // shift >= 32 bits, Ralt_count = Rcount-32
|
|
2101 bind(big_shift);
|
|
2102
|
|
2103 srl(Rin_high, Ralt_count, Rout_low);
|
|
2104 clr(Rout_high);
|
|
2105
|
|
2106 bind( done );
|
|
2107 }
|
|
2108
|
|
2109 #ifdef _LP64
|
|
2110 void MacroAssembler::lcmp( Register Ra, Register Rb, Register Rresult) {
|
|
2111 cmp(Ra, Rb);
|
|
2112 mov(-1, Rresult);
|
|
2113 movcc(equal, false, xcc, 0, Rresult);
|
|
2114 movcc(greater, false, xcc, 1, Rresult);
|
|
2115 }
|
|
2116 #endif
|
|
2117
|
|
2118
|
|
2119 void MacroAssembler::load_sized_value(Address src, Register dst, size_t size_in_bytes, bool is_signed) {
|
|
2120 switch (size_in_bytes) {
|
|
2121 case 8: ld_long(src, dst); break;
|
|
2122 case 4: ld( src, dst); break;
|
|
2123 case 2: is_signed ? ldsh(src, dst) : lduh(src, dst); break;
|
|
2124 case 1: is_signed ? ldsb(src, dst) : ldub(src, dst); break;
|
|
2125 default: ShouldNotReachHere();
|
|
2126 }
|
|
2127 }
|
|
2128
|
|
2129 void MacroAssembler::store_sized_value(Register src, Address dst, size_t size_in_bytes) {
|
|
2130 switch (size_in_bytes) {
|
|
2131 case 8: st_long(src, dst); break;
|
|
2132 case 4: st( src, dst); break;
|
|
2133 case 2: sth( src, dst); break;
|
|
2134 case 1: stb( src, dst); break;
|
|
2135 default: ShouldNotReachHere();
|
|
2136 }
|
|
2137 }
|
|
2138
|
|
2139
|
|
2140 void MacroAssembler::float_cmp( bool is_float, int unordered_result,
|
|
2141 FloatRegister Fa, FloatRegister Fb,
|
|
2142 Register Rresult) {
|
|
2143
|
|
2144 fcmp(is_float ? FloatRegisterImpl::S : FloatRegisterImpl::D, fcc0, Fa, Fb);
|
|
2145
|
|
2146 Condition lt = unordered_result == -1 ? f_unorderedOrLess : f_less;
|
|
2147 Condition eq = f_equal;
|
|
2148 Condition gt = unordered_result == 1 ? f_unorderedOrGreater : f_greater;
|
|
2149
|
|
2150 if (VM_Version::v9_instructions_work()) {
|
|
2151
|
|
2152 mov(-1, Rresult);
|
|
2153 movcc(eq, true, fcc0, 0, Rresult);
|
|
2154 movcc(gt, true, fcc0, 1, Rresult);
|
|
2155
|
|
2156 } else {
|
|
2157 Label done;
|
|
2158
|
|
2159 set( -1, Rresult );
|
|
2160 //fb(lt, true, pn, done); delayed()->set( -1, Rresult );
|
|
2161 fb( eq, true, pn, done); delayed()->set( 0, Rresult );
|
|
2162 fb( gt, true, pn, done); delayed()->set( 1, Rresult );
|
|
2163
|
|
2164 bind (done);
|
|
2165 }
|
|
2166 }
|
|
2167
|
|
2168
|
|
2169 void MacroAssembler::fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d)
|
|
2170 {
|
|
2171 if (VM_Version::v9_instructions_work()) {
|
|
2172 Assembler::fneg(w, s, d);
|
|
2173 } else {
|
|
2174 if (w == FloatRegisterImpl::S) {
|
|
2175 Assembler::fneg(w, s, d);
|
|
2176 } else if (w == FloatRegisterImpl::D) {
|
|
2177 // number() does a sanity check on the alignment.
|
|
2178 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) &&
|
|
2179 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check");
|
|
2180
|
|
2181 Assembler::fneg(FloatRegisterImpl::S, s, d);
|
|
2182 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
|
|
2183 } else {
|
|
2184 assert(w == FloatRegisterImpl::Q, "Invalid float register width");
|
|
2185
|
|
2186 // number() does a sanity check on the alignment.
|
|
2187 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) &&
|
|
2188 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check");
|
|
2189
|
|
2190 Assembler::fneg(FloatRegisterImpl::S, s, d);
|
|
2191 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
|
|
2192 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor());
|
|
2193 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor());
|
|
2194 }
|
|
2195 }
|
|
2196 }
|
|
2197
|
|
2198 void MacroAssembler::fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d)
|
|
2199 {
|
|
2200 if (VM_Version::v9_instructions_work()) {
|
|
2201 Assembler::fmov(w, s, d);
|
|
2202 } else {
|
|
2203 if (w == FloatRegisterImpl::S) {
|
|
2204 Assembler::fmov(w, s, d);
|
|
2205 } else if (w == FloatRegisterImpl::D) {
|
|
2206 // number() does a sanity check on the alignment.
|
|
2207 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) &&
|
|
2208 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check");
|
|
2209
|
|
2210 Assembler::fmov(FloatRegisterImpl::S, s, d);
|
|
2211 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
|
|
2212 } else {
|
|
2213 assert(w == FloatRegisterImpl::Q, "Invalid float register width");
|
|
2214
|
|
2215 // number() does a sanity check on the alignment.
|
|
2216 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) &&
|
|
2217 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check");
|
|
2218
|
|
2219 Assembler::fmov(FloatRegisterImpl::S, s, d);
|
|
2220 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
|
|
2221 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor());
|
|
2222 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor());
|
|
2223 }
|
|
2224 }
|
|
2225 }
|
|
2226
|
|
2227 void MacroAssembler::fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d)
|
|
2228 {
|
|
2229 if (VM_Version::v9_instructions_work()) {
|
|
2230 Assembler::fabs(w, s, d);
|
|
2231 } else {
|
|
2232 if (w == FloatRegisterImpl::S) {
|
|
2233 Assembler::fabs(w, s, d);
|
|
2234 } else if (w == FloatRegisterImpl::D) {
|
|
2235 // number() does a sanity check on the alignment.
|
|
2236 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) &&
|
|
2237 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check");
|
|
2238
|
|
2239 Assembler::fabs(FloatRegisterImpl::S, s, d);
|
|
2240 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
|
|
2241 } else {
|
|
2242 assert(w == FloatRegisterImpl::Q, "Invalid float register width");
|
|
2243
|
|
2244 // number() does a sanity check on the alignment.
|
|
2245 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) &&
|
|
2246 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check");
|
|
2247
|
|
2248 Assembler::fabs(FloatRegisterImpl::S, s, d);
|
|
2249 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
|
|
2250 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor());
|
|
2251 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor());
|
|
2252 }
|
|
2253 }
|
|
2254 }
|
|
2255
|
|
2256 void MacroAssembler::save_all_globals_into_locals() {
|
|
2257 mov(G1,L1);
|
|
2258 mov(G2,L2);
|
|
2259 mov(G3,L3);
|
|
2260 mov(G4,L4);
|
|
2261 mov(G5,L5);
|
|
2262 mov(G6,L6);
|
|
2263 mov(G7,L7);
|
|
2264 }
|
|
2265
|
|
2266 void MacroAssembler::restore_globals_from_locals() {
|
|
2267 mov(L1,G1);
|
|
2268 mov(L2,G2);
|
|
2269 mov(L3,G3);
|
|
2270 mov(L4,G4);
|
|
2271 mov(L5,G5);
|
|
2272 mov(L6,G6);
|
|
2273 mov(L7,G7);
|
|
2274 }
|
|
2275
|
|
2276 // Use for 64 bit operation.
|
|
2277 void MacroAssembler::casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm)
|
|
2278 {
|
|
2279 // store ptr_reg as the new top value
|
|
2280 #ifdef _LP64
|
|
2281 casx(top_ptr_reg, top_reg, ptr_reg);
|
|
2282 #else
|
|
2283 cas_under_lock(top_ptr_reg, top_reg, ptr_reg, lock_addr, use_call_vm);
|
|
2284 #endif // _LP64
|
|
2285 }
|
|
2286
|
|
2287 // [RGV] This routine does not handle 64 bit operations.
|
|
2288 // use casx_under_lock() or casx directly!!!
|
|
2289 void MacroAssembler::cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm)
|
|
2290 {
|
|
2291 // store ptr_reg as the new top value
|
|
2292 if (VM_Version::v9_instructions_work()) {
|
|
2293 cas(top_ptr_reg, top_reg, ptr_reg);
|
|
2294 } else {
|
|
2295
|
|
2296 // If the register is not an out nor global, it is not visible
|
|
2297 // after the save. Allocate a register for it, save its
|
|
2298 // value in the register save area (the save may not flush
|
|
2299 // registers to the save area).
|
|
2300
|
|
2301 Register top_ptr_reg_after_save;
|
|
2302 Register top_reg_after_save;
|
|
2303 Register ptr_reg_after_save;
|
|
2304
|
|
2305 if (top_ptr_reg->is_out() || top_ptr_reg->is_global()) {
|
|
2306 top_ptr_reg_after_save = top_ptr_reg->after_save();
|
|
2307 } else {
|
|
2308 Address reg_save_addr = top_ptr_reg->address_in_saved_window();
|
|
2309 top_ptr_reg_after_save = L0;
|
|
2310 st(top_ptr_reg, reg_save_addr);
|
|
2311 }
|
|
2312
|
|
2313 if (top_reg->is_out() || top_reg->is_global()) {
|
|
2314 top_reg_after_save = top_reg->after_save();
|
|
2315 } else {
|
|
2316 Address reg_save_addr = top_reg->address_in_saved_window();
|
|
2317 top_reg_after_save = L1;
|
|
2318 st(top_reg, reg_save_addr);
|
|
2319 }
|
|
2320
|
|
2321 if (ptr_reg->is_out() || ptr_reg->is_global()) {
|
|
2322 ptr_reg_after_save = ptr_reg->after_save();
|
|
2323 } else {
|
|
2324 Address reg_save_addr = ptr_reg->address_in_saved_window();
|
|
2325 ptr_reg_after_save = L2;
|
|
2326 st(ptr_reg, reg_save_addr);
|
|
2327 }
|
|
2328
|
|
2329 const Register& lock_reg = L3;
|
|
2330 const Register& lock_ptr_reg = L4;
|
|
2331 const Register& value_reg = L5;
|
|
2332 const Register& yield_reg = L6;
|
|
2333 const Register& yieldall_reg = L7;
|
|
2334
|
|
2335 save_frame();
|
|
2336
|
|
2337 if (top_ptr_reg_after_save == L0) {
|
|
2338 ld(top_ptr_reg->address_in_saved_window().after_save(), top_ptr_reg_after_save);
|
|
2339 }
|
|
2340
|
|
2341 if (top_reg_after_save == L1) {
|
|
2342 ld(top_reg->address_in_saved_window().after_save(), top_reg_after_save);
|
|
2343 }
|
|
2344
|
|
2345 if (ptr_reg_after_save == L2) {
|
|
2346 ld(ptr_reg->address_in_saved_window().after_save(), ptr_reg_after_save);
|
|
2347 }
|
|
2348
|
|
2349 Label(retry_get_lock);
|
|
2350 Label(not_same);
|
|
2351 Label(dont_yield);
|
|
2352
|
|
2353 assert(lock_addr, "lock_address should be non null for v8");
|
|
2354 set((intptr_t)lock_addr, lock_ptr_reg);
|
|
2355 // Initialize yield counter
|
|
2356 mov(G0,yield_reg);
|
|
2357 mov(G0, yieldall_reg);
|
|
2358 set(StubRoutines::Sparc::locked, lock_reg);
|
|
2359
|
|
2360 bind(retry_get_lock);
|
|
2361 cmp_and_br_short(yield_reg, V8AtomicOperationUnderLockSpinCount, Assembler::less, Assembler::pt, dont_yield);
|
|
2362
|
|
2363 if(use_call_vm) {
|
|
2364 Untested("Need to verify global reg consistancy");
|
|
2365 call_VM(noreg, CAST_FROM_FN_PTR(address, SharedRuntime::yield_all), yieldall_reg);
|
|
2366 } else {
|
|
2367 // Save the regs and make space for a C call
|
|
2368 save(SP, -96, SP);
|
|
2369 save_all_globals_into_locals();
|
|
2370 call(CAST_FROM_FN_PTR(address,os::yield_all));
|
|
2371 delayed()->mov(yieldall_reg, O0);
|
|
2372 restore_globals_from_locals();
|
|
2373 restore();
|
|
2374 }
|
|
2375
|
|
2376 // reset the counter
|
|
2377 mov(G0,yield_reg);
|
|
2378 add(yieldall_reg, 1, yieldall_reg);
|
|
2379
|
|
2380 bind(dont_yield);
|
|
2381 // try to get lock
|
|
2382 Assembler::swap(lock_ptr_reg, 0, lock_reg);
|
|
2383
|
|
2384 // did we get the lock?
|
|
2385 cmp(lock_reg, StubRoutines::Sparc::unlocked);
|
|
2386 br(Assembler::notEqual, true, Assembler::pn, retry_get_lock);
|
|
2387 delayed()->add(yield_reg,1,yield_reg);
|
|
2388
|
|
2389 // yes, got lock. do we have the same top?
|
|
2390 ld(top_ptr_reg_after_save, 0, value_reg);
|
|
2391 cmp_and_br_short(value_reg, top_reg_after_save, Assembler::notEqual, Assembler::pn, not_same);
|
|
2392
|
|
2393 // yes, same top.
|
|
2394 st(ptr_reg_after_save, top_ptr_reg_after_save, 0);
|
|
2395 membar(Assembler::StoreStore);
|
|
2396
|
|
2397 bind(not_same);
|
|
2398 mov(value_reg, ptr_reg_after_save);
|
|
2399 st(lock_reg, lock_ptr_reg, 0); // unlock
|
|
2400
|
|
2401 restore();
|
|
2402 }
|
|
2403 }
|
|
2404
|
|
2405 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
|
|
2406 Register tmp,
|
|
2407 int offset) {
|
|
2408 intptr_t value = *delayed_value_addr;
|
|
2409 if (value != 0)
|
|
2410 return RegisterOrConstant(value + offset);
|
|
2411
|
|
2412 // load indirectly to solve generation ordering problem
|
|
2413 AddressLiteral a(delayed_value_addr);
|
|
2414 load_ptr_contents(a, tmp);
|
|
2415
|
|
2416 #ifdef ASSERT
|
|
2417 tst(tmp);
|
|
2418 breakpoint_trap(zero, xcc);
|
|
2419 #endif
|
|
2420
|
|
2421 if (offset != 0)
|
|
2422 add(tmp, offset, tmp);
|
|
2423
|
|
2424 return RegisterOrConstant(tmp);
|
|
2425 }
|
|
2426
|
|
2427
|
|
2428 RegisterOrConstant MacroAssembler::regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) {
|
|
2429 assert(d.register_or_noreg() != G0, "lost side effect");
|
|
2430 if ((s2.is_constant() && s2.as_constant() == 0) ||
|
|
2431 (s2.is_register() && s2.as_register() == G0)) {
|
|
2432 // Do nothing, just move value.
|
|
2433 if (s1.is_register()) {
|
|
2434 if (d.is_constant()) d = temp;
|
|
2435 mov(s1.as_register(), d.as_register());
|
|
2436 return d;
|
|
2437 } else {
|
|
2438 return s1;
|
|
2439 }
|
|
2440 }
|
|
2441
|
|
2442 if (s1.is_register()) {
|
|
2443 assert_different_registers(s1.as_register(), temp);
|
|
2444 if (d.is_constant()) d = temp;
|
|
2445 andn(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register());
|
|
2446 return d;
|
|
2447 } else {
|
|
2448 if (s2.is_register()) {
|
|
2449 assert_different_registers(s2.as_register(), temp);
|
|
2450 if (d.is_constant()) d = temp;
|
|
2451 set(s1.as_constant(), temp);
|
|
2452 andn(temp, s2.as_register(), d.as_register());
|
|
2453 return d;
|
|
2454 } else {
|
|
2455 intptr_t res = s1.as_constant() & ~s2.as_constant();
|
|
2456 return res;
|
|
2457 }
|
|
2458 }
|
|
2459 }
|
|
2460
|
|
2461 RegisterOrConstant MacroAssembler::regcon_inc_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) {
|
|
2462 assert(d.register_or_noreg() != G0, "lost side effect");
|
|
2463 if ((s2.is_constant() && s2.as_constant() == 0) ||
|
|
2464 (s2.is_register() && s2.as_register() == G0)) {
|
|
2465 // Do nothing, just move value.
|
|
2466 if (s1.is_register()) {
|
|
2467 if (d.is_constant()) d = temp;
|
|
2468 mov(s1.as_register(), d.as_register());
|
|
2469 return d;
|
|
2470 } else {
|
|
2471 return s1;
|
|
2472 }
|
|
2473 }
|
|
2474
|
|
2475 if (s1.is_register()) {
|
|
2476 assert_different_registers(s1.as_register(), temp);
|
|
2477 if (d.is_constant()) d = temp;
|
|
2478 add(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register());
|
|
2479 return d;
|
|
2480 } else {
|
|
2481 if (s2.is_register()) {
|
|
2482 assert_different_registers(s2.as_register(), temp);
|
|
2483 if (d.is_constant()) d = temp;
|
|
2484 add(s2.as_register(), ensure_simm13_or_reg(s1, temp), d.as_register());
|
|
2485 return d;
|
|
2486 } else {
|
|
2487 intptr_t res = s1.as_constant() + s2.as_constant();
|
|
2488 return res;
|
|
2489 }
|
|
2490 }
|
|
2491 }
|
|
2492
|
|
2493 RegisterOrConstant MacroAssembler::regcon_sll_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) {
|
|
2494 assert(d.register_or_noreg() != G0, "lost side effect");
|
|
2495 if (!is_simm13(s2.constant_or_zero()))
|
|
2496 s2 = (s2.as_constant() & 0xFF);
|
|
2497 if ((s2.is_constant() && s2.as_constant() == 0) ||
|
|
2498 (s2.is_register() && s2.as_register() == G0)) {
|
|
2499 // Do nothing, just move value.
|
|
2500 if (s1.is_register()) {
|
|
2501 if (d.is_constant()) d = temp;
|
|
2502 mov(s1.as_register(), d.as_register());
|
|
2503 return d;
|
|
2504 } else {
|
|
2505 return s1;
|
|
2506 }
|
|
2507 }
|
|
2508
|
|
2509 if (s1.is_register()) {
|
|
2510 assert_different_registers(s1.as_register(), temp);
|
|
2511 if (d.is_constant()) d = temp;
|
|
2512 sll_ptr(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register());
|
|
2513 return d;
|
|
2514 } else {
|
|
2515 if (s2.is_register()) {
|
|
2516 assert_different_registers(s2.as_register(), temp);
|
|
2517 if (d.is_constant()) d = temp;
|
|
2518 set(s1.as_constant(), temp);
|
|
2519 sll_ptr(temp, s2.as_register(), d.as_register());
|
|
2520 return d;
|
|
2521 } else {
|
|
2522 intptr_t res = s1.as_constant() << s2.as_constant();
|
|
2523 return res;
|
|
2524 }
|
|
2525 }
|
|
2526 }
|
|
2527
|
|
2528
|
|
2529 // Look up the method for a megamorphic invokeinterface call.
|
|
2530 // The target method is determined by <intf_klass, itable_index>.
|
|
2531 // The receiver klass is in recv_klass.
|
|
2532 // On success, the result will be in method_result, and execution falls through.
|
|
2533 // On failure, execution transfers to the given label.
|
|
2534 void MacroAssembler::lookup_interface_method(Register recv_klass,
|
|
2535 Register intf_klass,
|
|
2536 RegisterOrConstant itable_index,
|
|
2537 Register method_result,
|
|
2538 Register scan_temp,
|
|
2539 Register sethi_temp,
|
|
2540 Label& L_no_such_interface) {
|
|
2541 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
|
|
2542 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
|
|
2543 "caller must use same register for non-constant itable index as for method");
|
|
2544
|
|
2545 Label L_no_such_interface_restore;
|
|
2546 bool did_save = false;
|
|
2547 if (scan_temp == noreg || sethi_temp == noreg) {
|
|
2548 Register recv_2 = recv_klass->is_global() ? recv_klass : L0;
|
|
2549 Register intf_2 = intf_klass->is_global() ? intf_klass : L1;
|
|
2550 assert(method_result->is_global(), "must be able to return value");
|
|
2551 scan_temp = L2;
|
|
2552 sethi_temp = L3;
|
|
2553 save_frame_and_mov(0, recv_klass, recv_2, intf_klass, intf_2);
|
|
2554 recv_klass = recv_2;
|
|
2555 intf_klass = intf_2;
|
|
2556 did_save = true;
|
|
2557 }
|
|
2558
|
|
2559 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
|
|
2560 int vtable_base = InstanceKlass::vtable_start_offset() * wordSize;
|
|
2561 int scan_step = itableOffsetEntry::size() * wordSize;
|
|
2562 int vte_size = vtableEntry::size() * wordSize;
|
|
2563
|
|
2564 lduw(recv_klass, InstanceKlass::vtable_length_offset() * wordSize, scan_temp);
|
|
2565 // %%% We should store the aligned, prescaled offset in the klassoop.
|
|
2566 // Then the next several instructions would fold away.
|
|
2567
|
|
2568 int round_to_unit = ((HeapWordsPerLong > 1) ? BytesPerLong : 0);
|
|
2569 int itb_offset = vtable_base;
|
|
2570 if (round_to_unit != 0) {
|
|
2571 // hoist first instruction of round_to(scan_temp, BytesPerLong):
|
|
2572 itb_offset += round_to_unit - wordSize;
|
|
2573 }
|
|
2574 int itb_scale = exact_log2(vtableEntry::size() * wordSize);
|
|
2575 sll(scan_temp, itb_scale, scan_temp);
|
|
2576 add(scan_temp, itb_offset, scan_temp);
|
|
2577 if (round_to_unit != 0) {
|
|
2578 // Round up to align_object_offset boundary
|
|
2579 // see code for InstanceKlass::start_of_itable!
|
|
2580 // Was: round_to(scan_temp, BytesPerLong);
|
|
2581 // Hoisted: add(scan_temp, BytesPerLong-1, scan_temp);
|
|
2582 and3(scan_temp, -round_to_unit, scan_temp);
|
|
2583 }
|
|
2584 add(recv_klass, scan_temp, scan_temp);
|
|
2585
|
|
2586 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
|
|
2587 RegisterOrConstant itable_offset = itable_index;
|
|
2588 itable_offset = regcon_sll_ptr(itable_index, exact_log2(itableMethodEntry::size() * wordSize), itable_offset);
|
|
2589 itable_offset = regcon_inc_ptr(itable_offset, itableMethodEntry::method_offset_in_bytes(), itable_offset);
|
|
2590 add(recv_klass, ensure_simm13_or_reg(itable_offset, sethi_temp), recv_klass);
|
|
2591
|
|
2592 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
|
|
2593 // if (scan->interface() == intf) {
|
|
2594 // result = (klass + scan->offset() + itable_index);
|
|
2595 // }
|
|
2596 // }
|
|
2597 Label L_search, L_found_method;
|
|
2598
|
|
2599 for (int peel = 1; peel >= 0; peel--) {
|
|
2600 // %%%% Could load both offset and interface in one ldx, if they were
|
|
2601 // in the opposite order. This would save a load.
|
|
2602 ld_ptr(scan_temp, itableOffsetEntry::interface_offset_in_bytes(), method_result);
|
|
2603
|
|
2604 // Check that this entry is non-null. A null entry means that
|
|
2605 // the receiver class doesn't implement the interface, and wasn't the
|
|
2606 // same as when the caller was compiled.
|
|
2607 bpr(Assembler::rc_z, false, Assembler::pn, method_result, did_save ? L_no_such_interface_restore : L_no_such_interface);
|
|
2608 delayed()->cmp(method_result, intf_klass);
|
|
2609
|
|
2610 if (peel) {
|
|
2611 brx(Assembler::equal, false, Assembler::pt, L_found_method);
|
|
2612 } else {
|
|
2613 brx(Assembler::notEqual, false, Assembler::pn, L_search);
|
|
2614 // (invert the test to fall through to found_method...)
|
|
2615 }
|
|
2616 delayed()->add(scan_temp, scan_step, scan_temp);
|
|
2617
|
|
2618 if (!peel) break;
|
|
2619
|
|
2620 bind(L_search);
|
|
2621 }
|
|
2622
|
|
2623 bind(L_found_method);
|
|
2624
|
|
2625 // Got a hit.
|
|
2626 int ito_offset = itableOffsetEntry::offset_offset_in_bytes();
|
|
2627 // scan_temp[-scan_step] points to the vtable offset we need
|
|
2628 ito_offset -= scan_step;
|
|
2629 lduw(scan_temp, ito_offset, scan_temp);
|
|
2630 ld_ptr(recv_klass, scan_temp, method_result);
|
|
2631
|
|
2632 if (did_save) {
|
|
2633 Label L_done;
|
|
2634 ba(L_done);
|
|
2635 delayed()->restore();
|
|
2636
|
|
2637 bind(L_no_such_interface_restore);
|
|
2638 ba(L_no_such_interface);
|
|
2639 delayed()->restore();
|
|
2640
|
|
2641 bind(L_done);
|
|
2642 }
|
|
2643 }
|
|
2644
|
|
2645
|
|
2646 // virtual method calling
|
|
2647 void MacroAssembler::lookup_virtual_method(Register recv_klass,
|
|
2648 RegisterOrConstant vtable_index,
|
|
2649 Register method_result) {
|
|
2650 assert_different_registers(recv_klass, method_result, vtable_index.register_or_noreg());
|
|
2651 Register sethi_temp = method_result;
|
|
2652 const int base = (InstanceKlass::vtable_start_offset() * wordSize +
|
|
2653 // method pointer offset within the vtable entry:
|
|
2654 vtableEntry::method_offset_in_bytes());
|
|
2655 RegisterOrConstant vtable_offset = vtable_index;
|
|
2656 // Each of the following three lines potentially generates an instruction.
|
|
2657 // But the total number of address formation instructions will always be
|
|
2658 // at most two, and will often be zero. In any case, it will be optimal.
|
|
2659 // If vtable_index is a register, we will have (sll_ptr N,x; inc_ptr B,x; ld_ptr k,x).
|
|
2660 // If vtable_index is a constant, we will have at most (set B+X<<N,t; ld_ptr k,t).
|
|
2661 vtable_offset = regcon_sll_ptr(vtable_index, exact_log2(vtableEntry::size() * wordSize), vtable_offset);
|
|
2662 vtable_offset = regcon_inc_ptr(vtable_offset, base, vtable_offset, sethi_temp);
|
|
2663 Address vtable_entry_addr(recv_klass, ensure_simm13_or_reg(vtable_offset, sethi_temp));
|
|
2664 ld_ptr(vtable_entry_addr, method_result);
|
|
2665 }
|
|
2666
|
|
2667
|
|
2668 void MacroAssembler::check_klass_subtype(Register sub_klass,
|
|
2669 Register super_klass,
|
|
2670 Register temp_reg,
|
|
2671 Register temp2_reg,
|
|
2672 Label& L_success) {
|
|
2673 Register sub_2 = sub_klass;
|
|
2674 Register sup_2 = super_klass;
|
|
2675 if (!sub_2->is_global()) sub_2 = L0;
|
|
2676 if (!sup_2->is_global()) sup_2 = L1;
|
|
2677 bool did_save = false;
|
|
2678 if (temp_reg == noreg || temp2_reg == noreg) {
|
|
2679 temp_reg = L2;
|
|
2680 temp2_reg = L3;
|
|
2681 save_frame_and_mov(0, sub_klass, sub_2, super_klass, sup_2);
|
|
2682 sub_klass = sub_2;
|
|
2683 super_klass = sup_2;
|
|
2684 did_save = true;
|
|
2685 }
|
|
2686 Label L_failure, L_pop_to_failure, L_pop_to_success;
|
|
2687 check_klass_subtype_fast_path(sub_klass, super_klass,
|
|
2688 temp_reg, temp2_reg,
|
|
2689 (did_save ? &L_pop_to_success : &L_success),
|
|
2690 (did_save ? &L_pop_to_failure : &L_failure), NULL);
|
|
2691
|
|
2692 if (!did_save)
|
|
2693 save_frame_and_mov(0, sub_klass, sub_2, super_klass, sup_2);
|
|
2694 check_klass_subtype_slow_path(sub_2, sup_2,
|
|
2695 L2, L3, L4, L5,
|
|
2696 NULL, &L_pop_to_failure);
|
|
2697
|
|
2698 // on success:
|
|
2699 bind(L_pop_to_success);
|
|
2700 restore();
|
|
2701 ba_short(L_success);
|
|
2702
|
|
2703 // on failure:
|
|
2704 bind(L_pop_to_failure);
|
|
2705 restore();
|
|
2706 bind(L_failure);
|
|
2707 }
|
|
2708
|
|
2709
|
|
2710 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
|
|
2711 Register super_klass,
|
|
2712 Register temp_reg,
|
|
2713 Register temp2_reg,
|
|
2714 Label* L_success,
|
|
2715 Label* L_failure,
|
|
2716 Label* L_slow_path,
|
|
2717 RegisterOrConstant super_check_offset) {
|
|
2718 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
|
|
2719 int sco_offset = in_bytes(Klass::super_check_offset_offset());
|
|
2720
|
|
2721 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
|
|
2722 bool need_slow_path = (must_load_sco ||
|
|
2723 super_check_offset.constant_or_zero() == sco_offset);
|
|
2724
|
|
2725 assert_different_registers(sub_klass, super_klass, temp_reg);
|
|
2726 if (super_check_offset.is_register()) {
|
|
2727 assert_different_registers(sub_klass, super_klass, temp_reg,
|
|
2728 super_check_offset.as_register());
|
|
2729 } else if (must_load_sco) {
|
|
2730 assert(temp2_reg != noreg, "supply either a temp or a register offset");
|
|
2731 }
|
|
2732
|
|
2733 Label L_fallthrough;
|
|
2734 int label_nulls = 0;
|
|
2735 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
|
|
2736 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
|
|
2737 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
|
|
2738 assert(label_nulls <= 1 ||
|
|
2739 (L_slow_path == &L_fallthrough && label_nulls <= 2 && !need_slow_path),
|
|
2740 "at most one NULL in the batch, usually");
|
|
2741
|
|
2742 // If the pointers are equal, we are done (e.g., String[] elements).
|
|
2743 // This self-check enables sharing of secondary supertype arrays among
|
|
2744 // non-primary types such as array-of-interface. Otherwise, each such
|
|
2745 // type would need its own customized SSA.
|
|
2746 // We move this check to the front of the fast path because many
|
|
2747 // type checks are in fact trivially successful in this manner,
|
|
2748 // so we get a nicely predicted branch right at the start of the check.
|
|
2749 cmp(super_klass, sub_klass);
|
|
2750 brx(Assembler::equal, false, Assembler::pn, *L_success);
|
|
2751 delayed()->nop();
|
|
2752
|
|
2753 // Check the supertype display:
|
|
2754 if (must_load_sco) {
|
|
2755 // The super check offset is always positive...
|
|
2756 lduw(super_klass, sco_offset, temp2_reg);
|
|
2757 super_check_offset = RegisterOrConstant(temp2_reg);
|
|
2758 // super_check_offset is register.
|
|
2759 assert_different_registers(sub_klass, super_klass, temp_reg, super_check_offset.as_register());
|
|
2760 }
|
|
2761 ld_ptr(sub_klass, super_check_offset, temp_reg);
|
|
2762 cmp(super_klass, temp_reg);
|
|
2763
|
|
2764 // This check has worked decisively for primary supers.
|
|
2765 // Secondary supers are sought in the super_cache ('super_cache_addr').
|
|
2766 // (Secondary supers are interfaces and very deeply nested subtypes.)
|
|
2767 // This works in the same check above because of a tricky aliasing
|
|
2768 // between the super_cache and the primary super display elements.
|
|
2769 // (The 'super_check_addr' can address either, as the case requires.)
|
|
2770 // Note that the cache is updated below if it does not help us find
|
|
2771 // what we need immediately.
|
|
2772 // So if it was a primary super, we can just fail immediately.
|
|
2773 // Otherwise, it's the slow path for us (no success at this point).
|
|
2774
|
|
2775 // Hacked ba(), which may only be used just before L_fallthrough.
|
|
2776 #define FINAL_JUMP(label) \
|
|
2777 if (&(label) != &L_fallthrough) { \
|
|
2778 ba(label); delayed()->nop(); \
|
|
2779 }
|
|
2780
|
|
2781 if (super_check_offset.is_register()) {
|
|
2782 brx(Assembler::equal, false, Assembler::pn, *L_success);
|
|
2783 delayed()->cmp(super_check_offset.as_register(), sc_offset);
|
|
2784
|
|
2785 if (L_failure == &L_fallthrough) {
|
|
2786 brx(Assembler::equal, false, Assembler::pt, *L_slow_path);
|
|
2787 delayed()->nop();
|
|
2788 } else {
|
|
2789 brx(Assembler::notEqual, false, Assembler::pn, *L_failure);
|
|
2790 delayed()->nop();
|
|
2791 FINAL_JUMP(*L_slow_path);
|
|
2792 }
|
|
2793 } else if (super_check_offset.as_constant() == sc_offset) {
|
|
2794 // Need a slow path; fast failure is impossible.
|
|
2795 if (L_slow_path == &L_fallthrough) {
|
|
2796 brx(Assembler::equal, false, Assembler::pt, *L_success);
|
|
2797 delayed()->nop();
|
|
2798 } else {
|
|
2799 brx(Assembler::notEqual, false, Assembler::pn, *L_slow_path);
|
|
2800 delayed()->nop();
|
|
2801 FINAL_JUMP(*L_success);
|
|
2802 }
|
|
2803 } else {
|
|
2804 // No slow path; it's a fast decision.
|
|
2805 if (L_failure == &L_fallthrough) {
|
|
2806 brx(Assembler::equal, false, Assembler::pt, *L_success);
|
|
2807 delayed()->nop();
|
|
2808 } else {
|
|
2809 brx(Assembler::notEqual, false, Assembler::pn, *L_failure);
|
|
2810 delayed()->nop();
|
|
2811 FINAL_JUMP(*L_success);
|
|
2812 }
|
|
2813 }
|
|
2814
|
|
2815 bind(L_fallthrough);
|
|
2816
|
|
2817 #undef FINAL_JUMP
|
|
2818 }
|
|
2819
|
|
2820
|
|
2821 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
|
|
2822 Register super_klass,
|
|
2823 Register count_temp,
|
|
2824 Register scan_temp,
|
|
2825 Register scratch_reg,
|
|
2826 Register coop_reg,
|
|
2827 Label* L_success,
|
|
2828 Label* L_failure) {
|
|
2829 assert_different_registers(sub_klass, super_klass,
|
|
2830 count_temp, scan_temp, scratch_reg, coop_reg);
|
|
2831
|
|
2832 Label L_fallthrough, L_loop;
|
|
2833 int label_nulls = 0;
|
|
2834 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
|
|
2835 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
|
|
2836 assert(label_nulls <= 1, "at most one NULL in the batch");
|
|
2837
|
|
2838 // a couple of useful fields in sub_klass:
|
|
2839 int ss_offset = in_bytes(Klass::secondary_supers_offset());
|
|
2840 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
|
|
2841
|
|
2842 // Do a linear scan of the secondary super-klass chain.
|
|
2843 // This code is rarely used, so simplicity is a virtue here.
|
|
2844
|
|
2845 #ifndef PRODUCT
|
|
2846 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
|
|
2847 inc_counter((address) pst_counter, count_temp, scan_temp);
|
|
2848 #endif
|
|
2849
|
|
2850 // We will consult the secondary-super array.
|
|
2851 ld_ptr(sub_klass, ss_offset, scan_temp);
|
|
2852
|
|
2853 Register search_key = super_klass;
|
|
2854
|
|
2855 // Load the array length. (Positive movl does right thing on LP64.)
|
|
2856 lduw(scan_temp, Array<Klass*>::length_offset_in_bytes(), count_temp);
|
|
2857
|
|
2858 // Check for empty secondary super list
|
|
2859 tst(count_temp);
|
|
2860
|
|
2861 // In the array of super classes elements are pointer sized.
|
|
2862 int element_size = wordSize;
|
|
2863
|
|
2864 // Top of search loop
|
|
2865 bind(L_loop);
|
|
2866 br(Assembler::equal, false, Assembler::pn, *L_failure);
|
|
2867 delayed()->add(scan_temp, element_size, scan_temp);
|
|
2868
|
|
2869 // Skip the array header in all array accesses.
|
|
2870 int elem_offset = Array<Klass*>::base_offset_in_bytes();
|
|
2871 elem_offset -= element_size; // the scan pointer was pre-incremented also
|
|
2872
|
|
2873 // Load next super to check
|
|
2874 ld_ptr( scan_temp, elem_offset, scratch_reg );
|
|
2875
|
|
2876 // Look for Rsuper_klass on Rsub_klass's secondary super-class-overflow list
|
|
2877 cmp(scratch_reg, search_key);
|
|
2878
|
|
2879 // A miss means we are NOT a subtype and need to keep looping
|
|
2880 brx(Assembler::notEqual, false, Assembler::pn, L_loop);
|
|
2881 delayed()->deccc(count_temp); // decrement trip counter in delay slot
|
|
2882
|
|
2883 // Success. Cache the super we found and proceed in triumph.
|
|
2884 st_ptr(super_klass, sub_klass, sc_offset);
|
|
2885
|
|
2886 if (L_success != &L_fallthrough) {
|
|
2887 ba(*L_success);
|
|
2888 delayed()->nop();
|
|
2889 }
|
|
2890
|
|
2891 bind(L_fallthrough);
|
|
2892 }
|
|
2893
|
|
2894
|
|
2895 RegisterOrConstant MacroAssembler::argument_offset(RegisterOrConstant arg_slot,
|
|
2896 Register temp_reg,
|
|
2897 int extra_slot_offset) {
|
|
2898 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
|
|
2899 int stackElementSize = Interpreter::stackElementSize;
|
|
2900 int offset = extra_slot_offset * stackElementSize;
|
|
2901 if (arg_slot.is_constant()) {
|
|
2902 offset += arg_slot.as_constant() * stackElementSize;
|
|
2903 return offset;
|
|
2904 } else {
|
|
2905 assert(temp_reg != noreg, "must specify");
|
|
2906 sll_ptr(arg_slot.as_register(), exact_log2(stackElementSize), temp_reg);
|
|
2907 if (offset != 0)
|
|
2908 add(temp_reg, offset, temp_reg);
|
|
2909 return temp_reg;
|
|
2910 }
|
|
2911 }
|
|
2912
|
|
2913
|
|
2914 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
|
|
2915 Register temp_reg,
|
|
2916 int extra_slot_offset) {
|
|
2917 return Address(Gargs, argument_offset(arg_slot, temp_reg, extra_slot_offset));
|
|
2918 }
|
|
2919
|
|
2920
|
|
2921 void MacroAssembler::biased_locking_enter(Register obj_reg, Register mark_reg,
|
|
2922 Register temp_reg,
|
|
2923 Label& done, Label* slow_case,
|
|
2924 BiasedLockingCounters* counters) {
|
|
2925 assert(UseBiasedLocking, "why call this otherwise?");
|
|
2926
|
|
2927 if (PrintBiasedLockingStatistics) {
|
|
2928 assert_different_registers(obj_reg, mark_reg, temp_reg, O7);
|
|
2929 if (counters == NULL)
|
|
2930 counters = BiasedLocking::counters();
|
|
2931 }
|
|
2932
|
|
2933 Label cas_label;
|
|
2934
|
|
2935 // Biased locking
|
|
2936 // See whether the lock is currently biased toward our thread and
|
|
2937 // whether the epoch is still valid
|
|
2938 // Note that the runtime guarantees sufficient alignment of JavaThread
|
|
2939 // pointers to allow age to be placed into low bits
|
|
2940 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
|
|
2941 and3(mark_reg, markOopDesc::biased_lock_mask_in_place, temp_reg);
|
|
2942 cmp_and_brx_short(temp_reg, markOopDesc::biased_lock_pattern, Assembler::notEqual, Assembler::pn, cas_label);
|
|
2943
|
|
2944 load_klass(obj_reg, temp_reg);
|
|
2945 ld_ptr(Address(temp_reg, Klass::prototype_header_offset()), temp_reg);
|
|
2946 or3(G2_thread, temp_reg, temp_reg);
|
|
2947 xor3(mark_reg, temp_reg, temp_reg);
|
|
2948 andcc(temp_reg, ~((int) markOopDesc::age_mask_in_place), temp_reg);
|
|
2949 if (counters != NULL) {
|
|
2950 cond_inc(Assembler::equal, (address) counters->biased_lock_entry_count_addr(), mark_reg, temp_reg);
|
|
2951 // Reload mark_reg as we may need it later
|
|
2952 ld_ptr(Address(obj_reg, oopDesc::mark_offset_in_bytes()), mark_reg);
|
|
2953 }
|
|
2954 brx(Assembler::equal, true, Assembler::pt, done);
|
|
2955 delayed()->nop();
|
|
2956
|
|
2957 Label try_revoke_bias;
|
|
2958 Label try_rebias;
|
|
2959 Address mark_addr = Address(obj_reg, oopDesc::mark_offset_in_bytes());
|
|
2960 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
|
|
2961
|
|
2962 // At this point we know that the header has the bias pattern and
|
|
2963 // that we are not the bias owner in the current epoch. We need to
|
|
2964 // figure out more details about the state of the header in order to
|
|
2965 // know what operations can be legally performed on the object's
|
|
2966 // header.
|
|
2967
|
|
2968 // If the low three bits in the xor result aren't clear, that means
|
|
2969 // the prototype header is no longer biased and we have to revoke
|
|
2970 // the bias on this object.
|
|
2971 btst(markOopDesc::biased_lock_mask_in_place, temp_reg);
|
|
2972 brx(Assembler::notZero, false, Assembler::pn, try_revoke_bias);
|
|
2973
|
|
2974 // Biasing is still enabled for this data type. See whether the
|
|
2975 // epoch of the current bias is still valid, meaning that the epoch
|
|
2976 // bits of the mark word are equal to the epoch bits of the
|
|
2977 // prototype header. (Note that the prototype header's epoch bits
|
|
2978 // only change at a safepoint.) If not, attempt to rebias the object
|
|
2979 // toward the current thread. Note that we must be absolutely sure
|
|
2980 // that the current epoch is invalid in order to do this because
|
|
2981 // otherwise the manipulations it performs on the mark word are
|
|
2982 // illegal.
|
|
2983 delayed()->btst(markOopDesc::epoch_mask_in_place, temp_reg);
|
|
2984 brx(Assembler::notZero, false, Assembler::pn, try_rebias);
|
|
2985
|
|
2986 // The epoch of the current bias is still valid but we know nothing
|
|
2987 // about the owner; it might be set or it might be clear. Try to
|
|
2988 // acquire the bias of the object using an atomic operation. If this
|
|
2989 // fails we will go in to the runtime to revoke the object's bias.
|
|
2990 // Note that we first construct the presumed unbiased header so we
|
|
2991 // don't accidentally blow away another thread's valid bias.
|
|
2992 delayed()->and3(mark_reg,
|
|
2993 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place,
|
|
2994 mark_reg);
|
|
2995 or3(G2_thread, mark_reg, temp_reg);
|
|
2996 casn(mark_addr.base(), mark_reg, temp_reg);
|
|
2997 // If the biasing toward our thread failed, this means that
|
|
2998 // another thread succeeded in biasing it toward itself and we
|
|
2999 // need to revoke that bias. The revocation will occur in the
|
|
3000 // interpreter runtime in the slow case.
|
|
3001 cmp(mark_reg, temp_reg);
|
|
3002 if (counters != NULL) {
|
|
3003 cond_inc(Assembler::zero, (address) counters->anonymously_biased_lock_entry_count_addr(), mark_reg, temp_reg);
|
|
3004 }
|
|
3005 if (slow_case != NULL) {
|
|
3006 brx(Assembler::notEqual, true, Assembler::pn, *slow_case);
|
|
3007 delayed()->nop();
|
|
3008 }
|
|
3009 ba_short(done);
|
|
3010
|
|
3011 bind(try_rebias);
|
|
3012 // At this point we know the epoch has expired, meaning that the
|
|
3013 // current "bias owner", if any, is actually invalid. Under these
|
|
3014 // circumstances _only_, we are allowed to use the current header's
|
|
3015 // value as the comparison value when doing the cas to acquire the
|
|
3016 // bias in the current epoch. In other words, we allow transfer of
|
|
3017 // the bias from one thread to another directly in this situation.
|
|
3018 //
|
|
3019 // FIXME: due to a lack of registers we currently blow away the age
|
|
3020 // bits in this situation. Should attempt to preserve them.
|
|
3021 load_klass(obj_reg, temp_reg);
|
|
3022 ld_ptr(Address(temp_reg, Klass::prototype_header_offset()), temp_reg);
|
|
3023 or3(G2_thread, temp_reg, temp_reg);
|
|
3024 casn(mark_addr.base(), mark_reg, temp_reg);
|
|
3025 // If the biasing toward our thread failed, this means that
|
|
3026 // another thread succeeded in biasing it toward itself and we
|
|
3027 // need to revoke that bias. The revocation will occur in the
|
|
3028 // interpreter runtime in the slow case.
|
|
3029 cmp(mark_reg, temp_reg);
|
|
3030 if (counters != NULL) {
|
|
3031 cond_inc(Assembler::zero, (address) counters->rebiased_lock_entry_count_addr(), mark_reg, temp_reg);
|
|
3032 }
|
|
3033 if (slow_case != NULL) {
|
|
3034 brx(Assembler::notEqual, true, Assembler::pn, *slow_case);
|
|
3035 delayed()->nop();
|
|
3036 }
|
|
3037 ba_short(done);
|
|
3038
|
|
3039 bind(try_revoke_bias);
|
|
3040 // The prototype mark in the klass doesn't have the bias bit set any
|
|
3041 // more, indicating that objects of this data type are not supposed
|
|
3042 // to be biased any more. We are going to try to reset the mark of
|
|
3043 // this object to the prototype value and fall through to the
|
|
3044 // CAS-based locking scheme. Note that if our CAS fails, it means
|
|
3045 // that another thread raced us for the privilege of revoking the
|
|
3046 // bias of this particular object, so it's okay to continue in the
|
|
3047 // normal locking code.
|
|
3048 //
|
|
3049 // FIXME: due to a lack of registers we currently blow away the age
|
|
3050 // bits in this situation. Should attempt to preserve them.
|
|
3051 load_klass(obj_reg, temp_reg);
|
|
3052 ld_ptr(Address(temp_reg, Klass::prototype_header_offset()), temp_reg);
|
|
3053 casn(mark_addr.base(), mark_reg, temp_reg);
|
|
3054 // Fall through to the normal CAS-based lock, because no matter what
|
|
3055 // the result of the above CAS, some thread must have succeeded in
|
|
3056 // removing the bias bit from the object's header.
|
|
3057 if (counters != NULL) {
|
|
3058 cmp(mark_reg, temp_reg);
|
|
3059 cond_inc(Assembler::zero, (address) counters->revoked_lock_entry_count_addr(), mark_reg, temp_reg);
|
|
3060 }
|
|
3061
|
|
3062 bind(cas_label);
|
|
3063 }
|
|
3064
|
|
3065 void MacroAssembler::biased_locking_exit (Address mark_addr, Register temp_reg, Label& done,
|
|
3066 bool allow_delay_slot_filling) {
|
|
3067 // Check for biased locking unlock case, which is a no-op
|
|
3068 // Note: we do not have to check the thread ID for two reasons.
|
|
3069 // First, the interpreter checks for IllegalMonitorStateException at
|
|
3070 // a higher level. Second, if the bias was revoked while we held the
|
|
3071 // lock, the object could not be rebiased toward another thread, so
|
|
3072 // the bias bit would be clear.
|
|
3073 ld_ptr(mark_addr, temp_reg);
|
|
3074 and3(temp_reg, markOopDesc::biased_lock_mask_in_place, temp_reg);
|
|
3075 cmp(temp_reg, markOopDesc::biased_lock_pattern);
|
|
3076 brx(Assembler::equal, allow_delay_slot_filling, Assembler::pt, done);
|
|
3077 delayed();
|
|
3078 if (!allow_delay_slot_filling) {
|
|
3079 nop();
|
|
3080 }
|
|
3081 }
|
|
3082
|
|
3083
|
|
3084 // CASN -- 32-64 bit switch hitter similar to the synthetic CASN provided by
|
|
3085 // Solaris/SPARC's "as". Another apt name would be cas_ptr()
|
|
3086
|
|
3087 void MacroAssembler::casn (Register addr_reg, Register cmp_reg, Register set_reg ) {
|
|
3088 casx_under_lock (addr_reg, cmp_reg, set_reg, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr());
|
|
3089 }
|
|
3090
|
|
3091
|
|
3092
|
|
3093 // compiler_lock_object() and compiler_unlock_object() are direct transliterations
|
|
3094 // of i486.ad fast_lock() and fast_unlock(). See those methods for detailed comments.
|
|
3095 // The code could be tightened up considerably.
|
|
3096 //
|
|
3097 // box->dhw disposition - post-conditions at DONE_LABEL.
|
|
3098 // - Successful inflated lock: box->dhw != 0.
|
|
3099 // Any non-zero value suffices.
|
|
3100 // Consider G2_thread, rsp, boxReg, or unused_mark()
|
|
3101 // - Successful Stack-lock: box->dhw == mark.
|
|
3102 // box->dhw must contain the displaced mark word value
|
|
3103 // - Failure -- icc.ZFlag == 0 and box->dhw is undefined.
|
|
3104 // The slow-path fast_enter() and slow_enter() operators
|
|
3105 // are responsible for setting box->dhw = NonZero (typically ::unused_mark).
|
|
3106 // - Biased: box->dhw is undefined
|
|
3107 //
|
|
3108 // SPARC refworkload performance - specifically jetstream and scimark - are
|
|
3109 // extremely sensitive to the size of the code emitted by compiler_lock_object
|
|
3110 // and compiler_unlock_object. Critically, the key factor is code size, not path
|
|
3111 // length. (Simply experiments to pad CLO with unexecuted NOPs demonstrte the
|
|
3112 // effect).
|
|
3113
|
|
3114
|
|
3115 void MacroAssembler::compiler_lock_object(Register Roop, Register Rmark,
|
|
3116 Register Rbox, Register Rscratch,
|
|
3117 BiasedLockingCounters* counters,
|
|
3118 bool try_bias) {
|
|
3119 Address mark_addr(Roop, oopDesc::mark_offset_in_bytes());
|
|
3120
|
|
3121 verify_oop(Roop);
|
|
3122 Label done ;
|
|
3123
|
|
3124 if (counters != NULL) {
|
|
3125 inc_counter((address) counters->total_entry_count_addr(), Rmark, Rscratch);
|
|
3126 }
|
|
3127
|
|
3128 if (EmitSync & 1) {
|
|
3129 mov(3, Rscratch);
|
|
3130 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
|
|
3131 cmp(SP, G0);
|
|
3132 return ;
|
|
3133 }
|
|
3134
|
|
3135 if (EmitSync & 2) {
|
|
3136
|
|
3137 // Fetch object's markword
|
|
3138 ld_ptr(mark_addr, Rmark);
|
|
3139
|
|
3140 if (try_bias) {
|
|
3141 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters);
|
|
3142 }
|
|
3143
|
|
3144 // Save Rbox in Rscratch to be used for the cas operation
|
|
3145 mov(Rbox, Rscratch);
|
|
3146
|
|
3147 // set Rmark to markOop | markOopDesc::unlocked_value
|
|
3148 or3(Rmark, markOopDesc::unlocked_value, Rmark);
|
|
3149
|
|
3150 // Initialize the box. (Must happen before we update the object mark!)
|
|
3151 st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes());
|
|
3152
|
|
3153 // compare object markOop with Rmark and if equal exchange Rscratch with object markOop
|
|
3154 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
|
|
3155 casx_under_lock(mark_addr.base(), Rmark, Rscratch,
|
|
3156 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr());
|
|
3157
|
|
3158 // if compare/exchange succeeded we found an unlocked object and we now have locked it
|
|
3159 // hence we are done
|
|
3160 cmp(Rmark, Rscratch);
|
|
3161 #ifdef _LP64
|
|
3162 sub(Rscratch, STACK_BIAS, Rscratch);
|
|
3163 #endif
|
|
3164 brx(Assembler::equal, false, Assembler::pt, done);
|
|
3165 delayed()->sub(Rscratch, SP, Rscratch); //pull next instruction into delay slot
|
|
3166
|
|
3167 // we did not find an unlocked object so see if this is a recursive case
|
|
3168 // sub(Rscratch, SP, Rscratch);
|
|
3169 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant");
|
|
3170 andcc(Rscratch, 0xfffff003, Rscratch);
|
|
3171 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
|
|
3172 bind (done);
|
|
3173 return ;
|
|
3174 }
|
|
3175
|
|
3176 Label Egress ;
|
|
3177
|
|
3178 if (EmitSync & 256) {
|
|
3179 Label IsInflated ;
|
|
3180
|
|
3181 ld_ptr(mark_addr, Rmark); // fetch obj->mark
|
|
3182 // Triage: biased, stack-locked, neutral, inflated
|
|
3183 if (try_bias) {
|
|
3184 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters);
|
|
3185 // Invariant: if control reaches this point in the emitted stream
|
|
3186 // then Rmark has not been modified.
|
|
3187 }
|
|
3188
|
|
3189 // Store mark into displaced mark field in the on-stack basic-lock "box"
|
|
3190 // Critically, this must happen before the CAS
|
|
3191 // Maximize the ST-CAS distance to minimize the ST-before-CAS penalty.
|
|
3192 st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes());
|
|
3193 andcc(Rmark, 2, G0);
|
|
3194 brx(Assembler::notZero, false, Assembler::pn, IsInflated);
|
|
3195 delayed()->
|
|
3196
|
|
3197 // Try stack-lock acquisition.
|
|
3198 // Beware: the 1st instruction is in a delay slot
|
|
3199 mov(Rbox, Rscratch);
|
|
3200 or3(Rmark, markOopDesc::unlocked_value, Rmark);
|
|
3201 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
|
|
3202 casn(mark_addr.base(), Rmark, Rscratch);
|
|
3203 cmp(Rmark, Rscratch);
|
|
3204 brx(Assembler::equal, false, Assembler::pt, done);
|
|
3205 delayed()->sub(Rscratch, SP, Rscratch);
|
|
3206
|
|
3207 // Stack-lock attempt failed - check for recursive stack-lock.
|
|
3208 // See the comments below about how we might remove this case.
|
|
3209 #ifdef _LP64
|
|
3210 sub(Rscratch, STACK_BIAS, Rscratch);
|
|
3211 #endif
|
|
3212 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant");
|
|
3213 andcc(Rscratch, 0xfffff003, Rscratch);
|
|
3214 br(Assembler::always, false, Assembler::pt, done);
|
|
3215 delayed()-> st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
|
|
3216
|
|
3217 bind(IsInflated);
|
|
3218 if (EmitSync & 64) {
|
|
3219 // If m->owner != null goto IsLocked
|
|
3220 // Pessimistic form: Test-and-CAS vs CAS
|
|
3221 // The optimistic form avoids RTS->RTO cache line upgrades.
|
|
3222 ld_ptr(Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch);
|
|
3223 andcc(Rscratch, Rscratch, G0);
|
|
3224 brx(Assembler::notZero, false, Assembler::pn, done);
|
|
3225 delayed()->nop();
|
|
3226 // m->owner == null : it's unlocked.
|
|
3227 }
|
|
3228
|
|
3229 // Try to CAS m->owner from null to Self
|
|
3230 // Invariant: if we acquire the lock then _recursions should be 0.
|
|
3231 add(Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark);
|
|
3232 mov(G2_thread, Rscratch);
|
|
3233 casn(Rmark, G0, Rscratch);
|
|
3234 cmp(Rscratch, G0);
|
|
3235 // Intentional fall-through into done
|
|
3236 } else {
|
|
3237 // Aggressively avoid the Store-before-CAS penalty
|
|
3238 // Defer the store into box->dhw until after the CAS
|
|
3239 Label IsInflated, Recursive ;
|
|
3240
|
|
3241 // Anticipate CAS -- Avoid RTS->RTO upgrade
|
|
3242 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads);
|
|
3243
|
|
3244 ld_ptr(mark_addr, Rmark); // fetch obj->mark
|
|
3245 // Triage: biased, stack-locked, neutral, inflated
|
|
3246
|
|
3247 if (try_bias) {
|
|
3248 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters);
|
|
3249 // Invariant: if control reaches this point in the emitted stream
|
|
3250 // then Rmark has not been modified.
|
|
3251 }
|
|
3252 andcc(Rmark, 2, G0);
|
|
3253 brx(Assembler::notZero, false, Assembler::pn, IsInflated);
|
|
3254 delayed()-> // Beware - dangling delay-slot
|
|
3255
|
|
3256 // Try stack-lock acquisition.
|
|
3257 // Transiently install BUSY (0) encoding in the mark word.
|
|
3258 // if the CAS of 0 into the mark was successful then we execute:
|
|
3259 // ST box->dhw = mark -- save fetched mark in on-stack basiclock box
|
|
3260 // ST obj->mark = box -- overwrite transient 0 value
|
|
3261 // This presumes TSO, of course.
|
|
3262
|
|
3263 mov(0, Rscratch);
|
|
3264 or3(Rmark, markOopDesc::unlocked_value, Rmark);
|
|
3265 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
|
|
3266 casn(mark_addr.base(), Rmark, Rscratch);
|
|
3267 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads);
|
|
3268 cmp(Rscratch, Rmark);
|
|
3269 brx(Assembler::notZero, false, Assembler::pn, Recursive);
|
|
3270 delayed()->st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes());
|
|
3271 if (counters != NULL) {
|
|
3272 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch);
|
|
3273 }
|
|
3274 ba(done);
|
|
3275 delayed()->st_ptr(Rbox, mark_addr);
|
|
3276
|
|
3277 bind(Recursive);
|
|
3278 // Stack-lock attempt failed - check for recursive stack-lock.
|
|
3279 // Tests show that we can remove the recursive case with no impact
|
|
3280 // on refworkload 0.83. If we need to reduce the size of the code
|
|
3281 // emitted by compiler_lock_object() the recursive case is perfect
|
|
3282 // candidate.
|
|
3283 //
|
|
3284 // A more extreme idea is to always inflate on stack-lock recursion.
|
|
3285 // This lets us eliminate the recursive checks in compiler_lock_object
|
|
3286 // and compiler_unlock_object and the (box->dhw == 0) encoding.
|
|
3287 // A brief experiment - requiring changes to synchronizer.cpp, interpreter,
|
|
3288 // and showed a performance *increase*. In the same experiment I eliminated
|
|
3289 // the fast-path stack-lock code from the interpreter and always passed
|
|
3290 // control to the "slow" operators in synchronizer.cpp.
|
|
3291
|
|
3292 // RScratch contains the fetched obj->mark value from the failed CASN.
|
|
3293 #ifdef _LP64
|
|
3294 sub(Rscratch, STACK_BIAS, Rscratch);
|
|
3295 #endif
|
|
3296 sub(Rscratch, SP, Rscratch);
|
|
3297 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant");
|
|
3298 andcc(Rscratch, 0xfffff003, Rscratch);
|
|
3299 if (counters != NULL) {
|
|
3300 // Accounting needs the Rscratch register
|
|
3301 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
|
|
3302 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch);
|
|
3303 ba_short(done);
|
|
3304 } else {
|
|
3305 ba(done);
|
|
3306 delayed()->st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
|
|
3307 }
|
|
3308
|
|
3309 bind (IsInflated);
|
|
3310 if (EmitSync & 64) {
|
|
3311 // If m->owner != null goto IsLocked
|
|
3312 // Test-and-CAS vs CAS
|
|
3313 // Pessimistic form avoids futile (doomed) CAS attempts
|
|
3314 // The optimistic form avoids RTS->RTO cache line upgrades.
|
|
3315 ld_ptr(Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch);
|
|
3316 andcc(Rscratch, Rscratch, G0);
|
|
3317 brx(Assembler::notZero, false, Assembler::pn, done);
|
|
3318 delayed()->nop();
|
|
3319 // m->owner == null : it's unlocked.
|
|
3320 }
|
|
3321
|
|
3322 // Try to CAS m->owner from null to Self
|
|
3323 // Invariant: if we acquire the lock then _recursions should be 0.
|
|
3324 add(Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark);
|
|
3325 mov(G2_thread, Rscratch);
|
|
3326 casn(Rmark, G0, Rscratch);
|
|
3327 cmp(Rscratch, G0);
|
|
3328 // ST box->displaced_header = NonZero.
|
|
3329 // Any non-zero value suffices:
|
|
3330 // unused_mark(), G2_thread, RBox, RScratch, rsp, etc.
|
|
3331 st_ptr(Rbox, Rbox, BasicLock::displaced_header_offset_in_bytes());
|
|
3332 // Intentional fall-through into done
|
|
3333 }
|
|
3334
|
|
3335 bind (done);
|
|
3336 }
|
|
3337
|
|
3338 void MacroAssembler::compiler_unlock_object(Register Roop, Register Rmark,
|
|
3339 Register Rbox, Register Rscratch,
|
|
3340 bool try_bias) {
|
|
3341 Address mark_addr(Roop, oopDesc::mark_offset_in_bytes());
|
|
3342
|
|
3343 Label done ;
|
|
3344
|
|
3345 if (EmitSync & 4) {
|
|
3346 cmp(SP, G0);
|
|
3347 return ;
|
|
3348 }
|
|
3349
|
|
3350 if (EmitSync & 8) {
|
|
3351 if (try_bias) {
|
|
3352 biased_locking_exit(mark_addr, Rscratch, done);
|
|
3353 }
|
|
3354
|
|
3355 // Test first if it is a fast recursive unlock
|
|
3356 ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rmark);
|
|
3357 br_null_short(Rmark, Assembler::pt, done);
|
|
3358
|
|
3359 // Check if it is still a light weight lock, this is is true if we see
|
|
3360 // the stack address of the basicLock in the markOop of the object
|
|
3361 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
|
|
3362 casx_under_lock(mark_addr.base(), Rbox, Rmark,
|
|
3363 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr());
|
|
3364 ba(done);
|
|
3365 delayed()->cmp(Rbox, Rmark);
|
|
3366 bind(done);
|
|
3367 return ;
|
|
3368 }
|
|
3369
|
|
3370 // Beware ... If the aggregate size of the code emitted by CLO and CUO is
|
|
3371 // is too large performance rolls abruptly off a cliff.
|
|
3372 // This could be related to inlining policies, code cache management, or
|
|
3373 // I$ effects.
|
|
3374 Label LStacked ;
|
|
3375
|
|
3376 if (try_bias) {
|
|
3377 // TODO: eliminate redundant LDs of obj->mark
|
|
3378 biased_locking_exit(mark_addr, Rscratch, done);
|
|
3379 }
|
|
3380
|
|
3381 ld_ptr(Roop, oopDesc::mark_offset_in_bytes(), Rmark);
|
|
3382 ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rscratch);
|
|
3383 andcc(Rscratch, Rscratch, G0);
|
|
3384 brx(Assembler::zero, false, Assembler::pn, done);
|
|
3385 delayed()->nop(); // consider: relocate fetch of mark, above, into this DS
|
|
3386 andcc(Rmark, 2, G0);
|
|
3387 brx(Assembler::zero, false, Assembler::pt, LStacked);
|
|
3388 delayed()->nop();
|
|
3389
|
|
3390 // It's inflated
|
|
3391 // Conceptually we need a #loadstore|#storestore "release" MEMBAR before
|
|
3392 // the ST of 0 into _owner which releases the lock. This prevents loads
|
|
3393 // and stores within the critical section from reordering (floating)
|
|
3394 // past the store that releases the lock. But TSO is a strong memory model
|
|
3395 // and that particular flavor of barrier is a noop, so we can safely elide it.
|
|
3396 // Note that we use 1-0 locking by default for the inflated case. We
|
|
3397 // close the resultant (and rare) race by having contented threads in
|
|
3398 // monitorenter periodically poll _owner.
|
|
3399 ld_ptr(Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch);
|
|
3400 ld_ptr(Rmark, ObjectMonitor::recursions_offset_in_bytes() - 2, Rbox);
|
|
3401 xor3(Rscratch, G2_thread, Rscratch);
|
|
3402 orcc(Rbox, Rscratch, Rbox);
|
|
3403 brx(Assembler::notZero, false, Assembler::pn, done);
|
|
3404 delayed()->
|
|
3405 ld_ptr(Rmark, ObjectMonitor::EntryList_offset_in_bytes() - 2, Rscratch);
|
|
3406 ld_ptr(Rmark, ObjectMonitor::cxq_offset_in_bytes() - 2, Rbox);
|
|
3407 orcc(Rbox, Rscratch, G0);
|
|
3408 if (EmitSync & 65536) {
|
|
3409 Label LSucc ;
|
|
3410 brx(Assembler::notZero, false, Assembler::pn, LSucc);
|
|
3411 delayed()->nop();
|
|
3412 ba(done);
|
|
3413 delayed()->st_ptr(G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2);
|
|
3414
|
|
3415 bind(LSucc);
|
|
3416 st_ptr(G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2);
|
|
3417 if (os::is_MP()) { membar (StoreLoad); }
|
|
3418 ld_ptr(Rmark, ObjectMonitor::succ_offset_in_bytes() - 2, Rscratch);
|
|
3419 andcc(Rscratch, Rscratch, G0);
|
|
3420 brx(Assembler::notZero, false, Assembler::pt, done);
|
|
3421 delayed()->andcc(G0, G0, G0);
|
|
3422 add(Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark);
|
|
3423 mov(G2_thread, Rscratch);
|
|
3424 casn(Rmark, G0, Rscratch);
|
|
3425 // invert icc.zf and goto done
|
|
3426 br_notnull(Rscratch, false, Assembler::pt, done);
|
|
3427 delayed()->cmp(G0, G0);
|
|
3428 ba(done);
|
|
3429 delayed()->cmp(G0, 1);
|
|
3430 } else {
|
|
3431 brx(Assembler::notZero, false, Assembler::pn, done);
|
|
3432 delayed()->nop();
|
|
3433 ba(done);
|
|
3434 delayed()->st_ptr(G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2);
|
|
3435 }
|
|
3436
|
|
3437 bind (LStacked);
|
|
3438 // Consider: we could replace the expensive CAS in the exit
|
|
3439 // path with a simple ST of the displaced mark value fetched from
|
|
3440 // the on-stack basiclock box. That admits a race where a thread T2
|
|
3441 // in the slow lock path -- inflating with monitor M -- could race a
|
|
3442 // thread T1 in the fast unlock path, resulting in a missed wakeup for T2.
|
|
3443 // More precisely T1 in the stack-lock unlock path could "stomp" the
|
|
3444 // inflated mark value M installed by T2, resulting in an orphan
|
|
3445 // object monitor M and T2 becoming stranded. We can remedy that situation
|
|
3446 // by having T2 periodically poll the object's mark word using timed wait
|
|
3447 // operations. If T2 discovers that a stomp has occurred it vacates
|
|
3448 // the monitor M and wakes any other threads stranded on the now-orphan M.
|
|
3449 // In addition the monitor scavenger, which performs deflation,
|
|
3450 // would also need to check for orpan monitors and stranded threads.
|
|
3451 //
|
|
3452 // Finally, inflation is also used when T2 needs to assign a hashCode
|
|
3453 // to O and O is stack-locked by T1. The "stomp" race could cause
|
|
3454 // an assigned hashCode value to be lost. We can avoid that condition
|
|
3455 // and provide the necessary hashCode stability invariants by ensuring
|
|
3456 // that hashCode generation is idempotent between copying GCs.
|
|
3457 // For example we could compute the hashCode of an object O as
|
|
3458 // O's heap address XOR some high quality RNG value that is refreshed
|
|
3459 // at GC-time. The monitor scavenger would install the hashCode
|
|
3460 // found in any orphan monitors. Again, the mechanism admits a
|
|
3461 // lost-update "stomp" WAW race but detects and recovers as needed.
|
|
3462 //
|
|
3463 // A prototype implementation showed excellent results, although
|
|
3464 // the scavenger and timeout code was rather involved.
|
|
3465
|
|
3466 casn(mark_addr.base(), Rbox, Rscratch);
|
|
3467 cmp(Rbox, Rscratch);
|
|
3468 // Intentional fall through into done ...
|
|
3469
|
|
3470 bind(done);
|
|
3471 }
|
|
3472
|
|
3473
|
|
3474
|
|
3475 void MacroAssembler::print_CPU_state() {
|
|
3476 // %%%%% need to implement this
|
|
3477 }
|
|
3478
|
|
3479 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
|
|
3480 // %%%%% need to implement this
|
|
3481 }
|
|
3482
|
|
3483 void MacroAssembler::push_IU_state() {
|
|
3484 // %%%%% need to implement this
|
|
3485 }
|
|
3486
|
|
3487
|
|
3488 void MacroAssembler::pop_IU_state() {
|
|
3489 // %%%%% need to implement this
|
|
3490 }
|
|
3491
|
|
3492
|
|
3493 void MacroAssembler::push_FPU_state() {
|
|
3494 // %%%%% need to implement this
|
|
3495 }
|
|
3496
|
|
3497
|
|
3498 void MacroAssembler::pop_FPU_state() {
|
|
3499 // %%%%% need to implement this
|
|
3500 }
|
|
3501
|
|
3502
|
|
3503 void MacroAssembler::push_CPU_state() {
|
|
3504 // %%%%% need to implement this
|
|
3505 }
|
|
3506
|
|
3507
|
|
3508 void MacroAssembler::pop_CPU_state() {
|
|
3509 // %%%%% need to implement this
|
|
3510 }
|
|
3511
|
|
3512
|
|
3513
|
|
3514 void MacroAssembler::verify_tlab() {
|
|
3515 #ifdef ASSERT
|
|
3516 if (UseTLAB && VerifyOops) {
|
|
3517 Label next, next2, ok;
|
|
3518 Register t1 = L0;
|
|
3519 Register t2 = L1;
|
|
3520 Register t3 = L2;
|
|
3521
|
|
3522 save_frame(0);
|
|
3523 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1);
|
|
3524 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t2);
|
|
3525 or3(t1, t2, t3);
|
|
3526 cmp_and_br_short(t1, t2, Assembler::greaterEqual, Assembler::pn, next);
|
|
3527 STOP("assert(top >= start)");
|
|
3528 should_not_reach_here();
|
|
3529
|
|
3530 bind(next);
|
|
3531 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1);
|
|
3532 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t2);
|
|
3533 or3(t3, t2, t3);
|
|
3534 cmp_and_br_short(t1, t2, Assembler::lessEqual, Assembler::pn, next2);
|
|
3535 STOP("assert(top <= end)");
|
|
3536 should_not_reach_here();
|
|
3537
|
|
3538 bind(next2);
|
|
3539 and3(t3, MinObjAlignmentInBytesMask, t3);
|
|
3540 cmp_and_br_short(t3, 0, Assembler::lessEqual, Assembler::pn, ok);
|
|
3541 STOP("assert(aligned)");
|
|
3542 should_not_reach_here();
|
|
3543
|
|
3544 bind(ok);
|
|
3545 restore();
|
|
3546 }
|
|
3547 #endif
|
|
3548 }
|
|
3549
|
|
3550
|
|
3551 void MacroAssembler::eden_allocate(
|
|
3552 Register obj, // result: pointer to object after successful allocation
|
|
3553 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
|
|
3554 int con_size_in_bytes, // object size in bytes if known at compile time
|
|
3555 Register t1, // temp register
|
|
3556 Register t2, // temp register
|
|
3557 Label& slow_case // continuation point if fast allocation fails
|
|
3558 ){
|
|
3559 // make sure arguments make sense
|
|
3560 assert_different_registers(obj, var_size_in_bytes, t1, t2);
|
|
3561 assert(0 <= con_size_in_bytes && Assembler::is_simm13(con_size_in_bytes), "illegal object size");
|
|
3562 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment");
|
|
3563
|
|
3564 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
|
|
3565 // No allocation in the shared eden.
|
|
3566 ba_short(slow_case);
|
|
3567 } else {
|
|
3568 // get eden boundaries
|
|
3569 // note: we need both top & top_addr!
|
|
3570 const Register top_addr = t1;
|
|
3571 const Register end = t2;
|
|
3572
|
|
3573 CollectedHeap* ch = Universe::heap();
|
|
3574 set((intx)ch->top_addr(), top_addr);
|
|
3575 intx delta = (intx)ch->end_addr() - (intx)ch->top_addr();
|
|
3576 ld_ptr(top_addr, delta, end);
|
|
3577 ld_ptr(top_addr, 0, obj);
|
|
3578
|
|
3579 // try to allocate
|
|
3580 Label retry;
|
|
3581 bind(retry);
|
|
3582 #ifdef ASSERT
|
|
3583 // make sure eden top is properly aligned
|
|
3584 {
|
|
3585 Label L;
|
|
3586 btst(MinObjAlignmentInBytesMask, obj);
|
|
3587 br(Assembler::zero, false, Assembler::pt, L);
|
|
3588 delayed()->nop();
|
|
3589 STOP("eden top is not properly aligned");
|
|
3590 bind(L);
|
|
3591 }
|
|
3592 #endif // ASSERT
|
|
3593 const Register free = end;
|
|
3594 sub(end, obj, free); // compute amount of free space
|
|
3595 if (var_size_in_bytes->is_valid()) {
|
|
3596 // size is unknown at compile time
|
|
3597 cmp(free, var_size_in_bytes);
|
|
3598 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case
|
|
3599 delayed()->add(obj, var_size_in_bytes, end);
|
|
3600 } else {
|
|
3601 // size is known at compile time
|
|
3602 cmp(free, con_size_in_bytes);
|
|
3603 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case
|
|
3604 delayed()->add(obj, con_size_in_bytes, end);
|
|
3605 }
|
|
3606 // Compare obj with the value at top_addr; if still equal, swap the value of
|
|
3607 // end with the value at top_addr. If not equal, read the value at top_addr
|
|
3608 // into end.
|
|
3609 casx_under_lock(top_addr, obj, end, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr());
|
|
3610 // if someone beat us on the allocation, try again, otherwise continue
|
|
3611 cmp(obj, end);
|
|
3612 brx(Assembler::notEqual, false, Assembler::pn, retry);
|
|
3613 delayed()->mov(end, obj); // nop if successfull since obj == end
|
|
3614
|
|
3615 #ifdef ASSERT
|
|
3616 // make sure eden top is properly aligned
|
|
3617 {
|
|
3618 Label L;
|
|
3619 const Register top_addr = t1;
|
|
3620
|
|
3621 set((intx)ch->top_addr(), top_addr);
|
|
3622 ld_ptr(top_addr, 0, top_addr);
|
|
3623 btst(MinObjAlignmentInBytesMask, top_addr);
|
|
3624 br(Assembler::zero, false, Assembler::pt, L);
|
|
3625 delayed()->nop();
|
|
3626 STOP("eden top is not properly aligned");
|
|
3627 bind(L);
|
|
3628 }
|
|
3629 #endif // ASSERT
|
|
3630 }
|
|
3631 }
|
|
3632
|
|
3633
|
|
3634 void MacroAssembler::tlab_allocate(
|
|
3635 Register obj, // result: pointer to object after successful allocation
|
|
3636 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
|
|
3637 int con_size_in_bytes, // object size in bytes if known at compile time
|
|
3638 Register t1, // temp register
|
|
3639 Label& slow_case // continuation point if fast allocation fails
|
|
3640 ){
|
|
3641 // make sure arguments make sense
|
|
3642 assert_different_registers(obj, var_size_in_bytes, t1);
|
|
3643 assert(0 <= con_size_in_bytes && is_simm13(con_size_in_bytes), "illegal object size");
|
|
3644 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment");
|
|
3645
|
|
3646 const Register free = t1;
|
|
3647
|
|
3648 verify_tlab();
|
|
3649
|
|
3650 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), obj);
|
|
3651
|
|
3652 // calculate amount of free space
|
|
3653 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), free);
|
|
3654 sub(free, obj, free);
|
|
3655
|
|
3656 Label done;
|
|
3657 if (var_size_in_bytes == noreg) {
|
|
3658 cmp(free, con_size_in_bytes);
|
|
3659 } else {
|
|
3660 cmp(free, var_size_in_bytes);
|
|
3661 }
|
|
3662 br(Assembler::less, false, Assembler::pn, slow_case);
|
|
3663 // calculate the new top pointer
|
|
3664 if (var_size_in_bytes == noreg) {
|
|
3665 delayed()->add(obj, con_size_in_bytes, free);
|
|
3666 } else {
|
|
3667 delayed()->add(obj, var_size_in_bytes, free);
|
|
3668 }
|
|
3669
|
|
3670 bind(done);
|
|
3671
|
|
3672 #ifdef ASSERT
|
|
3673 // make sure new free pointer is properly aligned
|
|
3674 {
|
|
3675 Label L;
|
|
3676 btst(MinObjAlignmentInBytesMask, free);
|
|
3677 br(Assembler::zero, false, Assembler::pt, L);
|
|
3678 delayed()->nop();
|
|
3679 STOP("updated TLAB free is not properly aligned");
|
|
3680 bind(L);
|
|
3681 }
|
|
3682 #endif // ASSERT
|
|
3683
|
|
3684 // update the tlab top pointer
|
|
3685 st_ptr(free, G2_thread, in_bytes(JavaThread::tlab_top_offset()));
|
|
3686 verify_tlab();
|
|
3687 }
|
|
3688
|
|
3689
|
|
3690 void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) {
|
|
3691 Register top = O0;
|
|
3692 Register t1 = G1;
|
|
3693 Register t2 = G3;
|
|
3694 Register t3 = O1;
|
|
3695 assert_different_registers(top, t1, t2, t3, G4, G5 /* preserve G4 and G5 */);
|
|
3696 Label do_refill, discard_tlab;
|
|
3697
|
|
3698 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
|
|
3699 // No allocation in the shared eden.
|
|
3700 ba_short(slow_case);
|
|
3701 }
|
|
3702
|
|
3703 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), top);
|
|
3704 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t1);
|
|
3705 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()), t2);
|
|
3706
|
|
3707 // calculate amount of free space
|
|
3708 sub(t1, top, t1);
|
|
3709 srl_ptr(t1, LogHeapWordSize, t1);
|
|
3710
|
|
3711 // Retain tlab and allocate object in shared space if
|
|
3712 // the amount free in the tlab is too large to discard.
|
|
3713 cmp(t1, t2);
|
|
3714 brx(Assembler::lessEqual, false, Assembler::pt, discard_tlab);
|
|
3715
|
|
3716 // increment waste limit to prevent getting stuck on this slow path
|
|
3717 delayed()->add(t2, ThreadLocalAllocBuffer::refill_waste_limit_increment(), t2);
|
|
3718 st_ptr(t2, G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()));
|
|
3719 if (TLABStats) {
|
|
3720 // increment number of slow_allocations
|
|
3721 ld(G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset()), t2);
|
|
3722 add(t2, 1, t2);
|
|
3723 stw(t2, G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset()));
|
|
3724 }
|
|
3725 ba_short(try_eden);
|
|
3726
|
|
3727 bind(discard_tlab);
|
|
3728 if (TLABStats) {
|
|
3729 // increment number of refills
|
|
3730 ld(G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset()), t2);
|
|
3731 add(t2, 1, t2);
|
|
3732 stw(t2, G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset()));
|
|
3733 // accumulate wastage
|
|
3734 ld(G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset()), t2);
|
|
3735 add(t2, t1, t2);
|
|
3736 stw(t2, G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset()));
|
|
3737 }
|
|
3738
|
|
3739 // if tlab is currently allocated (top or end != null) then
|
|
3740 // fill [top, end + alignment_reserve) with array object
|
|
3741 br_null_short(top, Assembler::pn, do_refill);
|
|
3742
|
|
3743 set((intptr_t)markOopDesc::prototype()->copy_set_hash(0x2), t2);
|
|
3744 st_ptr(t2, top, oopDesc::mark_offset_in_bytes()); // set up the mark word
|
|
3745 // set klass to intArrayKlass
|
|
3746 sub(t1, typeArrayOopDesc::header_size(T_INT), t1);
|
|
3747 add(t1, ThreadLocalAllocBuffer::alignment_reserve(), t1);
|
|
3748 sll_ptr(t1, log2_intptr(HeapWordSize/sizeof(jint)), t1);
|
|
3749 st(t1, top, arrayOopDesc::length_offset_in_bytes());
|
|
3750 set((intptr_t)Universe::intArrayKlassObj_addr(), t2);
|
|
3751 ld_ptr(t2, 0, t2);
|
|
3752 // store klass last. concurrent gcs assumes klass length is valid if
|
|
3753 // klass field is not null.
|
|
3754 store_klass(t2, top);
|
|
3755 verify_oop(top);
|
|
3756
|
|
3757 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t1);
|
|
3758 sub(top, t1, t1); // size of tlab's allocated portion
|
|
3759 incr_allocated_bytes(t1, t2, t3);
|
|
3760
|
|
3761 // refill the tlab with an eden allocation
|
|
3762 bind(do_refill);
|
|
3763 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t1);
|
|
3764 sll_ptr(t1, LogHeapWordSize, t1);
|
|
3765 // allocate new tlab, address returned in top
|
|
3766 eden_allocate(top, t1, 0, t2, t3, slow_case);
|
|
3767
|
|
3768 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_start_offset()));
|
|
3769 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_top_offset()));
|
|
3770 #ifdef ASSERT
|
|
3771 // check that tlab_size (t1) is still valid
|
|
3772 {
|
|
3773 Label ok;
|
|
3774 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t2);
|
|
3775 sll_ptr(t2, LogHeapWordSize, t2);
|
|
3776 cmp_and_br_short(t1, t2, Assembler::equal, Assembler::pt, ok);
|
|
3777 STOP("assert(t1 == tlab_size)");
|
|
3778 should_not_reach_here();
|
|
3779
|
|
3780 bind(ok);
|
|
3781 }
|
|
3782 #endif // ASSERT
|
|
3783 add(top, t1, top); // t1 is tlab_size
|
|
3784 sub(top, ThreadLocalAllocBuffer::alignment_reserve_in_bytes(), top);
|
|
3785 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_end_offset()));
|
|
3786 verify_tlab();
|
|
3787 ba_short(retry);
|
|
3788 }
|
|
3789
|
|
3790 void MacroAssembler::incr_allocated_bytes(RegisterOrConstant size_in_bytes,
|
|
3791 Register t1, Register t2) {
|
|
3792 // Bump total bytes allocated by this thread
|
|
3793 assert(t1->is_global(), "must be global reg"); // so all 64 bits are saved on a context switch
|
|
3794 assert_different_registers(size_in_bytes.register_or_noreg(), t1, t2);
|
|
3795 // v8 support has gone the way of the dodo
|
|
3796 ldx(G2_thread, in_bytes(JavaThread::allocated_bytes_offset()), t1);
|
|
3797 add(t1, ensure_simm13_or_reg(size_in_bytes, t2), t1);
|
|
3798 stx(t1, G2_thread, in_bytes(JavaThread::allocated_bytes_offset()));
|
|
3799 }
|
|
3800
|
|
3801 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
|
|
3802 switch (cond) {
|
|
3803 // Note some conditions are synonyms for others
|
|
3804 case Assembler::never: return Assembler::always;
|
|
3805 case Assembler::zero: return Assembler::notZero;
|
|
3806 case Assembler::lessEqual: return Assembler::greater;
|
|
3807 case Assembler::less: return Assembler::greaterEqual;
|
|
3808 case Assembler::lessEqualUnsigned: return Assembler::greaterUnsigned;
|
|
3809 case Assembler::lessUnsigned: return Assembler::greaterEqualUnsigned;
|
|
3810 case Assembler::negative: return Assembler::positive;
|
|
3811 case Assembler::overflowSet: return Assembler::overflowClear;
|
|
3812 case Assembler::always: return Assembler::never;
|
|
3813 case Assembler::notZero: return Assembler::zero;
|
|
3814 case Assembler::greater: return Assembler::lessEqual;
|
|
3815 case Assembler::greaterEqual: return Assembler::less;
|
|
3816 case Assembler::greaterUnsigned: return Assembler::lessEqualUnsigned;
|
|
3817 case Assembler::greaterEqualUnsigned: return Assembler::lessUnsigned;
|
|
3818 case Assembler::positive: return Assembler::negative;
|
|
3819 case Assembler::overflowClear: return Assembler::overflowSet;
|
|
3820 }
|
|
3821
|
|
3822 ShouldNotReachHere(); return Assembler::overflowClear;
|
|
3823 }
|
|
3824
|
|
3825 void MacroAssembler::cond_inc(Assembler::Condition cond, address counter_ptr,
|
|
3826 Register Rtmp1, Register Rtmp2 /*, Register Rtmp3, Register Rtmp4 */) {
|
|
3827 Condition negated_cond = negate_condition(cond);
|
|
3828 Label L;
|
|
3829 brx(negated_cond, false, Assembler::pt, L);
|
|
3830 delayed()->nop();
|
|
3831 inc_counter(counter_ptr, Rtmp1, Rtmp2);
|
|
3832 bind(L);
|
|
3833 }
|
|
3834
|
|
3835 void MacroAssembler::inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2) {
|
|
3836 AddressLiteral addrlit(counter_addr);
|
|
3837 sethi(addrlit, Rtmp1); // Move hi22 bits into temporary register.
|
|
3838 Address addr(Rtmp1, addrlit.low10()); // Build an address with low10 bits.
|
|
3839 ld(addr, Rtmp2);
|
|
3840 inc(Rtmp2);
|
|
3841 st(Rtmp2, addr);
|
|
3842 }
|
|
3843
|
|
3844 void MacroAssembler::inc_counter(int* counter_addr, Register Rtmp1, Register Rtmp2) {
|
|
3845 inc_counter((address) counter_addr, Rtmp1, Rtmp2);
|
|
3846 }
|
|
3847
|
|
3848 SkipIfEqual::SkipIfEqual(
|
|
3849 MacroAssembler* masm, Register temp, const bool* flag_addr,
|
|
3850 Assembler::Condition condition) {
|
|
3851 _masm = masm;
|
|
3852 AddressLiteral flag(flag_addr);
|
|
3853 _masm->sethi(flag, temp);
|
|
3854 _masm->ldub(temp, flag.low10(), temp);
|
|
3855 _masm->tst(temp);
|
|
3856 _masm->br(condition, false, Assembler::pt, _label);
|
|
3857 _masm->delayed()->nop();
|
|
3858 }
|
|
3859
|
|
3860 SkipIfEqual::~SkipIfEqual() {
|
|
3861 _masm->bind(_label);
|
|
3862 }
|
|
3863
|
|
3864
|
|
3865 // Writes to stack successive pages until offset reached to check for
|
|
3866 // stack overflow + shadow pages. This clobbers tsp and scratch.
|
|
3867 void MacroAssembler::bang_stack_size(Register Rsize, Register Rtsp,
|
|
3868 Register Rscratch) {
|
|
3869 // Use stack pointer in temp stack pointer
|
|
3870 mov(SP, Rtsp);
|
|
3871
|
|
3872 // Bang stack for total size given plus stack shadow page size.
|
|
3873 // Bang one page at a time because a large size can overflow yellow and
|
|
3874 // red zones (the bang will fail but stack overflow handling can't tell that
|
|
3875 // it was a stack overflow bang vs a regular segv).
|
|
3876 int offset = os::vm_page_size();
|
|
3877 Register Roffset = Rscratch;
|
|
3878
|
|
3879 Label loop;
|
|
3880 bind(loop);
|
|
3881 set((-offset)+STACK_BIAS, Rscratch);
|
|
3882 st(G0, Rtsp, Rscratch);
|
|
3883 set(offset, Roffset);
|
|
3884 sub(Rsize, Roffset, Rsize);
|
|
3885 cmp(Rsize, G0);
|
|
3886 br(Assembler::greater, false, Assembler::pn, loop);
|
|
3887 delayed()->sub(Rtsp, Roffset, Rtsp);
|
|
3888
|
|
3889 // Bang down shadow pages too.
|
|
3890 // The -1 because we already subtracted 1 page.
|
|
3891 for (int i = 0; i< StackShadowPages-1; i++) {
|
|
3892 set((-i*offset)+STACK_BIAS, Rscratch);
|
|
3893 st(G0, Rtsp, Rscratch);
|
|
3894 }
|
|
3895 }
|
|
3896
|
|
3897 ///////////////////////////////////////////////////////////////////////////////////
|
|
3898 #ifndef SERIALGC
|
|
3899
|
|
3900 static address satb_log_enqueue_with_frame = NULL;
|
|
3901 static u_char* satb_log_enqueue_with_frame_end = NULL;
|
|
3902
|
|
3903 static address satb_log_enqueue_frameless = NULL;
|
|
3904 static u_char* satb_log_enqueue_frameless_end = NULL;
|
|
3905
|
|
3906 static int EnqueueCodeSize = 128 DEBUG_ONLY( + 256); // Instructions?
|
|
3907
|
|
3908 static void generate_satb_log_enqueue(bool with_frame) {
|
|
3909 BufferBlob* bb = BufferBlob::create("enqueue_with_frame", EnqueueCodeSize);
|
|
3910 CodeBuffer buf(bb);
|
|
3911 MacroAssembler masm(&buf);
|
|
3912
|
|
3913 #define __ masm.
|
|
3914
|
|
3915 address start = __ pc();
|
|
3916 Register pre_val;
|
|
3917
|
|
3918 Label refill, restart;
|
|
3919 if (with_frame) {
|
|
3920 __ save_frame(0);
|
|
3921 pre_val = I0; // Was O0 before the save.
|
|
3922 } else {
|
|
3923 pre_val = O0;
|
|
3924 }
|
|
3925
|
|
3926 int satb_q_index_byte_offset =
|
|
3927 in_bytes(JavaThread::satb_mark_queue_offset() +
|
|
3928 PtrQueue::byte_offset_of_index());
|
|
3929
|
|
3930 int satb_q_buf_byte_offset =
|
|
3931 in_bytes(JavaThread::satb_mark_queue_offset() +
|
|
3932 PtrQueue::byte_offset_of_buf());
|
|
3933
|
|
3934 assert(in_bytes(PtrQueue::byte_width_of_index()) == sizeof(intptr_t) &&
|
|
3935 in_bytes(PtrQueue::byte_width_of_buf()) == sizeof(intptr_t),
|
|
3936 "check sizes in assembly below");
|
|
3937
|
|
3938 __ bind(restart);
|
|
3939
|
|
3940 // Load the index into the SATB buffer. PtrQueue::_index is a size_t
|
|
3941 // so ld_ptr is appropriate.
|
|
3942 __ ld_ptr(G2_thread, satb_q_index_byte_offset, L0);
|
|
3943
|
|
3944 // index == 0?
|
|
3945 __ cmp_and_brx_short(L0, G0, Assembler::equal, Assembler::pn, refill);
|
|
3946
|
|
3947 __ ld_ptr(G2_thread, satb_q_buf_byte_offset, L1);
|
|
3948 __ sub(L0, oopSize, L0);
|
|
3949
|
|
3950 __ st_ptr(pre_val, L1, L0); // [_buf + index] := I0
|
|
3951 if (!with_frame) {
|
|
3952 // Use return-from-leaf
|
|
3953 __ retl();
|
|
3954 __ delayed()->st_ptr(L0, G2_thread, satb_q_index_byte_offset);
|
|
3955 } else {
|
|
3956 // Not delayed.
|
|
3957 __ st_ptr(L0, G2_thread, satb_q_index_byte_offset);
|
|
3958 }
|
|
3959 if (with_frame) {
|
|
3960 __ ret();
|
|
3961 __ delayed()->restore();
|
|
3962 }
|
|
3963 __ bind(refill);
|
|
3964
|
|
3965 address handle_zero =
|
|
3966 CAST_FROM_FN_PTR(address,
|
|
3967 &SATBMarkQueueSet::handle_zero_index_for_thread);
|
|
3968 // This should be rare enough that we can afford to save all the
|
|
3969 // scratch registers that the calling context might be using.
|
|
3970 __ mov(G1_scratch, L0);
|
|
3971 __ mov(G3_scratch, L1);
|
|
3972 __ mov(G4, L2);
|
|
3973 // We need the value of O0 above (for the write into the buffer), so we
|
|
3974 // save and restore it.
|
|
3975 __ mov(O0, L3);
|
|
3976 // Since the call will overwrite O7, we save and restore that, as well.
|
|
3977 __ mov(O7, L4);
|
|
3978 __ call_VM_leaf(L5, handle_zero, G2_thread);
|
|
3979 __ mov(L0, G1_scratch);
|
|
3980 __ mov(L1, G3_scratch);
|
|
3981 __ mov(L2, G4);
|
|
3982 __ mov(L3, O0);
|
|
3983 __ br(Assembler::always, /*annul*/false, Assembler::pt, restart);
|
|
3984 __ delayed()->mov(L4, O7);
|
|
3985
|
|
3986 if (with_frame) {
|
|
3987 satb_log_enqueue_with_frame = start;
|
|
3988 satb_log_enqueue_with_frame_end = __ pc();
|
|
3989 } else {
|
|
3990 satb_log_enqueue_frameless = start;
|
|
3991 satb_log_enqueue_frameless_end = __ pc();
|
|
3992 }
|
|
3993
|
|
3994 #undef __
|
|
3995 }
|
|
3996
|
|
3997 static inline void generate_satb_log_enqueue_if_necessary(bool with_frame) {
|
|
3998 if (with_frame) {
|
|
3999 if (satb_log_enqueue_with_frame == 0) {
|
|
4000 generate_satb_log_enqueue(with_frame);
|
|
4001 assert(satb_log_enqueue_with_frame != 0, "postcondition.");
|
|
4002 if (G1SATBPrintStubs) {
|
|
4003 tty->print_cr("Generated with-frame satb enqueue:");
|
|
4004 Disassembler::decode((u_char*)satb_log_enqueue_with_frame,
|
|
4005 satb_log_enqueue_with_frame_end,
|
|
4006 tty);
|
|
4007 }
|
|
4008 }
|
|
4009 } else {
|
|
4010 if (satb_log_enqueue_frameless == 0) {
|
|
4011 generate_satb_log_enqueue(with_frame);
|
|
4012 assert(satb_log_enqueue_frameless != 0, "postcondition.");
|
|
4013 if (G1SATBPrintStubs) {
|
|
4014 tty->print_cr("Generated frameless satb enqueue:");
|
|
4015 Disassembler::decode((u_char*)satb_log_enqueue_frameless,
|
|
4016 satb_log_enqueue_frameless_end,
|
|
4017 tty);
|
|
4018 }
|
|
4019 }
|
|
4020 }
|
|
4021 }
|
|
4022
|
|
4023 void MacroAssembler::g1_write_barrier_pre(Register obj,
|
|
4024 Register index,
|
|
4025 int offset,
|
|
4026 Register pre_val,
|
|
4027 Register tmp,
|
|
4028 bool preserve_o_regs) {
|
|
4029 Label filtered;
|
|
4030
|
|
4031 if (obj == noreg) {
|
|
4032 // We are not loading the previous value so make
|
|
4033 // sure that we don't trash the value in pre_val
|
|
4034 // with the code below.
|
|
4035 assert_different_registers(pre_val, tmp);
|
|
4036 } else {
|
|
4037 // We will be loading the previous value
|
|
4038 // in this code so...
|
|
4039 assert(offset == 0 || index == noreg, "choose one");
|
|
4040 assert(pre_val == noreg, "check this code");
|
|
4041 }
|
|
4042
|
|
4043 // Is marking active?
|
|
4044 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
|
|
4045 ld(G2,
|
|
4046 in_bytes(JavaThread::satb_mark_queue_offset() +
|
|
4047 PtrQueue::byte_offset_of_active()),
|
|
4048 tmp);
|
|
4049 } else {
|
|
4050 guarantee(in_bytes(PtrQueue::byte_width_of_active()) == 1,
|
|
4051 "Assumption");
|
|
4052 ldsb(G2,
|
|
4053 in_bytes(JavaThread::satb_mark_queue_offset() +
|
|
4054 PtrQueue::byte_offset_of_active()),
|
|
4055 tmp);
|
|
4056 }
|
|
4057
|
|
4058 // Is marking active?
|
|
4059 cmp_and_br_short(tmp, G0, Assembler::equal, Assembler::pt, filtered);
|
|
4060
|
|
4061 // Do we need to load the previous value?
|
|
4062 if (obj != noreg) {
|
|
4063 // Load the previous value...
|
|
4064 if (index == noreg) {
|
|
4065 if (Assembler::is_simm13(offset)) {
|
|
4066 load_heap_oop(obj, offset, tmp);
|
|
4067 } else {
|
|
4068 set(offset, tmp);
|
|
4069 load_heap_oop(obj, tmp, tmp);
|
|
4070 }
|
|
4071 } else {
|
|
4072 load_heap_oop(obj, index, tmp);
|
|
4073 }
|
|
4074 // Previous value has been loaded into tmp
|
|
4075 pre_val = tmp;
|
|
4076 }
|
|
4077
|
|
4078 assert(pre_val != noreg, "must have a real register");
|
|
4079
|
|
4080 // Is the previous value null?
|
|
4081 cmp_and_brx_short(pre_val, G0, Assembler::equal, Assembler::pt, filtered);
|
|
4082
|
|
4083 // OK, it's not filtered, so we'll need to call enqueue. In the normal
|
|
4084 // case, pre_val will be a scratch G-reg, but there are some cases in
|
|
4085 // which it's an O-reg. In the first case, do a normal call. In the
|
|
4086 // latter, do a save here and call the frameless version.
|
|
4087
|
|
4088 guarantee(pre_val->is_global() || pre_val->is_out(),
|
|
4089 "Or we need to think harder.");
|
|
4090
|
|
4091 if (pre_val->is_global() && !preserve_o_regs) {
|
|
4092 generate_satb_log_enqueue_if_necessary(true); // with frame
|
|
4093
|
|
4094 call(satb_log_enqueue_with_frame);
|
|
4095 delayed()->mov(pre_val, O0);
|
|
4096 } else {
|
|
4097 generate_satb_log_enqueue_if_necessary(false); // frameless
|
|
4098
|
|
4099 save_frame(0);
|
|
4100 call(satb_log_enqueue_frameless);
|
|
4101 delayed()->mov(pre_val->after_save(), O0);
|
|
4102 restore();
|
|
4103 }
|
|
4104
|
|
4105 bind(filtered);
|
|
4106 }
|
|
4107
|
|
4108 static address dirty_card_log_enqueue = 0;
|
|
4109 static u_char* dirty_card_log_enqueue_end = 0;
|
|
4110
|
|
4111 // This gets to assume that o0 contains the object address.
|
|
4112 static void generate_dirty_card_log_enqueue(jbyte* byte_map_base) {
|
|
4113 BufferBlob* bb = BufferBlob::create("dirty_card_enqueue", EnqueueCodeSize*2);
|
|
4114 CodeBuffer buf(bb);
|
|
4115 MacroAssembler masm(&buf);
|
|
4116 #define __ masm.
|
|
4117 address start = __ pc();
|
|
4118
|
|
4119 Label not_already_dirty, restart, refill;
|
|
4120
|
|
4121 #ifdef _LP64
|
|
4122 __ srlx(O0, CardTableModRefBS::card_shift, O0);
|
|
4123 #else
|
|
4124 __ srl(O0, CardTableModRefBS::card_shift, O0);
|
|
4125 #endif
|
|
4126 AddressLiteral addrlit(byte_map_base);
|
|
4127 __ set(addrlit, O1); // O1 := <card table base>
|
|
4128 __ ldub(O0, O1, O2); // O2 := [O0 + O1]
|
|
4129
|
|
4130 assert(CardTableModRefBS::dirty_card_val() == 0, "otherwise check this code");
|
|
4131 __ cmp_and_br_short(O2, G0, Assembler::notEqual, Assembler::pt, not_already_dirty);
|
|
4132
|
|
4133 // We didn't take the branch, so we're already dirty: return.
|
|
4134 // Use return-from-leaf
|
|
4135 __ retl();
|
|
4136 __ delayed()->nop();
|
|
4137
|
|
4138 // Not dirty.
|
|
4139 __ bind(not_already_dirty);
|
|
4140
|
|
4141 // Get O0 + O1 into a reg by itself
|
|
4142 __ add(O0, O1, O3);
|
|
4143
|
|
4144 // First, dirty it.
|
|
4145 __ stb(G0, O3, G0); // [cardPtr] := 0 (i.e., dirty).
|
|
4146
|
|
4147 int dirty_card_q_index_byte_offset =
|
|
4148 in_bytes(JavaThread::dirty_card_queue_offset() +
|
|
4149 PtrQueue::byte_offset_of_index());
|
|
4150 int dirty_card_q_buf_byte_offset =
|
|
4151 in_bytes(JavaThread::dirty_card_queue_offset() +
|
|
4152 PtrQueue::byte_offset_of_buf());
|
|
4153 __ bind(restart);
|
|
4154
|
|
4155 // Load the index into the update buffer. PtrQueue::_index is
|
|
4156 // a size_t so ld_ptr is appropriate here.
|
|
4157 __ ld_ptr(G2_thread, dirty_card_q_index_byte_offset, L0);
|
|
4158
|
|
4159 // index == 0?
|
|
4160 __ cmp_and_brx_short(L0, G0, Assembler::equal, Assembler::pn, refill);
|
|
4161
|
|
4162 __ ld_ptr(G2_thread, dirty_card_q_buf_byte_offset, L1);
|
|
4163 __ sub(L0, oopSize, L0);
|
|
4164
|
|
4165 __ st_ptr(O3, L1, L0); // [_buf + index] := I0
|
|
4166 // Use return-from-leaf
|
|
4167 __ retl();
|
|
4168 __ delayed()->st_ptr(L0, G2_thread, dirty_card_q_index_byte_offset);
|
|
4169
|
|
4170 __ bind(refill);
|
|
4171 address handle_zero =
|
|
4172 CAST_FROM_FN_PTR(address,
|
|
4173 &DirtyCardQueueSet::handle_zero_index_for_thread);
|
|
4174 // This should be rare enough that we can afford to save all the
|
|
4175 // scratch registers that the calling context might be using.
|
|
4176 __ mov(G1_scratch, L3);
|
|
4177 __ mov(G3_scratch, L5);
|
|
4178 // We need the value of O3 above (for the write into the buffer), so we
|
|
4179 // save and restore it.
|
|
4180 __ mov(O3, L6);
|
|
4181 // Since the call will overwrite O7, we save and restore that, as well.
|
|
4182 __ mov(O7, L4);
|
|
4183
|
|
4184 __ call_VM_leaf(L7_thread_cache, handle_zero, G2_thread);
|
|
4185 __ mov(L3, G1_scratch);
|
|
4186 __ mov(L5, G3_scratch);
|
|
4187 __ mov(L6, O3);
|
|
4188 __ br(Assembler::always, /*annul*/false, Assembler::pt, restart);
|
|
4189 __ delayed()->mov(L4, O7);
|
|
4190
|
|
4191 dirty_card_log_enqueue = start;
|
|
4192 dirty_card_log_enqueue_end = __ pc();
|
|
4193 // XXX Should have a guarantee here about not going off the end!
|
|
4194 // Does it already do so? Do an experiment...
|
|
4195
|
|
4196 #undef __
|
|
4197
|
|
4198 }
|
|
4199
|
|
4200 static inline void
|
|
4201 generate_dirty_card_log_enqueue_if_necessary(jbyte* byte_map_base) {
|
|
4202 if (dirty_card_log_enqueue == 0) {
|
|
4203 generate_dirty_card_log_enqueue(byte_map_base);
|
|
4204 assert(dirty_card_log_enqueue != 0, "postcondition.");
|
|
4205 if (G1SATBPrintStubs) {
|
|
4206 tty->print_cr("Generated dirty_card enqueue:");
|
|
4207 Disassembler::decode((u_char*)dirty_card_log_enqueue,
|
|
4208 dirty_card_log_enqueue_end,
|
|
4209 tty);
|
|
4210 }
|
|
4211 }
|
|
4212 }
|
|
4213
|
|
4214
|
|
4215 void MacroAssembler::g1_write_barrier_post(Register store_addr, Register new_val, Register tmp) {
|
|
4216
|
|
4217 Label filtered;
|
|
4218 MacroAssembler* post_filter_masm = this;
|
|
4219
|
|
4220 if (new_val == G0) return;
|
|
4221
|
|
4222 G1SATBCardTableModRefBS* bs = (G1SATBCardTableModRefBS*) Universe::heap()->barrier_set();
|
|
4223 assert(bs->kind() == BarrierSet::G1SATBCT ||
|
|
4224 bs->kind() == BarrierSet::G1SATBCTLogging, "wrong barrier");
|
|
4225
|
|
4226 if (G1RSBarrierRegionFilter) {
|
|
4227 xor3(store_addr, new_val, tmp);
|
|
4228 #ifdef _LP64
|
|
4229 srlx(tmp, HeapRegion::LogOfHRGrainBytes, tmp);
|
|
4230 #else
|
|
4231 srl(tmp, HeapRegion::LogOfHRGrainBytes, tmp);
|
|
4232 #endif
|
|
4233
|
|
4234 // XXX Should I predict this taken or not? Does it matter?
|
|
4235 cmp_and_brx_short(tmp, G0, Assembler::equal, Assembler::pt, filtered);
|
|
4236 }
|
|
4237
|
|
4238 // If the "store_addr" register is an "in" or "local" register, move it to
|
|
4239 // a scratch reg so we can pass it as an argument.
|
|
4240 bool use_scr = !(store_addr->is_global() || store_addr->is_out());
|
|
4241 // Pick a scratch register different from "tmp".
|
|
4242 Register scr = (tmp == G1_scratch ? G3_scratch : G1_scratch);
|
|
4243 // Make sure we use up the delay slot!
|
|
4244 if (use_scr) {
|
|
4245 post_filter_masm->mov(store_addr, scr);
|
|
4246 } else {
|
|
4247 post_filter_masm->nop();
|
|
4248 }
|
|
4249 generate_dirty_card_log_enqueue_if_necessary(bs->byte_map_base);
|
|
4250 save_frame(0);
|
|
4251 call(dirty_card_log_enqueue);
|
|
4252 if (use_scr) {
|
|
4253 delayed()->mov(scr, O0);
|
|
4254 } else {
|
|
4255 delayed()->mov(store_addr->after_save(), O0);
|
|
4256 }
|
|
4257 restore();
|
|
4258
|
|
4259 bind(filtered);
|
|
4260 }
|
|
4261
|
|
4262 #endif // SERIALGC
|
|
4263 ///////////////////////////////////////////////////////////////////////////////////
|
|
4264
|
|
4265 void MacroAssembler::card_write_barrier_post(Register store_addr, Register new_val, Register tmp) {
|
|
4266 // If we're writing constant NULL, we can skip the write barrier.
|
|
4267 if (new_val == G0) return;
|
|
4268 CardTableModRefBS* bs = (CardTableModRefBS*) Universe::heap()->barrier_set();
|
|
4269 assert(bs->kind() == BarrierSet::CardTableModRef ||
|
|
4270 bs->kind() == BarrierSet::CardTableExtension, "wrong barrier");
|
|
4271 card_table_write(bs->byte_map_base, tmp, store_addr);
|
|
4272 }
|
|
4273
|
|
4274 void MacroAssembler::load_klass(Register src_oop, Register klass) {
|
|
4275 // The number of bytes in this code is used by
|
|
4276 // MachCallDynamicJavaNode::ret_addr_offset()
|
|
4277 // if this changes, change that.
|
|
4278 if (UseCompressedKlassPointers) {
|
|
4279 lduw(src_oop, oopDesc::klass_offset_in_bytes(), klass);
|
|
4280 decode_klass_not_null(klass);
|
|
4281 } else {
|
|
4282 ld_ptr(src_oop, oopDesc::klass_offset_in_bytes(), klass);
|
|
4283 }
|
|
4284 }
|
|
4285
|
|
4286 void MacroAssembler::store_klass(Register klass, Register dst_oop) {
|
|
4287 if (UseCompressedKlassPointers) {
|
|
4288 assert(dst_oop != klass, "not enough registers");
|
|
4289 encode_klass_not_null(klass);
|
|
4290 st(klass, dst_oop, oopDesc::klass_offset_in_bytes());
|
|
4291 } else {
|
|
4292 st_ptr(klass, dst_oop, oopDesc::klass_offset_in_bytes());
|
|
4293 }
|
|
4294 }
|
|
4295
|
|
4296 void MacroAssembler::store_klass_gap(Register s, Register d) {
|
|
4297 if (UseCompressedKlassPointers) {
|
|
4298 assert(s != d, "not enough registers");
|
|
4299 st(s, d, oopDesc::klass_gap_offset_in_bytes());
|
|
4300 }
|
|
4301 }
|
|
4302
|
|
4303 void MacroAssembler::load_heap_oop(const Address& s, Register d) {
|
|
4304 if (UseCompressedOops) {
|
|
4305 lduw(s, d);
|
|
4306 decode_heap_oop(d);
|
|
4307 } else {
|
|
4308 ld_ptr(s, d);
|
|
4309 }
|
|
4310 }
|
|
4311
|
|
4312 void MacroAssembler::load_heap_oop(Register s1, Register s2, Register d) {
|
|
4313 if (UseCompressedOops) {
|
|
4314 lduw(s1, s2, d);
|
|
4315 decode_heap_oop(d, d);
|
|
4316 } else {
|
|
4317 ld_ptr(s1, s2, d);
|
|
4318 }
|
|
4319 }
|
|
4320
|
|
4321 void MacroAssembler::load_heap_oop(Register s1, int simm13a, Register d) {
|
|
4322 if (UseCompressedOops) {
|
|
4323 lduw(s1, simm13a, d);
|
|
4324 decode_heap_oop(d, d);
|
|
4325 } else {
|
|
4326 ld_ptr(s1, simm13a, d);
|
|
4327 }
|
|
4328 }
|
|
4329
|
|
4330 void MacroAssembler::load_heap_oop(Register s1, RegisterOrConstant s2, Register d) {
|
|
4331 if (s2.is_constant()) load_heap_oop(s1, s2.as_constant(), d);
|
|
4332 else load_heap_oop(s1, s2.as_register(), d);
|
|
4333 }
|
|
4334
|
|
4335 void MacroAssembler::store_heap_oop(Register d, Register s1, Register s2) {
|
|
4336 if (UseCompressedOops) {
|
|
4337 assert(s1 != d && s2 != d, "not enough registers");
|
|
4338 encode_heap_oop(d);
|
|
4339 st(d, s1, s2);
|
|
4340 } else {
|
|
4341 st_ptr(d, s1, s2);
|
|
4342 }
|
|
4343 }
|
|
4344
|
|
4345 void MacroAssembler::store_heap_oop(Register d, Register s1, int simm13a) {
|
|
4346 if (UseCompressedOops) {
|
|
4347 assert(s1 != d, "not enough registers");
|
|
4348 encode_heap_oop(d);
|
|
4349 st(d, s1, simm13a);
|
|
4350 } else {
|
|
4351 st_ptr(d, s1, simm13a);
|
|
4352 }
|
|
4353 }
|
|
4354
|
|
4355 void MacroAssembler::store_heap_oop(Register d, const Address& a, int offset) {
|
|
4356 if (UseCompressedOops) {
|
|
4357 assert(a.base() != d, "not enough registers");
|
|
4358 encode_heap_oop(d);
|
|
4359 st(d, a, offset);
|
|
4360 } else {
|
|
4361 st_ptr(d, a, offset);
|
|
4362 }
|
|
4363 }
|
|
4364
|
|
4365
|
|
4366 void MacroAssembler::encode_heap_oop(Register src, Register dst) {
|
|
4367 assert (UseCompressedOops, "must be compressed");
|
|
4368 assert (Universe::heap() != NULL, "java heap should be initialized");
|
|
4369 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
|
|
4370 verify_oop(src);
|
|
4371 if (Universe::narrow_oop_base() == NULL) {
|
|
4372 srlx(src, LogMinObjAlignmentInBytes, dst);
|
|
4373 return;
|
|
4374 }
|
|
4375 Label done;
|
|
4376 if (src == dst) {
|
|
4377 // optimize for frequent case src == dst
|
|
4378 bpr(rc_nz, true, Assembler::pt, src, done);
|
|
4379 delayed() -> sub(src, G6_heapbase, dst); // annuled if not taken
|
|
4380 bind(done);
|
|
4381 srlx(src, LogMinObjAlignmentInBytes, dst);
|
|
4382 } else {
|
|
4383 bpr(rc_z, false, Assembler::pn, src, done);
|
|
4384 delayed() -> mov(G0, dst);
|
|
4385 // could be moved before branch, and annulate delay,
|
|
4386 // but may add some unneeded work decoding null
|
|
4387 sub(src, G6_heapbase, dst);
|
|
4388 srlx(dst, LogMinObjAlignmentInBytes, dst);
|
|
4389 bind(done);
|
|
4390 }
|
|
4391 }
|
|
4392
|
|
4393
|
|
4394 void MacroAssembler::encode_heap_oop_not_null(Register r) {
|
|
4395 assert (UseCompressedOops, "must be compressed");
|
|
4396 assert (Universe::heap() != NULL, "java heap should be initialized");
|
|
4397 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
|
|
4398 verify_oop(r);
|
|
4399 if (Universe::narrow_oop_base() != NULL)
|
|
4400 sub(r, G6_heapbase, r);
|
|
4401 srlx(r, LogMinObjAlignmentInBytes, r);
|
|
4402 }
|
|
4403
|
|
4404 void MacroAssembler::encode_heap_oop_not_null(Register src, Register dst) {
|
|
4405 assert (UseCompressedOops, "must be compressed");
|
|
4406 assert (Universe::heap() != NULL, "java heap should be initialized");
|
|
4407 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
|
|
4408 verify_oop(src);
|
|
4409 if (Universe::narrow_oop_base() == NULL) {
|
|
4410 srlx(src, LogMinObjAlignmentInBytes, dst);
|
|
4411 } else {
|
|
4412 sub(src, G6_heapbase, dst);
|
|
4413 srlx(dst, LogMinObjAlignmentInBytes, dst);
|
|
4414 }
|
|
4415 }
|
|
4416
|
|
4417 // Same algorithm as oops.inline.hpp decode_heap_oop.
|
|
4418 void MacroAssembler::decode_heap_oop(Register src, Register dst) {
|
|
4419 assert (UseCompressedOops, "must be compressed");
|
|
4420 assert (Universe::heap() != NULL, "java heap should be initialized");
|
|
4421 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
|
|
4422 sllx(src, LogMinObjAlignmentInBytes, dst);
|
|
4423 if (Universe::narrow_oop_base() != NULL) {
|
|
4424 Label done;
|
|
4425 bpr(rc_nz, true, Assembler::pt, dst, done);
|
|
4426 delayed() -> add(dst, G6_heapbase, dst); // annuled if not taken
|
|
4427 bind(done);
|
|
4428 }
|
|
4429 verify_oop(dst);
|
|
4430 }
|
|
4431
|
|
4432 void MacroAssembler::decode_heap_oop_not_null(Register r) {
|
|
4433 // Do not add assert code to this unless you change vtableStubs_sparc.cpp
|
|
4434 // pd_code_size_limit.
|
|
4435 // Also do not verify_oop as this is called by verify_oop.
|
|
4436 assert (UseCompressedOops, "must be compressed");
|
|
4437 assert (Universe::heap() != NULL, "java heap should be initialized");
|
|
4438 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
|
|
4439 sllx(r, LogMinObjAlignmentInBytes, r);
|
|
4440 if (Universe::narrow_oop_base() != NULL)
|
|
4441 add(r, G6_heapbase, r);
|
|
4442 }
|
|
4443
|
|
4444 void MacroAssembler::decode_heap_oop_not_null(Register src, Register dst) {
|
|
4445 // Do not add assert code to this unless you change vtableStubs_sparc.cpp
|
|
4446 // pd_code_size_limit.
|
|
4447 // Also do not verify_oop as this is called by verify_oop.
|
|
4448 assert (UseCompressedOops, "must be compressed");
|
|
4449 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
|
|
4450 sllx(src, LogMinObjAlignmentInBytes, dst);
|
|
4451 if (Universe::narrow_oop_base() != NULL)
|
|
4452 add(dst, G6_heapbase, dst);
|
|
4453 }
|
|
4454
|
|
4455 void MacroAssembler::encode_klass_not_null(Register r) {
|
|
4456 assert(Metaspace::is_initialized(), "metaspace should be initialized");
|
|
4457 assert (UseCompressedKlassPointers, "must be compressed");
|
|
4458 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
|
|
4459 if (Universe::narrow_klass_base() != NULL)
|
|
4460 sub(r, G6_heapbase, r);
|
|
4461 srlx(r, LogKlassAlignmentInBytes, r);
|
|
4462 }
|
|
4463
|
|
4464 void MacroAssembler::encode_klass_not_null(Register src, Register dst) {
|
|
4465 assert(Metaspace::is_initialized(), "metaspace should be initialized");
|
|
4466 assert (UseCompressedKlassPointers, "must be compressed");
|
|
4467 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
|
|
4468 if (Universe::narrow_klass_base() == NULL) {
|
|
4469 srlx(src, LogKlassAlignmentInBytes, dst);
|
|
4470 } else {
|
|
4471 sub(src, G6_heapbase, dst);
|
|
4472 srlx(dst, LogKlassAlignmentInBytes, dst);
|
|
4473 }
|
|
4474 }
|
|
4475
|
|
4476 void MacroAssembler::decode_klass_not_null(Register r) {
|
|
4477 assert(Metaspace::is_initialized(), "metaspace should be initialized");
|
|
4478 // Do not add assert code to this unless you change vtableStubs_sparc.cpp
|
|
4479 // pd_code_size_limit.
|
|
4480 assert (UseCompressedKlassPointers, "must be compressed");
|
|
4481 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
|
|
4482 sllx(r, LogKlassAlignmentInBytes, r);
|
|
4483 if (Universe::narrow_klass_base() != NULL)
|
|
4484 add(r, G6_heapbase, r);
|
|
4485 }
|
|
4486
|
|
4487 void MacroAssembler::decode_klass_not_null(Register src, Register dst) {
|
|
4488 assert(Metaspace::is_initialized(), "metaspace should be initialized");
|
|
4489 // Do not add assert code to this unless you change vtableStubs_sparc.cpp
|
|
4490 // pd_code_size_limit.
|
|
4491 assert (UseCompressedKlassPointers, "must be compressed");
|
|
4492 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
|
|
4493 sllx(src, LogKlassAlignmentInBytes, dst);
|
|
4494 if (Universe::narrow_klass_base() != NULL)
|
|
4495 add(dst, G6_heapbase, dst);
|
|
4496 }
|
|
4497
|
|
4498 void MacroAssembler::reinit_heapbase() {
|
|
4499 if (UseCompressedOops || UseCompressedKlassPointers) {
|
|
4500 AddressLiteral base(Universe::narrow_ptrs_base_addr());
|
|
4501 load_ptr_contents(base, G6_heapbase);
|
|
4502 }
|
|
4503 }
|
|
4504
|
|
4505 // Compare char[] arrays aligned to 4 bytes.
|
|
4506 void MacroAssembler::char_arrays_equals(Register ary1, Register ary2,
|
|
4507 Register limit, Register result,
|
|
4508 Register chr1, Register chr2, Label& Ldone) {
|
|
4509 Label Lvector, Lloop;
|
|
4510 assert(chr1 == result, "should be the same");
|
|
4511
|
|
4512 // Note: limit contains number of bytes (2*char_elements) != 0.
|
|
4513 andcc(limit, 0x2, chr1); // trailing character ?
|
|
4514 br(Assembler::zero, false, Assembler::pt, Lvector);
|
|
4515 delayed()->nop();
|
|
4516
|
|
4517 // compare the trailing char
|
|
4518 sub(limit, sizeof(jchar), limit);
|
|
4519 lduh(ary1, limit, chr1);
|
|
4520 lduh(ary2, limit, chr2);
|
|
4521 cmp(chr1, chr2);
|
|
4522 br(Assembler::notEqual, true, Assembler::pt, Ldone);
|
|
4523 delayed()->mov(G0, result); // not equal
|
|
4524
|
|
4525 // only one char ?
|
|
4526 cmp_zero_and_br(zero, limit, Ldone, true, Assembler::pn);
|
|
4527 delayed()->add(G0, 1, result); // zero-length arrays are equal
|
|
4528
|
|
4529 // word by word compare, dont't need alignment check
|
|
4530 bind(Lvector);
|
|
4531 // Shift ary1 and ary2 to the end of the arrays, negate limit
|
|
4532 add(ary1, limit, ary1);
|
|
4533 add(ary2, limit, ary2);
|
|
4534 neg(limit, limit);
|
|
4535
|
|
4536 lduw(ary1, limit, chr1);
|
|
4537 bind(Lloop);
|
|
4538 lduw(ary2, limit, chr2);
|
|
4539 cmp(chr1, chr2);
|
|
4540 br(Assembler::notEqual, true, Assembler::pt, Ldone);
|
|
4541 delayed()->mov(G0, result); // not equal
|
|
4542 inccc(limit, 2*sizeof(jchar));
|
|
4543 // annul LDUW if branch is not taken to prevent access past end of array
|
|
4544 br(Assembler::notZero, true, Assembler::pt, Lloop);
|
|
4545 delayed()->lduw(ary1, limit, chr1); // hoisted
|
|
4546
|
|
4547 // Caller should set it:
|
|
4548 // add(G0, 1, result); // equals
|
|
4549 }
|
|
4550
|
|
4551 // Use BIS for zeroing (count is in bytes).
|
|
4552 void MacroAssembler::bis_zeroing(Register to, Register count, Register temp, Label& Ldone) {
|
|
4553 assert(UseBlockZeroing && VM_Version::has_block_zeroing(), "only works with BIS zeroing");
|
|
4554 Register end = count;
|
|
4555 int cache_line_size = VM_Version::prefetch_data_size();
|
|
4556 // Minimum count when BIS zeroing can be used since
|
|
4557 // it needs membar which is expensive.
|
|
4558 int block_zero_size = MAX2(cache_line_size*3, (int)BlockZeroingLowLimit);
|
|
4559
|
|
4560 Label small_loop;
|
|
4561 // Check if count is negative (dead code) or zero.
|
|
4562 // Note, count uses 64bit in 64 bit VM.
|
|
4563 cmp_and_brx_short(count, 0, Assembler::lessEqual, Assembler::pn, Ldone);
|
|
4564
|
|
4565 // Use BIS zeroing only for big arrays since it requires membar.
|
|
4566 if (Assembler::is_simm13(block_zero_size)) { // < 4096
|
|
4567 cmp(count, block_zero_size);
|
|
4568 } else {
|
|
4569 set(block_zero_size, temp);
|
|
4570 cmp(count, temp);
|
|
4571 }
|
|
4572 br(Assembler::lessUnsigned, false, Assembler::pt, small_loop);
|
|
4573 delayed()->add(to, count, end);
|
|
4574
|
|
4575 // Note: size is >= three (32 bytes) cache lines.
|
|
4576
|
|
4577 // Clean the beginning of space up to next cache line.
|
|
4578 for (int offs = 0; offs < cache_line_size; offs += 8) {
|
|
4579 stx(G0, to, offs);
|
|
4580 }
|
|
4581
|
|
4582 // align to next cache line
|
|
4583 add(to, cache_line_size, to);
|
|
4584 and3(to, -cache_line_size, to);
|
|
4585
|
|
4586 // Note: size left >= two (32 bytes) cache lines.
|
|
4587
|
|
4588 // BIS should not be used to zero tail (64 bytes)
|
|
4589 // to avoid zeroing a header of the following object.
|
|
4590 sub(end, (cache_line_size*2)-8, end);
|
|
4591
|
|
4592 Label bis_loop;
|
|
4593 bind(bis_loop);
|
|
4594 stxa(G0, to, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
|
|
4595 add(to, cache_line_size, to);
|
|
4596 cmp_and_brx_short(to, end, Assembler::lessUnsigned, Assembler::pt, bis_loop);
|
|
4597
|
|
4598 // BIS needs membar.
|
|
4599 membar(Assembler::StoreLoad);
|
|
4600
|
|
4601 add(end, (cache_line_size*2)-8, end); // restore end
|
|
4602 cmp_and_brx_short(to, end, Assembler::greaterEqualUnsigned, Assembler::pn, Ldone);
|
|
4603
|
|
4604 // Clean the tail.
|
|
4605 bind(small_loop);
|
|
4606 stx(G0, to, 0);
|
|
4607 add(to, 8, to);
|
|
4608 cmp_and_brx_short(to, end, Assembler::lessUnsigned, Assembler::pt, small_loop);
|
|
4609 nop(); // Separate short branches
|
|
4610 }
|