Mercurial > hg > truffle
annotate src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp @ 2480:4b95bbb36464
7035870: JSR 292: Zero support
Summary: This adds support for JSR 292 to Zero.
Reviewed-by: twisti
Contributed-by: Gary Benson <gbenson@redhat.com>
author | twisti |
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date | Tue, 12 Apr 2011 02:40:23 -0700 |
parents | bb22629531fa |
children | 3d42f82cd811 |
rev | line source |
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0 | 1 /* |
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2 * Copyright (c) 2000, 2011, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
26 #include "c1/c1_Compilation.hpp" | |
27 #include "c1/c1_LIRAssembler.hpp" | |
28 #include "c1/c1_MacroAssembler.hpp" | |
29 #include "c1/c1_Runtime1.hpp" | |
30 #include "c1/c1_ValueStack.hpp" | |
31 #include "ci/ciArrayKlass.hpp" | |
32 #include "ci/ciInstance.hpp" | |
33 #include "gc_interface/collectedHeap.hpp" | |
34 #include "memory/barrierSet.hpp" | |
35 #include "memory/cardTableModRefBS.hpp" | |
36 #include "nativeInst_sparc.hpp" | |
37 #include "oops/objArrayKlass.hpp" | |
38 #include "runtime/sharedRuntime.hpp" | |
0 | 39 |
40 #define __ _masm-> | |
41 | |
42 | |
43 //------------------------------------------------------------ | |
44 | |
45 | |
46 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { | |
47 if (opr->is_constant()) { | |
48 LIR_Const* constant = opr->as_constant_ptr(); | |
49 switch (constant->type()) { | |
50 case T_INT: { | |
51 jint value = constant->as_jint(); | |
52 return Assembler::is_simm13(value); | |
53 } | |
54 | |
55 default: | |
56 return false; | |
57 } | |
58 } | |
59 return false; | |
60 } | |
61 | |
62 | |
63 bool LIR_Assembler::is_single_instruction(LIR_Op* op) { | |
64 switch (op->code()) { | |
65 case lir_null_check: | |
66 return true; | |
67 | |
68 | |
69 case lir_add: | |
70 case lir_ushr: | |
71 case lir_shr: | |
72 case lir_shl: | |
73 // integer shifts and adds are always one instruction | |
74 return op->result_opr()->is_single_cpu(); | |
75 | |
76 | |
77 case lir_move: { | |
78 LIR_Op1* op1 = op->as_Op1(); | |
79 LIR_Opr src = op1->in_opr(); | |
80 LIR_Opr dst = op1->result_opr(); | |
81 | |
82 if (src == dst) { | |
83 NEEDS_CLEANUP; | |
84 // this works around a problem where moves with the same src and dst | |
85 // end up in the delay slot and then the assembler swallows the mov | |
86 // since it has no effect and then it complains because the delay slot | |
87 // is empty. returning false stops the optimizer from putting this in | |
88 // the delay slot | |
89 return false; | |
90 } | |
91 | |
92 // don't put moves involving oops into the delay slot since the VerifyOops code | |
93 // will make it much larger than a single instruction. | |
94 if (VerifyOops) { | |
95 return false; | |
96 } | |
97 | |
98 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none || | |
99 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) { | |
100 return false; | |
101 } | |
102 | |
2002 | 103 if (UseCompressedOops) { |
104 if (dst->is_address() && !dst->is_stack() && (dst->type() == T_OBJECT || dst->type() == T_ARRAY)) return false; | |
105 if (src->is_address() && !src->is_stack() && (src->type() == T_OBJECT || src->type() == T_ARRAY)) return false; | |
106 } | |
107 | |
0 | 108 if (dst->is_register()) { |
109 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) { | |
110 return !PatchALot; | |
111 } else if (src->is_single_stack()) { | |
112 return true; | |
113 } | |
114 } | |
115 | |
116 if (src->is_register()) { | |
117 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) { | |
118 return !PatchALot; | |
119 } else if (dst->is_single_stack()) { | |
120 return true; | |
121 } | |
122 } | |
123 | |
124 if (dst->is_register() && | |
125 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) || | |
126 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) { | |
127 return true; | |
128 } | |
129 | |
130 return false; | |
131 } | |
132 | |
133 default: | |
134 return false; | |
135 } | |
136 ShouldNotReachHere(); | |
137 } | |
138 | |
139 | |
140 LIR_Opr LIR_Assembler::receiverOpr() { | |
141 return FrameMap::O0_oop_opr; | |
142 } | |
143 | |
144 | |
145 LIR_Opr LIR_Assembler::incomingReceiverOpr() { | |
146 return FrameMap::I0_oop_opr; | |
147 } | |
148 | |
149 | |
150 LIR_Opr LIR_Assembler::osrBufferPointer() { | |
151 return FrameMap::I0_opr; | |
152 } | |
153 | |
154 | |
155 int LIR_Assembler::initial_frame_size_in_bytes() { | |
156 return in_bytes(frame_map()->framesize_in_bytes()); | |
157 } | |
158 | |
159 | |
160 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5); | |
161 // we fetch the class of the receiver (O0) and compare it with the cached class. | |
162 // If they do not match we jump to slow case. | |
163 int LIR_Assembler::check_icache() { | |
164 int offset = __ offset(); | |
165 __ inline_cache_check(O0, G5_inline_cache_reg); | |
166 return offset; | |
167 } | |
168 | |
169 | |
170 void LIR_Assembler::osr_entry() { | |
171 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp): | |
172 // | |
173 // 1. Create a new compiled activation. | |
174 // 2. Initialize local variables in the compiled activation. The expression stack must be empty | |
175 // at the osr_bci; it is not initialized. | |
176 // 3. Jump to the continuation address in compiled code to resume execution. | |
177 | |
178 // OSR entry point | |
179 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); | |
180 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); | |
181 ValueStack* entry_state = osr_entry->end()->state(); | |
182 int number_of_locks = entry_state->locks_size(); | |
183 | |
184 // Create a frame for the compiled activation. | |
185 __ build_frame(initial_frame_size_in_bytes()); | |
186 | |
187 // OSR buffer is | |
188 // | |
189 // locals[nlocals-1..0] | |
190 // monitors[number_of_locks-1..0] | |
191 // | |
192 // locals is a direct copy of the interpreter frame so in the osr buffer | |
193 // so first slot in the local array is the last local from the interpreter | |
194 // and last slot is local[0] (receiver) from the interpreter | |
195 // | |
196 // Similarly with locks. The first lock slot in the osr buffer is the nth lock | |
197 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock | |
198 // in the interpreter frame (the method lock if a sync method) | |
199 | |
200 // Initialize monitors in the compiled activation. | |
201 // I0: pointer to osr buffer | |
202 // | |
203 // All other registers are dead at this point and the locals will be | |
204 // copied into place by code emitted in the IR. | |
205 | |
206 Register OSR_buf = osrBufferPointer()->as_register(); | |
207 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); | |
208 int monitor_offset = BytesPerWord * method()->max_locals() + | |
1060 | 209 (2 * BytesPerWord) * (number_of_locks - 1); |
210 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in | |
211 // the OSR buffer using 2 word entries: first the lock and then | |
212 // the oop. | |
0 | 213 for (int i = 0; i < number_of_locks; i++) { |
1060 | 214 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); |
0 | 215 #ifdef ASSERT |
216 // verify the interpreter's monitor has a non-null object | |
217 { | |
218 Label L; | |
1060 | 219 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7); |
0 | 220 __ cmp(G0, O7); |
221 __ br(Assembler::notEqual, false, Assembler::pt, L); | |
222 __ delayed()->nop(); | |
223 __ stop("locked object is NULL"); | |
224 __ bind(L); | |
225 } | |
226 #endif // ASSERT | |
227 // Copy the lock field into the compiled activation. | |
1060 | 228 __ ld_ptr(OSR_buf, slot_offset + 0, O7); |
0 | 229 __ st_ptr(O7, frame_map()->address_for_monitor_lock(i)); |
1060 | 230 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7); |
0 | 231 __ st_ptr(O7, frame_map()->address_for_monitor_object(i)); |
232 } | |
233 } | |
234 } | |
235 | |
236 | |
237 // Optimized Library calls | |
238 // This is the fast version of java.lang.String.compare; it has not | |
239 // OSR-entry and therefore, we generate a slow version for OSR's | |
240 void LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info) { | |
241 Register str0 = left->as_register(); | |
242 Register str1 = right->as_register(); | |
243 | |
244 Label Ldone; | |
245 | |
246 Register result = dst->as_register(); | |
247 { | |
248 // Get a pointer to the first character of string0 in tmp0 and get string0.count in str0 | |
249 // Get a pointer to the first character of string1 in tmp1 and get string1.count in str1 | |
250 // Also, get string0.count-string1.count in o7 and get the condition code set | |
251 // Note: some instructions have been hoisted for better instruction scheduling | |
252 | |
253 Register tmp0 = L0; | |
254 Register tmp1 = L1; | |
255 Register tmp2 = L2; | |
256 | |
257 int value_offset = java_lang_String:: value_offset_in_bytes(); // char array | |
258 int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position | |
259 int count_offset = java_lang_String:: count_offset_in_bytes(); | |
260 | |
2002 | 261 __ load_heap_oop(str0, value_offset, tmp0); |
727 | 262 __ ld(str0, offset_offset, tmp2); |
0 | 263 __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0); |
727 | 264 __ ld(str0, count_offset, str0); |
0 | 265 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2); |
266 | |
267 // str1 may be null | |
268 add_debug_info_for_null_check_here(info); | |
269 | |
2002 | 270 __ load_heap_oop(str1, value_offset, tmp1); |
0 | 271 __ add(tmp0, tmp2, tmp0); |
272 | |
727 | 273 __ ld(str1, offset_offset, tmp2); |
0 | 274 __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1); |
727 | 275 __ ld(str1, count_offset, str1); |
0 | 276 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2); |
277 __ subcc(str0, str1, O7); | |
278 __ add(tmp1, tmp2, tmp1); | |
279 } | |
280 | |
281 { | |
282 // Compute the minimum of the string lengths, scale it and store it in limit | |
283 Register count0 = I0; | |
284 Register count1 = I1; | |
285 Register limit = L3; | |
286 | |
287 Label Lskip; | |
288 __ sll(count0, exact_log2(sizeof(jchar)), limit); // string0 is shorter | |
289 __ br(Assembler::greater, true, Assembler::pt, Lskip); | |
290 __ delayed()->sll(count1, exact_log2(sizeof(jchar)), limit); // string1 is shorter | |
291 __ bind(Lskip); | |
292 | |
293 // If either string is empty (or both of them) the result is the difference in lengths | |
294 __ cmp(limit, 0); | |
295 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
296 __ delayed()->mov(O7, result); // result is difference in lengths | |
297 } | |
298 | |
299 { | |
300 // Neither string is empty | |
301 Label Lloop; | |
302 | |
303 Register base0 = L0; | |
304 Register base1 = L1; | |
305 Register chr0 = I0; | |
306 Register chr1 = I1; | |
307 Register limit = L3; | |
308 | |
309 // Shift base0 and base1 to the end of the arrays, negate limit | |
310 __ add(base0, limit, base0); | |
311 __ add(base1, limit, base1); | |
312 __ neg(limit); // limit = -min{string0.count, strin1.count} | |
313 | |
314 __ lduh(base0, limit, chr0); | |
315 __ bind(Lloop); | |
316 __ lduh(base1, limit, chr1); | |
317 __ subcc(chr0, chr1, chr0); | |
318 __ br(Assembler::notZero, false, Assembler::pn, Ldone); | |
319 assert(chr0 == result, "result must be pre-placed"); | |
320 __ delayed()->inccc(limit, sizeof(jchar)); | |
321 __ br(Assembler::notZero, true, Assembler::pt, Lloop); | |
322 __ delayed()->lduh(base0, limit, chr0); | |
323 } | |
324 | |
325 // If strings are equal up to min length, return the length difference. | |
326 __ mov(O7, result); | |
327 | |
328 // Otherwise, return the difference between the first mismatched chars. | |
329 __ bind(Ldone); | |
330 } | |
331 | |
332 | |
333 // -------------------------------------------------------------------------------------------- | |
334 | |
335 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) { | |
336 if (!GenerateSynchronizationCode) return; | |
337 | |
338 Register obj_reg = obj_opr->as_register(); | |
339 Register lock_reg = lock_opr->as_register(); | |
340 | |
341 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no); | |
342 Register reg = mon_addr.base(); | |
343 int offset = mon_addr.disp(); | |
344 // compute pointer to BasicLock | |
345 if (mon_addr.is_simm13()) { | |
346 __ add(reg, offset, lock_reg); | |
347 } | |
348 else { | |
349 __ set(offset, lock_reg); | |
350 __ add(reg, lock_reg, lock_reg); | |
351 } | |
352 // unlock object | |
353 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no); | |
354 // _slow_case_stubs->append(slow_case); | |
355 // temporary fix: must be created after exceptionhandler, therefore as call stub | |
356 _slow_case_stubs->append(slow_case); | |
357 if (UseFastLocking) { | |
358 // try inlined fast unlocking first, revert to slow locking if it fails | |
359 // note: lock_reg points to the displaced header since the displaced header offset is 0! | |
360 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
361 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry()); | |
362 } else { | |
363 // always do slow unlocking | |
364 // note: the slow unlocking code could be inlined here, however if we use | |
365 // slow unlocking, speed doesn't matter anyway and this solution is | |
366 // simpler and requires less duplicated code - additionally, the | |
367 // slow unlocking code is the same in either case which simplifies | |
368 // debugging | |
369 __ br(Assembler::always, false, Assembler::pt, *slow_case->entry()); | |
370 __ delayed()->nop(); | |
371 } | |
372 // done | |
373 __ bind(*slow_case->continuation()); | |
374 } | |
375 | |
376 | |
1204 | 377 int LIR_Assembler::emit_exception_handler() { |
0 | 378 // if the last instruction is a call (typically to do a throw which |
379 // is coming at the end after block reordering) the return address | |
380 // must still point into the code area in order to avoid assertion | |
381 // failures when searching for the corresponding bci => add a nop | |
382 // (was bug 5/14/1999 - gri) | |
383 __ nop(); | |
384 | |
385 // generate code for exception handler | |
386 ciMethod* method = compilation()->method(); | |
387 | |
388 address handler_base = __ start_a_stub(exception_handler_size); | |
389 | |
390 if (handler_base == NULL) { | |
391 // not enough space left for the handler | |
392 bailout("exception handler overflow"); | |
1204 | 393 return -1; |
0 | 394 } |
1204 | 395 |
0 | 396 int offset = code_offset(); |
397 | |
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398 __ call(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id), relocInfo::runtime_call_type); |
0 | 399 __ delayed()->nop(); |
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400 __ should_not_reach_here(); |
0 | 401 assert(code_offset() - offset <= exception_handler_size, "overflow"); |
402 __ end_a_stub(); | |
1204 | 403 |
404 return offset; | |
0 | 405 } |
406 | |
1204 | 407 |
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408 // Emit the code to remove the frame from the stack in the exception |
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409 // unwind path. |
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410 int LIR_Assembler::emit_unwind_handler() { |
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411 #ifndef PRODUCT |
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412 if (CommentedAssembly) { |
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413 _masm->block_comment("Unwind handler"); |
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414 } |
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415 #endif |
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416 |
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417 int offset = code_offset(); |
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418 |
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419 // Fetch the exception from TLS and clear out exception related thread state |
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420 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), O0); |
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421 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset())); |
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422 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset())); |
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423 |
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424 __ bind(_unwind_handler_entry); |
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425 __ verify_not_null_oop(O0); |
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426 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { |
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427 __ mov(O0, I0); // Preserve the exception |
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428 } |
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429 |
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430 // Preform needed unlocking |
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431 MonitorExitStub* stub = NULL; |
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432 if (method()->is_synchronized()) { |
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433 monitor_address(0, FrameMap::I1_opr); |
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434 stub = new MonitorExitStub(FrameMap::I1_opr, true, 0); |
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435 __ unlock_object(I3, I2, I1, *stub->entry()); |
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436 __ bind(*stub->continuation()); |
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437 } |
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438 |
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439 if (compilation()->env()->dtrace_method_probes()) { |
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440 __ mov(G2_thread, O0); |
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441 jobject2reg(method()->constant_encoding(), O1); |
1378
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442 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), relocInfo::runtime_call_type); |
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443 __ delayed()->nop(); |
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444 } |
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445 |
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446 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { |
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447 __ mov(I0, O0); // Restore the exception |
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448 } |
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449 |
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450 // dispatch to the unwind logic |
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451 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type); |
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452 __ delayed()->nop(); |
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453 |
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454 // Emit the slow path assembly |
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455 if (stub != NULL) { |
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456 stub->emit_code(this); |
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457 } |
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458 |
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459 return offset; |
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460 } |
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461 |
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462 |
1204 | 463 int LIR_Assembler::emit_deopt_handler() { |
0 | 464 // if the last instruction is a call (typically to do a throw which |
465 // is coming at the end after block reordering) the return address | |
466 // must still point into the code area in order to avoid assertion | |
467 // failures when searching for the corresponding bci => add a nop | |
468 // (was bug 5/14/1999 - gri) | |
469 __ nop(); | |
470 | |
471 // generate code for deopt handler | |
472 ciMethod* method = compilation()->method(); | |
473 address handler_base = __ start_a_stub(deopt_handler_size); | |
474 if (handler_base == NULL) { | |
475 // not enough space left for the handler | |
476 bailout("deopt handler overflow"); | |
1204 | 477 return -1; |
0 | 478 } |
1204 | 479 |
0 | 480 int offset = code_offset(); |
727 | 481 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); |
482 __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp | |
0 | 483 __ delayed()->nop(); |
484 assert(code_offset() - offset <= deopt_handler_size, "overflow"); | |
485 debug_only(__ stop("should have gone to the caller");) | |
486 __ end_a_stub(); | |
1204 | 487 |
488 return offset; | |
0 | 489 } |
490 | |
491 | |
492 void LIR_Assembler::jobject2reg(jobject o, Register reg) { | |
493 if (o == NULL) { | |
494 __ set(NULL_WORD, reg); | |
495 } else { | |
496 int oop_index = __ oop_recorder()->find_index(o); | |
497 RelocationHolder rspec = oop_Relocation::spec(oop_index); | |
498 __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created | |
499 } | |
500 } | |
501 | |
502 | |
503 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) { | |
504 // Allocate a new index in oop table to hold the oop once it's been patched | |
505 int oop_index = __ oop_recorder()->allocate_index((jobject)NULL); | |
506 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, oop_index); | |
507 | |
727 | 508 AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index)); |
509 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc"); | |
0 | 510 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the |
511 // NULL will be dynamically patched later and the patched value may be large. We must | |
512 // therefore generate the sethi/add as a placeholders | |
727 | 513 __ patchable_set(addrlit, reg); |
0 | 514 |
515 patching_epilog(patch, lir_patch_normal, reg, info); | |
516 } | |
517 | |
518 | |
519 void LIR_Assembler::emit_op3(LIR_Op3* op) { | |
520 Register Rdividend = op->in_opr1()->as_register(); | |
521 Register Rdivisor = noreg; | |
522 Register Rscratch = op->in_opr3()->as_register(); | |
523 Register Rresult = op->result_opr()->as_register(); | |
524 int divisor = -1; | |
525 | |
526 if (op->in_opr2()->is_register()) { | |
527 Rdivisor = op->in_opr2()->as_register(); | |
528 } else { | |
529 divisor = op->in_opr2()->as_constant_ptr()->as_jint(); | |
530 assert(Assembler::is_simm13(divisor), "can only handle simm13"); | |
531 } | |
532 | |
533 assert(Rdividend != Rscratch, ""); | |
534 assert(Rdivisor != Rscratch, ""); | |
535 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv"); | |
536 | |
537 if (Rdivisor == noreg && is_power_of_2(divisor)) { | |
538 // convert division by a power of two into some shifts and logical operations | |
539 if (op->code() == lir_idiv) { | |
540 if (divisor == 2) { | |
541 __ srl(Rdividend, 31, Rscratch); | |
542 } else { | |
543 __ sra(Rdividend, 31, Rscratch); | |
544 __ and3(Rscratch, divisor - 1, Rscratch); | |
545 } | |
546 __ add(Rdividend, Rscratch, Rscratch); | |
547 __ sra(Rscratch, log2_intptr(divisor), Rresult); | |
548 return; | |
549 } else { | |
550 if (divisor == 2) { | |
551 __ srl(Rdividend, 31, Rscratch); | |
552 } else { | |
553 __ sra(Rdividend, 31, Rscratch); | |
554 __ and3(Rscratch, divisor - 1,Rscratch); | |
555 } | |
556 __ add(Rdividend, Rscratch, Rscratch); | |
557 __ andn(Rscratch, divisor - 1,Rscratch); | |
558 __ sub(Rdividend, Rscratch, Rresult); | |
559 return; | |
560 } | |
561 } | |
562 | |
563 __ sra(Rdividend, 31, Rscratch); | |
564 __ wry(Rscratch); | |
565 if (!VM_Version::v9_instructions_work()) { | |
566 // v9 doesn't require these nops | |
567 __ nop(); | |
568 __ nop(); | |
569 __ nop(); | |
570 __ nop(); | |
571 } | |
572 | |
573 add_debug_info_for_div0_here(op->info()); | |
574 | |
575 if (Rdivisor != noreg) { | |
576 __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch)); | |
577 } else { | |
578 assert(Assembler::is_simm13(divisor), "can only handle simm13"); | |
579 __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch)); | |
580 } | |
581 | |
582 Label skip; | |
583 __ br(Assembler::overflowSet, true, Assembler::pn, skip); | |
584 __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch)); | |
585 __ bind(skip); | |
586 | |
587 if (op->code() == lir_irem) { | |
588 if (Rdivisor != noreg) { | |
589 __ smul(Rscratch, Rdivisor, Rscratch); | |
590 } else { | |
591 __ smul(Rscratch, divisor, Rscratch); | |
592 } | |
593 __ sub(Rdividend, Rscratch, Rresult); | |
594 } | |
595 } | |
596 | |
597 | |
598 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { | |
599 #ifdef ASSERT | |
600 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); | |
601 if (op->block() != NULL) _branch_target_blocks.append(op->block()); | |
602 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); | |
603 #endif | |
604 assert(op->info() == NULL, "shouldn't have CodeEmitInfo"); | |
605 | |
606 if (op->cond() == lir_cond_always) { | |
607 __ br(Assembler::always, false, Assembler::pt, *(op->label())); | |
608 } else if (op->code() == lir_cond_float_branch) { | |
609 assert(op->ublock() != NULL, "must have unordered successor"); | |
610 bool is_unordered = (op->ublock() == op->block()); | |
611 Assembler::Condition acond; | |
612 switch (op->cond()) { | |
613 case lir_cond_equal: acond = Assembler::f_equal; break; | |
614 case lir_cond_notEqual: acond = Assembler::f_notEqual; break; | |
615 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break; | |
616 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break; | |
617 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break; | |
618 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break; | |
619 default : ShouldNotReachHere(); | |
620 }; | |
621 | |
622 if (!VM_Version::v9_instructions_work()) { | |
623 __ nop(); | |
624 } | |
625 __ fb( acond, false, Assembler::pn, *(op->label())); | |
626 } else { | |
627 assert (op->code() == lir_branch, "just checking"); | |
628 | |
629 Assembler::Condition acond; | |
630 switch (op->cond()) { | |
631 case lir_cond_equal: acond = Assembler::equal; break; | |
632 case lir_cond_notEqual: acond = Assembler::notEqual; break; | |
633 case lir_cond_less: acond = Assembler::less; break; | |
634 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; | |
635 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break; | |
636 case lir_cond_greater: acond = Assembler::greater; break; | |
637 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break; | |
638 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break; | |
639 default: ShouldNotReachHere(); | |
640 }; | |
641 | |
642 // sparc has different condition codes for testing 32-bit | |
643 // vs. 64-bit values. We could always test xcc is we could | |
644 // guarantee that 32-bit loads always sign extended but that isn't | |
645 // true and since sign extension isn't free, it would impose a | |
646 // slight cost. | |
647 #ifdef _LP64 | |
648 if (op->type() == T_INT) { | |
649 __ br(acond, false, Assembler::pn, *(op->label())); | |
650 } else | |
651 #endif | |
652 __ brx(acond, false, Assembler::pn, *(op->label())); | |
653 } | |
654 // The peephole pass fills the delay slot | |
655 } | |
656 | |
657 | |
658 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { | |
659 Bytecodes::Code code = op->bytecode(); | |
660 LIR_Opr dst = op->result_opr(); | |
661 | |
662 switch(code) { | |
663 case Bytecodes::_i2l: { | |
664 Register rlo = dst->as_register_lo(); | |
665 Register rhi = dst->as_register_hi(); | |
666 Register rval = op->in_opr()->as_register(); | |
667 #ifdef _LP64 | |
668 __ sra(rval, 0, rlo); | |
669 #else | |
670 __ mov(rval, rlo); | |
671 __ sra(rval, BitsPerInt-1, rhi); | |
672 #endif | |
673 break; | |
674 } | |
675 case Bytecodes::_i2d: | |
676 case Bytecodes::_i2f: { | |
677 bool is_double = (code == Bytecodes::_i2d); | |
678 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg(); | |
679 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S; | |
680 FloatRegister rsrc = op->in_opr()->as_float_reg(); | |
681 if (rsrc != rdst) { | |
682 __ fmov(FloatRegisterImpl::S, rsrc, rdst); | |
683 } | |
684 __ fitof(w, rdst, rdst); | |
685 break; | |
686 } | |
687 case Bytecodes::_f2i:{ | |
688 FloatRegister rsrc = op->in_opr()->as_float_reg(); | |
689 Address addr = frame_map()->address_for_slot(dst->single_stack_ix()); | |
690 Label L; | |
691 // result must be 0 if value is NaN; test by comparing value to itself | |
692 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc); | |
693 if (!VM_Version::v9_instructions_work()) { | |
694 __ nop(); | |
695 } | |
696 __ fb(Assembler::f_unordered, true, Assembler::pn, L); | |
697 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN | |
698 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc); | |
699 // move integer result from float register to int register | |
700 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp()); | |
701 __ bind (L); | |
702 break; | |
703 } | |
704 case Bytecodes::_l2i: { | |
705 Register rlo = op->in_opr()->as_register_lo(); | |
706 Register rhi = op->in_opr()->as_register_hi(); | |
707 Register rdst = dst->as_register(); | |
708 #ifdef _LP64 | |
709 __ sra(rlo, 0, rdst); | |
710 #else | |
711 __ mov(rlo, rdst); | |
712 #endif | |
713 break; | |
714 } | |
715 case Bytecodes::_d2f: | |
716 case Bytecodes::_f2d: { | |
717 bool is_double = (code == Bytecodes::_f2d); | |
718 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check"); | |
719 LIR_Opr val = op->in_opr(); | |
720 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg(); | |
721 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg(); | |
722 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D; | |
723 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S; | |
724 __ ftof(vw, dw, rval, rdst); | |
725 break; | |
726 } | |
727 case Bytecodes::_i2s: | |
728 case Bytecodes::_i2b: { | |
729 Register rval = op->in_opr()->as_register(); | |
730 Register rdst = dst->as_register(); | |
731 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort); | |
732 __ sll (rval, shift, rdst); | |
733 __ sra (rdst, shift, rdst); | |
734 break; | |
735 } | |
736 case Bytecodes::_i2c: { | |
737 Register rval = op->in_opr()->as_register(); | |
738 Register rdst = dst->as_register(); | |
739 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte; | |
740 __ sll (rval, shift, rdst); | |
741 __ srl (rdst, shift, rdst); | |
742 break; | |
743 } | |
744 | |
745 default: ShouldNotReachHere(); | |
746 } | |
747 } | |
748 | |
749 | |
750 void LIR_Assembler::align_call(LIR_Code) { | |
751 // do nothing since all instructions are word aligned on sparc | |
752 } | |
753 | |
754 | |
1295 | 755 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { |
756 __ call(op->addr(), rtype); | |
1564 | 757 // The peephole pass fills the delay slot, add_call_info is done in |
758 // LIR_Assembler::emit_delay. | |
0 | 759 } |
760 | |
761 | |
1295 | 762 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { |
0 | 763 RelocationHolder rspec = virtual_call_Relocation::spec(pc()); |
764 __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg); | |
765 __ relocate(rspec); | |
1295 | 766 __ call(op->addr(), relocInfo::none); |
1564 | 767 // The peephole pass fills the delay slot, add_call_info is done in |
768 // LIR_Assembler::emit_delay. | |
0 | 769 } |
770 | |
771 | |
1295 | 772 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { |
773 add_debug_info_for_null_check_here(op->info()); | |
2002 | 774 __ load_klass(O0, G3_scratch); |
1295 | 775 if (__ is_simm13(op->vtable_offset())) { |
776 __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method); | |
0 | 777 } else { |
778 // This will generate 2 instructions | |
1295 | 779 __ set(op->vtable_offset(), G5_method); |
0 | 780 // ld_ptr, set_hi, set |
781 __ ld_ptr(G3_scratch, G5_method, G5_method); | |
782 } | |
727 | 783 __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3_scratch); |
0 | 784 __ callr(G3_scratch, G0); |
785 // the peephole pass fills the delay slot | |
786 } | |
787 | |
2002 | 788 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) { |
0 | 789 int store_offset; |
790 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) { | |
791 assert(!unaligned, "can't handle this"); | |
792 // for offsets larger than a simm13 we setup the offset in O7 | |
727 | 793 __ set(offset, O7); |
2002 | 794 store_offset = store(from_reg, base, O7, type, wide); |
0 | 795 } else { |
2002 | 796 if (type == T_ARRAY || type == T_OBJECT) { |
797 __ verify_oop(from_reg->as_register()); | |
798 } | |
0 | 799 store_offset = code_offset(); |
800 switch (type) { | |
801 case T_BOOLEAN: // fall through | |
802 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break; | |
803 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break; | |
804 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break; | |
805 case T_INT : __ stw(from_reg->as_register(), base, offset); break; | |
806 case T_LONG : | |
807 #ifdef _LP64 | |
808 if (unaligned || PatchALot) { | |
809 __ srax(from_reg->as_register_lo(), 32, O7); | |
810 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes); | |
811 __ stw(O7, base, offset + hi_word_offset_in_bytes); | |
812 } else { | |
813 __ stx(from_reg->as_register_lo(), base, offset); | |
814 } | |
815 #else | |
816 assert(Assembler::is_simm13(offset + 4), "must be"); | |
817 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes); | |
818 __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes); | |
819 #endif | |
820 break; | |
2002 | 821 case T_ADDRESS: |
822 __ st_ptr(from_reg->as_register(), base, offset); | |
823 break; | |
0 | 824 case T_ARRAY : // fall through |
2002 | 825 case T_OBJECT: |
826 { | |
827 if (UseCompressedOops && !wide) { | |
828 __ encode_heap_oop(from_reg->as_register(), G3_scratch); | |
829 store_offset = code_offset(); | |
830 __ stw(G3_scratch, base, offset); | |
831 } else { | |
832 __ st_ptr(from_reg->as_register(), base, offset); | |
833 } | |
834 break; | |
835 } | |
836 | |
0 | 837 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break; |
838 case T_DOUBLE: | |
839 { | |
840 FloatRegister reg = from_reg->as_double_reg(); | |
841 // split unaligned stores | |
842 if (unaligned || PatchALot) { | |
843 assert(Assembler::is_simm13(offset + 4), "must be"); | |
844 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4); | |
845 __ stf(FloatRegisterImpl::S, reg, base, offset); | |
846 } else { | |
847 __ stf(FloatRegisterImpl::D, reg, base, offset); | |
848 } | |
849 break; | |
850 } | |
851 default : ShouldNotReachHere(); | |
852 } | |
853 } | |
854 return store_offset; | |
855 } | |
856 | |
857 | |
2002 | 858 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) { |
859 if (type == T_ARRAY || type == T_OBJECT) { | |
860 __ verify_oop(from_reg->as_register()); | |
861 } | |
0 | 862 int store_offset = code_offset(); |
863 switch (type) { | |
864 case T_BOOLEAN: // fall through | |
865 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break; | |
866 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break; | |
867 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break; | |
868 case T_INT : __ stw(from_reg->as_register(), base, disp); break; | |
869 case T_LONG : | |
870 #ifdef _LP64 | |
871 __ stx(from_reg->as_register_lo(), base, disp); | |
872 #else | |
873 assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match"); | |
874 __ std(from_reg->as_register_hi(), base, disp); | |
875 #endif | |
876 break; | |
2002 | 877 case T_ADDRESS: |
878 __ st_ptr(from_reg->as_register(), base, disp); | |
879 break; | |
0 | 880 case T_ARRAY : // fall through |
2002 | 881 case T_OBJECT: |
882 { | |
883 if (UseCompressedOops && !wide) { | |
884 __ encode_heap_oop(from_reg->as_register(), G3_scratch); | |
885 store_offset = code_offset(); | |
886 __ stw(G3_scratch, base, disp); | |
887 } else { | |
888 __ st_ptr(from_reg->as_register(), base, disp); | |
889 } | |
890 break; | |
891 } | |
0 | 892 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break; |
893 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break; | |
894 default : ShouldNotReachHere(); | |
895 } | |
896 return store_offset; | |
897 } | |
898 | |
899 | |
2002 | 900 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) { |
0 | 901 int load_offset; |
902 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) { | |
903 assert(base != O7, "destroying register"); | |
904 assert(!unaligned, "can't handle this"); | |
905 // for offsets larger than a simm13 we setup the offset in O7 | |
727 | 906 __ set(offset, O7); |
2002 | 907 load_offset = load(base, O7, to_reg, type, wide); |
0 | 908 } else { |
909 load_offset = code_offset(); | |
910 switch(type) { | |
911 case T_BOOLEAN: // fall through | |
912 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break; | |
913 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break; | |
914 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break; | |
915 case T_INT : __ ld(base, offset, to_reg->as_register()); break; | |
916 case T_LONG : | |
917 if (!unaligned) { | |
918 #ifdef _LP64 | |
919 __ ldx(base, offset, to_reg->as_register_lo()); | |
920 #else | |
921 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(), | |
922 "must be sequential"); | |
923 __ ldd(base, offset, to_reg->as_register_hi()); | |
924 #endif | |
925 } else { | |
926 #ifdef _LP64 | |
927 assert(base != to_reg->as_register_lo(), "can't handle this"); | |
1060 | 928 assert(O7 != to_reg->as_register_lo(), "can't handle this"); |
0 | 929 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo()); |
1060 | 930 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last |
0 | 931 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo()); |
1060 | 932 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo()); |
0 | 933 #else |
934 if (base == to_reg->as_register_lo()) { | |
935 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi()); | |
936 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo()); | |
937 } else { | |
938 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo()); | |
939 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi()); | |
940 } | |
941 #endif | |
942 } | |
943 break; | |
2002 | 944 case T_ADDRESS: __ ld_ptr(base, offset, to_reg->as_register()); break; |
0 | 945 case T_ARRAY : // fall through |
2002 | 946 case T_OBJECT: |
947 { | |
948 if (UseCompressedOops && !wide) { | |
949 __ lduw(base, offset, to_reg->as_register()); | |
950 __ decode_heap_oop(to_reg->as_register()); | |
951 } else { | |
952 __ ld_ptr(base, offset, to_reg->as_register()); | |
953 } | |
954 break; | |
955 } | |
0 | 956 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break; |
957 case T_DOUBLE: | |
958 { | |
959 FloatRegister reg = to_reg->as_double_reg(); | |
960 // split unaligned loads | |
961 if (unaligned || PatchALot) { | |
1060 | 962 __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor()); |
963 __ ldf(FloatRegisterImpl::S, base, offset, reg); | |
0 | 964 } else { |
965 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg()); | |
966 } | |
967 break; | |
968 } | |
969 default : ShouldNotReachHere(); | |
970 } | |
2002 | 971 if (type == T_ARRAY || type == T_OBJECT) { |
972 __ verify_oop(to_reg->as_register()); | |
973 } | |
0 | 974 } |
975 return load_offset; | |
976 } | |
977 | |
978 | |
2002 | 979 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) { |
0 | 980 int load_offset = code_offset(); |
981 switch(type) { | |
982 case T_BOOLEAN: // fall through | |
2002 | 983 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break; |
984 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break; | |
985 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break; | |
986 case T_INT : __ ld(base, disp, to_reg->as_register()); break; | |
987 case T_ADDRESS: __ ld_ptr(base, disp, to_reg->as_register()); break; | |
0 | 988 case T_ARRAY : // fall through |
2002 | 989 case T_OBJECT: |
990 { | |
991 if (UseCompressedOops && !wide) { | |
992 __ lduw(base, disp, to_reg->as_register()); | |
993 __ decode_heap_oop(to_reg->as_register()); | |
994 } else { | |
995 __ ld_ptr(base, disp, to_reg->as_register()); | |
996 } | |
997 break; | |
998 } | |
0 | 999 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break; |
1000 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break; | |
1001 case T_LONG : | |
1002 #ifdef _LP64 | |
1003 __ ldx(base, disp, to_reg->as_register_lo()); | |
1004 #else | |
1005 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(), | |
1006 "must be sequential"); | |
1007 __ ldd(base, disp, to_reg->as_register_hi()); | |
1008 #endif | |
1009 break; | |
1010 default : ShouldNotReachHere(); | |
1011 } | |
2002 | 1012 if (type == T_ARRAY || type == T_OBJECT) { |
1013 __ verify_oop(to_reg->as_register()); | |
1014 } | |
0 | 1015 return load_offset; |
1016 } | |
1017 | |
1018 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { | |
1019 LIR_Const* c = src->as_constant_ptr(); | |
1020 switch (c->type()) { | |
1021 case T_INT: | |
2002 | 1022 case T_FLOAT: { |
1023 Register src_reg = O7; | |
1024 int value = c->as_jint_bits(); | |
1025 if (value == 0) { | |
1026 src_reg = G0; | |
1027 } else { | |
1028 __ set(value, O7); | |
1029 } | |
1030 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
1031 __ stw(src_reg, addr.base(), addr.disp()); | |
1032 break; | |
1033 } | |
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1034 case T_ADDRESS: { |
0 | 1035 Register src_reg = O7; |
1036 int value = c->as_jint_bits(); | |
1037 if (value == 0) { | |
1038 src_reg = G0; | |
1039 } else { | |
1040 __ set(value, O7); | |
1041 } | |
1042 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
2002 | 1043 __ st_ptr(src_reg, addr.base(), addr.disp()); |
0 | 1044 break; |
1045 } | |
1046 case T_OBJECT: { | |
1047 Register src_reg = O7; | |
1048 jobject2reg(c->as_jobject(), src_reg); | |
1049 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
1050 __ st_ptr(src_reg, addr.base(), addr.disp()); | |
1051 break; | |
1052 } | |
1053 case T_LONG: | |
1054 case T_DOUBLE: { | |
1055 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix()); | |
1056 | |
1057 Register tmp = O7; | |
1058 int value_lo = c->as_jint_lo_bits(); | |
1059 if (value_lo == 0) { | |
1060 tmp = G0; | |
1061 } else { | |
1062 __ set(value_lo, O7); | |
1063 } | |
1064 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes); | |
1065 int value_hi = c->as_jint_hi_bits(); | |
1066 if (value_hi == 0) { | |
1067 tmp = G0; | |
1068 } else { | |
1069 __ set(value_hi, O7); | |
1070 } | |
1071 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes); | |
1072 break; | |
1073 } | |
1074 default: | |
1075 Unimplemented(); | |
1076 } | |
1077 } | |
1078 | |
1079 | |
2002 | 1080 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { |
0 | 1081 LIR_Const* c = src->as_constant_ptr(); |
1082 LIR_Address* addr = dest->as_address_ptr(); | |
1083 Register base = addr->base()->as_pointer_register(); | |
2002 | 1084 int offset = -1; |
1085 | |
0 | 1086 switch (c->type()) { |
1087 case T_INT: | |
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1088 case T_FLOAT: |
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1089 case T_ADDRESS: { |
0 | 1090 LIR_Opr tmp = FrameMap::O7_opr; |
1091 int value = c->as_jint_bits(); | |
1092 if (value == 0) { | |
1093 tmp = FrameMap::G0_opr; | |
1094 } else if (Assembler::is_simm13(value)) { | |
1095 __ set(value, O7); | |
1096 } | |
1097 if (addr->index()->is_valid()) { | |
1098 assert(addr->disp() == 0, "must be zero"); | |
2002 | 1099 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide); |
0 | 1100 } else { |
1101 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses"); | |
2002 | 1102 offset = store(tmp, base, addr->disp(), type, wide, false); |
0 | 1103 } |
1104 break; | |
1105 } | |
1106 case T_LONG: | |
1107 case T_DOUBLE: { | |
1108 assert(!addr->index()->is_valid(), "can't handle reg reg address here"); | |
1109 assert(Assembler::is_simm13(addr->disp()) && | |
1110 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses"); | |
1111 | |
2002 | 1112 LIR_Opr tmp = FrameMap::O7_opr; |
0 | 1113 int value_lo = c->as_jint_lo_bits(); |
1114 if (value_lo == 0) { | |
2002 | 1115 tmp = FrameMap::G0_opr; |
0 | 1116 } else { |
1117 __ set(value_lo, O7); | |
1118 } | |
2002 | 1119 offset = store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT, wide, false); |
0 | 1120 int value_hi = c->as_jint_hi_bits(); |
1121 if (value_hi == 0) { | |
2002 | 1122 tmp = FrameMap::G0_opr; |
0 | 1123 } else { |
1124 __ set(value_hi, O7); | |
1125 } | |
2002 | 1126 offset = store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT, wide, false); |
0 | 1127 break; |
1128 } | |
1129 case T_OBJECT: { | |
1130 jobject obj = c->as_jobject(); | |
1131 LIR_Opr tmp; | |
1132 if (obj == NULL) { | |
1133 tmp = FrameMap::G0_opr; | |
1134 } else { | |
1135 tmp = FrameMap::O7_opr; | |
1136 jobject2reg(c->as_jobject(), O7); | |
1137 } | |
1138 // handle either reg+reg or reg+disp address | |
1139 if (addr->index()->is_valid()) { | |
1140 assert(addr->disp() == 0, "must be zero"); | |
2002 | 1141 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide); |
0 | 1142 } else { |
1143 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses"); | |
2002 | 1144 offset = store(tmp, base, addr->disp(), type, wide, false); |
0 | 1145 } |
1146 | |
1147 break; | |
1148 } | |
1149 default: | |
1150 Unimplemented(); | |
1151 } | |
2002 | 1152 if (info != NULL) { |
1153 assert(offset != -1, "offset should've been set"); | |
1154 add_debug_info_for_null_check(offset, info); | |
1155 } | |
0 | 1156 } |
1157 | |
1158 | |
1159 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { | |
1160 LIR_Const* c = src->as_constant_ptr(); | |
1161 LIR_Opr to_reg = dest; | |
1162 | |
1163 switch (c->type()) { | |
1164 case T_INT: | |
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1165 case T_ADDRESS: |
0 | 1166 { |
1167 jint con = c->as_jint(); | |
1168 if (to_reg->is_single_cpu()) { | |
1169 assert(patch_code == lir_patch_none, "no patching handled here"); | |
1170 __ set(con, to_reg->as_register()); | |
1171 } else { | |
1172 ShouldNotReachHere(); | |
1173 assert(to_reg->is_single_fpu(), "wrong register kind"); | |
1174 | |
1175 __ set(con, O7); | |
727 | 1176 Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS); |
0 | 1177 __ st(O7, temp_slot); |
1178 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg()); | |
1179 } | |
1180 } | |
1181 break; | |
1182 | |
1183 case T_LONG: | |
1184 { | |
1185 jlong con = c->as_jlong(); | |
1186 | |
1187 if (to_reg->is_double_cpu()) { | |
1188 #ifdef _LP64 | |
1189 __ set(con, to_reg->as_register_lo()); | |
1190 #else | |
1191 __ set(low(con), to_reg->as_register_lo()); | |
1192 __ set(high(con), to_reg->as_register_hi()); | |
1193 #endif | |
1194 #ifdef _LP64 | |
1195 } else if (to_reg->is_single_cpu()) { | |
1196 __ set(con, to_reg->as_register()); | |
1197 #endif | |
1198 } else { | |
1199 ShouldNotReachHere(); | |
1200 assert(to_reg->is_double_fpu(), "wrong register kind"); | |
727 | 1201 Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS); |
1202 Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS); | |
0 | 1203 __ set(low(con), O7); |
1204 __ st(O7, temp_slot_lo); | |
1205 __ set(high(con), O7); | |
1206 __ st(O7, temp_slot_hi); | |
1207 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg()); | |
1208 } | |
1209 } | |
1210 break; | |
1211 | |
1212 case T_OBJECT: | |
1213 { | |
1214 if (patch_code == lir_patch_none) { | |
1215 jobject2reg(c->as_jobject(), to_reg->as_register()); | |
1216 } else { | |
1217 jobject2reg_with_patching(to_reg->as_register(), info); | |
1218 } | |
1219 } | |
1220 break; | |
1221 | |
1222 case T_FLOAT: | |
1223 { | |
1224 address const_addr = __ float_constant(c->as_jfloat()); | |
1225 if (const_addr == NULL) { | |
1226 bailout("const section overflow"); | |
1227 break; | |
1228 } | |
1229 RelocationHolder rspec = internal_word_Relocation::spec(const_addr); | |
727 | 1230 AddressLiteral const_addrlit(const_addr, rspec); |
0 | 1231 if (to_reg->is_single_fpu()) { |
727 | 1232 __ patchable_sethi(const_addrlit, O7); |
0 | 1233 __ relocate(rspec); |
727 | 1234 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg()); |
0 | 1235 |
1236 } else { | |
1237 assert(to_reg->is_single_cpu(), "Must be a cpu register."); | |
1238 | |
727 | 1239 __ set(const_addrlit, O7); |
2002 | 1240 __ ld(O7, 0, to_reg->as_register()); |
0 | 1241 } |
1242 } | |
1243 break; | |
1244 | |
1245 case T_DOUBLE: | |
1246 { | |
1247 address const_addr = __ double_constant(c->as_jdouble()); | |
1248 if (const_addr == NULL) { | |
1249 bailout("const section overflow"); | |
1250 break; | |
1251 } | |
1252 RelocationHolder rspec = internal_word_Relocation::spec(const_addr); | |
1253 | |
1254 if (to_reg->is_double_fpu()) { | |
727 | 1255 AddressLiteral const_addrlit(const_addr, rspec); |
1256 __ patchable_sethi(const_addrlit, O7); | |
0 | 1257 __ relocate(rspec); |
727 | 1258 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg()); |
0 | 1259 } else { |
1260 assert(to_reg->is_double_cpu(), "Must be a long register."); | |
1261 #ifdef _LP64 | |
1262 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo()); | |
1263 #else | |
1264 __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo()); | |
1265 __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi()); | |
1266 #endif | |
1267 } | |
1268 | |
1269 } | |
1270 break; | |
1271 | |
1272 default: | |
1273 ShouldNotReachHere(); | |
1274 } | |
1275 } | |
1276 | |
1277 Address LIR_Assembler::as_Address(LIR_Address* addr) { | |
1278 Register reg = addr->base()->as_register(); | |
727 | 1279 return Address(reg, addr->disp()); |
0 | 1280 } |
1281 | |
1282 | |
1283 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { | |
1284 switch (type) { | |
1285 case T_INT: | |
1286 case T_FLOAT: { | |
1287 Register tmp = O7; | |
1288 Address from = frame_map()->address_for_slot(src->single_stack_ix()); | |
1289 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); | |
1290 __ lduw(from.base(), from.disp(), tmp); | |
1291 __ stw(tmp, to.base(), to.disp()); | |
1292 break; | |
1293 } | |
1294 case T_OBJECT: { | |
1295 Register tmp = O7; | |
1296 Address from = frame_map()->address_for_slot(src->single_stack_ix()); | |
1297 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); | |
1298 __ ld_ptr(from.base(), from.disp(), tmp); | |
1299 __ st_ptr(tmp, to.base(), to.disp()); | |
1300 break; | |
1301 } | |
1302 case T_LONG: | |
1303 case T_DOUBLE: { | |
1304 Register tmp = O7; | |
1305 Address from = frame_map()->address_for_double_slot(src->double_stack_ix()); | |
1306 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix()); | |
1307 __ lduw(from.base(), from.disp(), tmp); | |
1308 __ stw(tmp, to.base(), to.disp()); | |
1309 __ lduw(from.base(), from.disp() + 4, tmp); | |
1310 __ stw(tmp, to.base(), to.disp() + 4); | |
1311 break; | |
1312 } | |
1313 | |
1314 default: | |
1315 ShouldNotReachHere(); | |
1316 } | |
1317 } | |
1318 | |
1319 | |
1320 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { | |
1321 Address base = as_Address(addr); | |
727 | 1322 return Address(base.base(), base.disp() + hi_word_offset_in_bytes); |
0 | 1323 } |
1324 | |
1325 | |
1326 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { | |
1327 Address base = as_Address(addr); | |
727 | 1328 return Address(base.base(), base.disp() + lo_word_offset_in_bytes); |
0 | 1329 } |
1330 | |
1331 | |
1332 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, | |
2002 | 1333 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) { |
0 | 1334 |
1335 LIR_Address* addr = src_opr->as_address_ptr(); | |
1336 LIR_Opr to_reg = dest; | |
1337 | |
1338 Register src = addr->base()->as_pointer_register(); | |
1339 Register disp_reg = noreg; | |
1340 int disp_value = addr->disp(); | |
1341 bool needs_patching = (patch_code != lir_patch_none); | |
1342 | |
1343 if (addr->base()->type() == T_OBJECT) { | |
1344 __ verify_oop(src); | |
1345 } | |
1346 | |
1347 PatchingStub* patch = NULL; | |
1348 if (needs_patching) { | |
1349 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
1350 assert(!to_reg->is_double_cpu() || | |
1351 patch_code == lir_patch_none || | |
1352 patch_code == lir_patch_normal, "patching doesn't match register"); | |
1353 } | |
1354 | |
1355 if (addr->index()->is_illegal()) { | |
1356 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) { | |
1357 if (needs_patching) { | |
727 | 1358 __ patchable_set(0, O7); |
0 | 1359 } else { |
1360 __ set(disp_value, O7); | |
1361 } | |
1362 disp_reg = O7; | |
1363 } | |
1364 } else if (unaligned || PatchALot) { | |
1365 __ add(src, addr->index()->as_register(), O7); | |
1366 src = O7; | |
1367 } else { | |
1368 disp_reg = addr->index()->as_pointer_register(); | |
1369 assert(disp_value == 0, "can't handle 3 operand addresses"); | |
1370 } | |
1371 | |
1372 // remember the offset of the load. The patching_epilog must be done | |
1373 // before the call to add_debug_info, otherwise the PcDescs don't get | |
1374 // entered in increasing order. | |
1375 int offset = code_offset(); | |
1376 | |
1377 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up"); | |
1378 if (disp_reg == noreg) { | |
2002 | 1379 offset = load(src, disp_value, to_reg, type, wide, unaligned); |
0 | 1380 } else { |
1381 assert(!unaligned, "can't handle this"); | |
2002 | 1382 offset = load(src, disp_reg, to_reg, type, wide); |
0 | 1383 } |
1384 | |
1385 if (patch != NULL) { | |
1386 patching_epilog(patch, patch_code, src, info); | |
1387 } | |
1388 if (info != NULL) add_debug_info_for_null_check(offset, info); | |
1389 } | |
1390 | |
1391 | |
1392 void LIR_Assembler::prefetchr(LIR_Opr src) { | |
1393 LIR_Address* addr = src->as_address_ptr(); | |
1394 Address from_addr = as_Address(addr); | |
1395 | |
1396 if (VM_Version::has_v9()) { | |
1397 __ prefetch(from_addr, Assembler::severalReads); | |
1398 } | |
1399 } | |
1400 | |
1401 | |
1402 void LIR_Assembler::prefetchw(LIR_Opr src) { | |
1403 LIR_Address* addr = src->as_address_ptr(); | |
1404 Address from_addr = as_Address(addr); | |
1405 | |
1406 if (VM_Version::has_v9()) { | |
1407 __ prefetch(from_addr, Assembler::severalWritesAndPossiblyReads); | |
1408 } | |
1409 } | |
1410 | |
1411 | |
1412 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { | |
1413 Address addr; | |
1414 if (src->is_single_word()) { | |
1415 addr = frame_map()->address_for_slot(src->single_stack_ix()); | |
1416 } else if (src->is_double_word()) { | |
1417 addr = frame_map()->address_for_double_slot(src->double_stack_ix()); | |
1418 } | |
1419 | |
1420 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; | |
2002 | 1421 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned); |
0 | 1422 } |
1423 | |
1424 | |
1425 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { | |
1426 Address addr; | |
1427 if (dest->is_single_word()) { | |
1428 addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
1429 } else if (dest->is_double_word()) { | |
1430 addr = frame_map()->address_for_slot(dest->double_stack_ix()); | |
1431 } | |
1432 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; | |
2002 | 1433 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned); |
0 | 1434 } |
1435 | |
1436 | |
1437 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) { | |
1438 if (from_reg->is_float_kind() && to_reg->is_float_kind()) { | |
1439 if (from_reg->is_double_fpu()) { | |
1440 // double to double moves | |
1441 assert(to_reg->is_double_fpu(), "should match"); | |
1442 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg()); | |
1443 } else { | |
1444 // float to float moves | |
1445 assert(to_reg->is_single_fpu(), "should match"); | |
1446 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg()); | |
1447 } | |
1448 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) { | |
1449 if (from_reg->is_double_cpu()) { | |
1450 #ifdef _LP64 | |
1451 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register()); | |
1452 #else | |
1453 assert(to_reg->is_double_cpu() && | |
1454 from_reg->as_register_hi() != to_reg->as_register_lo() && | |
1455 from_reg->as_register_lo() != to_reg->as_register_hi(), | |
1456 "should both be long and not overlap"); | |
1457 // long to long moves | |
1458 __ mov(from_reg->as_register_hi(), to_reg->as_register_hi()); | |
1459 __ mov(from_reg->as_register_lo(), to_reg->as_register_lo()); | |
1460 #endif | |
1461 #ifdef _LP64 | |
1462 } else if (to_reg->is_double_cpu()) { | |
1463 // int to int moves | |
1464 __ mov(from_reg->as_register(), to_reg->as_register_lo()); | |
1465 #endif | |
1466 } else { | |
1467 // int to int moves | |
1468 __ mov(from_reg->as_register(), to_reg->as_register()); | |
1469 } | |
1470 } else { | |
1471 ShouldNotReachHere(); | |
1472 } | |
1473 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) { | |
1474 __ verify_oop(to_reg->as_register()); | |
1475 } | |
1476 } | |
1477 | |
1478 | |
1479 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type, | |
1480 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, | |
2002 | 1481 bool wide, bool unaligned) { |
0 | 1482 LIR_Address* addr = dest->as_address_ptr(); |
1483 | |
1484 Register src = addr->base()->as_pointer_register(); | |
1485 Register disp_reg = noreg; | |
1486 int disp_value = addr->disp(); | |
1487 bool needs_patching = (patch_code != lir_patch_none); | |
1488 | |
1489 if (addr->base()->is_oop_register()) { | |
1490 __ verify_oop(src); | |
1491 } | |
1492 | |
1493 PatchingStub* patch = NULL; | |
1494 if (needs_patching) { | |
1495 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
1496 assert(!from_reg->is_double_cpu() || | |
1497 patch_code == lir_patch_none || | |
1498 patch_code == lir_patch_normal, "patching doesn't match register"); | |
1499 } | |
1500 | |
1501 if (addr->index()->is_illegal()) { | |
1502 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) { | |
1503 if (needs_patching) { | |
727 | 1504 __ patchable_set(0, O7); |
0 | 1505 } else { |
1506 __ set(disp_value, O7); | |
1507 } | |
1508 disp_reg = O7; | |
1509 } | |
1510 } else if (unaligned || PatchALot) { | |
1511 __ add(src, addr->index()->as_register(), O7); | |
1512 src = O7; | |
1513 } else { | |
1514 disp_reg = addr->index()->as_pointer_register(); | |
1515 assert(disp_value == 0, "can't handle 3 operand addresses"); | |
1516 } | |
1517 | |
1518 // remember the offset of the store. The patching_epilog must be done | |
1519 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get | |
1520 // entered in increasing order. | |
1521 int offset; | |
1522 | |
1523 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up"); | |
1524 if (disp_reg == noreg) { | |
2002 | 1525 offset = store(from_reg, src, disp_value, type, wide, unaligned); |
0 | 1526 } else { |
1527 assert(!unaligned, "can't handle this"); | |
2002 | 1528 offset = store(from_reg, src, disp_reg, type, wide); |
0 | 1529 } |
1530 | |
1531 if (patch != NULL) { | |
1532 patching_epilog(patch, patch_code, src, info); | |
1533 } | |
1534 | |
1535 if (info != NULL) add_debug_info_for_null_check(offset, info); | |
1536 } | |
1537 | |
1538 | |
1539 void LIR_Assembler::return_op(LIR_Opr result) { | |
1540 // the poll may need a register so just pick one that isn't the return register | |
1783 | 1541 #if defined(TIERED) && !defined(_LP64) |
0 | 1542 if (result->type_field() == LIR_OprDesc::long_type) { |
1543 // Must move the result to G1 | |
1544 // Must leave proper result in O0,O1 and G1 (TIERED only) | |
1545 __ sllx(I0, 32, G1); // Shift bits into high G1 | |
1546 __ srl (I1, 0, I1); // Zero extend O1 (harmless?) | |
1547 __ or3 (I1, G1, G1); // OR 64 bits into G1 | |
1783 | 1548 #ifdef ASSERT |
1549 // mangle it so any problems will show up | |
1550 __ set(0xdeadbeef, I0); | |
1551 __ set(0xdeadbeef, I1); | |
1552 #endif | |
0 | 1553 } |
1554 #endif // TIERED | |
1555 __ set((intptr_t)os::get_polling_page(), L0); | |
1556 __ relocate(relocInfo::poll_return_type); | |
1557 __ ld_ptr(L0, 0, G0); | |
1558 __ ret(); | |
1559 __ delayed()->restore(); | |
1560 } | |
1561 | |
1562 | |
1563 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { | |
1564 __ set((intptr_t)os::get_polling_page(), tmp->as_register()); | |
1565 if (info != NULL) { | |
1566 add_debug_info_for_branch(info); | |
1567 } else { | |
1568 __ relocate(relocInfo::poll_type); | |
1569 } | |
1570 | |
1571 int offset = __ offset(); | |
1572 __ ld_ptr(tmp->as_register(), 0, G0); | |
1573 | |
1574 return offset; | |
1575 } | |
1576 | |
1577 | |
1578 void LIR_Assembler::emit_static_call_stub() { | |
1579 address call_pc = __ pc(); | |
1580 address stub = __ start_a_stub(call_stub_size); | |
1581 if (stub == NULL) { | |
1582 bailout("static call stub overflow"); | |
1583 return; | |
1584 } | |
1585 | |
1586 int start = __ offset(); | |
1587 __ relocate(static_stub_Relocation::spec(call_pc)); | |
1588 | |
1589 __ set_oop(NULL, G5); | |
1590 // must be set to -1 at code generation time | |
727 | 1591 AddressLiteral addrlit(-1); |
1592 __ jump_to(addrlit, G3); | |
0 | 1593 __ delayed()->nop(); |
1594 | |
1595 assert(__ offset() - start <= call_stub_size, "stub too big"); | |
1596 __ end_a_stub(); | |
1597 } | |
1598 | |
1599 | |
1600 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { | |
1601 if (opr1->is_single_fpu()) { | |
1602 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg()); | |
1603 } else if (opr1->is_double_fpu()) { | |
1604 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg()); | |
1605 } else if (opr1->is_single_cpu()) { | |
1606 if (opr2->is_constant()) { | |
1607 switch (opr2->as_constant_ptr()->type()) { | |
1608 case T_INT: | |
1609 { jint con = opr2->as_constant_ptr()->as_jint(); | |
1610 if (Assembler::is_simm13(con)) { | |
1611 __ cmp(opr1->as_register(), con); | |
1612 } else { | |
1613 __ set(con, O7); | |
1614 __ cmp(opr1->as_register(), O7); | |
1615 } | |
1616 } | |
1617 break; | |
1618 | |
1619 case T_OBJECT: | |
1620 // there are only equal/notequal comparisions on objects | |
1621 { jobject con = opr2->as_constant_ptr()->as_jobject(); | |
1622 if (con == NULL) { | |
1623 __ cmp(opr1->as_register(), 0); | |
1624 } else { | |
1625 jobject2reg(con, O7); | |
1626 __ cmp(opr1->as_register(), O7); | |
1627 } | |
1628 } | |
1629 break; | |
1630 | |
1631 default: | |
1632 ShouldNotReachHere(); | |
1633 break; | |
1634 } | |
1635 } else { | |
1636 if (opr2->is_address()) { | |
1637 LIR_Address * addr = opr2->as_address_ptr(); | |
1638 BasicType type = addr->type(); | |
1639 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7); | |
1640 else __ ld(as_Address(addr), O7); | |
1641 __ cmp(opr1->as_register(), O7); | |
1642 } else { | |
1643 __ cmp(opr1->as_register(), opr2->as_register()); | |
1644 } | |
1645 } | |
1646 } else if (opr1->is_double_cpu()) { | |
1647 Register xlo = opr1->as_register_lo(); | |
1648 Register xhi = opr1->as_register_hi(); | |
1649 if (opr2->is_constant() && opr2->as_jlong() == 0) { | |
1650 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases"); | |
1651 #ifdef _LP64 | |
1652 __ orcc(xhi, G0, G0); | |
1653 #else | |
1654 __ orcc(xhi, xlo, G0); | |
1655 #endif | |
1656 } else if (opr2->is_register()) { | |
1657 Register ylo = opr2->as_register_lo(); | |
1658 Register yhi = opr2->as_register_hi(); | |
1659 #ifdef _LP64 | |
1660 __ cmp(xlo, ylo); | |
1661 #else | |
1662 __ subcc(xlo, ylo, xlo); | |
1663 __ subccc(xhi, yhi, xhi); | |
1664 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { | |
1665 __ orcc(xhi, xlo, G0); | |
1666 } | |
1667 #endif | |
1668 } else { | |
1669 ShouldNotReachHere(); | |
1670 } | |
1671 } else if (opr1->is_address()) { | |
1672 LIR_Address * addr = opr1->as_address_ptr(); | |
1673 BasicType type = addr->type(); | |
1674 assert (opr2->is_constant(), "Checking"); | |
1675 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7); | |
1676 else __ ld(as_Address(addr), O7); | |
1677 __ cmp(O7, opr2->as_constant_ptr()->as_jint()); | |
1678 } else { | |
1679 ShouldNotReachHere(); | |
1680 } | |
1681 } | |
1682 | |
1683 | |
1684 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){ | |
1685 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { | |
1686 bool is_unordered_less = (code == lir_ucmp_fd2i); | |
1687 if (left->is_single_fpu()) { | |
1688 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register()); | |
1689 } else if (left->is_double_fpu()) { | |
1690 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register()); | |
1691 } else { | |
1692 ShouldNotReachHere(); | |
1693 } | |
1694 } else if (code == lir_cmp_l2i) { | |
1369 | 1695 #ifdef _LP64 |
1696 __ lcmp(left->as_register_lo(), right->as_register_lo(), dst->as_register()); | |
1697 #else | |
0 | 1698 __ lcmp(left->as_register_hi(), left->as_register_lo(), |
1699 right->as_register_hi(), right->as_register_lo(), | |
1700 dst->as_register()); | |
1369 | 1701 #endif |
0 | 1702 } else { |
1703 ShouldNotReachHere(); | |
1704 } | |
1705 } | |
1706 | |
1707 | |
2089
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1708 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { |
0 | 1709 Assembler::Condition acond; |
1710 switch (condition) { | |
1711 case lir_cond_equal: acond = Assembler::equal; break; | |
1712 case lir_cond_notEqual: acond = Assembler::notEqual; break; | |
1713 case lir_cond_less: acond = Assembler::less; break; | |
1714 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; | |
1715 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break; | |
1716 case lir_cond_greater: acond = Assembler::greater; break; | |
1717 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break; | |
1718 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break; | |
1719 default: ShouldNotReachHere(); | |
1720 }; | |
1721 | |
1722 if (opr1->is_constant() && opr1->type() == T_INT) { | |
1723 Register dest = result->as_register(); | |
1724 // load up first part of constant before branch | |
1725 // and do the rest in the delay slot. | |
1726 if (!Assembler::is_simm13(opr1->as_jint())) { | |
1727 __ sethi(opr1->as_jint(), dest); | |
1728 } | |
1729 } else if (opr1->is_constant()) { | |
1730 const2reg(opr1, result, lir_patch_none, NULL); | |
1731 } else if (opr1->is_register()) { | |
1732 reg2reg(opr1, result); | |
1733 } else if (opr1->is_stack()) { | |
1734 stack2reg(opr1, result, result->type()); | |
1735 } else { | |
1736 ShouldNotReachHere(); | |
1737 } | |
1738 Label skip; | |
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1739 #ifdef _LP64 |
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1740 if (type == T_INT) { |
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7009231: C1: Incorrect CAS code for longs on SPARC 32bit
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1741 __ br(acond, false, Assembler::pt, skip); |
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7009231: C1: Incorrect CAS code for longs on SPARC 32bit
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1742 } else |
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1743 #endif |
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1744 __ brx(acond, false, Assembler::pt, skip); // checks icc on 32bit and xcc on 64bit |
0 | 1745 if (opr1->is_constant() && opr1->type() == T_INT) { |
1746 Register dest = result->as_register(); | |
1747 if (Assembler::is_simm13(opr1->as_jint())) { | |
1748 __ delayed()->or3(G0, opr1->as_jint(), dest); | |
1749 } else { | |
1750 // the sethi has been done above, so just put in the low 10 bits | |
1751 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest); | |
1752 } | |
1753 } else { | |
1754 // can't do anything useful in the delay slot | |
1755 __ delayed()->nop(); | |
1756 } | |
1757 if (opr2->is_constant()) { | |
1758 const2reg(opr2, result, lir_patch_none, NULL); | |
1759 } else if (opr2->is_register()) { | |
1760 reg2reg(opr2, result); | |
1761 } else if (opr2->is_stack()) { | |
1762 stack2reg(opr2, result, result->type()); | |
1763 } else { | |
1764 ShouldNotReachHere(); | |
1765 } | |
1766 __ bind(skip); | |
1767 } | |
1768 | |
1769 | |
1770 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { | |
1771 assert(info == NULL, "unused on this code path"); | |
1772 assert(left->is_register(), "wrong items state"); | |
1773 assert(dest->is_register(), "wrong items state"); | |
1774 | |
1775 if (right->is_register()) { | |
1776 if (dest->is_float_kind()) { | |
1777 | |
1778 FloatRegister lreg, rreg, res; | |
1779 FloatRegisterImpl::Width w; | |
1780 if (right->is_single_fpu()) { | |
1781 w = FloatRegisterImpl::S; | |
1782 lreg = left->as_float_reg(); | |
1783 rreg = right->as_float_reg(); | |
1784 res = dest->as_float_reg(); | |
1785 } else { | |
1786 w = FloatRegisterImpl::D; | |
1787 lreg = left->as_double_reg(); | |
1788 rreg = right->as_double_reg(); | |
1789 res = dest->as_double_reg(); | |
1790 } | |
1791 | |
1792 switch (code) { | |
1793 case lir_add: __ fadd(w, lreg, rreg, res); break; | |
1794 case lir_sub: __ fsub(w, lreg, rreg, res); break; | |
1795 case lir_mul: // fall through | |
1796 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break; | |
1797 case lir_div: // fall through | |
1798 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break; | |
1799 default: ShouldNotReachHere(); | |
1800 } | |
1801 | |
1802 } else if (dest->is_double_cpu()) { | |
1803 #ifdef _LP64 | |
1804 Register dst_lo = dest->as_register_lo(); | |
1805 Register op1_lo = left->as_pointer_register(); | |
1806 Register op2_lo = right->as_pointer_register(); | |
1807 | |
1808 switch (code) { | |
1809 case lir_add: | |
1810 __ add(op1_lo, op2_lo, dst_lo); | |
1811 break; | |
1812 | |
1813 case lir_sub: | |
1814 __ sub(op1_lo, op2_lo, dst_lo); | |
1815 break; | |
1816 | |
1817 default: ShouldNotReachHere(); | |
1818 } | |
1819 #else | |
1820 Register op1_lo = left->as_register_lo(); | |
1821 Register op1_hi = left->as_register_hi(); | |
1822 Register op2_lo = right->as_register_lo(); | |
1823 Register op2_hi = right->as_register_hi(); | |
1824 Register dst_lo = dest->as_register_lo(); | |
1825 Register dst_hi = dest->as_register_hi(); | |
1826 | |
1827 switch (code) { | |
1828 case lir_add: | |
1829 __ addcc(op1_lo, op2_lo, dst_lo); | |
1830 __ addc (op1_hi, op2_hi, dst_hi); | |
1831 break; | |
1832 | |
1833 case lir_sub: | |
1834 __ subcc(op1_lo, op2_lo, dst_lo); | |
1835 __ subc (op1_hi, op2_hi, dst_hi); | |
1836 break; | |
1837 | |
1838 default: ShouldNotReachHere(); | |
1839 } | |
1840 #endif | |
1841 } else { | |
1842 assert (right->is_single_cpu(), "Just Checking"); | |
1843 | |
1844 Register lreg = left->as_register(); | |
1845 Register res = dest->as_register(); | |
1846 Register rreg = right->as_register(); | |
1847 switch (code) { | |
1848 case lir_add: __ add (lreg, rreg, res); break; | |
1849 case lir_sub: __ sub (lreg, rreg, res); break; | |
1850 case lir_mul: __ mult (lreg, rreg, res); break; | |
1851 default: ShouldNotReachHere(); | |
1852 } | |
1853 } | |
1854 } else { | |
1855 assert (right->is_constant(), "must be constant"); | |
1856 | |
1857 if (dest->is_single_cpu()) { | |
1858 Register lreg = left->as_register(); | |
1859 Register res = dest->as_register(); | |
1860 int simm13 = right->as_constant_ptr()->as_jint(); | |
1861 | |
1862 switch (code) { | |
1863 case lir_add: __ add (lreg, simm13, res); break; | |
1864 case lir_sub: __ sub (lreg, simm13, res); break; | |
1865 case lir_mul: __ mult (lreg, simm13, res); break; | |
1866 default: ShouldNotReachHere(); | |
1867 } | |
1868 } else { | |
1869 Register lreg = left->as_pointer_register(); | |
1870 Register res = dest->as_register_lo(); | |
1871 long con = right->as_constant_ptr()->as_jlong(); | |
1872 assert(Assembler::is_simm13(con), "must be simm13"); | |
1873 | |
1874 switch (code) { | |
1875 case lir_add: __ add (lreg, (int)con, res); break; | |
1876 case lir_sub: __ sub (lreg, (int)con, res); break; | |
1877 case lir_mul: __ mult (lreg, (int)con, res); break; | |
1878 default: ShouldNotReachHere(); | |
1879 } | |
1880 } | |
1881 } | |
1882 } | |
1883 | |
1884 | |
1885 void LIR_Assembler::fpop() { | |
1886 // do nothing | |
1887 } | |
1888 | |
1889 | |
1890 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) { | |
1891 switch (code) { | |
1892 case lir_sin: | |
1893 case lir_tan: | |
1894 case lir_cos: { | |
1895 assert(thread->is_valid(), "preserve the thread object for performance reasons"); | |
1896 assert(dest->as_double_reg() == F0, "the result will be in f0/f1"); | |
1897 break; | |
1898 } | |
1899 case lir_sqrt: { | |
1900 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt"); | |
1901 FloatRegister src_reg = value->as_double_reg(); | |
1902 FloatRegister dst_reg = dest->as_double_reg(); | |
1903 __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg); | |
1904 break; | |
1905 } | |
1906 case lir_abs: { | |
1907 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs"); | |
1908 FloatRegister src_reg = value->as_double_reg(); | |
1909 FloatRegister dst_reg = dest->as_double_reg(); | |
1910 __ fabs(FloatRegisterImpl::D, src_reg, dst_reg); | |
1911 break; | |
1912 } | |
1913 default: { | |
1914 ShouldNotReachHere(); | |
1915 break; | |
1916 } | |
1917 } | |
1918 } | |
1919 | |
1920 | |
1921 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) { | |
1922 if (right->is_constant()) { | |
1923 if (dest->is_single_cpu()) { | |
1924 int simm13 = right->as_constant_ptr()->as_jint(); | |
1925 switch (code) { | |
1926 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break; | |
1927 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break; | |
1928 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break; | |
1929 default: ShouldNotReachHere(); | |
1930 } | |
1931 } else { | |
1932 long c = right->as_constant_ptr()->as_jlong(); | |
1933 assert(c == (int)c && Assembler::is_simm13(c), "out of range"); | |
1934 int simm13 = (int)c; | |
1935 switch (code) { | |
1936 case lir_logic_and: | |
1937 #ifndef _LP64 | |
1938 __ and3 (left->as_register_hi(), 0, dest->as_register_hi()); | |
1939 #endif | |
1940 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo()); | |
1941 break; | |
1942 | |
1943 case lir_logic_or: | |
1944 #ifndef _LP64 | |
1945 __ or3 (left->as_register_hi(), 0, dest->as_register_hi()); | |
1946 #endif | |
1947 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo()); | |
1948 break; | |
1949 | |
1950 case lir_logic_xor: | |
1951 #ifndef _LP64 | |
1952 __ xor3 (left->as_register_hi(), 0, dest->as_register_hi()); | |
1953 #endif | |
1954 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo()); | |
1955 break; | |
1956 | |
1957 default: ShouldNotReachHere(); | |
1958 } | |
1959 } | |
1960 } else { | |
1961 assert(right->is_register(), "right should be in register"); | |
1962 | |
1963 if (dest->is_single_cpu()) { | |
1964 switch (code) { | |
1965 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break; | |
1966 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break; | |
1967 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break; | |
1968 default: ShouldNotReachHere(); | |
1969 } | |
1970 } else { | |
1971 #ifdef _LP64 | |
1972 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() : | |
1973 left->as_register_lo(); | |
1974 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() : | |
1975 right->as_register_lo(); | |
1976 | |
1977 switch (code) { | |
1978 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break; | |
1979 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break; | |
1980 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break; | |
1981 default: ShouldNotReachHere(); | |
1982 } | |
1983 #else | |
1984 switch (code) { | |
1985 case lir_logic_and: | |
1986 __ and3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); | |
1987 __ and3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); | |
1988 break; | |
1989 | |
1990 case lir_logic_or: | |
1991 __ or3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); | |
1992 __ or3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); | |
1993 break; | |
1994 | |
1995 case lir_logic_xor: | |
1996 __ xor3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); | |
1997 __ xor3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); | |
1998 break; | |
1999 | |
2000 default: ShouldNotReachHere(); | |
2001 } | |
2002 #endif | |
2003 } | |
2004 } | |
2005 } | |
2006 | |
2007 | |
2008 int LIR_Assembler::shift_amount(BasicType t) { | |
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2009 int elem_size = type2aelembytes(t); |
0 | 2010 switch (elem_size) { |
2011 case 1 : return 0; | |
2012 case 2 : return 1; | |
2013 case 4 : return 2; | |
2014 case 8 : return 3; | |
2015 } | |
2016 ShouldNotReachHere(); | |
2017 return -1; | |
2018 } | |
2019 | |
2020 | |
1378
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2021 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { |
0 | 2022 assert(exceptionOop->as_register() == Oexception, "should match"); |
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2023 assert(exceptionPC->as_register() == Oissuing_pc, "should match"); |
0 | 2024 |
2025 info->add_register_oop(exceptionOop); | |
2026 | |
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2027 // reuse the debug info from the safepoint poll for the throw op itself |
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2028 address pc_for_athrow = __ pc(); |
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2029 int pc_for_athrow_offset = __ offset(); |
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2030 RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow); |
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2031 __ set(pc_for_athrow, Oissuing_pc, rspec); |
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2032 add_call_info(pc_for_athrow_offset, info); // for exception handler |
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2033 |
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2034 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type); |
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2035 __ delayed()->nop(); |
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2036 } |
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2037 |
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2038 |
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2039 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { |
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2040 assert(exceptionOop->as_register() == Oexception, "should match"); |
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2041 |
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2042 __ br(Assembler::always, false, Assembler::pt, _unwind_handler_entry); |
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2043 __ delayed()->nop(); |
0 | 2044 } |
2045 | |
2046 | |
2047 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { | |
2048 Register src = op->src()->as_register(); | |
2049 Register dst = op->dst()->as_register(); | |
2050 Register src_pos = op->src_pos()->as_register(); | |
2051 Register dst_pos = op->dst_pos()->as_register(); | |
2052 Register length = op->length()->as_register(); | |
2053 Register tmp = op->tmp()->as_register(); | |
2054 Register tmp2 = O7; | |
2055 | |
2056 int flags = op->flags(); | |
2057 ciArrayKlass* default_type = op->expected_type(); | |
2058 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; | |
2059 if (basic_type == T_ARRAY) basic_type = T_OBJECT; | |
2060 | |
2449
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2061 #ifdef _LP64 |
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2062 // higher 32bits must be null |
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2063 __ sra(dst_pos, 0, dst_pos); |
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2064 __ sra(src_pos, 0, src_pos); |
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2065 __ sra(length, 0, length); |
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2066 #endif |
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2067 |
0 | 2068 // set up the arraycopy stub information |
2069 ArrayCopyStub* stub = op->stub(); | |
2070 | |
2071 // always do stub if no type information is available. it's ok if | |
2072 // the known type isn't loaded since the code sanity checks | |
2073 // in debug mode and the type isn't required when we know the exact type | |
2074 // also check that the type is an array type. | |
2446 | 2075 if (op->expected_type() == NULL) { |
0 | 2076 __ mov(src, O0); |
2077 __ mov(src_pos, O1); | |
2078 __ mov(dst, O2); | |
2079 __ mov(dst_pos, O3); | |
2080 __ mov(length, O4); | |
2446 | 2081 address copyfunc_addr = StubRoutines::generic_arraycopy(); |
2082 | |
2083 if (copyfunc_addr == NULL) { // Use C version if stub was not generated | |
2084 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy)); | |
2085 } else { | |
2086 #ifndef PRODUCT | |
2087 if (PrintC1Statistics) { | |
2088 address counter = (address)&Runtime1::_generic_arraycopystub_cnt; | |
2089 __ inc_counter(counter, G1, G3); | |
2090 } | |
2091 #endif | |
2092 __ call_VM_leaf(tmp, copyfunc_addr); | |
2093 } | |
2094 | |
2095 if (copyfunc_addr != NULL) { | |
2096 __ xor3(O0, -1, tmp); | |
2097 __ sub(length, tmp, length); | |
2098 __ add(src_pos, tmp, src_pos); | |
2099 __ br_zero(Assembler::less, false, Assembler::pn, O0, *stub->entry()); | |
2100 __ delayed()->add(dst_pos, tmp, dst_pos); | |
2101 } else { | |
2102 __ br_zero(Assembler::less, false, Assembler::pn, O0, *stub->entry()); | |
2103 __ delayed()->nop(); | |
2104 } | |
0 | 2105 __ bind(*stub->continuation()); |
2106 return; | |
2107 } | |
2108 | |
2109 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point"); | |
2110 | |
2111 // make sure src and dst are non-null and load array length | |
2112 if (flags & LIR_OpArrayCopy::src_null_check) { | |
2113 __ tst(src); | |
2002 | 2114 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry()); |
0 | 2115 __ delayed()->nop(); |
2116 } | |
2117 | |
2118 if (flags & LIR_OpArrayCopy::dst_null_check) { | |
2119 __ tst(dst); | |
2002 | 2120 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry()); |
0 | 2121 __ delayed()->nop(); |
2122 } | |
2123 | |
2124 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { | |
2125 // test src_pos register | |
2126 __ tst(src_pos); | |
2127 __ br(Assembler::less, false, Assembler::pn, *stub->entry()); | |
2128 __ delayed()->nop(); | |
2129 } | |
2130 | |
2131 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { | |
2132 // test dst_pos register | |
2133 __ tst(dst_pos); | |
2134 __ br(Assembler::less, false, Assembler::pn, *stub->entry()); | |
2135 __ delayed()->nop(); | |
2136 } | |
2137 | |
2138 if (flags & LIR_OpArrayCopy::length_positive_check) { | |
2139 // make sure length isn't negative | |
2140 __ tst(length); | |
2141 __ br(Assembler::less, false, Assembler::pn, *stub->entry()); | |
2142 __ delayed()->nop(); | |
2143 } | |
2144 | |
2145 if (flags & LIR_OpArrayCopy::src_range_check) { | |
2146 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2); | |
2147 __ add(length, src_pos, tmp); | |
2148 __ cmp(tmp2, tmp); | |
2149 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry()); | |
2150 __ delayed()->nop(); | |
2151 } | |
2152 | |
2153 if (flags & LIR_OpArrayCopy::dst_range_check) { | |
2154 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2); | |
2155 __ add(length, dst_pos, tmp); | |
2156 __ cmp(tmp2, tmp); | |
2157 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry()); | |
2158 __ delayed()->nop(); | |
2159 } | |
2160 | |
2446 | 2161 int shift = shift_amount(basic_type); |
2162 | |
0 | 2163 if (flags & LIR_OpArrayCopy::type_check) { |
2446 | 2164 // We don't know the array types are compatible |
2165 if (basic_type != T_OBJECT) { | |
2166 // Simple test for basic type arrays | |
2167 if (UseCompressedOops) { | |
2168 // We don't need decode because we just need to compare | |
2169 __ lduw(src, oopDesc::klass_offset_in_bytes(), tmp); | |
2170 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2); | |
2171 __ cmp(tmp, tmp2); | |
2172 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry()); | |
2173 } else { | |
2174 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp); | |
2175 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2); | |
2176 __ cmp(tmp, tmp2); | |
2177 __ brx(Assembler::notEqual, false, Assembler::pt, *stub->entry()); | |
2178 } | |
2179 __ delayed()->nop(); | |
2002 | 2180 } else { |
2446 | 2181 // For object arrays, if src is a sub class of dst then we can |
2182 // safely do the copy. | |
2183 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); | |
2184 | |
2185 Label cont, slow; | |
2186 assert_different_registers(tmp, tmp2, G3, G1); | |
2187 | |
2188 __ load_klass(src, G3); | |
2189 __ load_klass(dst, G1); | |
2190 | |
2191 __ check_klass_subtype_fast_path(G3, G1, tmp, tmp2, &cont, copyfunc_addr == NULL ? stub->entry() : &slow, NULL); | |
2192 | |
2193 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); | |
2194 __ delayed()->nop(); | |
2195 | |
2196 __ cmp(G3, 0); | |
2197 if (copyfunc_addr != NULL) { // use stub if available | |
2198 // src is not a sub class of dst so we have to do a | |
2199 // per-element check. | |
2200 __ br(Assembler::notEqual, false, Assembler::pt, cont); | |
2201 __ delayed()->nop(); | |
2202 | |
2203 __ bind(slow); | |
2204 | |
2205 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; | |
2206 if ((flags & mask) != mask) { | |
2207 // Check that at least both of them object arrays. | |
2208 assert(flags & mask, "one of the two should be known to be an object array"); | |
2209 | |
2210 if (!(flags & LIR_OpArrayCopy::src_objarray)) { | |
2211 __ load_klass(src, tmp); | |
2212 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { | |
2213 __ load_klass(dst, tmp); | |
2214 } | |
2215 int lh_offset = klassOopDesc::header_size() * HeapWordSize + | |
2216 Klass::layout_helper_offset_in_bytes(); | |
2217 | |
2218 __ lduw(tmp, lh_offset, tmp2); | |
2219 | |
2220 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); | |
2221 __ set(objArray_lh, tmp); | |
2222 __ cmp(tmp, tmp2); | |
2223 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry()); | |
2224 __ delayed()->nop(); | |
2225 } | |
2226 | |
2227 Register src_ptr = O0; | |
2228 Register dst_ptr = O1; | |
2229 Register len = O2; | |
2230 Register chk_off = O3; | |
2231 Register super_k = O4; | |
2232 | |
2233 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr); | |
2234 if (shift == 0) { | |
2235 __ add(src_ptr, src_pos, src_ptr); | |
2236 } else { | |
2237 __ sll(src_pos, shift, tmp); | |
2238 __ add(src_ptr, tmp, src_ptr); | |
2239 } | |
2240 | |
2241 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr); | |
2242 if (shift == 0) { | |
2243 __ add(dst_ptr, dst_pos, dst_ptr); | |
2244 } else { | |
2245 __ sll(dst_pos, shift, tmp); | |
2246 __ add(dst_ptr, tmp, dst_ptr); | |
2247 } | |
2248 __ mov(length, len); | |
2249 __ load_klass(dst, tmp); | |
2250 | |
2251 int ek_offset = (klassOopDesc::header_size() * HeapWordSize + | |
2252 objArrayKlass::element_klass_offset_in_bytes()); | |
2253 __ ld_ptr(tmp, ek_offset, super_k); | |
2254 | |
2255 int sco_offset = (klassOopDesc::header_size() * HeapWordSize + | |
2256 Klass::super_check_offset_offset_in_bytes()); | |
2257 __ lduw(super_k, sco_offset, chk_off); | |
2258 | |
2259 __ call_VM_leaf(tmp, copyfunc_addr); | |
2260 | |
2261 #ifndef PRODUCT | |
2262 if (PrintC1Statistics) { | |
2263 Label failed; | |
2264 __ br_notnull(O0, false, Assembler::pn, failed); | |
2265 __ delayed()->nop(); | |
2266 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_cnt, G1, G3); | |
2267 __ bind(failed); | |
2268 } | |
2269 #endif | |
2270 | |
2271 __ br_null(O0, false, Assembler::pt, *stub->continuation()); | |
2272 __ delayed()->xor3(O0, -1, tmp); | |
2273 | |
2274 #ifndef PRODUCT | |
2275 if (PrintC1Statistics) { | |
2276 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_attempt_cnt, G1, G3); | |
2277 } | |
2278 #endif | |
2279 | |
2280 __ sub(length, tmp, length); | |
2281 __ add(src_pos, tmp, src_pos); | |
2282 __ br(Assembler::always, false, Assembler::pt, *stub->entry()); | |
2283 __ delayed()->add(dst_pos, tmp, dst_pos); | |
2284 | |
2285 __ bind(cont); | |
2286 } else { | |
2287 __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); | |
2288 __ delayed()->nop(); | |
2289 __ bind(cont); | |
2290 } | |
2002 | 2291 } |
0 | 2292 } |
2293 | |
2294 #ifdef ASSERT | |
2295 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { | |
2296 // Sanity check the known type with the incoming class. For the | |
2297 // primitive case the types must match exactly with src.klass and | |
2298 // dst.klass each exactly matching the default type. For the | |
2299 // object array case, if no type check is needed then either the | |
2300 // dst type is exactly the expected type and the src type is a | |
2301 // subtype which we can't check or src is the same array as dst | |
2302 // but not necessarily exactly of type default_type. | |
2303 Label known_ok, halt; | |
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2304 jobject2reg(op->expected_type()->constant_encoding(), tmp); |
2002 | 2305 if (UseCompressedOops) { |
2306 // tmp holds the default type. It currently comes uncompressed after the | |
2307 // load of a constant, so encode it. | |
2308 __ encode_heap_oop(tmp); | |
2309 // load the raw value of the dst klass, since we will be comparing | |
2310 // uncompressed values directly. | |
2311 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2); | |
2312 if (basic_type != T_OBJECT) { | |
2313 __ cmp(tmp, tmp2); | |
2314 __ br(Assembler::notEqual, false, Assembler::pn, halt); | |
2315 // load the raw value of the src klass. | |
2316 __ delayed()->lduw(src, oopDesc::klass_offset_in_bytes(), tmp2); | |
2317 __ cmp(tmp, tmp2); | |
2318 __ br(Assembler::equal, false, Assembler::pn, known_ok); | |
2319 __ delayed()->nop(); | |
2320 } else { | |
2321 __ cmp(tmp, tmp2); | |
2322 __ br(Assembler::equal, false, Assembler::pn, known_ok); | |
2323 __ delayed()->cmp(src, dst); | |
2324 __ brx(Assembler::equal, false, Assembler::pn, known_ok); | |
2325 __ delayed()->nop(); | |
2326 } | |
0 | 2327 } else { |
2002 | 2328 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2); |
2329 if (basic_type != T_OBJECT) { | |
2330 __ cmp(tmp, tmp2); | |
2331 __ brx(Assembler::notEqual, false, Assembler::pn, halt); | |
2332 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2); | |
2333 __ cmp(tmp, tmp2); | |
2334 __ brx(Assembler::equal, false, Assembler::pn, known_ok); | |
2335 __ delayed()->nop(); | |
2336 } else { | |
2337 __ cmp(tmp, tmp2); | |
2338 __ brx(Assembler::equal, false, Assembler::pn, known_ok); | |
2339 __ delayed()->cmp(src, dst); | |
2340 __ brx(Assembler::equal, false, Assembler::pn, known_ok); | |
2341 __ delayed()->nop(); | |
2342 } | |
0 | 2343 } |
2344 __ bind(halt); | |
2345 __ stop("incorrect type information in arraycopy"); | |
2346 __ bind(known_ok); | |
2347 } | |
2348 #endif | |
2349 | |
2446 | 2350 #ifndef PRODUCT |
2351 if (PrintC1Statistics) { | |
2352 address counter = Runtime1::arraycopy_count_address(basic_type); | |
2353 __ inc_counter(counter, G1, G3); | |
2354 } | |
2355 #endif | |
0 | 2356 |
2357 Register src_ptr = O0; | |
2358 Register dst_ptr = O1; | |
2359 Register len = O2; | |
2360 | |
2361 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr); | |
2362 if (shift == 0) { | |
2363 __ add(src_ptr, src_pos, src_ptr); | |
2364 } else { | |
2365 __ sll(src_pos, shift, tmp); | |
2366 __ add(src_ptr, tmp, src_ptr); | |
2367 } | |
2368 | |
2369 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr); | |
2370 if (shift == 0) { | |
2371 __ add(dst_ptr, dst_pos, dst_ptr); | |
2372 } else { | |
2373 __ sll(dst_pos, shift, tmp); | |
2374 __ add(dst_ptr, tmp, dst_ptr); | |
2375 } | |
2376 | |
2446 | 2377 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; |
2378 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; | |
2379 const char *name; | |
2380 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); | |
2381 | |
2382 // arraycopy stubs takes a length in number of elements, so don't scale it. | |
2383 __ mov(length, len); | |
2384 __ call_VM_leaf(tmp, entry); | |
0 | 2385 |
2386 __ bind(*stub->continuation()); | |
2387 } | |
2388 | |
2389 | |
2390 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { | |
2391 if (dest->is_single_cpu()) { | |
2392 #ifdef _LP64 | |
2393 if (left->type() == T_OBJECT) { | |
2394 switch (code) { | |
2395 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break; | |
2396 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break; | |
2397 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break; | |
2398 default: ShouldNotReachHere(); | |
2399 } | |
2400 } else | |
2401 #endif | |
2402 switch (code) { | |
2403 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break; | |
2404 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break; | |
2405 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break; | |
2406 default: ShouldNotReachHere(); | |
2407 } | |
2408 } else { | |
2409 #ifdef _LP64 | |
2410 switch (code) { | |
2411 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; | |
2412 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; | |
2413 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; | |
2414 default: ShouldNotReachHere(); | |
2415 } | |
2416 #else | |
2417 switch (code) { | |
2418 case lir_shl: __ lshl (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; | |
2419 case lir_shr: __ lshr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; | |
2420 case lir_ushr: __ lushr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; | |
2421 default: ShouldNotReachHere(); | |
2422 } | |
2423 #endif | |
2424 } | |
2425 } | |
2426 | |
2427 | |
2428 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { | |
2429 #ifdef _LP64 | |
2430 if (left->type() == T_OBJECT) { | |
2431 count = count & 63; // shouldn't shift by more than sizeof(intptr_t) | |
2432 Register l = left->as_register(); | |
2433 Register d = dest->as_register_lo(); | |
2434 switch (code) { | |
2435 case lir_shl: __ sllx (l, count, d); break; | |
2436 case lir_shr: __ srax (l, count, d); break; | |
2437 case lir_ushr: __ srlx (l, count, d); break; | |
2438 default: ShouldNotReachHere(); | |
2439 } | |
2440 return; | |
2441 } | |
2442 #endif | |
2443 | |
2444 if (dest->is_single_cpu()) { | |
2445 count = count & 0x1F; // Java spec | |
2446 switch (code) { | |
2447 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break; | |
2448 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break; | |
2449 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break; | |
2450 default: ShouldNotReachHere(); | |
2451 } | |
2452 } else if (dest->is_double_cpu()) { | |
2453 count = count & 63; // Java spec | |
2454 switch (code) { | |
2455 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break; | |
2456 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break; | |
2457 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break; | |
2458 default: ShouldNotReachHere(); | |
2459 } | |
2460 } else { | |
2461 ShouldNotReachHere(); | |
2462 } | |
2463 } | |
2464 | |
2465 | |
2466 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { | |
2467 assert(op->tmp1()->as_register() == G1 && | |
2468 op->tmp2()->as_register() == G3 && | |
2469 op->tmp3()->as_register() == G4 && | |
2470 op->obj()->as_register() == O0 && | |
2471 op->klass()->as_register() == G5, "must be"); | |
2472 if (op->init_check()) { | |
2473 __ ld(op->klass()->as_register(), | |
2474 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc), | |
2475 op->tmp1()->as_register()); | |
2476 add_debug_info_for_null_check_here(op->stub()->info()); | |
2477 __ cmp(op->tmp1()->as_register(), instanceKlass::fully_initialized); | |
2478 __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry()); | |
2479 __ delayed()->nop(); | |
2480 } | |
2481 __ allocate_object(op->obj()->as_register(), | |
2482 op->tmp1()->as_register(), | |
2483 op->tmp2()->as_register(), | |
2484 op->tmp3()->as_register(), | |
2485 op->header_size(), | |
2486 op->object_size(), | |
2487 op->klass()->as_register(), | |
2488 *op->stub()->entry()); | |
2489 __ bind(*op->stub()->continuation()); | |
2490 __ verify_oop(op->obj()->as_register()); | |
2491 } | |
2492 | |
2493 | |
2494 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { | |
2495 assert(op->tmp1()->as_register() == G1 && | |
2496 op->tmp2()->as_register() == G3 && | |
2497 op->tmp3()->as_register() == G4 && | |
2498 op->tmp4()->as_register() == O1 && | |
2499 op->klass()->as_register() == G5, "must be"); | |
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2500 |
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2501 LP64_ONLY( __ signx(op->len()->as_register()); ) |
0 | 2502 if (UseSlowPath || |
2503 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || | |
2504 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { | |
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2505 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); |
0 | 2506 __ delayed()->nop(); |
2507 } else { | |
2508 __ allocate_array(op->obj()->as_register(), | |
2509 op->len()->as_register(), | |
2510 op->tmp1()->as_register(), | |
2511 op->tmp2()->as_register(), | |
2512 op->tmp3()->as_register(), | |
2513 arrayOopDesc::header_size(op->type()), | |
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2514 type2aelembytes(op->type()), |
0 | 2515 op->klass()->as_register(), |
2516 *op->stub()->entry()); | |
2517 } | |
2518 __ bind(*op->stub()->continuation()); | |
2519 } | |
2520 | |
2521 | |
1783 | 2522 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias, |
2523 ciMethodData *md, ciProfileData *data, | |
2524 Register recv, Register tmp1, Label* update_done) { | |
2525 uint i; | |
2526 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
2527 Label next_test; | |
2528 // See if the receiver is receiver[n]. | |
2529 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - | |
2530 mdo_offset_bias); | |
2531 __ ld_ptr(receiver_addr, tmp1); | |
2532 __ verify_oop(tmp1); | |
2533 __ cmp(recv, tmp1); | |
2534 __ brx(Assembler::notEqual, false, Assembler::pt, next_test); | |
2535 __ delayed()->nop(); | |
2536 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - | |
2537 mdo_offset_bias); | |
2538 __ ld_ptr(data_addr, tmp1); | |
2539 __ add(tmp1, DataLayout::counter_increment, tmp1); | |
2540 __ st_ptr(tmp1, data_addr); | |
2541 __ ba(false, *update_done); | |
2542 __ delayed()->nop(); | |
2543 __ bind(next_test); | |
2544 } | |
2545 | |
2546 // Didn't find receiver; find next empty slot and fill it in | |
2547 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
2548 Label next_test; | |
2549 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - | |
2550 mdo_offset_bias); | |
2002 | 2551 __ ld_ptr(recv_addr, tmp1); |
1783 | 2552 __ br_notnull(tmp1, false, Assembler::pt, next_test); |
2553 __ delayed()->nop(); | |
2554 __ st_ptr(recv, recv_addr); | |
2555 __ set(DataLayout::counter_increment, tmp1); | |
2556 __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - | |
2557 mdo_offset_bias); | |
2558 __ ba(false, *update_done); | |
2559 __ delayed()->nop(); | |
2560 __ bind(next_test); | |
2561 } | |
2562 } | |
2563 | |
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2564 |
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2565 void LIR_Assembler::setup_md_access(ciMethod* method, int bci, |
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2566 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) { |
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2567 md = method->method_data_or_null(); |
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2568 assert(md != NULL, "Sanity"); |
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2569 data = md->bci_to_data(bci); |
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2570 assert(data != NULL, "need data for checkcast"); |
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2571 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); |
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2572 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) { |
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2573 // The offset is large so bias the mdo by the base of the slot so |
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2574 // that the ld can use simm13s to reference the slots of the data |
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2575 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset()); |
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2576 } |
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2577 } |
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2578 |
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2579 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { |
1783 | 2580 // we always need a stub for the failure case. |
2581 CodeStub* stub = op->stub(); | |
2582 Register obj = op->object()->as_register(); | |
2583 Register k_RInfo = op->tmp1()->as_register(); | |
2584 Register klass_RInfo = op->tmp2()->as_register(); | |
2585 Register dst = op->result_opr()->as_register(); | |
2586 Register Rtmp1 = op->tmp3()->as_register(); | |
2587 ciKlass* k = op->klass(); | |
2588 | |
2589 | |
2590 if (obj == k_RInfo) { | |
2591 k_RInfo = klass_RInfo; | |
2592 klass_RInfo = obj; | |
2593 } | |
2594 | |
2595 ciMethodData* md; | |
2596 ciProfileData* data; | |
2597 int mdo_offset_bias = 0; | |
2598 if (op->should_profile()) { | |
2599 ciMethod* method = op->profiled_method(); | |
2600 assert(method != NULL, "Should have method"); | |
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2601 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias); |
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2602 |
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2603 Label not_null; |
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2604 __ br_notnull(obj, false, Assembler::pn, not_null); |
1783 | 2605 __ delayed()->nop(); |
2606 Register mdo = k_RInfo; | |
2607 Register data_val = Rtmp1; | |
2608 jobject2reg(md->constant_encoding(), mdo); | |
2609 if (mdo_offset_bias > 0) { | |
2610 __ set(mdo_offset_bias, data_val); | |
2611 __ add(mdo, data_val, mdo); | |
2612 } | |
2613 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias); | |
2614 __ ldub(flags_addr, data_val); | |
2615 __ or3(data_val, BitData::null_seen_byte_constant(), data_val); | |
2616 __ stb(data_val, flags_addr); | |
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2617 __ ba(false, *obj_is_null); |
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2618 __ delayed()->nop(); |
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2619 __ bind(not_null); |
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2620 } else { |
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2621 __ br_null(obj, false, Assembler::pn, *obj_is_null); |
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2622 __ delayed()->nop(); |
1783 | 2623 } |
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2624 |
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2625 Label profile_cast_failure, profile_cast_success; |
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2626 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; |
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2627 Label *success_target = op->should_profile() ? &profile_cast_success : success; |
1783 | 2628 |
2629 // patching may screw with our temporaries on sparc, | |
2630 // so let's do it before loading the class | |
2631 if (k->is_loaded()) { | |
2632 jobject2reg(k->constant_encoding(), k_RInfo); | |
2633 } else { | |
2634 jobject2reg_with_patching(k_RInfo, op->info_for_patch()); | |
2635 } | |
2636 assert(obj != k_RInfo, "must be different"); | |
2637 | |
2638 // get object class | |
2639 // not a safepoint as obj null check happens earlier | |
2002 | 2640 __ load_klass(obj, klass_RInfo); |
1783 | 2641 if (op->fast_check()) { |
2642 assert_different_registers(klass_RInfo, k_RInfo); | |
2643 __ cmp(k_RInfo, klass_RInfo); | |
2644 __ brx(Assembler::notEqual, false, Assembler::pt, *failure_target); | |
2645 __ delayed()->nop(); | |
2646 } else { | |
2647 bool need_slow_path = true; | |
2648 if (k->is_loaded()) { | |
2649 if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()) | |
2650 need_slow_path = false; | |
2651 // perform the fast part of the checking logic | |
2652 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg, | |
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2653 (need_slow_path ? success_target : NULL), |
1783 | 2654 failure_target, NULL, |
2655 RegisterOrConstant(k->super_check_offset())); | |
2656 } else { | |
2657 // perform the fast part of the checking logic | |
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2658 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, |
1783 | 2659 failure_target, NULL); |
2660 } | |
2661 if (need_slow_path) { | |
2662 // call out-of-line instance of __ check_klass_subtype_slow_path(...): | |
2663 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup"); | |
2664 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); | |
2665 __ delayed()->nop(); | |
2666 __ cmp(G3, 0); | |
2667 __ br(Assembler::equal, false, Assembler::pn, *failure_target); | |
2668 __ delayed()->nop(); | |
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2669 // Fall through to success case |
1783 | 2670 } |
2671 } | |
2672 | |
2673 if (op->should_profile()) { | |
2674 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1; | |
2675 assert_different_registers(obj, mdo, recv, tmp1); | |
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2676 __ bind(profile_cast_success); |
1783 | 2677 jobject2reg(md->constant_encoding(), mdo); |
2678 if (mdo_offset_bias > 0) { | |
2679 __ set(mdo_offset_bias, tmp1); | |
2680 __ add(mdo, tmp1, mdo); | |
2681 } | |
2002 | 2682 __ load_klass(obj, recv); |
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2683 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success); |
1783 | 2684 // Jump over the failure case |
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2685 __ ba(false, *success); |
1783 | 2686 __ delayed()->nop(); |
2687 // Cast failure case | |
2688 __ bind(profile_cast_failure); | |
2689 jobject2reg(md->constant_encoding(), mdo); | |
2690 if (mdo_offset_bias > 0) { | |
2691 __ set(mdo_offset_bias, tmp1); | |
2692 __ add(mdo, tmp1, mdo); | |
2693 } | |
2694 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); | |
2695 __ ld_ptr(data_addr, tmp1); | |
2696 __ sub(tmp1, DataLayout::counter_increment, tmp1); | |
2697 __ st_ptr(tmp1, data_addr); | |
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2698 __ ba(false, *failure); |
1783 | 2699 __ delayed()->nop(); |
2700 } | |
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2701 __ ba(false, *success); |
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2702 __ delayed()->nop(); |
1783 | 2703 } |
2704 | |
0 | 2705 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { |
2706 LIR_Code code = op->code(); | |
2707 if (code == lir_store_check) { | |
2708 Register value = op->object()->as_register(); | |
2709 Register array = op->array()->as_register(); | |
2710 Register k_RInfo = op->tmp1()->as_register(); | |
2711 Register klass_RInfo = op->tmp2()->as_register(); | |
2712 Register Rtmp1 = op->tmp3()->as_register(); | |
2713 | |
2714 __ verify_oop(value); | |
2715 CodeStub* stub = op->stub(); | |
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2716 // check if it needs to be profiled |
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2717 ciMethodData* md; |
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2718 ciProfileData* data; |
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2719 int mdo_offset_bias = 0; |
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2720 if (op->should_profile()) { |
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2721 ciMethod* method = op->profiled_method(); |
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2722 assert(method != NULL, "Should have method"); |
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2723 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias); |
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2724 } |
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2725 Label profile_cast_success, profile_cast_failure, done; |
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2726 Label *success_target = op->should_profile() ? &profile_cast_success : &done; |
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2727 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); |
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2728 |
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2729 if (op->should_profile()) { |
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2730 Label not_null; |
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2731 __ br_notnull(value, false, Assembler::pn, not_null); |
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2732 __ delayed()->nop(); |
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2733 Register mdo = k_RInfo; |
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2734 Register data_val = Rtmp1; |
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2735 jobject2reg(md->constant_encoding(), mdo); |
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2736 if (mdo_offset_bias > 0) { |
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2737 __ set(mdo_offset_bias, data_val); |
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2738 __ add(mdo, data_val, mdo); |
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2739 } |
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2740 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias); |
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2741 __ ldub(flags_addr, data_val); |
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2742 __ or3(data_val, BitData::null_seen_byte_constant(), data_val); |
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2743 __ stb(data_val, flags_addr); |
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2744 __ ba(false, done); |
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2745 __ delayed()->nop(); |
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2746 __ bind(not_null); |
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2747 } else { |
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2748 __ br_null(value, false, Assembler::pn, done); |
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2749 __ delayed()->nop(); |
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2750 } |
2002 | 2751 add_debug_info_for_null_check_here(op->info_for_exception()); |
2752 __ load_klass(array, k_RInfo); | |
2753 __ load_klass(value, klass_RInfo); | |
0 | 2754 |
2755 // get instance klass | |
2002 | 2756 __ ld_ptr(Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc)), k_RInfo); |
644
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2757 // perform the fast part of the checking logic |
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2758 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, failure_target, NULL); |
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2759 |
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2760 // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
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2761 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup"); |
0 | 2762 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); |
2763 __ delayed()->nop(); | |
2764 __ cmp(G3, 0); | |
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2765 __ br(Assembler::equal, false, Assembler::pn, *failure_target); |
0 | 2766 __ delayed()->nop(); |
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2767 // fall through to the success case |
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2768 |
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2769 if (op->should_profile()) { |
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2770 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1; |
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2771 assert_different_registers(value, mdo, recv, tmp1); |
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2772 __ bind(profile_cast_success); |
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2773 jobject2reg(md->constant_encoding(), mdo); |
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2774 if (mdo_offset_bias > 0) { |
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2775 __ set(mdo_offset_bias, tmp1); |
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2776 __ add(mdo, tmp1, mdo); |
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2777 } |
2002 | 2778 __ load_klass(value, recv); |
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2779 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done); |
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2780 __ ba(false, done); |
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2781 __ delayed()->nop(); |
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2782 // Cast failure case |
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2783 __ bind(profile_cast_failure); |
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2784 jobject2reg(md->constant_encoding(), mdo); |
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2785 if (mdo_offset_bias > 0) { |
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2786 __ set(mdo_offset_bias, tmp1); |
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2787 __ add(mdo, tmp1, mdo); |
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2788 } |
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2789 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); |
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2790 __ ld_ptr(data_addr, tmp1); |
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2791 __ sub(tmp1, DataLayout::counter_increment, tmp1); |
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2792 __ st_ptr(tmp1, data_addr); |
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2793 __ ba(false, *stub->entry()); |
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2794 __ delayed()->nop(); |
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2795 } |
0 | 2796 __ bind(done); |
1791
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2797 } else if (code == lir_checkcast) { |
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2798 Register obj = op->object()->as_register(); |
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2799 Register dst = op->result_opr()->as_register(); |
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2800 Label success; |
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2801 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); |
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2802 __ bind(success); |
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2803 __ mov(obj, dst); |
0 | 2804 } else if (code == lir_instanceof) { |
2805 Register obj = op->object()->as_register(); | |
2806 Register dst = op->result_opr()->as_register(); | |
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2807 Label success, failure, done; |
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2808 emit_typecheck_helper(op, &success, &failure, &failure); |
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2809 __ bind(failure); |
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2810 __ set(0, dst); |
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2811 __ ba(false, done); |
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2812 __ delayed()->nop(); |
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2813 __ bind(success); |
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2814 __ set(1, dst); |
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2815 __ bind(done); |
0 | 2816 } else { |
2817 ShouldNotReachHere(); | |
2818 } | |
2819 | |
2820 } | |
2821 | |
2822 | |
2823 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { | |
2824 if (op->code() == lir_cas_long) { | |
2825 assert(VM_Version::supports_cx8(), "wrong machine"); | |
2826 Register addr = op->addr()->as_pointer_register(); | |
2827 Register cmp_value_lo = op->cmp_value()->as_register_lo(); | |
2828 Register cmp_value_hi = op->cmp_value()->as_register_hi(); | |
2829 Register new_value_lo = op->new_value()->as_register_lo(); | |
2830 Register new_value_hi = op->new_value()->as_register_hi(); | |
2831 Register t1 = op->tmp1()->as_register(); | |
2832 Register t2 = op->tmp2()->as_register(); | |
2833 #ifdef _LP64 | |
2834 __ mov(cmp_value_lo, t1); | |
2835 __ mov(new_value_lo, t2); | |
2089
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7009231: C1: Incorrect CAS code for longs on SPARC 32bit
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2010
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changeset
|
2836 // perform the compare and swap operation |
037c727f35fb
7009231: C1: Incorrect CAS code for longs on SPARC 32bit
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2010
diff
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|
2837 __ casx(addr, t1, t2); |
037c727f35fb
7009231: C1: Incorrect CAS code for longs on SPARC 32bit
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2010
diff
changeset
|
2838 // generate condition code - if the swap succeeded, t2 ("new value" reg) was |
037c727f35fb
7009231: C1: Incorrect CAS code for longs on SPARC 32bit
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2010
diff
changeset
|
2839 // overwritten with the original value in "addr" and will be equal to t1. |
037c727f35fb
7009231: C1: Incorrect CAS code for longs on SPARC 32bit
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2010
diff
changeset
|
2840 __ cmp(t1, t2); |
0 | 2841 #else |
2842 // move high and low halves of long values into single registers | |
2843 __ sllx(cmp_value_hi, 32, t1); // shift high half into temp reg | |
2844 __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half | |
2845 __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value | |
2846 __ sllx(new_value_hi, 32, t2); | |
2847 __ srl(new_value_lo, 0, new_value_lo); | |
2848 __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap | |
2849 // perform the compare and swap operation | |
2850 __ casx(addr, t1, t2); | |
2851 // generate condition code - if the swap succeeded, t2 ("new value" reg) was | |
2852 // overwritten with the original value in "addr" and will be equal to t1. | |
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037c727f35fb
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2010
diff
changeset
|
2853 // Produce icc flag for 32bit. |
037c727f35fb
7009231: C1: Incorrect CAS code for longs on SPARC 32bit
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2010
diff
changeset
|
2854 __ sub(t1, t2, t2); |
037c727f35fb
7009231: C1: Incorrect CAS code for longs on SPARC 32bit
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2010
diff
changeset
|
2855 __ srlx(t2, 32, t1); |
037c727f35fb
7009231: C1: Incorrect CAS code for longs on SPARC 32bit
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2010
diff
changeset
|
2856 __ orcc(t2, t1, G0); |
037c727f35fb
7009231: C1: Incorrect CAS code for longs on SPARC 32bit
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2857 #endif |
0 | 2858 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) { |
2859 Register addr = op->addr()->as_pointer_register(); | |
2860 Register cmp_value = op->cmp_value()->as_register(); | |
2861 Register new_value = op->new_value()->as_register(); | |
2862 Register t1 = op->tmp1()->as_register(); | |
2863 Register t2 = op->tmp2()->as_register(); | |
2864 __ mov(cmp_value, t1); | |
2865 __ mov(new_value, t2); | |
2866 if (op->code() == lir_cas_obj) { | |
2002 | 2867 if (UseCompressedOops) { |
2868 __ encode_heap_oop(t1); | |
2869 __ encode_heap_oop(t2); | |
0 | 2870 __ cas(addr, t1, t2); |
2002 | 2871 } else { |
2010 | 2872 __ cas_ptr(addr, t1, t2); |
0 | 2873 } |
2002 | 2874 } else { |
2875 __ cas(addr, t1, t2); | |
2876 } | |
0 | 2877 __ cmp(t1, t2); |
2878 } else { | |
2879 Unimplemented(); | |
2880 } | |
2881 } | |
2882 | |
2883 void LIR_Assembler::set_24bit_FPU() { | |
2884 Unimplemented(); | |
2885 } | |
2886 | |
2887 | |
2888 void LIR_Assembler::reset_FPU() { | |
2889 Unimplemented(); | |
2890 } | |
2891 | |
2892 | |
2893 void LIR_Assembler::breakpoint() { | |
2894 __ breakpoint_trap(); | |
2895 } | |
2896 | |
2897 | |
2898 void LIR_Assembler::push(LIR_Opr opr) { | |
2899 Unimplemented(); | |
2900 } | |
2901 | |
2902 | |
2903 void LIR_Assembler::pop(LIR_Opr opr) { | |
2904 Unimplemented(); | |
2905 } | |
2906 | |
2907 | |
2908 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) { | |
2909 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no); | |
2910 Register dst = dst_opr->as_register(); | |
2911 Register reg = mon_addr.base(); | |
2912 int offset = mon_addr.disp(); | |
2913 // compute pointer to BasicLock | |
2914 if (mon_addr.is_simm13()) { | |
2915 __ add(reg, offset, dst); | |
2916 } else { | |
2917 __ set(offset, dst); | |
2918 __ add(dst, reg, dst); | |
2919 } | |
2920 } | |
2921 | |
2922 | |
2923 void LIR_Assembler::emit_lock(LIR_OpLock* op) { | |
2924 Register obj = op->obj_opr()->as_register(); | |
2925 Register hdr = op->hdr_opr()->as_register(); | |
2926 Register lock = op->lock_opr()->as_register(); | |
2927 | |
2928 // obj may not be an oop | |
2929 if (op->code() == lir_lock) { | |
2930 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub(); | |
2931 if (UseFastLocking) { | |
2932 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
2933 // add debug info for NullPointerException only if one is possible | |
2934 if (op->info() != NULL) { | |
2935 add_debug_info_for_null_check_here(op->info()); | |
2936 } | |
2937 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry()); | |
2938 } else { | |
2939 // always do slow locking | |
2940 // note: the slow locking code could be inlined here, however if we use | |
2941 // slow locking, speed doesn't matter anyway and this solution is | |
2942 // simpler and requires less duplicated code - additionally, the | |
2943 // slow locking code is the same in either case which simplifies | |
2944 // debugging | |
2945 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); | |
2946 __ delayed()->nop(); | |
2947 } | |
2948 } else { | |
2949 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock"); | |
2950 if (UseFastLocking) { | |
2951 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
2952 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); | |
2953 } else { | |
2954 // always do slow unlocking | |
2955 // note: the slow unlocking code could be inlined here, however if we use | |
2956 // slow unlocking, speed doesn't matter anyway and this solution is | |
2957 // simpler and requires less duplicated code - additionally, the | |
2958 // slow unlocking code is the same in either case which simplifies | |
2959 // debugging | |
2960 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); | |
2961 __ delayed()->nop(); | |
2962 } | |
2963 } | |
2964 __ bind(*op->stub()->continuation()); | |
2965 } | |
2966 | |
2967 | |
2968 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { | |
2969 ciMethod* method = op->profiled_method(); | |
2970 int bci = op->profiled_bci(); | |
2971 | |
2972 // Update counter for all call types | |
2007
5ddfcf4b079e
7003554: (tiered) assert(is_null_object() || handle() != NULL) failed: cannot embed null pointer
iveresov
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2002
diff
changeset
|
2973 ciMethodData* md = method->method_data_or_null(); |
5ddfcf4b079e
7003554: (tiered) assert(is_null_object() || handle() != NULL) failed: cannot embed null pointer
iveresov
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diff
changeset
|
2974 assert(md != NULL, "Sanity"); |
0 | 2975 ciProfileData* data = md->bci_to_data(bci); |
2976 assert(data->is_CounterData(), "need CounterData for calls"); | |
2977 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); | |
1783 | 2978 Register mdo = op->mdo()->as_register(); |
2979 #ifdef _LP64 | |
2980 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated"); | |
2981 Register tmp1 = op->tmp1()->as_register_lo(); | |
2982 #else | |
0 | 2983 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated"); |
2984 Register tmp1 = op->tmp1()->as_register(); | |
1783 | 2985 #endif |
989
148e5441d916
6863023: need non-perm oops in code cache for JSR 292
jrose
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780
diff
changeset
|
2986 jobject2reg(md->constant_encoding(), mdo); |
0 | 2987 int mdo_offset_bias = 0; |
2988 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) + | |
2989 data->size_in_bytes())) { | |
2990 // The offset is large so bias the mdo by the base of the slot so | |
2991 // that the ld can use simm13s to reference the slots of the data | |
2992 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset()); | |
2993 __ set(mdo_offset_bias, O7); | |
2994 __ add(mdo, O7, mdo); | |
2995 } | |
2996 | |
727 | 2997 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); |
0 | 2998 Bytecodes::Code bc = method->java_code_at_bci(bci); |
2999 // Perform additional virtual call profiling for invokevirtual and | |
3000 // invokeinterface bytecodes | |
3001 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && | |
1783 | 3002 C1ProfileVirtualCalls) { |
0 | 3003 assert(op->recv()->is_single_cpu(), "recv must be allocated"); |
3004 Register recv = op->recv()->as_register(); | |
3005 assert_different_registers(mdo, tmp1, recv); | |
3006 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); | |
3007 ciKlass* known_klass = op->known_holder(); | |
1783 | 3008 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { |
0 | 3009 // We know the type that will be seen at this call site; we can |
3010 // statically update the methodDataOop rather than needing to do | |
3011 // dynamic tests on the receiver type | |
3012 | |
3013 // NOTE: we should probably put a lock around this search to | |
3014 // avoid collisions by concurrent compilations | |
3015 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; | |
3016 uint i; | |
3017 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
3018 ciKlass* receiver = vc_data->receiver(i); | |
3019 if (known_klass->equals(receiver)) { | |
727 | 3020 Address data_addr(mdo, md->byte_offset_of_slot(data, |
3021 VirtualCallData::receiver_count_offset(i)) - | |
0 | 3022 mdo_offset_bias); |
1783 | 3023 __ ld_ptr(data_addr, tmp1); |
0 | 3024 __ add(tmp1, DataLayout::counter_increment, tmp1); |
1783 | 3025 __ st_ptr(tmp1, data_addr); |
0 | 3026 return; |
3027 } | |
3028 } | |
3029 | |
3030 // Receiver type not found in profile data; select an empty slot | |
3031 | |
3032 // Note that this is less efficient than it should be because it | |
3033 // always does a write to the receiver part of the | |
3034 // VirtualCallData rather than just the first time | |
3035 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
3036 ciKlass* receiver = vc_data->receiver(i); | |
3037 if (receiver == NULL) { | |
727 | 3038 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - |
0 | 3039 mdo_offset_bias); |
989
148e5441d916
6863023: need non-perm oops in code cache for JSR 292
jrose
parents:
780
diff
changeset
|
3040 jobject2reg(known_klass->constant_encoding(), tmp1); |
0 | 3041 __ st_ptr(tmp1, recv_addr); |
727 | 3042 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - |
0 | 3043 mdo_offset_bias); |
1783 | 3044 __ ld_ptr(data_addr, tmp1); |
0 | 3045 __ add(tmp1, DataLayout::counter_increment, tmp1); |
1783 | 3046 __ st_ptr(tmp1, data_addr); |
0 | 3047 return; |
3048 } | |
3049 } | |
3050 } else { | |
2002 | 3051 __ load_klass(recv, recv); |
0 | 3052 Label update_done; |
1783 | 3053 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done); |
1251
576e77447e3c
6923002: assert(false,"this call site should not be polymorphic")
kvn
parents:
1204
diff
changeset
|
3054 // Receiver did not match any saved receiver and there is no empty row for it. |
576e77447e3c
6923002: assert(false,"this call site should not be polymorphic")
kvn
parents:
1204
diff
changeset
|
3055 // Increment total counter to indicate polymorphic case. |
1783 | 3056 __ ld_ptr(counter_addr, tmp1); |
1251
576e77447e3c
6923002: assert(false,"this call site should not be polymorphic")
kvn
parents:
1204
diff
changeset
|
3057 __ add(tmp1, DataLayout::counter_increment, tmp1); |
1783 | 3058 __ st_ptr(tmp1, counter_addr); |
0 | 3059 |
3060 __ bind(update_done); | |
3061 } | |
1251
576e77447e3c
6923002: assert(false,"this call site should not be polymorphic")
kvn
parents:
1204
diff
changeset
|
3062 } else { |
576e77447e3c
6923002: assert(false,"this call site should not be polymorphic")
kvn
parents:
1204
diff
changeset
|
3063 // Static call |
1783 | 3064 __ ld_ptr(counter_addr, tmp1); |
1251
576e77447e3c
6923002: assert(false,"this call site should not be polymorphic")
kvn
parents:
1204
diff
changeset
|
3065 __ add(tmp1, DataLayout::counter_increment, tmp1); |
1783 | 3066 __ st_ptr(tmp1, counter_addr); |
0 | 3067 } |
3068 } | |
3069 | |
3070 void LIR_Assembler::align_backward_branch_target() { | |
1365 | 3071 __ align(OptoLoopAlignment); |
0 | 3072 } |
3073 | |
3074 | |
3075 void LIR_Assembler::emit_delay(LIR_OpDelay* op) { | |
3076 // make sure we are expecting a delay | |
3077 // this has the side effect of clearing the delay state | |
3078 // so we can use _masm instead of _masm->delayed() to do the | |
3079 // code generation. | |
3080 __ delayed(); | |
3081 | |
3082 // make sure we only emit one instruction | |
3083 int offset = code_offset(); | |
3084 op->delay_op()->emit_code(this); | |
3085 #ifdef ASSERT | |
3086 if (code_offset() - offset != NativeInstruction::nop_instruction_size) { | |
3087 op->delay_op()->print(); | |
3088 } | |
3089 assert(code_offset() - offset == NativeInstruction::nop_instruction_size, | |
3090 "only one instruction can go in a delay slot"); | |
3091 #endif | |
3092 | |
3093 // we may also be emitting the call info for the instruction | |
3094 // which we are the delay slot of. | |
1564 | 3095 CodeEmitInfo* call_info = op->call_info(); |
0 | 3096 if (call_info) { |
3097 add_call_info(code_offset(), call_info); | |
3098 } | |
3099 | |
3100 if (VerifyStackAtCalls) { | |
3101 _masm->sub(FP, SP, O7); | |
3102 _masm->cmp(O7, initial_frame_size_in_bytes()); | |
3103 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 ); | |
3104 } | |
3105 } | |
3106 | |
3107 | |
3108 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { | |
3109 assert(left->is_register(), "can only handle registers"); | |
3110 | |
3111 if (left->is_single_cpu()) { | |
3112 __ neg(left->as_register(), dest->as_register()); | |
3113 } else if (left->is_single_fpu()) { | |
3114 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg()); | |
3115 } else if (left->is_double_fpu()) { | |
3116 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg()); | |
3117 } else { | |
3118 assert (left->is_double_cpu(), "Must be a long"); | |
3119 Register Rlow = left->as_register_lo(); | |
3120 Register Rhi = left->as_register_hi(); | |
3121 #ifdef _LP64 | |
3122 __ sub(G0, Rlow, dest->as_register_lo()); | |
3123 #else | |
3124 __ subcc(G0, Rlow, dest->as_register_lo()); | |
3125 __ subc (G0, Rhi, dest->as_register_hi()); | |
3126 #endif | |
3127 } | |
3128 } | |
3129 | |
3130 | |
3131 void LIR_Assembler::fxch(int i) { | |
3132 Unimplemented(); | |
3133 } | |
3134 | |
3135 void LIR_Assembler::fld(int i) { | |
3136 Unimplemented(); | |
3137 } | |
3138 | |
3139 void LIR_Assembler::ffree(int i) { | |
3140 Unimplemented(); | |
3141 } | |
3142 | |
3143 void LIR_Assembler::rt_call(LIR_Opr result, address dest, | |
3144 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { | |
3145 | |
3146 // if tmp is invalid, then the function being called doesn't destroy the thread | |
3147 if (tmp->is_valid()) { | |
3148 __ save_thread(tmp->as_register()); | |
3149 } | |
3150 __ call(dest, relocInfo::runtime_call_type); | |
3151 __ delayed()->nop(); | |
3152 if (info != NULL) { | |
3153 add_call_info_here(info); | |
3154 } | |
3155 if (tmp->is_valid()) { | |
3156 __ restore_thread(tmp->as_register()); | |
3157 } | |
3158 | |
3159 #ifdef ASSERT | |
3160 __ verify_thread(); | |
3161 #endif // ASSERT | |
3162 } | |
3163 | |
3164 | |
3165 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { | |
3166 #ifdef _LP64 | |
3167 ShouldNotReachHere(); | |
3168 #endif | |
3169 | |
3170 NEEDS_CLEANUP; | |
3171 if (type == T_LONG) { | |
3172 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr(); | |
3173 | |
3174 // (extended to allow indexed as well as constant displaced for JSR-166) | |
3175 Register idx = noreg; // contains either constant offset or index | |
3176 | |
3177 int disp = mem_addr->disp(); | |
3178 if (mem_addr->index() == LIR_OprFact::illegalOpr) { | |
3179 if (!Assembler::is_simm13(disp)) { | |
3180 idx = O7; | |
3181 __ set(disp, idx); | |
3182 } | |
3183 } else { | |
3184 assert(disp == 0, "not both indexed and disp"); | |
3185 idx = mem_addr->index()->as_register(); | |
3186 } | |
3187 | |
3188 int null_check_offset = -1; | |
3189 | |
3190 Register base = mem_addr->base()->as_register(); | |
3191 if (src->is_register() && dest->is_address()) { | |
3192 // G4 is high half, G5 is low half | |
3193 if (VM_Version::v9_instructions_work()) { | |
3194 // clear the top bits of G5, and scale up G4 | |
3195 __ srl (src->as_register_lo(), 0, G5); | |
3196 __ sllx(src->as_register_hi(), 32, G4); | |
3197 // combine the two halves into the 64 bits of G4 | |
3198 __ or3(G4, G5, G4); | |
3199 null_check_offset = __ offset(); | |
3200 if (idx == noreg) { | |
3201 __ stx(G4, base, disp); | |
3202 } else { | |
3203 __ stx(G4, base, idx); | |
3204 } | |
3205 } else { | |
3206 __ mov (src->as_register_hi(), G4); | |
3207 __ mov (src->as_register_lo(), G5); | |
3208 null_check_offset = __ offset(); | |
3209 if (idx == noreg) { | |
3210 __ std(G4, base, disp); | |
3211 } else { | |
3212 __ std(G4, base, idx); | |
3213 } | |
3214 } | |
3215 } else if (src->is_address() && dest->is_register()) { | |
3216 null_check_offset = __ offset(); | |
3217 if (VM_Version::v9_instructions_work()) { | |
3218 if (idx == noreg) { | |
3219 __ ldx(base, disp, G5); | |
3220 } else { | |
3221 __ ldx(base, idx, G5); | |
3222 } | |
3223 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi | |
3224 __ mov (G5, dest->as_register_lo()); // copy low half into lo | |
3225 } else { | |
3226 if (idx == noreg) { | |
3227 __ ldd(base, disp, G4); | |
3228 } else { | |
3229 __ ldd(base, idx, G4); | |
3230 } | |
3231 // G4 is high half, G5 is low half | |
3232 __ mov (G4, dest->as_register_hi()); | |
3233 __ mov (G5, dest->as_register_lo()); | |
3234 } | |
3235 } else { | |
3236 Unimplemented(); | |
3237 } | |
3238 if (info != NULL) { | |
3239 add_debug_info_for_null_check(null_check_offset, info); | |
3240 } | |
3241 | |
3242 } else { | |
3243 // use normal move for all other volatiles since they don't need | |
3244 // special handling to remain atomic. | |
2002 | 3245 move_op(src, dest, type, lir_patch_none, info, false, false, false); |
0 | 3246 } |
3247 } | |
3248 | |
3249 void LIR_Assembler::membar() { | |
3250 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode | |
3251 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); | |
3252 } | |
3253 | |
3254 void LIR_Assembler::membar_acquire() { | |
3255 // no-op on TSO | |
3256 } | |
3257 | |
3258 void LIR_Assembler::membar_release() { | |
3259 // no-op on TSO | |
3260 } | |
3261 | |
1783 | 3262 // Pack two sequential registers containing 32 bit values |
0 | 3263 // into a single 64 bit register. |
1783 | 3264 // src and src->successor() are packed into dst |
3265 // src and dst may be the same register. | |
3266 // Note: src is destroyed | |
3267 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) { | |
3268 Register rs = src->as_register(); | |
3269 Register rd = dst->as_register_lo(); | |
0 | 3270 __ sllx(rs, 32, rs); |
3271 __ srl(rs->successor(), 0, rs->successor()); | |
3272 __ or3(rs, rs->successor(), rd); | |
3273 } | |
3274 | |
1783 | 3275 // Unpack a 64 bit value in a register into |
0 | 3276 // two sequential registers. |
1783 | 3277 // src is unpacked into dst and dst->successor() |
3278 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) { | |
3279 Register rs = src->as_register_lo(); | |
3280 Register rd = dst->as_register_hi(); | |
3281 assert_different_registers(rs, rd, rd->successor()); | |
3282 __ srlx(rs, 32, rd); | |
3283 __ srl (rs, 0, rd->successor()); | |
0 | 3284 } |
3285 | |
3286 | |
3287 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) { | |
3288 LIR_Address* addr = addr_opr->as_address_ptr(); | |
3289 assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1 && Assembler::is_simm13(addr->disp()), "can't handle complex addresses yet"); | |
1783 | 3290 |
3291 __ add(addr->base()->as_pointer_register(), addr->disp(), dest->as_pointer_register()); | |
0 | 3292 } |
3293 | |
3294 | |
3295 void LIR_Assembler::get_thread(LIR_Opr result_reg) { | |
3296 assert(result_reg->is_register(), "check"); | |
3297 __ mov(G2_thread, result_reg->as_register()); | |
3298 } | |
3299 | |
3300 | |
3301 void LIR_Assembler::peephole(LIR_List* lir) { | |
3302 LIR_OpList* inst = lir->instructions_list(); | |
3303 for (int i = 0; i < inst->length(); i++) { | |
3304 LIR_Op* op = inst->at(i); | |
3305 switch (op->code()) { | |
3306 case lir_cond_float_branch: | |
3307 case lir_branch: { | |
3308 LIR_OpBranch* branch = op->as_OpBranch(); | |
3309 assert(branch->info() == NULL, "shouldn't be state on branches anymore"); | |
3310 LIR_Op* delay_op = NULL; | |
3311 // we'd like to be able to pull following instructions into | |
3312 // this slot but we don't know enough to do it safely yet so | |
3313 // only optimize block to block control flow. | |
3314 if (LIRFillDelaySlots && branch->block()) { | |
3315 LIR_Op* prev = inst->at(i - 1); | |
3316 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) { | |
3317 // swap previous instruction into delay slot | |
3318 inst->at_put(i - 1, op); | |
3319 inst->at_put(i, new LIR_OpDelay(prev, op->info())); | |
3320 #ifndef PRODUCT | |
3321 if (LIRTracePeephole) { | |
3322 tty->print_cr("delayed"); | |
3323 inst->at(i - 1)->print(); | |
3324 inst->at(i)->print(); | |
1564 | 3325 tty->cr(); |
0 | 3326 } |
3327 #endif | |
3328 continue; | |
3329 } | |
3330 } | |
3331 | |
3332 if (!delay_op) { | |
3333 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL); | |
3334 } | |
3335 inst->insert_before(i + 1, delay_op); | |
3336 break; | |
3337 } | |
3338 case lir_static_call: | |
3339 case lir_virtual_call: | |
3340 case lir_icvirtual_call: | |
1564 | 3341 case lir_optvirtual_call: |
3342 case lir_dynamic_call: { | |
0 | 3343 LIR_Op* prev = inst->at(i - 1); |
3344 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL && | |
3345 (op->code() != lir_virtual_call || | |
3346 !prev->result_opr()->is_single_cpu() || | |
3347 prev->result_opr()->as_register() != O0) && | |
3348 LIR_Assembler::is_single_instruction(prev)) { | |
3349 // Only moves without info can be put into the delay slot. | |
3350 // Also don't allow the setup of the receiver in the delay | |
3351 // slot for vtable calls. | |
3352 inst->at_put(i - 1, op); | |
3353 inst->at_put(i, new LIR_OpDelay(prev, op->info())); | |
3354 #ifndef PRODUCT | |
3355 if (LIRTracePeephole) { | |
3356 tty->print_cr("delayed"); | |
3357 inst->at(i - 1)->print(); | |
3358 inst->at(i)->print(); | |
1564 | 3359 tty->cr(); |
0 | 3360 } |
3361 #endif | |
1783 | 3362 } else { |
3363 LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info()); | |
3364 inst->insert_before(i + 1, delay_op); | |
3365 i++; | |
0 | 3366 } |
3367 | |
1783 | 3368 #if defined(TIERED) && !defined(_LP64) |
3369 // fixup the return value from G1 to O0/O1 for long returns. | |
3370 // It's done here instead of in LIRGenerator because there's | |
3371 // such a mismatch between the single reg and double reg | |
3372 // calling convention. | |
3373 LIR_OpJavaCall* callop = op->as_OpJavaCall(); | |
3374 if (callop->result_opr() == FrameMap::out_long_opr) { | |
3375 LIR_OpJavaCall* call; | |
3376 LIR_OprList* arguments = new LIR_OprList(callop->arguments()->length()); | |
3377 for (int a = 0; a < arguments->length(); a++) { | |
3378 arguments[a] = callop->arguments()[a]; | |
3379 } | |
3380 if (op->code() == lir_virtual_call) { | |
3381 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr, | |
3382 callop->vtable_offset(), arguments, callop->info()); | |
3383 } else { | |
3384 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr, | |
3385 callop->addr(), arguments, callop->info()); | |
3386 } | |
3387 inst->at_put(i - 1, call); | |
3388 inst->insert_before(i + 1, new LIR_Op1(lir_unpack64, FrameMap::g1_long_single_opr, callop->result_opr(), | |
3389 T_LONG, lir_patch_none, NULL)); | |
3390 } | |
3391 #endif | |
0 | 3392 break; |
3393 } | |
3394 } | |
3395 } | |
3396 } | |
3397 | |
3398 | |
3399 | |
3400 | |
3401 #undef __ |