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1 /*
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337
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2 * Copyright 2005-2008 Sun Microsystems, Inc. All Rights Reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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20 * CA 95054 USA or visit www.sun.com if you need additional information or
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21 * have any questions.
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22 *
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23 */
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24
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25 inline bool LinearScan::is_processed_reg_num(int reg_num) {
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304
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26 #ifndef _LP64
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0
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27 // rsp and rbp (numbers 6 ancd 7) are ignored
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28 assert(FrameMap::rsp_opr->cpu_regnr() == 6, "wrong assumption below");
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29 assert(FrameMap::rbp_opr->cpu_regnr() == 7, "wrong assumption below");
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30 assert(reg_num >= 0, "invalid reg_num");
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31
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32 return reg_num < 6 || reg_num > 7;
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304
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33 #else
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34 // rsp and rbp, r10, r15 (numbers 6 ancd 7) are ignored
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35 assert(FrameMap::r10_opr->cpu_regnr() == 12, "wrong assumption below");
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36 assert(FrameMap::r15_opr->cpu_regnr() == 13, "wrong assumption below");
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37 assert(FrameMap::rsp_opr->cpu_regnrLo() == 14, "wrong assumption below");
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38 assert(FrameMap::rbp_opr->cpu_regnrLo() == 15, "wrong assumption below");
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39 assert(reg_num >= 0, "invalid reg_num");
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40
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41 return reg_num < 12 || reg_num > 15;
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42 #endif // _LP64
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0
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43 }
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44
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45 inline int LinearScan::num_physical_regs(BasicType type) {
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46 // Intel requires two cpu registers for long,
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47 // but requires only one fpu register for double
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304
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48 if (LP64_ONLY(false &&) type == T_LONG) {
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0
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49 return 2;
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50 }
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51 return 1;
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52 }
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53
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54
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55 inline bool LinearScan::requires_adjacent_regs(BasicType type) {
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56 return false;
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57 }
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58
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59 inline bool LinearScan::is_caller_save(int assigned_reg) {
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60 assert(assigned_reg >= 0 && assigned_reg < nof_regs, "should call this only for registers");
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61 return true; // no callee-saved registers on Intel
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62
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63 }
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64
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65
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66 inline void LinearScan::pd_add_temps(LIR_Op* op) {
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67 switch (op->code()) {
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68 case lir_tan:
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69 case lir_sin:
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70 case lir_cos: {
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71 // The slow path for these functions may need to save and
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72 // restore all live registers but we don't want to save and
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73 // restore everything all the time, so mark the xmms as being
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74 // killed. If the slow path were explicit or we could propagate
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75 // live register masks down to the assembly we could do better
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76 // but we don't have any easy way to do that right now. We
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77 // could also consider not killing all xmm registers if we
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78 // assume that slow paths are uncommon but it's not clear that
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79 // would be a good idea.
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80 if (UseSSE > 0) {
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81 #ifndef PRODUCT
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82 if (TraceLinearScanLevel >= 2) {
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83 tty->print_cr("killing XMMs for trig");
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84 }
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85 #endif
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86 int op_id = op->id();
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87 for (int xmm = 0; xmm < FrameMap::nof_caller_save_xmm_regs; xmm++) {
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88 LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(xmm);
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89 add_temp(reg_num(opr), op_id, noUse, T_ILLEGAL);
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90 }
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91 }
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92 break;
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93 }
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94 }
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95 }
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96
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97
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98 // Implementation of LinearScanWalker
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99
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100 inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur) {
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101 if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::byte_reg)) {
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102 assert(cur->type() != T_FLOAT && cur->type() != T_DOUBLE, "cpu regs only");
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103 _first_reg = pd_first_byte_reg;
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104 _last_reg = pd_last_byte_reg;
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105 return true;
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106 } else if ((UseSSE >= 1 && cur->type() == T_FLOAT) || (UseSSE >= 2 && cur->type() == T_DOUBLE)) {
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107 _first_reg = pd_first_xmm_reg;
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108 _last_reg = pd_last_xmm_reg;
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109 return true;
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110 }
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111
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112 return false;
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113 }
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114
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115
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116 class FpuStackAllocator VALUE_OBJ_CLASS_SPEC {
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117 private:
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118 Compilation* _compilation;
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119 LinearScan* _allocator;
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120
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121 LIR_OpVisitState visitor;
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122
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123 LIR_List* _lir;
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124 int _pos;
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125 FpuStackSim _sim;
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126 FpuStackSim _temp_sim;
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127
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128 bool _debug_information_computed;
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129
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130 LinearScan* allocator() { return _allocator; }
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131 Compilation* compilation() const { return _compilation; }
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132
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133 // unified bailout support
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134 void bailout(const char* msg) const { compilation()->bailout(msg); }
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135 bool bailed_out() const { return compilation()->bailed_out(); }
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136
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137 int pos() { return _pos; }
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138 void set_pos(int pos) { _pos = pos; }
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139 LIR_Op* cur_op() { return lir()->instructions_list()->at(pos()); }
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140 LIR_List* lir() { return _lir; }
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141 void set_lir(LIR_List* lir) { _lir = lir; }
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142 FpuStackSim* sim() { return &_sim; }
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143 FpuStackSim* temp_sim() { return &_temp_sim; }
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144
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145 int fpu_num(LIR_Opr opr);
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146 int tos_offset(LIR_Opr opr);
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147 LIR_Opr to_fpu_stack_top(LIR_Opr opr, bool dont_check_offset = false);
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148
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149 // Helper functions for handling operations
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150 void insert_op(LIR_Op* op);
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151 void insert_exchange(int offset);
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152 void insert_exchange(LIR_Opr opr);
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153 void insert_free(int offset);
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154 void insert_free_if_dead(LIR_Opr opr);
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155 void insert_free_if_dead(LIR_Opr opr, LIR_Opr ignore);
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156 void insert_copy(LIR_Opr from, LIR_Opr to);
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157 void do_rename(LIR_Opr from, LIR_Opr to);
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158 void do_push(LIR_Opr opr);
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159 void pop_if_last_use(LIR_Op* op, LIR_Opr opr);
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160 void pop_always(LIR_Op* op, LIR_Opr opr);
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161 void clear_fpu_stack(LIR_Opr preserve);
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162 void handle_op1(LIR_Op1* op1);
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163 void handle_op2(LIR_Op2* op2);
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164 void handle_opCall(LIR_OpCall* opCall);
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165 void compute_debug_information(LIR_Op* op);
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166 void allocate_exception_handler(XHandler* xhandler);
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167 void allocate_block(BlockBegin* block);
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168
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169 #ifndef PRODUCT
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170 void check_invalid_lir_op(LIR_Op* op);
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171 #endif
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172
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173 // Helper functions for merging of fpu stacks
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174 void merge_insert_add(LIR_List* instrs, FpuStackSim* cur_sim, int reg);
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175 void merge_insert_xchg(LIR_List* instrs, FpuStackSim* cur_sim, int slot);
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176 void merge_insert_pop(LIR_List* instrs, FpuStackSim* cur_sim);
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177 bool merge_rename(FpuStackSim* cur_sim, FpuStackSim* sux_sim, int start_slot, int change_slot);
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178 void merge_fpu_stack(LIR_List* instrs, FpuStackSim* cur_sim, FpuStackSim* sux_sim);
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179 void merge_cleanup_fpu_stack(LIR_List* instrs, FpuStackSim* cur_sim, BitMap& live_fpu_regs);
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180 bool merge_fpu_stack_with_successors(BlockBegin* block);
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181
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182 public:
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183 LIR_Opr to_fpu_stack(LIR_Opr opr); // used by LinearScan for creation of debug information
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184
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185 FpuStackAllocator(Compilation* compilation, LinearScan* allocator);
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186 void allocate();
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187 };
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