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annotate src/os_cpu/aix_ppc/vm/orderAccess_aix_ppc.inline.hpp @ 14415:666e6ce3976c
8023038: PPC64 (part 15): Platform files for AIX/PPC64 support
Reviewed-by: kvn
author | simonis |
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date | Fri, 06 Sep 2013 20:16:09 +0200 |
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children | 67fa91961822 |
rev | line source |
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1 /* |
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2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
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3 * Copyright 2012, 2013 SAP AG. All rights reserved. |
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4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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5 * |
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6 * This code is free software; you can redistribute it and/or modify it |
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7 * under the terms of the GNU General Public License version 2 only, as |
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8 * published by the Free Software Foundation. |
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9 * |
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10 * This code is distributed in the hope that it will be useful, but WITHOUT |
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11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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13 * version 2 for more details (a copy is included in the LICENSE file that |
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14 * accompanied this code). |
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15 * |
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16 * You should have received a copy of the GNU General Public License version |
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17 * 2 along with this work; if not, write to the Free Software Foundation, |
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18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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19 * |
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20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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21 * or visit www.oracle.com if you need additional information or have any |
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22 * questions. |
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23 * |
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24 */ |
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25 |
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26 #ifndef OS_CPU_AIX_OJDKPPC_VM_ORDERACCESS_AIX_PPC_INLINE_HPP |
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27 #define OS_CPU_AIX_OJDKPPC_VM_ORDERACCESS_AIX_PPC_INLINE_HPP |
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28 |
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29 #include "runtime/orderAccess.hpp" |
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30 #include "vm_version_ppc.hpp" |
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31 |
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32 // Implementation of class OrderAccess. |
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33 |
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34 // |
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35 // Machine barrier instructions: |
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36 // |
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37 // - ppc_sync Two-way memory barrier, aka fence. |
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38 // - ppc_lwsync orders Store|Store, |
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39 // Load|Store, |
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40 // Load|Load, |
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41 // but not Store|Load |
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42 // - ppc_eieio orders Store|Store |
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43 // - ppc_isync Invalidates speculatively executed instructions, |
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44 // but isync may complete before storage accesses |
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45 // associated with instructions preceding isync have |
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46 // been performed. |
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47 // |
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48 // Semantic barrier instructions: |
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49 // (as defined in orderAccess.hpp) |
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50 // |
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51 // - ppc_release orders Store|Store, (maps to ppc_lwsync) |
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52 // Load|Store |
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53 // - ppc_acquire orders Load|Store, (maps to ppc_lwsync) |
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54 // Load|Load |
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55 // - ppc_fence orders Store|Store, (maps to ppc_sync) |
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56 // Load|Store, |
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57 // Load|Load, |
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58 // Store|Load |
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59 // |
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60 |
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61 #define inlasm_ppc_sync() __asm__ __volatile__ ("sync" : : : "memory"); |
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62 #define inlasm_ppc_lwsync() __asm__ __volatile__ ("lwsync" : : : "memory"); |
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63 #define inlasm_ppc_eieio() __asm__ __volatile__ ("eieio" : : : "memory"); |
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64 #define inlasm_ppc_isync() __asm__ __volatile__ ("isync" : : : "memory"); |
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65 #define inlasm_ppc_release() inlasm_ppc_lwsync(); |
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66 #define inlasm_ppc_acquire() inlasm_ppc_lwsync(); |
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67 // Use twi-isync for load_acquire (faster than lwsync). |
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68 // ATTENTION: seems like xlC 10.1 has problems with this inline assembler macro (VerifyMethodHandles found "bad vminfo in AMH.conv"): |
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69 // #define inlasm_ppc_acquire_reg(X) __asm__ __volatile__ ("twi 0,%0,0\n isync\n" : : "r" (X) : "memory"); |
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70 #define inlasm_ppc_acquire_reg(X) inlasm_ppc_lwsync(); |
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71 #define inlasm_ppc_fence() inlasm_ppc_sync(); |
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72 |
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73 inline void OrderAccess::loadload() { inlasm_ppc_lwsync(); } |
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74 inline void OrderAccess::storestore() { inlasm_ppc_lwsync(); } |
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75 inline void OrderAccess::loadstore() { inlasm_ppc_lwsync(); } |
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76 inline void OrderAccess::storeload() { inlasm_ppc_fence(); } |
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77 |
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78 inline void OrderAccess::acquire() { inlasm_ppc_acquire(); } |
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79 inline void OrderAccess::release() { inlasm_ppc_release(); } |
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80 inline void OrderAccess::fence() { inlasm_ppc_fence(); } |
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81 |
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82 inline jbyte OrderAccess::load_acquire(volatile jbyte* p) { register jbyte t = *p; inlasm_ppc_acquire_reg(t); return t; } |
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83 inline jshort OrderAccess::load_acquire(volatile jshort* p) { register jshort t = *p; inlasm_ppc_acquire_reg(t); return t; } |
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84 inline jint OrderAccess::load_acquire(volatile jint* p) { register jint t = *p; inlasm_ppc_acquire_reg(t); return t; } |
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85 inline jlong OrderAccess::load_acquire(volatile jlong* p) { register jlong t = *p; inlasm_ppc_acquire_reg(t); return t; } |
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86 inline jubyte OrderAccess::load_acquire(volatile jubyte* p) { register jubyte t = *p; inlasm_ppc_acquire_reg(t); return t; } |
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87 inline jushort OrderAccess::load_acquire(volatile jushort* p) { register jushort t = *p; inlasm_ppc_acquire_reg(t); return t; } |
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88 inline juint OrderAccess::load_acquire(volatile juint* p) { register juint t = *p; inlasm_ppc_acquire_reg(t); return t; } |
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89 inline julong OrderAccess::load_acquire(volatile julong* p) { return (julong)load_acquire((volatile jlong*)p); } |
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90 inline jfloat OrderAccess::load_acquire(volatile jfloat* p) { register jfloat t = *p; inlasm_ppc_acquire(); return t; } |
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91 inline jdouble OrderAccess::load_acquire(volatile jdouble* p) { register jdouble t = *p; inlasm_ppc_acquire(); return t; } |
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92 |
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93 inline intptr_t OrderAccess::load_ptr_acquire(volatile intptr_t* p) { return (intptr_t)load_acquire((volatile jlong*)p); } |
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94 inline void* OrderAccess::load_ptr_acquire(volatile void* p) { return (void*) load_acquire((volatile jlong*)p); } |
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95 inline void* OrderAccess::load_ptr_acquire(const volatile void* p) { return (void*) load_acquire((volatile jlong*)p); } |
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96 |
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97 inline void OrderAccess::release_store(volatile jbyte* p, jbyte v) { inlasm_ppc_release(); *p = v; } |
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98 inline void OrderAccess::release_store(volatile jshort* p, jshort v) { inlasm_ppc_release(); *p = v; } |
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99 inline void OrderAccess::release_store(volatile jint* p, jint v) { inlasm_ppc_release(); *p = v; } |
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100 inline void OrderAccess::release_store(volatile jlong* p, jlong v) { inlasm_ppc_release(); *p = v; } |
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101 inline void OrderAccess::release_store(volatile jubyte* p, jubyte v) { inlasm_ppc_release(); *p = v; } |
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102 inline void OrderAccess::release_store(volatile jushort* p, jushort v) { inlasm_ppc_release(); *p = v; } |
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103 inline void OrderAccess::release_store(volatile juint* p, juint v) { inlasm_ppc_release(); *p = v; } |
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104 inline void OrderAccess::release_store(volatile julong* p, julong v) { inlasm_ppc_release(); *p = v; } |
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105 inline void OrderAccess::release_store(volatile jfloat* p, jfloat v) { inlasm_ppc_release(); *p = v; } |
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106 inline void OrderAccess::release_store(volatile jdouble* p, jdouble v) { inlasm_ppc_release(); *p = v; } |
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107 |
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108 inline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { inlasm_ppc_release(); *p = v; } |
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109 inline void OrderAccess::release_store_ptr(volatile void* p, void* v) { inlasm_ppc_release(); *(void* volatile *)p = v; } |
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110 |
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111 inline void OrderAccess::store_fence(jbyte* p, jbyte v) { *p = v; inlasm_ppc_fence(); } |
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112 inline void OrderAccess::store_fence(jshort* p, jshort v) { *p = v; inlasm_ppc_fence(); } |
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113 inline void OrderAccess::store_fence(jint* p, jint v) { *p = v; inlasm_ppc_fence(); } |
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114 inline void OrderAccess::store_fence(jlong* p, jlong v) { *p = v; inlasm_ppc_fence(); } |
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115 inline void OrderAccess::store_fence(jubyte* p, jubyte v) { *p = v; inlasm_ppc_fence(); } |
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116 inline void OrderAccess::store_fence(jushort* p, jushort v) { *p = v; inlasm_ppc_fence(); } |
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117 inline void OrderAccess::store_fence(juint* p, juint v) { *p = v; inlasm_ppc_fence(); } |
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118 inline void OrderAccess::store_fence(julong* p, julong v) { *p = v; inlasm_ppc_fence(); } |
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119 inline void OrderAccess::store_fence(jfloat* p, jfloat v) { *p = v; inlasm_ppc_fence(); } |
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120 inline void OrderAccess::store_fence(jdouble* p, jdouble v) { *p = v; inlasm_ppc_fence(); } |
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121 |
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122 inline void OrderAccess::store_ptr_fence(intptr_t* p, intptr_t v) { *p = v; inlasm_ppc_fence(); } |
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123 inline void OrderAccess::store_ptr_fence(void** p, void* v) { *p = v; inlasm_ppc_fence(); } |
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124 |
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125 inline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) { inlasm_ppc_release(); *p = v; inlasm_ppc_fence(); } |
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126 inline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) { inlasm_ppc_release(); *p = v; inlasm_ppc_fence(); } |
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127 inline void OrderAccess::release_store_fence(volatile jint* p, jint v) { inlasm_ppc_release(); *p = v; inlasm_ppc_fence(); } |
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128 inline void OrderAccess::release_store_fence(volatile jlong* p, jlong v) { inlasm_ppc_release(); *p = v; inlasm_ppc_fence(); } |
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129 inline void OrderAccess::release_store_fence(volatile jubyte* p, jubyte v) { inlasm_ppc_release(); *p = v; inlasm_ppc_fence(); } |
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130 inline void OrderAccess::release_store_fence(volatile jushort* p, jushort v) { inlasm_ppc_release(); *p = v; inlasm_ppc_fence(); } |
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131 inline void OrderAccess::release_store_fence(volatile juint* p, juint v) { inlasm_ppc_release(); *p = v; inlasm_ppc_fence(); } |
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132 inline void OrderAccess::release_store_fence(volatile julong* p, julong v) { inlasm_ppc_release(); *p = v; inlasm_ppc_fence(); } |
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133 inline void OrderAccess::release_store_fence(volatile jfloat* p, jfloat v) { inlasm_ppc_release(); *p = v; inlasm_ppc_fence(); } |
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134 inline void OrderAccess::release_store_fence(volatile jdouble* p, jdouble v) { inlasm_ppc_release(); *p = v; inlasm_ppc_fence(); } |
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135 |
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136 inline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) { inlasm_ppc_release(); *p = v; inlasm_ppc_fence(); } |
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137 inline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) { inlasm_ppc_release(); *(void* volatile *)p = v; inlasm_ppc_fence(); } |
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138 |
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139 #undef inlasm_ppc_sync |
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140 #undef inlasm_ppc_lwsync |
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141 #undef inlasm_ppc_eieio |
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142 #undef inlasm_ppc_isync |
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143 #undef inlasm_ppc_release |
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144 #undef inlasm_ppc_acquire |
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145 #undef inlasm_ppc_fence |
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146 |
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147 #endif // OS_CPU_AIX_OJDKPPC_VM_ORDERACCESS_AIX_PPC_INLINE_HPP |