Mercurial > hg > truffle
annotate src/cpu/sparc/vm/assembler_sparc.cpp @ 6475:67b94a9fba57
append global stub address when disassembling a call to a global stub
author | Doug Simon <doug.simon@oracle.com> |
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date | Mon, 01 Oct 2012 22:10:47 +0200 |
parents | 957c266d8bc5 |
children | e522a00b91aa |
rev | line source |
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0 | 1 /* |
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2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
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26 #include "asm/assembler.hpp" |
1972 | 27 #include "assembler_sparc.inline.hpp" |
28 #include "gc_interface/collectedHeap.inline.hpp" | |
29 #include "interpreter/interpreter.hpp" | |
30 #include "memory/cardTableModRefBS.hpp" | |
31 #include "memory/resourceArea.hpp" | |
32 #include "prims/methodHandles.hpp" | |
33 #include "runtime/biasedLocking.hpp" | |
34 #include "runtime/interfaceSupport.hpp" | |
35 #include "runtime/objectMonitor.hpp" | |
36 #include "runtime/os.hpp" | |
37 #include "runtime/sharedRuntime.hpp" | |
38 #include "runtime/stubRoutines.hpp" | |
39 #ifndef SERIALGC | |
40 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp" | |
41 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp" | |
42 #include "gc_implementation/g1/heapRegion.hpp" | |
43 #endif | |
0 | 44 |
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45 #ifdef PRODUCT |
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46 #define BLOCK_COMMENT(str) /* nothing */ |
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47 #define STOP(error) stop(error) |
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48 #else |
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49 #define BLOCK_COMMENT(str) block_comment(str) |
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50 #define STOP(error) block_comment(error); stop(error) |
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51 #endif |
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52 |
727 | 53 // Convert the raw encoding form into the form expected by the |
54 // constructor for Address. | |
55 Address Address::make_raw(int base, int index, int scale, int disp, bool disp_is_oop) { | |
56 assert(scale == 0, "not supported"); | |
57 RelocationHolder rspec; | |
58 if (disp_is_oop) { | |
59 rspec = Relocation::spec_simple(relocInfo::oop_type); | |
0 | 60 } |
727 | 61 |
62 Register rindex = as_Register(index); | |
63 if (rindex != G0) { | |
64 Address madr(as_Register(base), rindex); | |
65 madr._rspec = rspec; | |
66 return madr; | |
67 } else { | |
68 Address madr(as_Register(base), disp); | |
69 madr._rspec = rspec; | |
70 return madr; | |
71 } | |
72 } | |
73 | |
74 Address Argument::address_in_frame() const { | |
75 // Warning: In LP64 mode disp will occupy more than 10 bits, but | |
76 // op codes such as ld or ldx, only access disp() to get | |
77 // their simm13 argument. | |
78 int disp = ((_number - Argument::n_register_parameters + frame::memory_parameter_word_sp_offset) * BytesPerWord) + STACK_BIAS; | |
79 if (is_in()) | |
80 return Address(FP, disp); // In argument. | |
81 else | |
82 return Address(SP, disp); // Out argument. | |
0 | 83 } |
84 | |
85 static const char* argumentNames[][2] = { | |
86 {"A0","P0"}, {"A1","P1"}, {"A2","P2"}, {"A3","P3"}, {"A4","P4"}, | |
87 {"A5","P5"}, {"A6","P6"}, {"A7","P7"}, {"A8","P8"}, {"A9","P9"}, | |
88 {"A(n>9)","P(n>9)"} | |
89 }; | |
90 | |
91 const char* Argument::name() const { | |
92 int nofArgs = sizeof argumentNames / sizeof argumentNames[0]; | |
93 int num = number(); | |
94 if (num >= nofArgs) num = nofArgs - 1; | |
95 return argumentNames[num][is_in() ? 1 : 0]; | |
96 } | |
97 | |
98 void Assembler::print_instruction(int inst) { | |
99 const char* s; | |
100 switch (inv_op(inst)) { | |
101 default: s = "????"; break; | |
102 case call_op: s = "call"; break; | |
103 case branch_op: | |
104 switch (inv_op2(inst)) { | |
105 case fb_op2: s = "fb"; break; | |
106 case fbp_op2: s = "fbp"; break; | |
107 case br_op2: s = "br"; break; | |
108 case bp_op2: s = "bp"; break; | |
109 case cb_op2: s = "cb"; break; | |
3839 | 110 case bpr_op2: { |
111 if (is_cbcond(inst)) { | |
112 s = is_cxb(inst) ? "cxb" : "cwb"; | |
113 } else { | |
114 s = "bpr"; | |
115 } | |
116 break; | |
117 } | |
0 | 118 default: s = "????"; break; |
119 } | |
120 } | |
121 ::tty->print("%s", s); | |
122 } | |
123 | |
124 | |
125 // Patch instruction inst at offset inst_pos to refer to dest_pos | |
126 // and return the resulting instruction. | |
127 // We should have pcs, not offsets, but since all is relative, it will work out | |
128 // OK. | |
129 int Assembler::patched_branch(int dest_pos, int inst, int inst_pos) { | |
130 | |
131 int m; // mask for displacement field | |
132 int v; // new value for displacement field | |
133 const int word_aligned_ones = -4; | |
134 switch (inv_op(inst)) { | |
135 default: ShouldNotReachHere(); | |
136 case call_op: m = wdisp(word_aligned_ones, 0, 30); v = wdisp(dest_pos, inst_pos, 30); break; | |
137 case branch_op: | |
138 switch (inv_op2(inst)) { | |
139 case fbp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break; | |
140 case bp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break; | |
141 case fb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break; | |
142 case br_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break; | |
143 case cb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break; | |
3839 | 144 case bpr_op2: { |
145 if (is_cbcond(inst)) { | |
146 m = wdisp10(word_aligned_ones, 0); | |
147 v = wdisp10(dest_pos, inst_pos); | |
148 } else { | |
149 m = wdisp16(word_aligned_ones, 0); | |
150 v = wdisp16(dest_pos, inst_pos); | |
151 } | |
152 break; | |
153 } | |
0 | 154 default: ShouldNotReachHere(); |
155 } | |
156 } | |
157 return inst & ~m | v; | |
158 } | |
159 | |
160 // Return the offset of the branch destionation of instruction inst | |
161 // at offset pos. | |
162 // Should have pcs, but since all is relative, it works out. | |
163 int Assembler::branch_destination(int inst, int pos) { | |
164 int r; | |
165 switch (inv_op(inst)) { | |
166 default: ShouldNotReachHere(); | |
167 case call_op: r = inv_wdisp(inst, pos, 30); break; | |
168 case branch_op: | |
169 switch (inv_op2(inst)) { | |
170 case fbp_op2: r = inv_wdisp( inst, pos, 19); break; | |
171 case bp_op2: r = inv_wdisp( inst, pos, 19); break; | |
172 case fb_op2: r = inv_wdisp( inst, pos, 22); break; | |
173 case br_op2: r = inv_wdisp( inst, pos, 22); break; | |
174 case cb_op2: r = inv_wdisp( inst, pos, 22); break; | |
3839 | 175 case bpr_op2: { |
176 if (is_cbcond(inst)) { | |
177 r = inv_wdisp10(inst, pos); | |
178 } else { | |
179 r = inv_wdisp16(inst, pos); | |
180 } | |
181 break; | |
182 } | |
0 | 183 default: ShouldNotReachHere(); |
184 } | |
185 } | |
186 return r; | |
187 } | |
188 | |
189 int AbstractAssembler::code_fill_byte() { | |
190 return 0x00; // illegal instruction 0x00000000 | |
191 } | |
192 | |
342
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193 Assembler::Condition Assembler::reg_cond_to_cc_cond(Assembler::RCondition in) { |
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194 switch (in) { |
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195 case rc_z: return equal; |
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196 case rc_lez: return lessEqual; |
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197 case rc_lz: return less; |
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198 case rc_nz: return notEqual; |
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199 case rc_gz: return greater; |
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200 case rc_gez: return greaterEqual; |
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201 default: |
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202 ShouldNotReachHere(); |
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203 } |
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204 return equal; |
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205 } |
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206 |
0 | 207 // Generate a bunch 'o stuff (including v9's |
208 #ifndef PRODUCT | |
209 void Assembler::test_v9() { | |
210 add( G0, G1, G2 ); | |
211 add( G3, 0, G4 ); | |
212 | |
213 addcc( G5, G6, G7 ); | |
214 addcc( I0, 1, I1 ); | |
215 addc( I2, I3, I4 ); | |
216 addc( I5, -1, I6 ); | |
217 addccc( I7, L0, L1 ); | |
218 addccc( L2, (1 << 12) - 2, L3 ); | |
219 | |
220 Label lbl1, lbl2, lbl3; | |
221 | |
222 bind(lbl1); | |
223 | |
224 bpr( rc_z, true, pn, L4, pc(), relocInfo::oop_type ); | |
225 delayed()->nop(); | |
226 bpr( rc_lez, false, pt, L5, lbl1); | |
227 delayed()->nop(); | |
228 | |
229 fb( f_never, true, pc() + 4, relocInfo::none); | |
230 delayed()->nop(); | |
231 fb( f_notEqual, false, lbl2 ); | |
232 delayed()->nop(); | |
233 | |
234 fbp( f_notZero, true, fcc0, pn, pc() - 4, relocInfo::none); | |
235 delayed()->nop(); | |
236 fbp( f_lessOrGreater, false, fcc1, pt, lbl3 ); | |
237 delayed()->nop(); | |
238 | |
239 br( equal, true, pc() + 1024, relocInfo::none); | |
240 delayed()->nop(); | |
241 br( lessEqual, false, lbl1 ); | |
242 delayed()->nop(); | |
243 br( never, false, lbl1 ); | |
244 delayed()->nop(); | |
245 | |
246 bp( less, true, icc, pn, pc(), relocInfo::none); | |
247 delayed()->nop(); | |
248 bp( lessEqualUnsigned, false, xcc, pt, lbl2 ); | |
249 delayed()->nop(); | |
250 | |
251 call( pc(), relocInfo::none); | |
252 delayed()->nop(); | |
253 call( lbl3 ); | |
254 delayed()->nop(); | |
255 | |
256 | |
257 casa( L6, L7, O0 ); | |
258 casxa( O1, O2, O3, 0 ); | |
259 | |
260 udiv( O4, O5, O7 ); | |
261 udiv( G0, (1 << 12) - 1, G1 ); | |
262 sdiv( G1, G2, G3 ); | |
263 sdiv( G4, -((1 << 12) - 1), G5 ); | |
264 udivcc( G6, G7, I0 ); | |
265 udivcc( I1, -((1 << 12) - 2), I2 ); | |
266 sdivcc( I3, I4, I5 ); | |
267 sdivcc( I6, -((1 << 12) - 0), I7 ); | |
268 | |
269 done(); | |
270 retry(); | |
271 | |
272 fadd( FloatRegisterImpl::S, F0, F1, F2 ); | |
273 fsub( FloatRegisterImpl::D, F34, F0, F62 ); | |
274 | |
275 fcmp( FloatRegisterImpl::Q, fcc0, F0, F60); | |
276 fcmpe( FloatRegisterImpl::S, fcc1, F31, F30); | |
277 | |
278 ftox( FloatRegisterImpl::D, F2, F4 ); | |
279 ftoi( FloatRegisterImpl::Q, F4, F8 ); | |
280 | |
281 ftof( FloatRegisterImpl::S, FloatRegisterImpl::Q, F3, F12 ); | |
282 | |
283 fxtof( FloatRegisterImpl::S, F4, F5 ); | |
284 fitof( FloatRegisterImpl::D, F6, F8 ); | |
285 | |
286 fmov( FloatRegisterImpl::Q, F16, F20 ); | |
287 fneg( FloatRegisterImpl::S, F6, F7 ); | |
288 fabs( FloatRegisterImpl::D, F10, F12 ); | |
289 | |
290 fmul( FloatRegisterImpl::Q, F24, F28, F32 ); | |
291 fmul( FloatRegisterImpl::S, FloatRegisterImpl::D, F8, F9, F14 ); | |
292 fdiv( FloatRegisterImpl::S, F10, F11, F12 ); | |
293 | |
294 fsqrt( FloatRegisterImpl::S, F13, F14 ); | |
295 | |
296 flush( L0, L1 ); | |
297 flush( L2, -1 ); | |
298 | |
299 flushw(); | |
300 | |
301 illtrap( (1 << 22) - 2); | |
302 | |
303 impdep1( 17, (1 << 19) - 1 ); | |
304 impdep2( 3, 0 ); | |
305 | |
306 jmpl( L3, L4, L5 ); | |
307 delayed()->nop(); | |
308 jmpl( L6, -1, L7, Relocation::spec_simple(relocInfo::none)); | |
309 delayed()->nop(); | |
310 | |
311 | |
312 ldf( FloatRegisterImpl::S, O0, O1, F15 ); | |
313 ldf( FloatRegisterImpl::D, O2, -1, F14 ); | |
314 | |
315 | |
316 ldfsr( O3, O4 ); | |
317 ldfsr( O5, -1 ); | |
318 ldxfsr( O6, O7 ); | |
319 ldxfsr( I0, -1 ); | |
320 | |
321 ldfa( FloatRegisterImpl::D, I1, I2, 1, F16 ); | |
322 ldfa( FloatRegisterImpl::Q, I3, -1, F36 ); | |
323 | |
324 ldsb( I4, I5, I6 ); | |
325 ldsb( I7, -1, G0 ); | |
326 ldsh( G1, G3, G4 ); | |
327 ldsh( G5, -1, G6 ); | |
328 ldsw( G7, L0, L1 ); | |
329 ldsw( L2, -1, L3 ); | |
330 ldub( L4, L5, L6 ); | |
331 ldub( L7, -1, O0 ); | |
332 lduh( O1, O2, O3 ); | |
333 lduh( O4, -1, O5 ); | |
334 lduw( O6, O7, G0 ); | |
335 lduw( G1, -1, G2 ); | |
336 ldx( G3, G4, G5 ); | |
337 ldx( G6, -1, G7 ); | |
338 ldd( I0, I1, I2 ); | |
339 ldd( I3, -1, I4 ); | |
340 | |
341 ldsba( I5, I6, 2, I7 ); | |
342 ldsba( L0, -1, L1 ); | |
343 ldsha( L2, L3, 3, L4 ); | |
344 ldsha( L5, -1, L6 ); | |
345 ldswa( L7, O0, (1 << 8) - 1, O1 ); | |
346 ldswa( O2, -1, O3 ); | |
347 lduba( O4, O5, 0, O6 ); | |
348 lduba( O7, -1, I0 ); | |
349 lduha( I1, I2, 1, I3 ); | |
350 lduha( I4, -1, I5 ); | |
351 lduwa( I6, I7, 2, L0 ); | |
352 lduwa( L1, -1, L2 ); | |
353 ldxa( L3, L4, 3, L5 ); | |
354 ldxa( L6, -1, L7 ); | |
355 ldda( G0, G1, 4, G2 ); | |
356 ldda( G3, -1, G4 ); | |
357 | |
358 ldstub( G5, G6, G7 ); | |
359 ldstub( O0, -1, O1 ); | |
360 | |
361 ldstuba( O2, O3, 5, O4 ); | |
362 ldstuba( O5, -1, O6 ); | |
363 | |
364 and3( I0, L0, O0 ); | |
365 and3( G7, -1, O7 ); | |
366 andcc( L2, I2, G2 ); | |
367 andcc( L4, -1, G4 ); | |
368 andn( I5, I6, I7 ); | |
369 andn( I6, -1, I7 ); | |
370 andncc( I5, I6, I7 ); | |
371 andncc( I7, -1, I6 ); | |
372 or3( I5, I6, I7 ); | |
373 or3( I7, -1, I6 ); | |
374 orcc( I5, I6, I7 ); | |
375 orcc( I7, -1, I6 ); | |
376 orn( I5, I6, I7 ); | |
377 orn( I7, -1, I6 ); | |
378 orncc( I5, I6, I7 ); | |
379 orncc( I7, -1, I6 ); | |
380 xor3( I5, I6, I7 ); | |
381 xor3( I7, -1, I6 ); | |
382 xorcc( I5, I6, I7 ); | |
383 xorcc( I7, -1, I6 ); | |
384 xnor( I5, I6, I7 ); | |
385 xnor( I7, -1, I6 ); | |
386 xnorcc( I5, I6, I7 ); | |
387 xnorcc( I7, -1, I6 ); | |
388 | |
389 membar( Membar_mask_bits(StoreStore | LoadStore | StoreLoad | LoadLoad | Sync | MemIssue | Lookaside ) ); | |
390 membar( StoreStore ); | |
391 membar( LoadStore ); | |
392 membar( StoreLoad ); | |
393 membar( LoadLoad ); | |
394 membar( Sync ); | |
395 membar( MemIssue ); | |
396 membar( Lookaside ); | |
397 | |
398 fmov( FloatRegisterImpl::S, f_ordered, true, fcc2, F16, F17 ); | |
399 fmov( FloatRegisterImpl::D, rc_lz, L5, F18, F20 ); | |
400 | |
401 movcc( overflowClear, false, icc, I6, L4 ); | |
402 movcc( f_unorderedOrEqual, true, fcc2, (1 << 10) - 1, O0 ); | |
403 | |
404 movr( rc_nz, I5, I6, I7 ); | |
405 movr( rc_gz, L1, -1, L2 ); | |
406 | |
407 mulx( I5, I6, I7 ); | |
408 mulx( I7, -1, I6 ); | |
409 sdivx( I5, I6, I7 ); | |
410 sdivx( I7, -1, I6 ); | |
411 udivx( I5, I6, I7 ); | |
412 udivx( I7, -1, I6 ); | |
413 | |
414 umul( I5, I6, I7 ); | |
415 umul( I7, -1, I6 ); | |
416 smul( I5, I6, I7 ); | |
417 smul( I7, -1, I6 ); | |
418 umulcc( I5, I6, I7 ); | |
419 umulcc( I7, -1, I6 ); | |
420 smulcc( I5, I6, I7 ); | |
421 smulcc( I7, -1, I6 ); | |
422 | |
423 mulscc( I5, I6, I7 ); | |
424 mulscc( I7, -1, I6 ); | |
425 | |
426 nop(); | |
427 | |
428 | |
429 popc( G0, G1); | |
430 popc( -1, G2); | |
431 | |
432 prefetch( L1, L2, severalReads ); | |
433 prefetch( L3, -1, oneRead ); | |
434 prefetcha( O3, O2, 6, severalWritesAndPossiblyReads ); | |
435 prefetcha( G2, -1, oneWrite ); | |
436 | |
437 rett( I7, I7); | |
438 delayed()->nop(); | |
439 rett( G0, -1, relocInfo::none); | |
440 delayed()->nop(); | |
441 | |
442 save( I5, I6, I7 ); | |
443 save( I7, -1, I6 ); | |
444 restore( I5, I6, I7 ); | |
445 restore( I7, -1, I6 ); | |
446 | |
447 saved(); | |
448 restored(); | |
449 | |
450 sethi( 0xaaaaaaaa, I3, Relocation::spec_simple(relocInfo::none)); | |
451 | |
452 sll( I5, I6, I7 ); | |
453 sll( I7, 31, I6 ); | |
454 srl( I5, I6, I7 ); | |
455 srl( I7, 0, I6 ); | |
456 sra( I5, I6, I7 ); | |
457 sra( I7, 30, I6 ); | |
458 sllx( I5, I6, I7 ); | |
459 sllx( I7, 63, I6 ); | |
460 srlx( I5, I6, I7 ); | |
461 srlx( I7, 0, I6 ); | |
462 srax( I5, I6, I7 ); | |
463 srax( I7, 62, I6 ); | |
464 | |
465 sir( -1 ); | |
466 | |
467 stbar(); | |
468 | |
469 stf( FloatRegisterImpl::Q, F40, G0, I7 ); | |
470 stf( FloatRegisterImpl::S, F18, I3, -1 ); | |
471 | |
472 stfsr( L1, L2 ); | |
473 stfsr( I7, -1 ); | |
474 stxfsr( I6, I5 ); | |
475 stxfsr( L4, -1 ); | |
476 | |
477 stfa( FloatRegisterImpl::D, F22, I6, I7, 7 ); | |
478 stfa( FloatRegisterImpl::Q, F44, G0, -1 ); | |
479 | |
480 stb( L5, O2, I7 ); | |
481 stb( I7, I6, -1 ); | |
482 sth( L5, O2, I7 ); | |
483 sth( I7, I6, -1 ); | |
484 stw( L5, O2, I7 ); | |
485 stw( I7, I6, -1 ); | |
486 stx( L5, O2, I7 ); | |
487 stx( I7, I6, -1 ); | |
488 std( L5, O2, I7 ); | |
489 std( I7, I6, -1 ); | |
490 | |
491 stba( L5, O2, I7, 8 ); | |
492 stba( I7, I6, -1 ); | |
493 stha( L5, O2, I7, 9 ); | |
494 stha( I7, I6, -1 ); | |
495 stwa( L5, O2, I7, 0 ); | |
496 stwa( I7, I6, -1 ); | |
497 stxa( L5, O2, I7, 11 ); | |
498 stxa( I7, I6, -1 ); | |
499 stda( L5, O2, I7, 12 ); | |
500 stda( I7, I6, -1 ); | |
501 | |
502 sub( I5, I6, I7 ); | |
503 sub( I7, -1, I6 ); | |
504 subcc( I5, I6, I7 ); | |
505 subcc( I7, -1, I6 ); | |
506 subc( I5, I6, I7 ); | |
507 subc( I7, -1, I6 ); | |
508 subccc( I5, I6, I7 ); | |
509 subccc( I7, -1, I6 ); | |
510 | |
511 swap( I5, I6, I7 ); | |
512 swap( I7, -1, I6 ); | |
513 | |
514 swapa( G0, G1, 13, G2 ); | |
515 swapa( I7, -1, I6 ); | |
516 | |
517 taddcc( I5, I6, I7 ); | |
518 taddcc( I7, -1, I6 ); | |
519 taddcctv( I5, I6, I7 ); | |
520 taddcctv( I7, -1, I6 ); | |
521 | |
522 tsubcc( I5, I6, I7 ); | |
523 tsubcc( I7, -1, I6 ); | |
524 tsubcctv( I5, I6, I7 ); | |
525 tsubcctv( I7, -1, I6 ); | |
526 | |
527 trap( overflowClear, xcc, G0, G1 ); | |
528 trap( lessEqual, icc, I7, 17 ); | |
529 | |
530 bind(lbl2); | |
531 bind(lbl3); | |
532 | |
533 code()->decode(); | |
534 } | |
535 | |
536 // Generate a bunch 'o stuff unique to V8 | |
537 void Assembler::test_v8_onlys() { | |
538 Label lbl1; | |
539 | |
540 cb( cp_0or1or2, false, pc() - 4, relocInfo::none); | |
541 delayed()->nop(); | |
542 cb( cp_never, true, lbl1); | |
543 delayed()->nop(); | |
544 | |
545 cpop1(1, 2, 3, 4); | |
546 cpop2(5, 6, 7, 8); | |
547 | |
548 ldc( I0, I1, 31); | |
549 ldc( I2, -1, 0); | |
550 | |
551 lddc( I4, I4, 30); | |
552 lddc( I6, 0, 1 ); | |
553 | |
554 ldcsr( L0, L1, 0); | |
555 ldcsr( L1, (1 << 12) - 1, 17 ); | |
556 | |
557 stc( 31, L4, L5); | |
558 stc( 30, L6, -(1 << 12) ); | |
559 | |
560 stdc( 0, L7, G0); | |
561 stdc( 1, G1, 0 ); | |
562 | |
563 stcsr( 16, G2, G3); | |
564 stcsr( 17, G4, 1 ); | |
565 | |
566 stdcq( 4, G5, G6); | |
567 stdcq( 5, G7, -1 ); | |
568 | |
569 bind(lbl1); | |
570 | |
571 code()->decode(); | |
572 } | |
573 #endif | |
574 | |
575 // Implementation of MacroAssembler | |
576 | |
577 void MacroAssembler::null_check(Register reg, int offset) { | |
578 if (needs_explicit_null_check((intptr_t)offset)) { | |
579 // provoke OS NULL exception if reg = NULL by | |
580 // accessing M[reg] w/o changing any registers | |
581 ld_ptr(reg, 0, G0); | |
582 } | |
583 else { | |
584 // nothing to do, (later) access of M[reg + offset] | |
585 // will provoke OS NULL exception if reg = NULL | |
586 } | |
587 } | |
588 | |
589 // Ring buffer jumps | |
590 | |
591 #ifndef PRODUCT | |
592 void MacroAssembler::ret( bool trace ) { if (trace) { | |
593 mov(I7, O7); // traceable register | |
594 JMP(O7, 2 * BytesPerInstWord); | |
595 } else { | |
596 jmpl( I7, 2 * BytesPerInstWord, G0 ); | |
597 } | |
598 } | |
599 | |
600 void MacroAssembler::retl( bool trace ) { if (trace) JMP(O7, 2 * BytesPerInstWord); | |
601 else jmpl( O7, 2 * BytesPerInstWord, G0 ); } | |
602 #endif /* PRODUCT */ | |
603 | |
604 | |
605 void MacroAssembler::jmp2(Register r1, Register r2, const char* file, int line ) { | |
606 assert_not_delayed(); | |
607 // This can only be traceable if r1 & r2 are visible after a window save | |
608 if (TraceJumps) { | |
609 #ifndef PRODUCT | |
610 save_frame(0); | |
611 verify_thread(); | |
612 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); | |
613 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); | |
614 sll(O0, exact_log2(4*sizeof(intptr_t)), O2); | |
615 add(O2, O1, O1); | |
616 | |
617 add(r1->after_save(), r2->after_save(), O2); | |
618 set((intptr_t)file, O3); | |
619 set(line, O4); | |
620 Label L; | |
621 // get nearby pc, store jmp target | |
622 call(L, relocInfo::none); // No relocation for call to pc+0x8 | |
623 delayed()->st(O2, O1, 0); | |
624 bind(L); | |
625 | |
626 // store nearby pc | |
627 st(O7, O1, sizeof(intptr_t)); | |
628 // store file | |
629 st(O3, O1, 2*sizeof(intptr_t)); | |
630 // store line | |
631 st(O4, O1, 3*sizeof(intptr_t)); | |
632 add(O0, 1, O0); | |
633 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); | |
634 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); | |
635 restore(); | |
636 #endif /* PRODUCT */ | |
637 } | |
638 jmpl(r1, r2, G0); | |
639 } | |
640 void MacroAssembler::jmp(Register r1, int offset, const char* file, int line ) { | |
641 assert_not_delayed(); | |
642 // This can only be traceable if r1 is visible after a window save | |
643 if (TraceJumps) { | |
644 #ifndef PRODUCT | |
645 save_frame(0); | |
646 verify_thread(); | |
647 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); | |
648 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); | |
649 sll(O0, exact_log2(4*sizeof(intptr_t)), O2); | |
650 add(O2, O1, O1); | |
651 | |
652 add(r1->after_save(), offset, O2); | |
653 set((intptr_t)file, O3); | |
654 set(line, O4); | |
655 Label L; | |
656 // get nearby pc, store jmp target | |
657 call(L, relocInfo::none); // No relocation for call to pc+0x8 | |
658 delayed()->st(O2, O1, 0); | |
659 bind(L); | |
660 | |
661 // store nearby pc | |
662 st(O7, O1, sizeof(intptr_t)); | |
663 // store file | |
664 st(O3, O1, 2*sizeof(intptr_t)); | |
665 // store line | |
666 st(O4, O1, 3*sizeof(intptr_t)); | |
667 add(O0, 1, O0); | |
668 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); | |
669 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); | |
670 restore(); | |
671 #endif /* PRODUCT */ | |
672 } | |
673 jmp(r1, offset); | |
674 } | |
675 | |
676 // This code sequence is relocatable to any address, even on LP64. | |
1680
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677 void MacroAssembler::jumpl(const AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line) { |
0 | 678 assert_not_delayed(); |
679 // Force fixed length sethi because NativeJump and NativeFarCall don't handle | |
680 // variable length instruction streams. | |
727 | 681 patchable_sethi(addrlit, temp); |
682 Address a(temp, addrlit.low10() + offset); // Add the offset to the displacement. | |
0 | 683 if (TraceJumps) { |
684 #ifndef PRODUCT | |
685 // Must do the add here so relocation can find the remainder of the | |
686 // value to be relocated. | |
727 | 687 add(a.base(), a.disp(), a.base(), addrlit.rspec(offset)); |
0 | 688 save_frame(0); |
689 verify_thread(); | |
690 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); | |
691 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); | |
692 sll(O0, exact_log2(4*sizeof(intptr_t)), O2); | |
693 add(O2, O1, O1); | |
694 | |
695 set((intptr_t)file, O3); | |
696 set(line, O4); | |
697 Label L; | |
698 | |
699 // get nearby pc, store jmp target | |
700 call(L, relocInfo::none); // No relocation for call to pc+0x8 | |
701 delayed()->st(a.base()->after_save(), O1, 0); | |
702 bind(L); | |
703 | |
704 // store nearby pc | |
705 st(O7, O1, sizeof(intptr_t)); | |
706 // store file | |
707 st(O3, O1, 2*sizeof(intptr_t)); | |
708 // store line | |
709 st(O4, O1, 3*sizeof(intptr_t)); | |
710 add(O0, 1, O0); | |
711 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); | |
712 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); | |
713 restore(); | |
714 jmpl(a.base(), G0, d); | |
715 #else | |
727 | 716 jmpl(a.base(), a.disp(), d); |
0 | 717 #endif /* PRODUCT */ |
718 } else { | |
727 | 719 jmpl(a.base(), a.disp(), d); |
0 | 720 } |
721 } | |
722 | |
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723 void MacroAssembler::jump(const AddressLiteral& addrlit, Register temp, int offset, const char* file, int line) { |
727 | 724 jumpl(addrlit, temp, G0, offset, file, line); |
0 | 725 } |
726 | |
727 | |
728 // Convert to C varargs format | |
729 void MacroAssembler::set_varargs( Argument inArg, Register d ) { | |
730 // spill register-resident args to their memory slots | |
731 // (SPARC calling convention requires callers to have already preallocated these) | |
732 // Note that the inArg might in fact be an outgoing argument, | |
733 // if a leaf routine or stub does some tricky argument shuffling. | |
734 // This routine must work even though one of the saved arguments | |
735 // is in the d register (e.g., set_varargs(Argument(0, false), O0)). | |
736 for (Argument savePtr = inArg; | |
737 savePtr.is_register(); | |
738 savePtr = savePtr.successor()) { | |
739 st_ptr(savePtr.as_register(), savePtr.address_in_frame()); | |
740 } | |
741 // return the address of the first memory slot | |
727 | 742 Address a = inArg.address_in_frame(); |
743 add(a.base(), a.disp(), d); | |
0 | 744 } |
745 | |
746 // Conditional breakpoint (for assertion checks in assembly code) | |
747 void MacroAssembler::breakpoint_trap(Condition c, CC cc) { | |
748 trap(c, cc, G0, ST_RESERVED_FOR_USER_0); | |
749 } | |
750 | |
751 // We want to use ST_BREAKPOINT here, but the debugger is confused by it. | |
752 void MacroAssembler::breakpoint_trap() { | |
753 trap(ST_RESERVED_FOR_USER_0); | |
754 } | |
755 | |
756 // flush windows (except current) using flushw instruction if avail. | |
757 void MacroAssembler::flush_windows() { | |
758 if (VM_Version::v9_instructions_work()) flushw(); | |
759 else flush_windows_trap(); | |
760 } | |
761 | |
762 // Write serialization page so VM thread can do a pseudo remote membar | |
763 // We use the current thread pointer to calculate a thread specific | |
764 // offset to write to within the page. This minimizes bus traffic | |
765 // due to cache line collision. | |
766 void MacroAssembler::serialize_memory(Register thread, Register tmp1, Register tmp2) { | |
767 srl(thread, os::get_serialize_page_shift_count(), tmp2); | |
768 if (Assembler::is_simm13(os::vm_page_size())) { | |
769 and3(tmp2, (os::vm_page_size() - sizeof(int)), tmp2); | |
770 } | |
771 else { | |
772 set((os::vm_page_size() - sizeof(int)), tmp1); | |
773 and3(tmp2, tmp1, tmp2); | |
774 } | |
727 | 775 set(os::get_memory_serialize_page(), tmp1); |
0 | 776 st(G0, tmp1, tmp2); |
777 } | |
778 | |
779 | |
780 | |
781 void MacroAssembler::enter() { | |
782 Unimplemented(); | |
783 } | |
784 | |
785 void MacroAssembler::leave() { | |
786 Unimplemented(); | |
787 } | |
788 | |
789 void MacroAssembler::mult(Register s1, Register s2, Register d) { | |
790 if(VM_Version::v9_instructions_work()) { | |
791 mulx (s1, s2, d); | |
792 } else { | |
793 smul (s1, s2, d); | |
794 } | |
795 } | |
796 | |
797 void MacroAssembler::mult(Register s1, int simm13a, Register d) { | |
798 if(VM_Version::v9_instructions_work()) { | |
799 mulx (s1, simm13a, d); | |
800 } else { | |
801 smul (s1, simm13a, d); | |
802 } | |
803 } | |
804 | |
805 | |
806 #ifdef ASSERT | |
807 void MacroAssembler::read_ccr_v8_assert(Register ccr_save) { | |
808 const Register s1 = G3_scratch; | |
809 const Register s2 = G4_scratch; | |
810 Label get_psr_test; | |
811 // Get the condition codes the V8 way. | |
812 read_ccr_trap(s1); | |
813 mov(ccr_save, s2); | |
814 // This is a test of V8 which has icc but not xcc | |
815 // so mask off the xcc bits | |
816 and3(s2, 0xf, s2); | |
817 // Compare condition codes from the V8 and V9 ways. | |
818 subcc(s2, s1, G0); | |
819 br(Assembler::notEqual, true, Assembler::pt, get_psr_test); | |
820 delayed()->breakpoint_trap(); | |
821 bind(get_psr_test); | |
822 } | |
823 | |
824 void MacroAssembler::write_ccr_v8_assert(Register ccr_save) { | |
825 const Register s1 = G3_scratch; | |
826 const Register s2 = G4_scratch; | |
827 Label set_psr_test; | |
828 // Write out the saved condition codes the V8 way | |
829 write_ccr_trap(ccr_save, s1, s2); | |
830 // Read back the condition codes using the V9 instruction | |
831 rdccr(s1); | |
832 mov(ccr_save, s2); | |
833 // This is a test of V8 which has icc but not xcc | |
834 // so mask off the xcc bits | |
835 and3(s2, 0xf, s2); | |
836 and3(s1, 0xf, s1); | |
837 // Compare the V8 way with the V9 way. | |
838 subcc(s2, s1, G0); | |
839 br(Assembler::notEqual, true, Assembler::pt, set_psr_test); | |
840 delayed()->breakpoint_trap(); | |
841 bind(set_psr_test); | |
842 } | |
843 #else | |
844 #define read_ccr_v8_assert(x) | |
845 #define write_ccr_v8_assert(x) | |
846 #endif // ASSERT | |
847 | |
848 void MacroAssembler::read_ccr(Register ccr_save) { | |
849 if (VM_Version::v9_instructions_work()) { | |
850 rdccr(ccr_save); | |
851 // Test code sequence used on V8. Do not move above rdccr. | |
852 read_ccr_v8_assert(ccr_save); | |
853 } else { | |
854 read_ccr_trap(ccr_save); | |
855 } | |
856 } | |
857 | |
858 void MacroAssembler::write_ccr(Register ccr_save) { | |
859 if (VM_Version::v9_instructions_work()) { | |
860 // Test code sequence used on V8. Do not move below wrccr. | |
861 write_ccr_v8_assert(ccr_save); | |
862 wrccr(ccr_save); | |
863 } else { | |
864 const Register temp_reg1 = G3_scratch; | |
865 const Register temp_reg2 = G4_scratch; | |
866 write_ccr_trap(ccr_save, temp_reg1, temp_reg2); | |
867 } | |
868 } | |
869 | |
870 | |
871 // Calls to C land | |
872 | |
873 #ifdef ASSERT | |
874 // a hook for debugging | |
875 static Thread* reinitialize_thread() { | |
876 return ThreadLocalStorage::thread(); | |
877 } | |
878 #else | |
879 #define reinitialize_thread ThreadLocalStorage::thread | |
880 #endif | |
881 | |
882 #ifdef ASSERT | |
883 address last_get_thread = NULL; | |
884 #endif | |
885 | |
886 // call this when G2_thread is not known to be valid | |
887 void MacroAssembler::get_thread() { | |
888 save_frame(0); // to avoid clobbering O0 | |
889 mov(G1, L0); // avoid clobbering G1 | |
890 mov(G5_method, L1); // avoid clobbering G5 | |
891 mov(G3, L2); // avoid clobbering G3 also | |
892 mov(G4, L5); // avoid clobbering G4 | |
893 #ifdef ASSERT | |
727 | 894 AddressLiteral last_get_thread_addrlit(&last_get_thread); |
895 set(last_get_thread_addrlit, L3); | |
0 | 896 inc(L4, get_pc(L4) + 2 * BytesPerInstWord); // skip getpc() code + inc + st_ptr to point L4 at call |
727 | 897 st_ptr(L4, L3, 0); |
0 | 898 #endif |
899 call(CAST_FROM_FN_PTR(address, reinitialize_thread), relocInfo::runtime_call_type); | |
900 delayed()->nop(); | |
901 mov(L0, G1); | |
902 mov(L1, G5_method); | |
903 mov(L2, G3); | |
904 mov(L5, G4); | |
905 restore(O0, 0, G2_thread); | |
906 } | |
907 | |
908 static Thread* verify_thread_subroutine(Thread* gthread_value) { | |
909 Thread* correct_value = ThreadLocalStorage::thread(); | |
910 guarantee(gthread_value == correct_value, "G2_thread value must be the thread"); | |
911 return correct_value; | |
912 } | |
913 | |
914 void MacroAssembler::verify_thread() { | |
915 if (VerifyThread) { | |
916 // NOTE: this chops off the heads of the 64-bit O registers. | |
917 #ifdef CC_INTERP | |
918 save_frame(0); | |
919 #else | |
920 // make sure G2_thread contains the right value | |
921 save_frame_and_mov(0, Lmethod, Lmethod); // to avoid clobbering O0 (and propagate Lmethod for -Xprof) | |
922 mov(G1, L1); // avoid clobbering G1 | |
923 // G2 saved below | |
924 mov(G3, L3); // avoid clobbering G3 | |
925 mov(G4, L4); // avoid clobbering G4 | |
926 mov(G5_method, L5); // avoid clobbering G5_method | |
927 #endif /* CC_INTERP */ | |
928 #if defined(COMPILER2) && !defined(_LP64) | |
929 // Save & restore possible 64-bit Long arguments in G-regs | |
930 srlx(G1,32,L0); | |
931 srlx(G4,32,L6); | |
932 #endif | |
933 call(CAST_FROM_FN_PTR(address,verify_thread_subroutine), relocInfo::runtime_call_type); | |
934 delayed()->mov(G2_thread, O0); | |
935 | |
936 mov(L1, G1); // Restore G1 | |
937 // G2 restored below | |
938 mov(L3, G3); // restore G3 | |
939 mov(L4, G4); // restore G4 | |
940 mov(L5, G5_method); // restore G5_method | |
941 #if defined(COMPILER2) && !defined(_LP64) | |
942 // Save & restore possible 64-bit Long arguments in G-regs | |
943 sllx(L0,32,G2); // Move old high G1 bits high in G2 | |
2002 | 944 srl(G1, 0,G1); // Clear current high G1 bits |
0 | 945 or3 (G1,G2,G1); // Recover 64-bit G1 |
946 sllx(L6,32,G2); // Move old high G4 bits high in G2 | |
2002 | 947 srl(G4, 0,G4); // Clear current high G4 bits |
0 | 948 or3 (G4,G2,G4); // Recover 64-bit G4 |
949 #endif | |
950 restore(O0, 0, G2_thread); | |
951 } | |
952 } | |
953 | |
954 | |
955 void MacroAssembler::save_thread(const Register thread_cache) { | |
956 verify_thread(); | |
957 if (thread_cache->is_valid()) { | |
958 assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile"); | |
959 mov(G2_thread, thread_cache); | |
960 } | |
961 if (VerifyThread) { | |
962 // smash G2_thread, as if the VM were about to anyway | |
963 set(0x67676767, G2_thread); | |
964 } | |
965 } | |
966 | |
967 | |
968 void MacroAssembler::restore_thread(const Register thread_cache) { | |
969 if (thread_cache->is_valid()) { | |
970 assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile"); | |
971 mov(thread_cache, G2_thread); | |
972 verify_thread(); | |
973 } else { | |
974 // do it the slow way | |
975 get_thread(); | |
976 } | |
977 } | |
978 | |
979 | |
980 // %%% maybe get rid of [re]set_last_Java_frame | |
981 void MacroAssembler::set_last_Java_frame(Register last_java_sp, Register last_Java_pc) { | |
982 assert_not_delayed(); | |
727 | 983 Address flags(G2_thread, JavaThread::frame_anchor_offset() + |
984 JavaFrameAnchor::flags_offset()); | |
985 Address pc_addr(G2_thread, JavaThread::last_Java_pc_offset()); | |
0 | 986 |
987 // Always set last_Java_pc and flags first because once last_Java_sp is visible | |
988 // has_last_Java_frame is true and users will look at the rest of the fields. | |
989 // (Note: flags should always be zero before we get here so doesn't need to be set.) | |
990 | |
991 #ifdef ASSERT | |
992 // Verify that flags was zeroed on return to Java | |
993 Label PcOk; | |
994 save_frame(0); // to avoid clobbering O0 | |
995 ld_ptr(pc_addr, L0); | |
3839 | 996 br_null_short(L0, Assembler::pt, PcOk); |
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997 STOP("last_Java_pc not zeroed before leaving Java"); |
0 | 998 bind(PcOk); |
999 | |
1000 // Verify that flags was zeroed on return to Java | |
1001 Label FlagsOk; | |
1002 ld(flags, L0); | |
1003 tst(L0); | |
1004 br(Assembler::zero, false, Assembler::pt, FlagsOk); | |
1005 delayed() -> restore(); | |
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1006 STOP("flags not zeroed before leaving Java"); |
0 | 1007 bind(FlagsOk); |
1008 #endif /* ASSERT */ | |
1009 // | |
1010 // When returning from calling out from Java mode the frame anchor's last_Java_pc | |
1011 // will always be set to NULL. It is set here so that if we are doing a call to | |
1012 // native (not VM) that we capture the known pc and don't have to rely on the | |
1013 // native call having a standard frame linkage where we can find the pc. | |
1014 | |
1015 if (last_Java_pc->is_valid()) { | |
1016 st_ptr(last_Java_pc, pc_addr); | |
1017 } | |
1018 | |
1019 #ifdef _LP64 | |
1020 #ifdef ASSERT | |
1021 // Make sure that we have an odd stack | |
1022 Label StackOk; | |
1023 andcc(last_java_sp, 0x01, G0); | |
1024 br(Assembler::notZero, false, Assembler::pt, StackOk); | |
3839 | 1025 delayed()->nop(); |
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1026 STOP("Stack Not Biased in set_last_Java_frame"); |
0 | 1027 bind(StackOk); |
1028 #endif // ASSERT | |
1029 assert( last_java_sp != G4_scratch, "bad register usage in set_last_Java_frame"); | |
1030 add( last_java_sp, STACK_BIAS, G4_scratch ); | |
727 | 1031 st_ptr(G4_scratch, G2_thread, JavaThread::last_Java_sp_offset()); |
0 | 1032 #else |
727 | 1033 st_ptr(last_java_sp, G2_thread, JavaThread::last_Java_sp_offset()); |
0 | 1034 #endif // _LP64 |
1035 } | |
1036 | |
1037 void MacroAssembler::reset_last_Java_frame(void) { | |
1038 assert_not_delayed(); | |
1039 | |
727 | 1040 Address sp_addr(G2_thread, JavaThread::last_Java_sp_offset()); |
1041 Address pc_addr(G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); | |
1042 Address flags (G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset()); | |
0 | 1043 |
1044 #ifdef ASSERT | |
1045 // check that it WAS previously set | |
1046 #ifdef CC_INTERP | |
1047 save_frame(0); | |
1048 #else | |
1049 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod to helper frame for -Xprof | |
1050 #endif /* CC_INTERP */ | |
1051 ld_ptr(sp_addr, L0); | |
1052 tst(L0); | |
1053 breakpoint_trap(Assembler::zero, Assembler::ptr_cc); | |
1054 restore(); | |
1055 #endif // ASSERT | |
1056 | |
1057 st_ptr(G0, sp_addr); | |
1058 // Always return last_Java_pc to zero | |
1059 st_ptr(G0, pc_addr); | |
1060 // Always null flags after return to Java | |
1061 st(G0, flags); | |
1062 } | |
1063 | |
1064 | |
1065 void MacroAssembler::call_VM_base( | |
1066 Register oop_result, | |
1067 Register thread_cache, | |
1068 Register last_java_sp, | |
1069 address entry_point, | |
1070 int number_of_arguments, | |
1071 bool check_exceptions) | |
1072 { | |
1073 assert_not_delayed(); | |
1074 | |
1075 // determine last_java_sp register | |
1076 if (!last_java_sp->is_valid()) { | |
1077 last_java_sp = SP; | |
1078 } | |
1079 // debugging support | |
1080 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); | |
1081 | |
1082 // 64-bit last_java_sp is biased! | |
1083 set_last_Java_frame(last_java_sp, noreg); | |
1084 if (VerifyThread) mov(G2_thread, O0); // about to be smashed; pass early | |
1085 save_thread(thread_cache); | |
1086 // do the call | |
1087 call(entry_point, relocInfo::runtime_call_type); | |
1088 if (!VerifyThread) | |
1089 delayed()->mov(G2_thread, O0); // pass thread as first argument | |
1090 else | |
1091 delayed()->nop(); // (thread already passed) | |
1092 restore_thread(thread_cache); | |
1093 reset_last_Java_frame(); | |
1094 | |
1095 // check for pending exceptions. use Gtemp as scratch register. | |
1096 if (check_exceptions) { | |
1097 check_and_forward_exception(Gtemp); | |
1098 } | |
1099 | |
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1100 #ifdef ASSERT |
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1101 set(badHeapWordVal, G3); |
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1102 set(badHeapWordVal, G4); |
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1103 set(badHeapWordVal, G5); |
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1104 #endif |
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1105 |
0 | 1106 // get oop result if there is one and reset the value in the thread |
1107 if (oop_result->is_valid()) { | |
1108 get_vm_result(oop_result); | |
1109 } | |
1110 } | |
1111 | |
1112 void MacroAssembler::check_and_forward_exception(Register scratch_reg) | |
1113 { | |
1114 Label L; | |
1115 | |
1116 check_and_handle_popframe(scratch_reg); | |
1117 check_and_handle_earlyret(scratch_reg); | |
1118 | |
727 | 1119 Address exception_addr(G2_thread, Thread::pending_exception_offset()); |
0 | 1120 ld_ptr(exception_addr, scratch_reg); |
3839 | 1121 br_null_short(scratch_reg, pt, L); |
0 | 1122 // we use O7 linkage so that forward_exception_entry has the issuing PC |
1123 call(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type); | |
1124 delayed()->nop(); | |
1125 bind(L); | |
1126 } | |
1127 | |
1128 | |
1129 void MacroAssembler::check_and_handle_popframe(Register scratch_reg) { | |
1130 } | |
1131 | |
1132 | |
1133 void MacroAssembler::check_and_handle_earlyret(Register scratch_reg) { | |
1134 } | |
1135 | |
1136 | |
1137 void MacroAssembler::call_VM(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { | |
1138 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions); | |
1139 } | |
1140 | |
1141 | |
1142 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions) { | |
1143 // O0 is reserved for the thread | |
1144 mov(arg_1, O1); | |
1145 call_VM(oop_result, entry_point, 1, check_exceptions); | |
1146 } | |
1147 | |
1148 | |
1149 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) { | |
1150 // O0 is reserved for the thread | |
1151 mov(arg_1, O1); | |
1152 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); | |
1153 call_VM(oop_result, entry_point, 2, check_exceptions); | |
1154 } | |
1155 | |
1156 | |
1157 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) { | |
1158 // O0 is reserved for the thread | |
1159 mov(arg_1, O1); | |
1160 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); | |
1161 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument"); | |
1162 call_VM(oop_result, entry_point, 3, check_exceptions); | |
1163 } | |
1164 | |
1165 | |
1166 | |
1167 // Note: The following call_VM overloadings are useful when a "save" | |
1168 // has already been performed by a stub, and the last Java frame is | |
1169 // the previous one. In that case, last_java_sp must be passed as FP | |
1170 // instead of SP. | |
1171 | |
1172 | |
1173 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments, bool check_exceptions) { | |
1174 call_VM_base(oop_result, noreg, last_java_sp, entry_point, number_of_arguments, check_exceptions); | |
1175 } | |
1176 | |
1177 | |
1178 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions) { | |
1179 // O0 is reserved for the thread | |
1180 mov(arg_1, O1); | |
1181 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); | |
1182 } | |
1183 | |
1184 | |
1185 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) { | |
1186 // O0 is reserved for the thread | |
1187 mov(arg_1, O1); | |
1188 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); | |
1189 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); | |
1190 } | |
1191 | |
1192 | |
1193 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) { | |
1194 // O0 is reserved for the thread | |
1195 mov(arg_1, O1); | |
1196 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); | |
1197 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument"); | |
1198 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); | |
1199 } | |
1200 | |
1201 | |
1202 | |
1203 void MacroAssembler::call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments) { | |
1204 assert_not_delayed(); | |
1205 save_thread(thread_cache); | |
1206 // do the call | |
1207 call(entry_point, relocInfo::runtime_call_type); | |
1208 delayed()->nop(); | |
1209 restore_thread(thread_cache); | |
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1210 #ifdef ASSERT |
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1211 set(badHeapWordVal, G3); |
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1212 set(badHeapWordVal, G4); |
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1213 set(badHeapWordVal, G5); |
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1214 #endif |
0 | 1215 } |
1216 | |
1217 | |
1218 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments) { | |
1219 call_VM_leaf_base(thread_cache, entry_point, number_of_arguments); | |
1220 } | |
1221 | |
1222 | |
1223 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1) { | |
1224 mov(arg_1, O0); | |
1225 call_VM_leaf(thread_cache, entry_point, 1); | |
1226 } | |
1227 | |
1228 | |
1229 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2) { | |
1230 mov(arg_1, O0); | |
1231 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument"); | |
1232 call_VM_leaf(thread_cache, entry_point, 2); | |
1233 } | |
1234 | |
1235 | |
1236 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3) { | |
1237 mov(arg_1, O0); | |
1238 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument"); | |
1239 mov(arg_3, O2); assert(arg_3 != O0 && arg_3 != O1, "smashed argument"); | |
1240 call_VM_leaf(thread_cache, entry_point, 3); | |
1241 } | |
1242 | |
1243 | |
1244 void MacroAssembler::get_vm_result(Register oop_result) { | |
1245 verify_thread(); | |
727 | 1246 Address vm_result_addr(G2_thread, JavaThread::vm_result_offset()); |
0 | 1247 ld_ptr( vm_result_addr, oop_result); |
1248 st_ptr(G0, vm_result_addr); | |
1249 verify_oop(oop_result); | |
1250 } | |
1251 | |
1252 | |
1253 void MacroAssembler::get_vm_result_2(Register oop_result) { | |
1254 verify_thread(); | |
727 | 1255 Address vm_result_addr_2(G2_thread, JavaThread::vm_result_2_offset()); |
0 | 1256 ld_ptr(vm_result_addr_2, oop_result); |
1257 st_ptr(G0, vm_result_addr_2); | |
1258 verify_oop(oop_result); | |
1259 } | |
1260 | |
1261 | |
1262 // We require that C code which does not return a value in vm_result will | |
1263 // leave it undisturbed. | |
1264 void MacroAssembler::set_vm_result(Register oop_result) { | |
1265 verify_thread(); | |
727 | 1266 Address vm_result_addr(G2_thread, JavaThread::vm_result_offset()); |
0 | 1267 verify_oop(oop_result); |
1268 | |
1269 # ifdef ASSERT | |
1270 // Check that we are not overwriting any other oop. | |
1271 #ifdef CC_INTERP | |
1272 save_frame(0); | |
1273 #else | |
1274 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod for -Xprof | |
1275 #endif /* CC_INTERP */ | |
1276 ld_ptr(vm_result_addr, L0); | |
1277 tst(L0); | |
1278 restore(); | |
1279 breakpoint_trap(notZero, Assembler::ptr_cc); | |
1280 // } | |
1281 # endif | |
1282 | |
1283 st_ptr(oop_result, vm_result_addr); | |
1284 } | |
1285 | |
1286 | |
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1287 void MacroAssembler::card_table_write(jbyte* byte_map_base, |
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1288 Register tmp, Register obj) { |
0 | 1289 #ifdef _LP64 |
1290 srlx(obj, CardTableModRefBS::card_shift, obj); | |
1291 #else | |
1292 srl(obj, CardTableModRefBS::card_shift, obj); | |
1293 #endif | |
727 | 1294 assert(tmp != obj, "need separate temp reg"); |
1295 set((address) byte_map_base, tmp); | |
1296 stb(G0, tmp, obj); | |
0 | 1297 } |
1298 | |
727 | 1299 |
1300 void MacroAssembler::internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) { | |
0 | 1301 address save_pc; |
1302 int shiftcnt; | |
1303 #ifdef _LP64 | |
1304 # ifdef CHECK_DELAY | |
727 | 1305 assert_not_delayed((char*) "cannot put two instructions in delay slot"); |
0 | 1306 # endif |
1307 v9_dep(); | |
1308 save_pc = pc(); | |
727 | 1309 |
1310 int msb32 = (int) (addrlit.value() >> 32); | |
1311 int lsb32 = (int) (addrlit.value()); | |
1312 | |
1313 if (msb32 == 0 && lsb32 >= 0) { | |
1314 Assembler::sethi(lsb32, d, addrlit.rspec()); | |
0 | 1315 } |
727 | 1316 else if (msb32 == -1) { |
1317 Assembler::sethi(~lsb32, d, addrlit.rspec()); | |
1318 xor3(d, ~low10(~0), d); | |
0 | 1319 } |
1320 else { | |
727 | 1321 Assembler::sethi(msb32, d, addrlit.rspec()); // msb 22-bits |
1322 if (msb32 & 0x3ff) // Any bits? | |
1323 or3(d, msb32 & 0x3ff, d); // msb 32-bits are now in lsb 32 | |
1324 if (lsb32 & 0xFFFFFC00) { // done? | |
1325 if ((lsb32 >> 20) & 0xfff) { // Any bits set? | |
1326 sllx(d, 12, d); // Make room for next 12 bits | |
1327 or3(d, (lsb32 >> 20) & 0xfff, d); // Or in next 12 | |
1328 shiftcnt = 0; // We already shifted | |
0 | 1329 } |
1330 else | |
1331 shiftcnt = 12; | |
727 | 1332 if ((lsb32 >> 10) & 0x3ff) { |
1333 sllx(d, shiftcnt + 10, d); // Make room for last 10 bits | |
1334 or3(d, (lsb32 >> 10) & 0x3ff, d); // Or in next 10 | |
0 | 1335 shiftcnt = 0; |
1336 } | |
1337 else | |
1338 shiftcnt = 10; | |
727 | 1339 sllx(d, shiftcnt + 10, d); // Shift leaving disp field 0'd |
0 | 1340 } |
1341 else | |
727 | 1342 sllx(d, 32, d); |
0 | 1343 } |
727 | 1344 // Pad out the instruction sequence so it can be patched later. |
1345 if (ForceRelocatable || (addrlit.rtype() != relocInfo::none && | |
1346 addrlit.rtype() != relocInfo::runtime_call_type)) { | |
1347 while (pc() < (save_pc + (7 * BytesPerInstWord))) | |
0 | 1348 nop(); |
1349 } | |
1350 #else | |
727 | 1351 Assembler::sethi(addrlit.value(), d, addrlit.rspec()); |
0 | 1352 #endif |
727 | 1353 } |
1354 | |
1355 | |
1356 void MacroAssembler::sethi(const AddressLiteral& addrlit, Register d) { | |
1357 internal_sethi(addrlit, d, false); | |
0 | 1358 } |
1359 | |
727 | 1360 |
1361 void MacroAssembler::patchable_sethi(const AddressLiteral& addrlit, Register d) { | |
1362 internal_sethi(addrlit, d, true); | |
1363 } | |
1364 | |
1365 | |
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1366 int MacroAssembler::insts_for_sethi(address a, bool worst_case) { |
0 | 1367 #ifdef _LP64 |
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1368 if (worst_case) return 7; |
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1369 intptr_t iaddr = (intptr_t) a; |
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1370 int msb32 = (int) (iaddr >> 32); |
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1371 int lsb32 = (int) (iaddr); |
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1372 int count; |
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1373 if (msb32 == 0 && lsb32 >= 0) |
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1374 count = 1; |
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1375 else if (msb32 == -1) |
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1376 count = 2; |
0 | 1377 else { |
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1378 count = 2; |
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1379 if (msb32 & 0x3ff) |
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1380 count++; |
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1381 if (lsb32 & 0xFFFFFC00 ) { |
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1382 if ((lsb32 >> 20) & 0xfff) count += 2; |
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1383 if ((lsb32 >> 10) & 0x3ff) count += 2; |
0 | 1384 } |
1385 } | |
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1386 return count; |
0 | 1387 #else |
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1388 return 1; |
0 | 1389 #endif |
1390 } | |
1391 | |
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1392 int MacroAssembler::worst_case_insts_for_set() { |
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1393 return insts_for_sethi(NULL, true) + 1; |
0 | 1394 } |
1395 | |
727 | 1396 |
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1397 // Keep in sync with MacroAssembler::insts_for_internal_set |
727 | 1398 void MacroAssembler::internal_set(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) { |
1399 intptr_t value = addrlit.value(); | |
1400 | |
1401 if (!ForceRelocatable && addrlit.rspec().type() == relocInfo::none) { | |
0 | 1402 // can optimize |
727 | 1403 if (-4096 <= value && value <= 4095) { |
0 | 1404 or3(G0, value, d); // setsw (this leaves upper 32 bits sign-extended) |
1405 return; | |
1406 } | |
1407 if (inv_hi22(hi22(value)) == value) { | |
727 | 1408 sethi(addrlit, d); |
0 | 1409 return; |
1410 } | |
1411 } | |
727 | 1412 assert_not_delayed((char*) "cannot put two instructions in delay slot"); |
1413 internal_sethi(addrlit, d, ForceRelocatable); | |
1414 if (ForceRelocatable || addrlit.rspec().type() != relocInfo::none || addrlit.low10() != 0) { | |
1415 add(d, addrlit.low10(), d, addrlit.rspec()); | |
0 | 1416 } |
1417 } | |
1418 | |
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1419 // Keep in sync with MacroAssembler::internal_set |
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1420 int MacroAssembler::insts_for_internal_set(intptr_t value) { |
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1421 // can optimize |
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1422 if (-4096 <= value && value <= 4095) { |
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1423 return 1; |
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1424 } |
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1425 if (inv_hi22(hi22(value)) == value) { |
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1426 return insts_for_sethi((address) value); |
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1427 } |
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1428 int count = insts_for_sethi((address) value); |
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1429 AddressLiteral al(value); |
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1430 if (al.low10() != 0) { |
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1431 count++; |
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1432 } |
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1433 return count; |
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1434 } |
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1435 |
727 | 1436 void MacroAssembler::set(const AddressLiteral& al, Register d) { |
1437 internal_set(al, d, false); | |
1438 } | |
1439 | |
1440 void MacroAssembler::set(intptr_t value, Register d) { | |
1441 AddressLiteral al(value); | |
1442 internal_set(al, d, false); | |
0 | 1443 } |
1444 | |
727 | 1445 void MacroAssembler::set(address addr, Register d, RelocationHolder const& rspec) { |
1446 AddressLiteral al(addr, rspec); | |
1447 internal_set(al, d, false); | |
1448 } | |
1449 | |
1450 void MacroAssembler::patchable_set(const AddressLiteral& al, Register d) { | |
1451 internal_set(al, d, true); | |
1452 } | |
1453 | |
1454 void MacroAssembler::patchable_set(intptr_t value, Register d) { | |
1455 AddressLiteral al(value); | |
1456 internal_set(al, d, true); | |
1457 } | |
0 | 1458 |
1459 | |
1460 void MacroAssembler::set64(jlong value, Register d, Register tmp) { | |
1461 assert_not_delayed(); | |
1462 v9_dep(); | |
1463 | |
1464 int hi = (int)(value >> 32); | |
1465 int lo = (int)(value & ~0); | |
1466 // (Matcher::isSimpleConstant64 knows about the following optimizations.) | |
1467 if (Assembler::is_simm13(lo) && value == lo) { | |
1468 or3(G0, lo, d); | |
1469 } else if (hi == 0) { | |
1470 Assembler::sethi(lo, d); // hardware version zero-extends to upper 32 | |
1471 if (low10(lo) != 0) | |
1472 or3(d, low10(lo), d); | |
1473 } | |
1474 else if (hi == -1) { | |
1475 Assembler::sethi(~lo, d); // hardware version zero-extends to upper 32 | |
1476 xor3(d, low10(lo) ^ ~low10(~0), d); | |
1477 } | |
1478 else if (lo == 0) { | |
1479 if (Assembler::is_simm13(hi)) { | |
1480 or3(G0, hi, d); | |
1481 } else { | |
1482 Assembler::sethi(hi, d); // hardware version zero-extends to upper 32 | |
1483 if (low10(hi) != 0) | |
1484 or3(d, low10(hi), d); | |
1485 } | |
1486 sllx(d, 32, d); | |
1487 } | |
1488 else { | |
1489 Assembler::sethi(hi, tmp); | |
1490 Assembler::sethi(lo, d); // macro assembler version sign-extends | |
1491 if (low10(hi) != 0) | |
1492 or3 (tmp, low10(hi), tmp); | |
1493 if (low10(lo) != 0) | |
1494 or3 ( d, low10(lo), d); | |
1495 sllx(tmp, 32, tmp); | |
1496 or3 (d, tmp, d); | |
1497 } | |
1498 } | |
1499 | |
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1500 int MacroAssembler::insts_for_set64(jlong value) { |
2008 | 1501 v9_dep(); |
1502 | |
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1503 int hi = (int) (value >> 32); |
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1504 int lo = (int) (value & ~0); |
2008 | 1505 int count = 0; |
1506 | |
1507 // (Matcher::isSimpleConstant64 knows about the following optimizations.) | |
1508 if (Assembler::is_simm13(lo) && value == lo) { | |
1509 count++; | |
1510 } else if (hi == 0) { | |
1511 count++; | |
1512 if (low10(lo) != 0) | |
1513 count++; | |
1514 } | |
1515 else if (hi == -1) { | |
1516 count += 2; | |
1517 } | |
1518 else if (lo == 0) { | |
1519 if (Assembler::is_simm13(hi)) { | |
1520 count++; | |
1521 } else { | |
1522 count++; | |
1523 if (low10(hi) != 0) | |
1524 count++; | |
1525 } | |
1526 count++; | |
1527 } | |
1528 else { | |
1529 count += 2; | |
1530 if (low10(hi) != 0) | |
1531 count++; | |
1532 if (low10(lo) != 0) | |
1533 count++; | |
1534 count += 2; | |
1535 } | |
1536 return count; | |
1537 } | |
1538 | |
0 | 1539 // compute size in bytes of sparc frame, given |
1540 // number of extraWords | |
1541 int MacroAssembler::total_frame_size_in_bytes(int extraWords) { | |
1542 | |
1543 int nWords = frame::memory_parameter_word_sp_offset; | |
1544 | |
1545 nWords += extraWords; | |
1546 | |
1547 if (nWords & 1) ++nWords; // round up to double-word | |
1548 | |
1549 return nWords * BytesPerWord; | |
1550 } | |
1551 | |
1552 | |
1553 // save_frame: given number of "extra" words in frame, | |
1554 // issue approp. save instruction (p 200, v8 manual) | |
1555 | |
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1556 void MacroAssembler::save_frame(int extraWords) { |
0 | 1557 int delta = -total_frame_size_in_bytes(extraWords); |
1558 if (is_simm13(delta)) { | |
1559 save(SP, delta, SP); | |
1560 } else { | |
1561 set(delta, G3_scratch); | |
1562 save(SP, G3_scratch, SP); | |
1563 } | |
1564 } | |
1565 | |
1566 | |
1567 void MacroAssembler::save_frame_c1(int size_in_bytes) { | |
1568 if (is_simm13(-size_in_bytes)) { | |
1569 save(SP, -size_in_bytes, SP); | |
1570 } else { | |
1571 set(-size_in_bytes, G3_scratch); | |
1572 save(SP, G3_scratch, SP); | |
1573 } | |
1574 } | |
1575 | |
1576 | |
1577 void MacroAssembler::save_frame_and_mov(int extraWords, | |
1578 Register s1, Register d1, | |
1579 Register s2, Register d2) { | |
1580 assert_not_delayed(); | |
1581 | |
1582 // The trick here is to use precisely the same memory word | |
1583 // that trap handlers also use to save the register. | |
1584 // This word cannot be used for any other purpose, but | |
1585 // it works fine to save the register's value, whether or not | |
1586 // an interrupt flushes register windows at any given moment! | |
1587 Address s1_addr; | |
1588 if (s1->is_valid() && (s1->is_in() || s1->is_local())) { | |
1589 s1_addr = s1->address_in_saved_window(); | |
1590 st_ptr(s1, s1_addr); | |
1591 } | |
1592 | |
1593 Address s2_addr; | |
1594 if (s2->is_valid() && (s2->is_in() || s2->is_local())) { | |
1595 s2_addr = s2->address_in_saved_window(); | |
1596 st_ptr(s2, s2_addr); | |
1597 } | |
1598 | |
1599 save_frame(extraWords); | |
1600 | |
1601 if (s1_addr.base() == SP) { | |
1602 ld_ptr(s1_addr.after_save(), d1); | |
1603 } else if (s1->is_valid()) { | |
1604 mov(s1->after_save(), d1); | |
1605 } | |
1606 | |
1607 if (s2_addr.base() == SP) { | |
1608 ld_ptr(s2_addr.after_save(), d2); | |
1609 } else if (s2->is_valid()) { | |
1610 mov(s2->after_save(), d2); | |
1611 } | |
1612 } | |
1613 | |
1614 | |
727 | 1615 AddressLiteral MacroAssembler::allocate_oop_address(jobject obj) { |
0 | 1616 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
1617 int oop_index = oop_recorder()->allocate_index(obj); | |
727 | 1618 return AddressLiteral(obj, oop_Relocation::spec(oop_index)); |
0 | 1619 } |
1620 | |
1621 | |
727 | 1622 AddressLiteral MacroAssembler::constant_oop_address(jobject obj) { |
0 | 1623 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
1624 int oop_index = oop_recorder()->find_index(obj); | |
727 | 1625 return AddressLiteral(obj, oop_Relocation::spec(oop_index)); |
0 | 1626 } |
1627 | |
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1628 void MacroAssembler::set_narrow_oop(jobject obj, Register d) { |
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1629 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
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1630 int oop_index = oop_recorder()->find_index(obj); |
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1631 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
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1632 |
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1633 assert_not_delayed(); |
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1634 // Relocation with special format (see relocInfo_sparc.hpp). |
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1635 relocate(rspec, 1); |
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1636 // Assembler::sethi(0x3fffff, d); |
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1637 emit_long( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(0x3fffff) ); |
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1638 // Don't add relocation for 'add'. Do patching during 'sethi' processing. |
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1639 add(d, 0x3ff, d); |
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1640 |
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1641 } |
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1642 |
0 | 1643 |
1644 void MacroAssembler::align(int modulus) { | |
1645 while (offset() % modulus != 0) nop(); | |
1646 } | |
1647 | |
1648 | |
1649 void MacroAssembler::safepoint() { | |
1650 relocate(breakpoint_Relocation::spec(breakpoint_Relocation::safepoint)); | |
1651 } | |
1652 | |
1653 | |
1654 void RegistersForDebugging::print(outputStream* s) { | |
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1655 FlagSetting fs(Debugging, true); |
0 | 1656 int j; |
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1657 for (j = 0; j < 8; ++j) { |
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1658 if (j != 6) { s->print("i%d = ", j); os::print_location(s, i[j]); } |
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1659 else { s->print( "fp = " ); os::print_location(s, i[j]); } |
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1660 } |
0 | 1661 s->cr(); |
1662 | |
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1663 for (j = 0; j < 8; ++j) { |
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1664 s->print("l%d = ", j); os::print_location(s, l[j]); |
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1665 } |
0 | 1666 s->cr(); |
1667 | |
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1668 for (j = 0; j < 8; ++j) { |
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1669 if (j != 6) { s->print("o%d = ", j); os::print_location(s, o[j]); } |
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1670 else { s->print( "sp = " ); os::print_location(s, o[j]); } |
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1671 } |
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1672 s->cr(); |
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1673 |
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1674 for (j = 0; j < 8; ++j) { |
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1675 s->print("g%d = ", j); os::print_location(s, g[j]); |
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1676 } |
0 | 1677 s->cr(); |
1678 | |
1679 // print out floats with compression | |
1680 for (j = 0; j < 32; ) { | |
1681 jfloat val = f[j]; | |
1682 int last = j; | |
1683 for ( ; last+1 < 32; ++last ) { | |
1684 char b1[1024], b2[1024]; | |
1685 sprintf(b1, "%f", val); | |
1686 sprintf(b2, "%f", f[last+1]); | |
1687 if (strcmp(b1, b2)) | |
1688 break; | |
1689 } | |
1690 s->print("f%d", j); | |
1691 if ( j != last ) s->print(" - f%d", last); | |
1692 s->print(" = %f", val); | |
1693 s->fill_to(25); | |
1694 s->print_cr(" (0x%x)", val); | |
1695 j = last + 1; | |
1696 } | |
1697 s->cr(); | |
1698 | |
1699 // and doubles (evens only) | |
1700 for (j = 0; j < 32; ) { | |
1701 jdouble val = d[j]; | |
1702 int last = j; | |
1703 for ( ; last+1 < 32; ++last ) { | |
1704 char b1[1024], b2[1024]; | |
1705 sprintf(b1, "%f", val); | |
1706 sprintf(b2, "%f", d[last+1]); | |
1707 if (strcmp(b1, b2)) | |
1708 break; | |
1709 } | |
1710 s->print("d%d", 2 * j); | |
1711 if ( j != last ) s->print(" - d%d", last); | |
1712 s->print(" = %f", val); | |
1713 s->fill_to(30); | |
1714 s->print("(0x%x)", *(int*)&val); | |
1715 s->fill_to(42); | |
1716 s->print_cr("(0x%x)", *(1 + (int*)&val)); | |
1717 j = last + 1; | |
1718 } | |
1719 s->cr(); | |
1720 } | |
1721 | |
1722 void RegistersForDebugging::save_registers(MacroAssembler* a) { | |
1723 a->sub(FP, round_to(sizeof(RegistersForDebugging), sizeof(jdouble)) - STACK_BIAS, O0); | |
1724 a->flush_windows(); | |
1725 int i; | |
1726 for (i = 0; i < 8; ++i) { | |
1727 a->ld_ptr(as_iRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, i_offset(i)); | |
1728 a->ld_ptr(as_lRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, l_offset(i)); | |
1729 a->st_ptr(as_oRegister(i)->after_save(), O0, o_offset(i)); | |
1730 a->st_ptr(as_gRegister(i)->after_save(), O0, g_offset(i)); | |
1731 } | |
1732 for (i = 0; i < 32; ++i) { | |
1733 a->stf(FloatRegisterImpl::S, as_FloatRegister(i), O0, f_offset(i)); | |
1734 } | |
1735 for (i = 0; i < (VM_Version::v9_instructions_work() ? 64 : 32); i += 2) { | |
1736 a->stf(FloatRegisterImpl::D, as_FloatRegister(i), O0, d_offset(i)); | |
1737 } | |
1738 } | |
1739 | |
1740 void RegistersForDebugging::restore_registers(MacroAssembler* a, Register r) { | |
1741 for (int i = 1; i < 8; ++i) { | |
1742 a->ld_ptr(r, g_offset(i), as_gRegister(i)); | |
1743 } | |
1744 for (int j = 0; j < 32; ++j) { | |
1745 a->ldf(FloatRegisterImpl::S, O0, f_offset(j), as_FloatRegister(j)); | |
1746 } | |
1747 for (int k = 0; k < (VM_Version::v9_instructions_work() ? 64 : 32); k += 2) { | |
1748 a->ldf(FloatRegisterImpl::D, O0, d_offset(k), as_FloatRegister(k)); | |
1749 } | |
1750 } | |
1751 | |
1752 | |
1753 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack | |
1754 void MacroAssembler::push_fTOS() { | |
1755 // %%%%%% need to implement this | |
1756 } | |
1757 | |
1758 // pops double TOS element from CPU stack and pushes on FPU stack | |
1759 void MacroAssembler::pop_fTOS() { | |
1760 // %%%%%% need to implement this | |
1761 } | |
1762 | |
1763 void MacroAssembler::empty_FPU_stack() { | |
1764 // %%%%%% need to implement this | |
1765 } | |
1766 | |
1767 void MacroAssembler::_verify_oop(Register reg, const char* msg, const char * file, int line) { | |
1768 // plausibility check for oops | |
1769 if (!VerifyOops) return; | |
1770 | |
1771 if (reg == G0) return; // always NULL, which is always an oop | |
1772 | |
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1773 BLOCK_COMMENT("verify_oop {"); |
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1774 char buffer[64]; |
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1775 #ifdef COMPILER1 |
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1776 if (CommentedAssembly) { |
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1777 snprintf(buffer, sizeof(buffer), "verify_oop at %d", offset()); |
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1778 block_comment(buffer); |
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1779 } |
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1780 #endif |
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1781 |
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1782 int len = strlen(file) + strlen(msg) + 1 + 4; |
0 | 1783 sprintf(buffer, "%d", line); |
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1784 len += strlen(buffer); |
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1785 sprintf(buffer, " at offset %d ", offset()); |
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1786 len += strlen(buffer); |
0 | 1787 char * real_msg = new char[len]; |
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1788 sprintf(real_msg, "%s%s(%s:%d)", msg, buffer, file, line); |
0 | 1789 |
1790 // Call indirectly to solve generation ordering problem | |
727 | 1791 AddressLiteral a(StubRoutines::verify_oop_subroutine_entry_address()); |
0 | 1792 |
1793 // Make some space on stack above the current register window. | |
1794 // Enough to hold 8 64-bit registers. | |
1795 add(SP,-8*8,SP); | |
1796 | |
1797 // Save some 64-bit registers; a normal 'save' chops the heads off | |
1798 // of 64-bit longs in the 32-bit build. | |
1799 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8); | |
1800 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8); | |
1801 mov(reg,O0); // Move arg into O0; arg might be in O7 which is about to be crushed | |
1802 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8); | |
1803 | |
3898 | 1804 // Size of set() should stay the same |
1805 patchable_set((intptr_t)real_msg, O1); | |
0 | 1806 // Load address to call to into O7 |
1807 load_ptr_contents(a, O7); | |
1808 // Register call to verify_oop_subroutine | |
1809 callr(O7, G0); | |
1810 delayed()->nop(); | |
1811 // recover frame size | |
1812 add(SP, 8*8,SP); | |
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1813 BLOCK_COMMENT("} verify_oop"); |
0 | 1814 } |
1815 | |
1816 void MacroAssembler::_verify_oop_addr(Address addr, const char* msg, const char * file, int line) { | |
1817 // plausibility check for oops | |
1818 if (!VerifyOops) return; | |
1819 | |
1820 char buffer[64]; | |
1821 sprintf(buffer, "%d", line); | |
1822 int len = strlen(file) + strlen(msg) + 1 + 4 + strlen(buffer); | |
1823 sprintf(buffer, " at SP+%d ", addr.disp()); | |
1824 len += strlen(buffer); | |
1825 char * real_msg = new char[len]; | |
1826 sprintf(real_msg, "%s at SP+%d (%s:%d)", msg, addr.disp(), file, line); | |
1827 | |
1828 // Call indirectly to solve generation ordering problem | |
727 | 1829 AddressLiteral a(StubRoutines::verify_oop_subroutine_entry_address()); |
0 | 1830 |
1831 // Make some space on stack above the current register window. | |
1832 // Enough to hold 8 64-bit registers. | |
1833 add(SP,-8*8,SP); | |
1834 | |
1835 // Save some 64-bit registers; a normal 'save' chops the heads off | |
1836 // of 64-bit longs in the 32-bit build. | |
1837 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8); | |
1838 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8); | |
1839 ld_ptr(addr.base(), addr.disp() + 8*8, O0); // Load arg into O0; arg might be in O7 which is about to be crushed | |
1840 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8); | |
1841 | |
3898 | 1842 // Size of set() should stay the same |
1843 patchable_set((intptr_t)real_msg, O1); | |
0 | 1844 // Load address to call to into O7 |
1845 load_ptr_contents(a, O7); | |
1846 // Register call to verify_oop_subroutine | |
1847 callr(O7, G0); | |
1848 delayed()->nop(); | |
1849 // recover frame size | |
1850 add(SP, 8*8,SP); | |
1851 } | |
1852 | |
1853 // side-door communication with signalHandler in os_solaris.cpp | |
1854 address MacroAssembler::_verify_oop_implicit_branch[3] = { NULL }; | |
1855 | |
1856 // This macro is expanded just once; it creates shared code. Contract: | |
1857 // receives an oop in O0. Must restore O0 & O7 from TLS. Must not smash ANY | |
1858 // registers, including flags. May not use a register 'save', as this blows | |
1859 // the high bits of the O-regs if they contain Long values. Acts as a 'leaf' | |
1860 // call. | |
1861 void MacroAssembler::verify_oop_subroutine() { | |
1862 assert( VM_Version::v9_instructions_work(), "VerifyOops not supported for V8" ); | |
1863 | |
1864 // Leaf call; no frame. | |
1865 Label succeed, fail, null_or_fail; | |
1866 | |
1867 // O0 and O7 were saved already (O0 in O0's TLS home, O7 in O5's TLS home). | |
1868 // O0 is now the oop to be checked. O7 is the return address. | |
1869 Register O0_obj = O0; | |
1870 | |
1871 // Save some more registers for temps. | |
1872 stx(O2,SP,frame::register_save_words*wordSize+STACK_BIAS+2*8); | |
1873 stx(O3,SP,frame::register_save_words*wordSize+STACK_BIAS+3*8); | |
1874 stx(O4,SP,frame::register_save_words*wordSize+STACK_BIAS+4*8); | |
1875 stx(O5,SP,frame::register_save_words*wordSize+STACK_BIAS+5*8); | |
1876 | |
1877 // Save flags | |
1878 Register O5_save_flags = O5; | |
1879 rdccr( O5_save_flags ); | |
1880 | |
1881 { // count number of verifies | |
1882 Register O2_adr = O2; | |
1883 Register O3_accum = O3; | |
727 | 1884 inc_counter(StubRoutines::verify_oop_count_addr(), O2_adr, O3_accum); |
0 | 1885 } |
1886 | |
1887 Register O2_mask = O2; | |
1888 Register O3_bits = O3; | |
1889 Register O4_temp = O4; | |
1890 | |
1891 // mark lower end of faulting range | |
1892 assert(_verify_oop_implicit_branch[0] == NULL, "set once"); | |
1893 _verify_oop_implicit_branch[0] = pc(); | |
1894 | |
1895 // We can't check the mark oop because it could be in the process of | |
1896 // locking or unlocking while this is running. | |
1897 set(Universe::verify_oop_mask (), O2_mask); | |
1898 set(Universe::verify_oop_bits (), O3_bits); | |
1899 | |
1900 // assert((obj & oop_mask) == oop_bits); | |
1901 and3(O0_obj, O2_mask, O4_temp); | |
3839 | 1902 cmp_and_brx_short(O4_temp, O3_bits, notEqual, pn, null_or_fail); |
0 | 1903 |
1904 if ((NULL_WORD & Universe::verify_oop_mask()) == Universe::verify_oop_bits()) { | |
1905 // the null_or_fail case is useless; must test for null separately | |
3839 | 1906 br_null_short(O0_obj, pn, succeed); |
0 | 1907 } |
1908 | |
1909 // Check the klassOop of this object for being in the right area of memory. | |
1910 // Cannot do the load in the delay above slot in case O0 is null | |
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1911 load_klass(O0_obj, O0_obj); |
0 | 1912 // assert((klass & klass_mask) == klass_bits); |
1913 if( Universe::verify_klass_mask() != Universe::verify_oop_mask() ) | |
1914 set(Universe::verify_klass_mask(), O2_mask); | |
1915 if( Universe::verify_klass_bits() != Universe::verify_oop_bits() ) | |
1916 set(Universe::verify_klass_bits(), O3_bits); | |
1917 and3(O0_obj, O2_mask, O4_temp); | |
3839 | 1918 cmp_and_brx_short(O4_temp, O3_bits, notEqual, pn, fail); |
0 | 1919 // Check the klass's klass |
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1920 load_klass(O0_obj, O0_obj); |
0 | 1921 and3(O0_obj, O2_mask, O4_temp); |
1922 cmp(O4_temp, O3_bits); | |
1923 brx(notEqual, false, pn, fail); | |
1924 delayed()->wrccr( O5_save_flags ); // Restore CCR's | |
1925 | |
1926 // mark upper end of faulting range | |
1927 _verify_oop_implicit_branch[1] = pc(); | |
1928 | |
1929 //----------------------- | |
1930 // all tests pass | |
1931 bind(succeed); | |
1932 | |
1933 // Restore prior 64-bit registers | |
1934 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+0*8,O0); | |
1935 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+1*8,O1); | |
1936 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+2*8,O2); | |
1937 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+3*8,O3); | |
1938 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+4*8,O4); | |
1939 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+5*8,O5); | |
1940 | |
1941 retl(); // Leaf return; restore prior O7 in delay slot | |
1942 delayed()->ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+7*8,O7); | |
1943 | |
1944 //----------------------- | |
1945 bind(null_or_fail); // nulls are less common but OK | |
1946 br_null(O0_obj, false, pt, succeed); | |
1947 delayed()->wrccr( O5_save_flags ); // Restore CCR's | |
1948 | |
1949 //----------------------- | |
1950 // report failure: | |
1951 bind(fail); | |
1952 _verify_oop_implicit_branch[2] = pc(); | |
1953 | |
1954 wrccr( O5_save_flags ); // Restore CCR's | |
1955 | |
1956 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2)); | |
1957 | |
1958 // stop_subroutine expects message pointer in I1. | |
1959 mov(I1, O1); | |
1960 | |
1961 // Restore prior 64-bit registers | |
1962 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+0*8,I0); | |
1963 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+1*8,I1); | |
1964 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+2*8,I2); | |
1965 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+3*8,I3); | |
1966 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+4*8,I4); | |
1967 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+5*8,I5); | |
1968 | |
1969 // factor long stop-sequence into subroutine to save space | |
1970 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet"); | |
1971 | |
1972 // call indirectly to solve generation ordering problem | |
727 | 1973 AddressLiteral al(StubRoutines::Sparc::stop_subroutine_entry_address()); |
1974 load_ptr_contents(al, O5); | |
0 | 1975 jmpl(O5, 0, O7); |
1976 delayed()->nop(); | |
1977 } | |
1978 | |
1979 | |
1980 void MacroAssembler::stop(const char* msg) { | |
1981 // save frame first to get O7 for return address | |
1982 // add one word to size in case struct is odd number of words long | |
1983 // It must be doubleword-aligned for storing doubles into it. | |
1984 | |
1985 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2)); | |
1986 | |
1987 // stop_subroutine expects message pointer in I1. | |
3898 | 1988 // Size of set() should stay the same |
1989 patchable_set((intptr_t)msg, O1); | |
0 | 1990 |
1991 // factor long stop-sequence into subroutine to save space | |
1992 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet"); | |
1993 | |
1994 // call indirectly to solve generation ordering problem | |
727 | 1995 AddressLiteral a(StubRoutines::Sparc::stop_subroutine_entry_address()); |
0 | 1996 load_ptr_contents(a, O5); |
1997 jmpl(O5, 0, O7); | |
1998 delayed()->nop(); | |
1999 | |
2000 breakpoint_trap(); // make stop actually stop rather than writing | |
2001 // unnoticeable results in the output files. | |
2002 | |
2003 // restore(); done in callee to save space! | |
2004 } | |
2005 | |
2006 | |
2007 void MacroAssembler::warn(const char* msg) { | |
2008 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2)); | |
2009 RegistersForDebugging::save_registers(this); | |
2010 mov(O0, L0); | |
3898 | 2011 // Size of set() should stay the same |
2012 patchable_set((intptr_t)msg, O0); | |
0 | 2013 call( CAST_FROM_FN_PTR(address, warning) ); |
2014 delayed()->nop(); | |
2015 // ret(); | |
2016 // delayed()->restore(); | |
2017 RegistersForDebugging::restore_registers(this, L0); | |
2018 restore(); | |
2019 } | |
2020 | |
2021 | |
2022 void MacroAssembler::untested(const char* what) { | |
2023 // We must be able to turn interactive prompting off | |
2024 // in order to run automated test scripts on the VM | |
2025 // Use the flag ShowMessageBoxOnError | |
2026 | |
2027 char* b = new char[1024]; | |
2028 sprintf(b, "untested: %s", what); | |
2029 | |
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2030 if (ShowMessageBoxOnError) { STOP(b); } |
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2031 else { warn(b); } |
0 | 2032 } |
2033 | |
2034 | |
2035 void MacroAssembler::stop_subroutine() { | |
2036 RegistersForDebugging::save_registers(this); | |
2037 | |
2038 // for the sake of the debugger, stick a PC on the current frame | |
2039 // (this assumes that the caller has performed an extra "save") | |
2040 mov(I7, L7); | |
2041 add(O7, -7 * BytesPerInt, I7); | |
2042 | |
2043 save_frame(); // one more save to free up another O7 register | |
2044 mov(I0, O1); // addr of reg save area | |
2045 | |
2046 // We expect pointer to message in I1. Caller must set it up in O1 | |
2047 mov(I1, O0); // get msg | |
2048 call (CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type); | |
2049 delayed()->nop(); | |
2050 | |
2051 restore(); | |
2052 | |
2053 RegistersForDebugging::restore_registers(this, O0); | |
2054 | |
2055 save_frame(0); | |
2056 call(CAST_FROM_FN_PTR(address,breakpoint)); | |
2057 delayed()->nop(); | |
2058 restore(); | |
2059 | |
2060 mov(L7, I7); | |
2061 retl(); | |
2062 delayed()->restore(); // see stop above | |
2063 } | |
2064 | |
2065 | |
2066 void MacroAssembler::debug(char* msg, RegistersForDebugging* regs) { | |
2067 if ( ShowMessageBoxOnError ) { | |
2068 JavaThreadState saved_state = JavaThread::current()->thread_state(); | |
2069 JavaThread::current()->set_thread_state(_thread_in_vm); | |
2070 { | |
2071 // In order to get locks work, we need to fake a in_VM state | |
2072 ttyLocker ttyl; | |
2073 ::tty->print_cr("EXECUTION STOPPED: %s\n", msg); | |
2074 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { | |
2075 ::tty->print_cr("Interpreter::bytecode_counter = %d", BytecodeCounter::counter_value()); | |
2076 } | |
2077 if (os::message_box(msg, "Execution stopped, print registers?")) | |
2078 regs->print(::tty); | |
2079 } | |
2080 ThreadStateTransition::transition(JavaThread::current(), _thread_in_vm, saved_state); | |
2081 } | |
2082 else | |
2083 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); | |
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2084 assert(false, err_msg("DEBUG MESSAGE: %s", msg)); |
0 | 2085 } |
2086 | |
2087 | |
2088 #ifndef PRODUCT | |
2089 void MacroAssembler::test() { | |
2090 ResourceMark rm; | |
2091 | |
2092 CodeBuffer cb("test", 10000, 10000); | |
2093 MacroAssembler* a = new MacroAssembler(&cb); | |
2094 VM_Version::allow_all(); | |
2095 a->test_v9(); | |
2096 a->test_v8_onlys(); | |
2097 VM_Version::revert(); | |
2098 | |
2099 StubRoutines::Sparc::test_stop_entry()(); | |
2100 } | |
2101 #endif | |
2102 | |
2103 | |
2104 void MacroAssembler::calc_mem_param_words(Register Rparam_words, Register Rresult) { | |
2105 subcc( Rparam_words, Argument::n_register_parameters, Rresult); // how many mem words? | |
2106 Label no_extras; | |
2107 br( negative, true, pt, no_extras ); // if neg, clear reg | |
727 | 2108 delayed()->set(0, Rresult); // annuled, so only if taken |
0 | 2109 bind( no_extras ); |
2110 } | |
2111 | |
2112 | |
2113 void MacroAssembler::calc_frame_size(Register Rextra_words, Register Rresult) { | |
2114 #ifdef _LP64 | |
2115 add(Rextra_words, frame::memory_parameter_word_sp_offset, Rresult); | |
2116 #else | |
2117 add(Rextra_words, frame::memory_parameter_word_sp_offset + 1, Rresult); | |
2118 #endif | |
2119 bclr(1, Rresult); | |
2120 sll(Rresult, LogBytesPerWord, Rresult); // Rresult has total frame bytes | |
2121 } | |
2122 | |
2123 | |
2124 void MacroAssembler::calc_frame_size_and_save(Register Rextra_words, Register Rresult) { | |
2125 calc_frame_size(Rextra_words, Rresult); | |
2126 neg(Rresult); | |
2127 save(SP, Rresult, SP); | |
2128 } | |
2129 | |
2130 | |
2131 // --------------------------------------------------------- | |
2132 Assembler::RCondition cond2rcond(Assembler::Condition c) { | |
2133 switch (c) { | |
2134 /*case zero: */ | |
2135 case Assembler::equal: return Assembler::rc_z; | |
2136 case Assembler::lessEqual: return Assembler::rc_lez; | |
2137 case Assembler::less: return Assembler::rc_lz; | |
2138 /*case notZero:*/ | |
2139 case Assembler::notEqual: return Assembler::rc_nz; | |
2140 case Assembler::greater: return Assembler::rc_gz; | |
2141 case Assembler::greaterEqual: return Assembler::rc_gez; | |
2142 } | |
2143 ShouldNotReachHere(); | |
2144 return Assembler::rc_z; | |
2145 } | |
2146 | |
3839 | 2147 // compares (32 bit) register with zero and branches. NOT FOR USE WITH 64-bit POINTERS |
2148 void MacroAssembler::cmp_zero_and_br(Condition c, Register s1, Label& L, bool a, Predict p) { | |
0 | 2149 tst(s1); |
2150 br (c, a, p, L); | |
2151 } | |
2152 | |
2153 // Compares a pointer register with zero and branches on null. | |
2154 // Does a test & branch on 32-bit systems and a register-branch on 64-bit. | |
2155 void MacroAssembler::br_null( Register s1, bool a, Predict p, Label& L ) { | |
2156 assert_not_delayed(); | |
2157 #ifdef _LP64 | |
2158 bpr( rc_z, a, p, s1, L ); | |
2159 #else | |
2160 tst(s1); | |
2161 br ( zero, a, p, L ); | |
2162 #endif | |
2163 } | |
2164 | |
2165 void MacroAssembler::br_notnull( Register s1, bool a, Predict p, Label& L ) { | |
2166 assert_not_delayed(); | |
2167 #ifdef _LP64 | |
2168 bpr( rc_nz, a, p, s1, L ); | |
2169 #else | |
2170 tst(s1); | |
2171 br ( notZero, a, p, L ); | |
2172 #endif | |
2173 } | |
2174 | |
3839 | 2175 // Compare registers and branch with nop in delay slot or cbcond without delay slot. |
2176 | |
2177 // Compare integer (32 bit) values (icc only). | |
2178 void MacroAssembler::cmp_and_br_short(Register s1, Register s2, Condition c, | |
2179 Predict p, Label& L) { | |
2180 assert_not_delayed(); | |
2181 if (use_cbcond(L)) { | |
2182 Assembler::cbcond(c, icc, s1, s2, L); | |
2183 } else { | |
2184 cmp(s1, s2); | |
2185 br(c, false, p, L); | |
2186 delayed()->nop(); | |
2187 } | |
2188 } | |
2189 | |
2190 // Compare integer (32 bit) values (icc only). | |
2191 void MacroAssembler::cmp_and_br_short(Register s1, int simm13a, Condition c, | |
2192 Predict p, Label& L) { | |
2193 assert_not_delayed(); | |
2194 if (is_simm(simm13a,5) && use_cbcond(L)) { | |
2195 Assembler::cbcond(c, icc, s1, simm13a, L); | |
2196 } else { | |
2197 cmp(s1, simm13a); | |
2198 br(c, false, p, L); | |
2199 delayed()->nop(); | |
2200 } | |
2201 } | |
2202 | |
2203 // Branch that tests xcc in LP64 and icc in !LP64 | |
2204 void MacroAssembler::cmp_and_brx_short(Register s1, Register s2, Condition c, | |
2205 Predict p, Label& L) { | |
2206 assert_not_delayed(); | |
2207 if (use_cbcond(L)) { | |
2208 Assembler::cbcond(c, ptr_cc, s1, s2, L); | |
2209 } else { | |
2210 cmp(s1, s2); | |
2211 brx(c, false, p, L); | |
2212 delayed()->nop(); | |
2213 } | |
2214 } | |
2215 | |
2216 // Branch that tests xcc in LP64 and icc in !LP64 | |
2217 void MacroAssembler::cmp_and_brx_short(Register s1, int simm13a, Condition c, | |
2218 Predict p, Label& L) { | |
2219 assert_not_delayed(); | |
2220 if (is_simm(simm13a,5) && use_cbcond(L)) { | |
2221 Assembler::cbcond(c, ptr_cc, s1, simm13a, L); | |
2222 } else { | |
2223 cmp(s1, simm13a); | |
2224 brx(c, false, p, L); | |
2225 delayed()->nop(); | |
2226 } | |
2227 } | |
2228 | |
2229 // Short branch version for compares a pointer with zero. | |
2230 | |
2231 void MacroAssembler::br_null_short(Register s1, Predict p, Label& L) { | |
2232 assert_not_delayed(); | |
2233 if (use_cbcond(L)) { | |
2234 Assembler::cbcond(zero, ptr_cc, s1, 0, L); | |
2235 return; | |
2236 } | |
2237 br_null(s1, false, p, L); | |
2238 delayed()->nop(); | |
2239 } | |
2240 | |
2241 void MacroAssembler::br_notnull_short(Register s1, Predict p, Label& L) { | |
2242 assert_not_delayed(); | |
2243 if (use_cbcond(L)) { | |
2244 Assembler::cbcond(notZero, ptr_cc, s1, 0, L); | |
2245 return; | |
2246 } | |
2247 br_notnull(s1, false, p, L); | |
2248 delayed()->nop(); | |
2249 } | |
2250 | |
2251 // Unconditional short branch | |
2252 void MacroAssembler::ba_short(Label& L) { | |
2253 if (use_cbcond(L)) { | |
2254 Assembler::cbcond(equal, icc, G0, G0, L); | |
2255 return; | |
2256 } | |
2257 br(always, false, pt, L); | |
2258 delayed()->nop(); | |
2259 } | |
0 | 2260 |
2261 // instruction sequences factored across compiler & interpreter | |
2262 | |
2263 | |
2264 void MacroAssembler::lcmp( Register Ra_hi, Register Ra_low, | |
2265 Register Rb_hi, Register Rb_low, | |
2266 Register Rresult) { | |
2267 | |
2268 Label check_low_parts, done; | |
2269 | |
2270 cmp(Ra_hi, Rb_hi ); // compare hi parts | |
2271 br(equal, true, pt, check_low_parts); | |
2272 delayed()->cmp(Ra_low, Rb_low); // test low parts | |
2273 | |
2274 // And, with an unsigned comparison, it does not matter if the numbers | |
2275 // are negative or not. | |
2276 // E.g., -2 cmp -1: the low parts are 0xfffffffe and 0xffffffff. | |
2277 // The second one is bigger (unsignedly). | |
2278 | |
2279 // Other notes: The first move in each triplet can be unconditional | |
2280 // (and therefore probably prefetchable). | |
2281 // And the equals case for the high part does not need testing, | |
2282 // since that triplet is reached only after finding the high halves differ. | |
2283 | |
2284 if (VM_Version::v9_instructions_work()) { | |
3839 | 2285 mov(-1, Rresult); |
2286 ba(done); delayed()-> movcc(greater, false, icc, 1, Rresult); | |
2287 } else { | |
0 | 2288 br(less, true, pt, done); delayed()-> set(-1, Rresult); |
2289 br(greater, true, pt, done); delayed()-> set( 1, Rresult); | |
2290 } | |
2291 | |
2292 bind( check_low_parts ); | |
2293 | |
2294 if (VM_Version::v9_instructions_work()) { | |
2295 mov( -1, Rresult); | |
2296 movcc(equal, false, icc, 0, Rresult); | |
2297 movcc(greaterUnsigned, false, icc, 1, Rresult); | |
3839 | 2298 } else { |
2299 set(-1, Rresult); | |
0 | 2300 br(equal, true, pt, done); delayed()->set( 0, Rresult); |
2301 br(greaterUnsigned, true, pt, done); delayed()->set( 1, Rresult); | |
2302 } | |
2303 bind( done ); | |
2304 } | |
2305 | |
2306 void MacroAssembler::lneg( Register Rhi, Register Rlow ) { | |
2307 subcc( G0, Rlow, Rlow ); | |
2308 subc( G0, Rhi, Rhi ); | |
2309 } | |
2310 | |
2311 void MacroAssembler::lshl( Register Rin_high, Register Rin_low, | |
2312 Register Rcount, | |
2313 Register Rout_high, Register Rout_low, | |
2314 Register Rtemp ) { | |
2315 | |
2316 | |
2317 Register Ralt_count = Rtemp; | |
2318 Register Rxfer_bits = Rtemp; | |
2319 | |
2320 assert( Ralt_count != Rin_high | |
2321 && Ralt_count != Rin_low | |
2322 && Ralt_count != Rcount | |
2323 && Rxfer_bits != Rin_low | |
2324 && Rxfer_bits != Rin_high | |
2325 && Rxfer_bits != Rcount | |
2326 && Rxfer_bits != Rout_low | |
2327 && Rout_low != Rin_high, | |
2328 "register alias checks"); | |
2329 | |
2330 Label big_shift, done; | |
2331 | |
2332 // This code can be optimized to use the 64 bit shifts in V9. | |
2333 // Here we use the 32 bit shifts. | |
2334 | |
3839 | 2335 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits |
2336 subcc(Rcount, 31, Ralt_count); | |
0 | 2337 br(greater, true, pn, big_shift); |
3839 | 2338 delayed()->dec(Ralt_count); |
0 | 2339 |
2340 // shift < 32 bits, Ralt_count = Rcount-31 | |
2341 | |
2342 // We get the transfer bits by shifting right by 32-count the low | |
2343 // register. This is done by shifting right by 31-count and then by one | |
2344 // more to take care of the special (rare) case where count is zero | |
2345 // (shifting by 32 would not work). | |
2346 | |
3839 | 2347 neg(Ralt_count); |
0 | 2348 |
2349 // The order of the next two instructions is critical in the case where | |
2350 // Rin and Rout are the same and should not be reversed. | |
2351 | |
3839 | 2352 srl(Rin_low, Ralt_count, Rxfer_bits); // shift right by 31-count |
0 | 2353 if (Rcount != Rout_low) { |
3839 | 2354 sll(Rin_low, Rcount, Rout_low); // low half |
0 | 2355 } |
3839 | 2356 sll(Rin_high, Rcount, Rout_high); |
0 | 2357 if (Rcount == Rout_low) { |
3839 | 2358 sll(Rin_low, Rcount, Rout_low); // low half |
0 | 2359 } |
3839 | 2360 srl(Rxfer_bits, 1, Rxfer_bits ); // shift right by one more |
2361 ba(done); | |
2362 delayed()->or3(Rout_high, Rxfer_bits, Rout_high); // new hi value: or in shifted old hi part and xfer from low | |
0 | 2363 |
2364 // shift >= 32 bits, Ralt_count = Rcount-32 | |
2365 bind(big_shift); | |
3839 | 2366 sll(Rin_low, Ralt_count, Rout_high ); |
2367 clr(Rout_low); | |
0 | 2368 |
2369 bind(done); | |
2370 } | |
2371 | |
2372 | |
2373 void MacroAssembler::lshr( Register Rin_high, Register Rin_low, | |
2374 Register Rcount, | |
2375 Register Rout_high, Register Rout_low, | |
2376 Register Rtemp ) { | |
2377 | |
2378 Register Ralt_count = Rtemp; | |
2379 Register Rxfer_bits = Rtemp; | |
2380 | |
2381 assert( Ralt_count != Rin_high | |
2382 && Ralt_count != Rin_low | |
2383 && Ralt_count != Rcount | |
2384 && Rxfer_bits != Rin_low | |
2385 && Rxfer_bits != Rin_high | |
2386 && Rxfer_bits != Rcount | |
2387 && Rxfer_bits != Rout_high | |
2388 && Rout_high != Rin_low, | |
2389 "register alias checks"); | |
2390 | |
2391 Label big_shift, done; | |
2392 | |
2393 // This code can be optimized to use the 64 bit shifts in V9. | |
2394 // Here we use the 32 bit shifts. | |
2395 | |
3839 | 2396 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits |
2397 subcc(Rcount, 31, Ralt_count); | |
0 | 2398 br(greater, true, pn, big_shift); |
2399 delayed()->dec(Ralt_count); | |
2400 | |
2401 // shift < 32 bits, Ralt_count = Rcount-31 | |
2402 | |
2403 // We get the transfer bits by shifting left by 32-count the high | |
2404 // register. This is done by shifting left by 31-count and then by one | |
2405 // more to take care of the special (rare) case where count is zero | |
2406 // (shifting by 32 would not work). | |
2407 | |
3839 | 2408 neg(Ralt_count); |
0 | 2409 if (Rcount != Rout_low) { |
3839 | 2410 srl(Rin_low, Rcount, Rout_low); |
0 | 2411 } |
2412 | |
2413 // The order of the next two instructions is critical in the case where | |
2414 // Rin and Rout are the same and should not be reversed. | |
2415 | |
3839 | 2416 sll(Rin_high, Ralt_count, Rxfer_bits); // shift left by 31-count |
2417 sra(Rin_high, Rcount, Rout_high ); // high half | |
2418 sll(Rxfer_bits, 1, Rxfer_bits); // shift left by one more | |
0 | 2419 if (Rcount == Rout_low) { |
3839 | 2420 srl(Rin_low, Rcount, Rout_low); |
0 | 2421 } |
3839 | 2422 ba(done); |
2423 delayed()->or3(Rout_low, Rxfer_bits, Rout_low); // new low value: or shifted old low part and xfer from high | |
0 | 2424 |
2425 // shift >= 32 bits, Ralt_count = Rcount-32 | |
2426 bind(big_shift); | |
2427 | |
3839 | 2428 sra(Rin_high, Ralt_count, Rout_low); |
2429 sra(Rin_high, 31, Rout_high); // sign into hi | |
0 | 2430 |
2431 bind( done ); | |
2432 } | |
2433 | |
2434 | |
2435 | |
2436 void MacroAssembler::lushr( Register Rin_high, Register Rin_low, | |
2437 Register Rcount, | |
2438 Register Rout_high, Register Rout_low, | |
2439 Register Rtemp ) { | |
2440 | |
2441 Register Ralt_count = Rtemp; | |
2442 Register Rxfer_bits = Rtemp; | |
2443 | |
2444 assert( Ralt_count != Rin_high | |
2445 && Ralt_count != Rin_low | |
2446 && Ralt_count != Rcount | |
2447 && Rxfer_bits != Rin_low | |
2448 && Rxfer_bits != Rin_high | |
2449 && Rxfer_bits != Rcount | |
2450 && Rxfer_bits != Rout_high | |
2451 && Rout_high != Rin_low, | |
2452 "register alias checks"); | |
2453 | |
2454 Label big_shift, done; | |
2455 | |
2456 // This code can be optimized to use the 64 bit shifts in V9. | |
2457 // Here we use the 32 bit shifts. | |
2458 | |
3839 | 2459 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits |
2460 subcc(Rcount, 31, Ralt_count); | |
0 | 2461 br(greater, true, pn, big_shift); |
2462 delayed()->dec(Ralt_count); | |
2463 | |
2464 // shift < 32 bits, Ralt_count = Rcount-31 | |
2465 | |
2466 // We get the transfer bits by shifting left by 32-count the high | |
2467 // register. This is done by shifting left by 31-count and then by one | |
2468 // more to take care of the special (rare) case where count is zero | |
2469 // (shifting by 32 would not work). | |
2470 | |
3839 | 2471 neg(Ralt_count); |
0 | 2472 if (Rcount != Rout_low) { |
3839 | 2473 srl(Rin_low, Rcount, Rout_low); |
0 | 2474 } |
2475 | |
2476 // The order of the next two instructions is critical in the case where | |
2477 // Rin and Rout are the same and should not be reversed. | |
2478 | |
3839 | 2479 sll(Rin_high, Ralt_count, Rxfer_bits); // shift left by 31-count |
2480 srl(Rin_high, Rcount, Rout_high ); // high half | |
2481 sll(Rxfer_bits, 1, Rxfer_bits); // shift left by one more | |
0 | 2482 if (Rcount == Rout_low) { |
3839 | 2483 srl(Rin_low, Rcount, Rout_low); |
0 | 2484 } |
3839 | 2485 ba(done); |
2486 delayed()->or3(Rout_low, Rxfer_bits, Rout_low); // new low value: or shifted old low part and xfer from high | |
0 | 2487 |
2488 // shift >= 32 bits, Ralt_count = Rcount-32 | |
2489 bind(big_shift); | |
2490 | |
3839 | 2491 srl(Rin_high, Ralt_count, Rout_low); |
2492 clr(Rout_high); | |
0 | 2493 |
2494 bind( done ); | |
2495 } | |
2496 | |
2497 #ifdef _LP64 | |
2498 void MacroAssembler::lcmp( Register Ra, Register Rb, Register Rresult) { | |
2499 cmp(Ra, Rb); | |
3839 | 2500 mov(-1, Rresult); |
0 | 2501 movcc(equal, false, xcc, 0, Rresult); |
2502 movcc(greater, false, xcc, 1, Rresult); | |
2503 } | |
2504 #endif | |
2505 | |
2506 | |
2258
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2507 void MacroAssembler::load_sized_value(Address src, Register dst, size_t size_in_bytes, bool is_signed) { |
1503 | 2508 switch (size_in_bytes) { |
2258
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2509 case 8: ld_long(src, dst); break; |
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2510 case 4: ld( src, dst); break; |
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2511 case 2: is_signed ? ldsh(src, dst) : lduh(src, dst); break; |
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2512 case 1: is_signed ? ldsb(src, dst) : ldub(src, dst); break; |
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2513 default: ShouldNotReachHere(); |
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2514 } |
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2515 } |
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2516 |
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2517 void MacroAssembler::store_sized_value(Register src, Address dst, size_t size_in_bytes) { |
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2518 switch (size_in_bytes) { |
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2519 case 8: st_long(src, dst); break; |
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2520 case 4: st( src, dst); break; |
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2521 case 2: sth( src, dst); break; |
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2522 case 1: stb( src, dst); break; |
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2523 default: ShouldNotReachHere(); |
1503 | 2524 } |
2525 } | |
2526 | |
2527 | |
0 | 2528 void MacroAssembler::float_cmp( bool is_float, int unordered_result, |
2529 FloatRegister Fa, FloatRegister Fb, | |
2530 Register Rresult) { | |
2531 | |
2532 fcmp(is_float ? FloatRegisterImpl::S : FloatRegisterImpl::D, fcc0, Fa, Fb); | |
2533 | |
2534 Condition lt = unordered_result == -1 ? f_unorderedOrLess : f_less; | |
2535 Condition eq = f_equal; | |
2536 Condition gt = unordered_result == 1 ? f_unorderedOrGreater : f_greater; | |
2537 | |
2538 if (VM_Version::v9_instructions_work()) { | |
2539 | |
3839 | 2540 mov(-1, Rresult); |
2541 movcc(eq, true, fcc0, 0, Rresult); | |
2542 movcc(gt, true, fcc0, 1, Rresult); | |
0 | 2543 |
2544 } else { | |
2545 Label done; | |
2546 | |
3839 | 2547 set( -1, Rresult ); |
0 | 2548 //fb(lt, true, pn, done); delayed()->set( -1, Rresult ); |
2549 fb( eq, true, pn, done); delayed()->set( 0, Rresult ); | |
2550 fb( gt, true, pn, done); delayed()->set( 1, Rresult ); | |
2551 | |
2552 bind (done); | |
2553 } | |
2554 } | |
2555 | |
2556 | |
2557 void MacroAssembler::fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) | |
2558 { | |
2559 if (VM_Version::v9_instructions_work()) { | |
2560 Assembler::fneg(w, s, d); | |
2561 } else { | |
2562 if (w == FloatRegisterImpl::S) { | |
2563 Assembler::fneg(w, s, d); | |
2564 } else if (w == FloatRegisterImpl::D) { | |
2565 // number() does a sanity check on the alignment. | |
2566 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) && | |
2567 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check"); | |
2568 | |
2569 Assembler::fneg(FloatRegisterImpl::S, s, d); | |
2570 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); | |
2571 } else { | |
2572 assert(w == FloatRegisterImpl::Q, "Invalid float register width"); | |
2573 | |
2574 // number() does a sanity check on the alignment. | |
2575 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) && | |
2576 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check"); | |
2577 | |
2578 Assembler::fneg(FloatRegisterImpl::S, s, d); | |
2579 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); | |
2580 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor()); | |
2581 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor()); | |
2582 } | |
2583 } | |
2584 } | |
2585 | |
2586 void MacroAssembler::fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) | |
2587 { | |
2588 if (VM_Version::v9_instructions_work()) { | |
2589 Assembler::fmov(w, s, d); | |
2590 } else { | |
2591 if (w == FloatRegisterImpl::S) { | |
2592 Assembler::fmov(w, s, d); | |
2593 } else if (w == FloatRegisterImpl::D) { | |
2594 // number() does a sanity check on the alignment. | |
2595 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) && | |
2596 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check"); | |
2597 | |
2598 Assembler::fmov(FloatRegisterImpl::S, s, d); | |
2599 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); | |
2600 } else { | |
2601 assert(w == FloatRegisterImpl::Q, "Invalid float register width"); | |
2602 | |
2603 // number() does a sanity check on the alignment. | |
2604 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) && | |
2605 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check"); | |
2606 | |
2607 Assembler::fmov(FloatRegisterImpl::S, s, d); | |
2608 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); | |
2609 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor()); | |
2610 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor()); | |
2611 } | |
2612 } | |
2613 } | |
2614 | |
2615 void MacroAssembler::fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) | |
2616 { | |
2617 if (VM_Version::v9_instructions_work()) { | |
2618 Assembler::fabs(w, s, d); | |
2619 } else { | |
2620 if (w == FloatRegisterImpl::S) { | |
2621 Assembler::fabs(w, s, d); | |
2622 } else if (w == FloatRegisterImpl::D) { | |
2623 // number() does a sanity check on the alignment. | |
2624 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) && | |
2625 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check"); | |
2626 | |
2627 Assembler::fabs(FloatRegisterImpl::S, s, d); | |
2628 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); | |
2629 } else { | |
2630 assert(w == FloatRegisterImpl::Q, "Invalid float register width"); | |
2631 | |
2632 // number() does a sanity check on the alignment. | |
2633 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) && | |
2634 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check"); | |
2635 | |
2636 Assembler::fabs(FloatRegisterImpl::S, s, d); | |
2637 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); | |
2638 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor()); | |
2639 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor()); | |
2640 } | |
2641 } | |
2642 } | |
2643 | |
2644 void MacroAssembler::save_all_globals_into_locals() { | |
2645 mov(G1,L1); | |
2646 mov(G2,L2); | |
2647 mov(G3,L3); | |
2648 mov(G4,L4); | |
2649 mov(G5,L5); | |
2650 mov(G6,L6); | |
2651 mov(G7,L7); | |
2652 } | |
2653 | |
2654 void MacroAssembler::restore_globals_from_locals() { | |
2655 mov(L1,G1); | |
2656 mov(L2,G2); | |
2657 mov(L3,G3); | |
2658 mov(L4,G4); | |
2659 mov(L5,G5); | |
2660 mov(L6,G6); | |
2661 mov(L7,G7); | |
2662 } | |
2663 | |
2664 // Use for 64 bit operation. | |
2665 void MacroAssembler::casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm) | |
2666 { | |
2667 // store ptr_reg as the new top value | |
2668 #ifdef _LP64 | |
2669 casx(top_ptr_reg, top_reg, ptr_reg); | |
2670 #else | |
2671 cas_under_lock(top_ptr_reg, top_reg, ptr_reg, lock_addr, use_call_vm); | |
2672 #endif // _LP64 | |
2673 } | |
2674 | |
2675 // [RGV] This routine does not handle 64 bit operations. | |
2676 // use casx_under_lock() or casx directly!!! | |
2677 void MacroAssembler::cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm) | |
2678 { | |
2679 // store ptr_reg as the new top value | |
2680 if (VM_Version::v9_instructions_work()) { | |
2681 cas(top_ptr_reg, top_reg, ptr_reg); | |
2682 } else { | |
2683 | |
2684 // If the register is not an out nor global, it is not visible | |
2685 // after the save. Allocate a register for it, save its | |
2686 // value in the register save area (the save may not flush | |
2687 // registers to the save area). | |
2688 | |
2689 Register top_ptr_reg_after_save; | |
2690 Register top_reg_after_save; | |
2691 Register ptr_reg_after_save; | |
2692 | |
2693 if (top_ptr_reg->is_out() || top_ptr_reg->is_global()) { | |
2694 top_ptr_reg_after_save = top_ptr_reg->after_save(); | |
2695 } else { | |
2696 Address reg_save_addr = top_ptr_reg->address_in_saved_window(); | |
2697 top_ptr_reg_after_save = L0; | |
2698 st(top_ptr_reg, reg_save_addr); | |
2699 } | |
2700 | |
2701 if (top_reg->is_out() || top_reg->is_global()) { | |
2702 top_reg_after_save = top_reg->after_save(); | |
2703 } else { | |
2704 Address reg_save_addr = top_reg->address_in_saved_window(); | |
2705 top_reg_after_save = L1; | |
2706 st(top_reg, reg_save_addr); | |
2707 } | |
2708 | |
2709 if (ptr_reg->is_out() || ptr_reg->is_global()) { | |
2710 ptr_reg_after_save = ptr_reg->after_save(); | |
2711 } else { | |
2712 Address reg_save_addr = ptr_reg->address_in_saved_window(); | |
2713 ptr_reg_after_save = L2; | |
2714 st(ptr_reg, reg_save_addr); | |
2715 } | |
2716 | |
2717 const Register& lock_reg = L3; | |
2718 const Register& lock_ptr_reg = L4; | |
2719 const Register& value_reg = L5; | |
2720 const Register& yield_reg = L6; | |
2721 const Register& yieldall_reg = L7; | |
2722 | |
2723 save_frame(); | |
2724 | |
2725 if (top_ptr_reg_after_save == L0) { | |
2726 ld(top_ptr_reg->address_in_saved_window().after_save(), top_ptr_reg_after_save); | |
2727 } | |
2728 | |
2729 if (top_reg_after_save == L1) { | |
2730 ld(top_reg->address_in_saved_window().after_save(), top_reg_after_save); | |
2731 } | |
2732 | |
2733 if (ptr_reg_after_save == L2) { | |
2734 ld(ptr_reg->address_in_saved_window().after_save(), ptr_reg_after_save); | |
2735 } | |
2736 | |
2737 Label(retry_get_lock); | |
2738 Label(not_same); | |
2739 Label(dont_yield); | |
2740 | |
2741 assert(lock_addr, "lock_address should be non null for v8"); | |
2742 set((intptr_t)lock_addr, lock_ptr_reg); | |
2743 // Initialize yield counter | |
2744 mov(G0,yield_reg); | |
2745 mov(G0, yieldall_reg); | |
2746 set(StubRoutines::Sparc::locked, lock_reg); | |
2747 | |
2748 bind(retry_get_lock); | |
3839 | 2749 cmp_and_br_short(yield_reg, V8AtomicOperationUnderLockSpinCount, Assembler::less, Assembler::pt, dont_yield); |
0 | 2750 |
2751 if(use_call_vm) { | |
2752 Untested("Need to verify global reg consistancy"); | |
2753 call_VM(noreg, CAST_FROM_FN_PTR(address, SharedRuntime::yield_all), yieldall_reg); | |
2754 } else { | |
2755 // Save the regs and make space for a C call | |
2756 save(SP, -96, SP); | |
2757 save_all_globals_into_locals(); | |
2758 call(CAST_FROM_FN_PTR(address,os::yield_all)); | |
2759 delayed()->mov(yieldall_reg, O0); | |
2760 restore_globals_from_locals(); | |
2761 restore(); | |
2762 } | |
2763 | |
2764 // reset the counter | |
2765 mov(G0,yield_reg); | |
2766 add(yieldall_reg, 1, yieldall_reg); | |
2767 | |
2768 bind(dont_yield); | |
2769 // try to get lock | |
2770 swap(lock_ptr_reg, 0, lock_reg); | |
2771 | |
2772 // did we get the lock? | |
2773 cmp(lock_reg, StubRoutines::Sparc::unlocked); | |
2774 br(Assembler::notEqual, true, Assembler::pn, retry_get_lock); | |
2775 delayed()->add(yield_reg,1,yield_reg); | |
2776 | |
2777 // yes, got lock. do we have the same top? | |
2778 ld(top_ptr_reg_after_save, 0, value_reg); | |
3839 | 2779 cmp_and_br_short(value_reg, top_reg_after_save, Assembler::notEqual, Assembler::pn, not_same); |
0 | 2780 |
2781 // yes, same top. | |
2782 st(ptr_reg_after_save, top_ptr_reg_after_save, 0); | |
2783 membar(Assembler::StoreStore); | |
2784 | |
2785 bind(not_same); | |
2786 mov(value_reg, ptr_reg_after_save); | |
2787 st(lock_reg, lock_ptr_reg, 0); // unlock | |
2788 | |
2789 restore(); | |
2790 } | |
2791 } | |
2792 | |
665
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2793 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, |
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2794 Register tmp, |
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2795 int offset) { |
622
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2796 intptr_t value = *delayed_value_addr; |
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2797 if (value != 0) |
665
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2798 return RegisterOrConstant(value + offset); |
622
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2799 |
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2800 // load indirectly to solve generation ordering problem |
727 | 2801 AddressLiteral a(delayed_value_addr); |
622
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2802 load_ptr_contents(a, tmp); |
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2803 |
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2804 #ifdef ASSERT |
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2805 tst(tmp); |
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2806 breakpoint_trap(zero, xcc); |
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2807 #endif |
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|
2808 |
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2809 if (offset != 0) |
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2810 add(tmp, offset, tmp); |
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2811 |
665
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2812 return RegisterOrConstant(tmp); |
622
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2813 } |
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|
2814 |
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2815 |
1503 | 2816 RegisterOrConstant MacroAssembler::regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) { |
2817 assert(d.register_or_noreg() != G0, "lost side effect"); | |
2818 if ((s2.is_constant() && s2.as_constant() == 0) || | |
2819 (s2.is_register() && s2.as_register() == G0)) { | |
2820 // Do nothing, just move value. | |
2821 if (s1.is_register()) { | |
2822 if (d.is_constant()) d = temp; | |
2823 mov(s1.as_register(), d.as_register()); | |
2824 return d; | |
2825 } else { | |
2826 return s1; | |
2827 } | |
2828 } | |
2829 | |
2830 if (s1.is_register()) { | |
2831 assert_different_registers(s1.as_register(), temp); | |
2832 if (d.is_constant()) d = temp; | |
2833 andn(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register()); | |
2834 return d; | |
623
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2835 } else { |
1503 | 2836 if (s2.is_register()) { |
2837 assert_different_registers(s2.as_register(), temp); | |
2838 if (d.is_constant()) d = temp; | |
2839 set(s1.as_constant(), temp); | |
2840 andn(temp, s2.as_register(), d.as_register()); | |
2841 return d; | |
2842 } else { | |
2843 intptr_t res = s1.as_constant() & ~s2.as_constant(); | |
2844 return res; | |
2845 } | |
623
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2846 } |
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|
2847 } |
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2848 |
1503 | 2849 RegisterOrConstant MacroAssembler::regcon_inc_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) { |
2850 assert(d.register_or_noreg() != G0, "lost side effect"); | |
2851 if ((s2.is_constant() && s2.as_constant() == 0) || | |
2852 (s2.is_register() && s2.as_register() == G0)) { | |
2853 // Do nothing, just move value. | |
2854 if (s1.is_register()) { | |
2855 if (d.is_constant()) d = temp; | |
2856 mov(s1.as_register(), d.as_register()); | |
2857 return d; | |
2858 } else { | |
2859 return s1; | |
2860 } | |
2861 } | |
2862 | |
2863 if (s1.is_register()) { | |
2864 assert_different_registers(s1.as_register(), temp); | |
2865 if (d.is_constant()) d = temp; | |
2866 add(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register()); | |
2867 return d; | |
623
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2868 } else { |
1503 | 2869 if (s2.is_register()) { |
2870 assert_different_registers(s2.as_register(), temp); | |
2871 if (d.is_constant()) d = temp; | |
2872 add(s2.as_register(), ensure_simm13_or_reg(s1, temp), d.as_register()); | |
2873 return d; | |
2874 } else { | |
2875 intptr_t res = s1.as_constant() + s2.as_constant(); | |
2876 return res; | |
2877 } | |
2878 } | |
2879 } | |
2880 | |
2881 RegisterOrConstant MacroAssembler::regcon_sll_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) { | |
2882 assert(d.register_or_noreg() != G0, "lost side effect"); | |
2883 if (!is_simm13(s2.constant_or_zero())) | |
2884 s2 = (s2.as_constant() & 0xFF); | |
2885 if ((s2.is_constant() && s2.as_constant() == 0) || | |
2886 (s2.is_register() && s2.as_register() == G0)) { | |
2887 // Do nothing, just move value. | |
2888 if (s1.is_register()) { | |
2889 if (d.is_constant()) d = temp; | |
2890 mov(s1.as_register(), d.as_register()); | |
2891 return d; | |
2892 } else { | |
2893 return s1; | |
2894 } | |
2895 } | |
2896 | |
2897 if (s1.is_register()) { | |
2898 assert_different_registers(s1.as_register(), temp); | |
2899 if (d.is_constant()) d = temp; | |
2900 sll_ptr(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register()); | |
2901 return d; | |
2902 } else { | |
2903 if (s2.is_register()) { | |
2904 assert_different_registers(s2.as_register(), temp); | |
2905 if (d.is_constant()) d = temp; | |
2906 set(s1.as_constant(), temp); | |
2907 sll_ptr(temp, s2.as_register(), d.as_register()); | |
2908 return d; | |
2909 } else { | |
2910 intptr_t res = s1.as_constant() << s2.as_constant(); | |
2911 return res; | |
2912 } | |
623
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2913 } |
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|
2914 } |
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|
2915 |
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|
2916 |
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|
2917 // Look up the method for a megamorphic invokeinterface call. |
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2918 // The target method is determined by <intf_klass, itable_index>. |
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2919 // The receiver klass is in recv_klass. |
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2920 // On success, the result will be in method_result, and execution falls through. |
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2921 // On failure, execution transfers to the given label. |
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2922 void MacroAssembler::lookup_interface_method(Register recv_klass, |
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2923 Register intf_klass, |
665
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2924 RegisterOrConstant itable_index, |
623
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2925 Register method_result, |
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2926 Register scan_temp, |
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2927 Register sethi_temp, |
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2928 Label& L_no_such_interface) { |
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2929 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); |
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2930 assert(itable_index.is_constant() || itable_index.as_register() == method_result, |
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2931 "caller must use same register for non-constant itable index as for method"); |
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2932 |
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2933 // Compute start of first itableOffsetEntry (which is at the end of the vtable) |
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2934 int vtable_base = instanceKlass::vtable_start_offset() * wordSize; |
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2935 int scan_step = itableOffsetEntry::size() * wordSize; |
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2936 int vte_size = vtableEntry::size() * wordSize; |
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|
2937 |
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|
2938 lduw(recv_klass, instanceKlass::vtable_length_offset() * wordSize, scan_temp); |
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2939 // %%% We should store the aligned, prescaled offset in the klassoop. |
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2940 // Then the next several instructions would fold away. |
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|
2941 |
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|
2942 int round_to_unit = ((HeapWordsPerLong > 1) ? BytesPerLong : 0); |
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2943 int itb_offset = vtable_base; |
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|
2944 if (round_to_unit != 0) { |
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diff
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|
2945 // hoist first instruction of round_to(scan_temp, BytesPerLong): |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2946 itb_offset += round_to_unit - wordSize; |
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|
2947 } |
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|
2948 int itb_scale = exact_log2(vtableEntry::size() * wordSize); |
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|
2949 sll(scan_temp, itb_scale, scan_temp); |
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|
2950 add(scan_temp, itb_offset, scan_temp); |
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|
2951 if (round_to_unit != 0) { |
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|
2952 // Round up to align_object_offset boundary |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2953 // see code for instanceKlass::start_of_itable! |
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|
2954 // Was: round_to(scan_temp, BytesPerLong); |
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|
2955 // Hoisted: add(scan_temp, BytesPerLong-1, scan_temp); |
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|
2956 and3(scan_temp, -round_to_unit, scan_temp); |
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|
2957 } |
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|
2958 add(recv_klass, scan_temp, scan_temp); |
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|
2959 |
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|
2960 // Adjust recv_klass by scaled itable_index, so we can free itable_index. |
665
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|
2961 RegisterOrConstant itable_offset = itable_index; |
1503 | 2962 itable_offset = regcon_sll_ptr(itable_index, exact_log2(itableMethodEntry::size() * wordSize), itable_offset); |
2963 itable_offset = regcon_inc_ptr(itable_offset, itableMethodEntry::method_offset_in_bytes(), itable_offset); | |
1006
dcf03e02b020
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986
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|
2964 add(recv_klass, ensure_simm13_or_reg(itable_offset, sethi_temp), recv_klass); |
623
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|
2965 |
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|
2966 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { |
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2967 // if (scan->interface() == intf) { |
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2968 // result = (klass + scan->offset() + itable_index); |
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2969 // } |
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|
2970 // } |
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|
2971 Label search, found_method; |
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|
2972 |
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|
2973 for (int peel = 1; peel >= 0; peel--) { |
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|
2974 // %%%% Could load both offset and interface in one ldx, if they were |
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|
2975 // in the opposite order. This would save a load. |
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|
2976 ld_ptr(scan_temp, itableOffsetEntry::interface_offset_in_bytes(), method_result); |
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|
2977 |
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|
2978 // Check that this entry is non-null. A null entry means that |
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|
2979 // the receiver class doesn't implement the interface, and wasn't the |
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|
2980 // same as when the caller was compiled. |
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|
2981 bpr(Assembler::rc_z, false, Assembler::pn, method_result, L_no_such_interface); |
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|
2982 delayed()->cmp(method_result, intf_klass); |
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|
2983 |
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|
2984 if (peel) { |
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|
2985 brx(Assembler::equal, false, Assembler::pt, found_method); |
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|
2986 } else { |
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|
2987 brx(Assembler::notEqual, false, Assembler::pn, search); |
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|
2988 // (invert the test to fall through to found_method...) |
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|
2989 } |
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|
2990 delayed()->add(scan_temp, scan_step, scan_temp); |
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|
2991 |
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|
2992 if (!peel) break; |
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|
2993 |
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|
2994 bind(search); |
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|
2995 } |
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|
2996 |
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|
2997 bind(found_method); |
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|
2998 |
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|
2999 // Got a hit. |
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|
3000 int ito_offset = itableOffsetEntry::offset_offset_in_bytes(); |
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|
3001 // scan_temp[-scan_step] points to the vtable offset we need |
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|
3002 ito_offset -= scan_step; |
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|
3003 lduw(scan_temp, ito_offset, scan_temp); |
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|
3004 ld_ptr(recv_klass, scan_temp, method_result); |
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|
3005 } |
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|
3006 |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
3007 |
6266
1d7922586cf6
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diff
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|
3008 // virtual method calling |
1d7922586cf6
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diff
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|
3009 void MacroAssembler::lookup_virtual_method(Register recv_klass, |
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
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|
3010 RegisterOrConstant vtable_index, |
1d7922586cf6
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4762
diff
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|
3011 Register method_result) { |
1d7922586cf6
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diff
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|
3012 assert_different_registers(recv_klass, method_result, vtable_index.register_or_noreg()); |
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
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|
3013 Register sethi_temp = method_result; |
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
twisti
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diff
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|
3014 const int base = (instanceKlass::vtable_start_offset() * wordSize + |
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
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4762
diff
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|
3015 // method pointer offset within the vtable entry: |
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
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diff
changeset
|
3016 vtableEntry::method_offset_in_bytes()); |
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
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diff
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|
3017 RegisterOrConstant vtable_offset = vtable_index; |
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
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diff
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|
3018 // Each of the following three lines potentially generates an instruction. |
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
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4762
diff
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|
3019 // But the total number of address formation instructions will always be |
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
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diff
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|
3020 // at most two, and will often be zero. In any case, it will be optimal. |
1d7922586cf6
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diff
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|
3021 // If vtable_index is a register, we will have (sll_ptr N,x; inc_ptr B,x; ld_ptr k,x). |
1d7922586cf6
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4762
diff
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|
3022 // If vtable_index is a constant, we will have at most (set B+X<<N,t; ld_ptr k,t). |
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
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diff
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|
3023 vtable_offset = regcon_sll_ptr(vtable_index, exact_log2(vtableEntry::size() * wordSize), vtable_offset); |
1d7922586cf6
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twisti
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diff
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|
3024 vtable_offset = regcon_inc_ptr(vtable_offset, base, vtable_offset, sethi_temp); |
1d7922586cf6
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diff
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|
3025 Address vtable_entry_addr(recv_klass, ensure_simm13_or_reg(vtable_offset, sethi_temp)); |
1d7922586cf6
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diff
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|
3026 ld_ptr(vtable_entry_addr, method_result); |
1d7922586cf6
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4762
diff
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|
3027 } |
1d7922586cf6
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diff
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|
3028 |
1d7922586cf6
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diff
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|
3029 |
644
c517646eef23
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|
3030 void MacroAssembler::check_klass_subtype(Register sub_klass, |
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diff
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|
3031 Register super_klass, |
c517646eef23
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diff
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|
3032 Register temp_reg, |
c517646eef23
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diff
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|
3033 Register temp2_reg, |
c517646eef23
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diff
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|
3034 Label& L_success) { |
c517646eef23
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diff
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|
3035 Register sub_2 = sub_klass; |
c517646eef23
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diff
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|
3036 Register sup_2 = super_klass; |
c517646eef23
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|
3037 if (!sub_2->is_global()) sub_2 = L0; |
c517646eef23
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|
3038 if (!sup_2->is_global()) sup_2 = L1; |
6266
1d7922586cf6
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diff
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|
3039 bool did_save = false; |
1d7922586cf6
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diff
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|
3040 if (temp_reg == noreg || temp2_reg == noreg) { |
1d7922586cf6
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diff
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|
3041 temp_reg = L2; |
1d7922586cf6
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diff
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|
3042 temp2_reg = L3; |
1d7922586cf6
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|
3043 save_frame_and_mov(0, sub_klass, sub_2, super_klass, sup_2); |
1d7922586cf6
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|
3044 sub_klass = sub_2; |
1d7922586cf6
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diff
changeset
|
3045 super_klass = sup_2; |
1d7922586cf6
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diff
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|
3046 did_save = true; |
1d7922586cf6
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diff
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|
3047 } |
1d7922586cf6
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diff
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|
3048 Label L_failure, L_pop_to_failure, L_pop_to_success; |
1d7922586cf6
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diff
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|
3049 check_klass_subtype_fast_path(sub_klass, super_klass, |
1d7922586cf6
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4762
diff
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|
3050 temp_reg, temp2_reg, |
1d7922586cf6
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diff
changeset
|
3051 (did_save ? &L_pop_to_success : &L_success), |
1d7922586cf6
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diff
changeset
|
3052 (did_save ? &L_pop_to_failure : &L_failure), NULL); |
1d7922586cf6
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|
3053 |
1d7922586cf6
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diff
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|
3054 if (!did_save) |
1d7922586cf6
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diff
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|
3055 save_frame_and_mov(0, sub_klass, sub_2, super_klass, sup_2); |
644
c517646eef23
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diff
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|
3056 check_klass_subtype_slow_path(sub_2, sup_2, |
c517646eef23
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diff
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|
3057 L2, L3, L4, L5, |
c517646eef23
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diff
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|
3058 NULL, &L_pop_to_failure); |
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|
3059 |
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diff
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|
3060 // on success: |
6266
1d7922586cf6
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|
3061 bind(L_pop_to_success); |
644
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|
3062 restore(); |
3839 | 3063 ba_short(L_success); |
644
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3064 |
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3065 // on failure: |
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|
3066 bind(L_pop_to_failure); |
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|
3067 restore(); |
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|
3068 bind(L_failure); |
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|
3069 } |
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|
3070 |
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3071 |
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3072 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, |
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3073 Register super_klass, |
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|
3074 Register temp_reg, |
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|
3075 Register temp2_reg, |
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|
3076 Label* L_success, |
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|
3077 Label* L_failure, |
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3078 Label* L_slow_path, |
3839 | 3079 RegisterOrConstant super_check_offset) { |
4762
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3080 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); |
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3081 int sco_offset = in_bytes(Klass::super_check_offset_offset()); |
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3082 |
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3083 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); |
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3084 bool need_slow_path = (must_load_sco || |
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3085 super_check_offset.constant_or_zero() == sco_offset); |
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3086 |
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3087 assert_different_registers(sub_klass, super_klass, temp_reg); |
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3088 if (super_check_offset.is_register()) { |
1503 | 3089 assert_different_registers(sub_klass, super_klass, temp_reg, |
644
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3090 super_check_offset.as_register()); |
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3091 } else if (must_load_sco) { |
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3092 assert(temp2_reg != noreg, "supply either a temp or a register offset"); |
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3093 } |
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3094 |
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3095 Label L_fallthrough; |
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|
3096 int label_nulls = 0; |
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3097 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
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3098 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
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3099 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } |
3839 | 3100 assert(label_nulls <= 1 || |
644
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3101 (L_slow_path == &L_fallthrough && label_nulls <= 2 && !need_slow_path), |
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3102 "at most one NULL in the batch, usually"); |
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3103 |
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3104 // If the pointers are equal, we are done (e.g., String[] elements). |
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3105 // This self-check enables sharing of secondary supertype arrays among |
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3106 // non-primary types such as array-of-interface. Otherwise, each such |
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3107 // type would need its own customized SSA. |
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3108 // We move this check to the front of the fast path because many |
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3109 // type checks are in fact trivially successful in this manner, |
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3110 // so we get a nicely predicted branch right at the start of the check. |
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|
3111 cmp(super_klass, sub_klass); |
3839 | 3112 brx(Assembler::equal, false, Assembler::pn, *L_success); |
3113 delayed()->nop(); | |
644
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|
3114 |
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3115 // Check the supertype display: |
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|
3116 if (must_load_sco) { |
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3117 // The super check offset is always positive... |
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|
3118 lduw(super_klass, sco_offset, temp2_reg); |
665
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|
3119 super_check_offset = RegisterOrConstant(temp2_reg); |
1503 | 3120 // super_check_offset is register. |
3121 assert_different_registers(sub_klass, super_klass, temp_reg, super_check_offset.as_register()); | |
644
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|
3122 } |
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|
3123 ld_ptr(sub_klass, super_check_offset, temp_reg); |
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3124 cmp(super_klass, temp_reg); |
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|
3125 |
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|
3126 // This check has worked decisively for primary supers. |
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3127 // Secondary supers are sought in the super_cache ('super_cache_addr'). |
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3128 // (Secondary supers are interfaces and very deeply nested subtypes.) |
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|
3129 // This works in the same check above because of a tricky aliasing |
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3130 // between the super_cache and the primary super display elements. |
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3131 // (The 'super_check_addr' can address either, as the case requires.) |
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|
3132 // Note that the cache is updated below if it does not help us find |
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|
3133 // what we need immediately. |
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diff
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|
3134 // So if it was a primary super, we can just fail immediately. |
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|
3135 // Otherwise, it's the slow path for us (no success at this point). |
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|
3136 |
3839 | 3137 // Hacked ba(), which may only be used just before L_fallthrough. |
3138 #define FINAL_JUMP(label) \ | |
3139 if (&(label) != &L_fallthrough) { \ | |
3140 ba(label); delayed()->nop(); \ | |
3141 } | |
3142 | |
644
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|
3143 if (super_check_offset.is_register()) { |
3839 | 3144 brx(Assembler::equal, false, Assembler::pn, *L_success); |
3145 delayed()->cmp(super_check_offset.as_register(), sc_offset); | |
644
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|
3146 |
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|
3147 if (L_failure == &L_fallthrough) { |
3839 | 3148 brx(Assembler::equal, false, Assembler::pt, *L_slow_path); |
644
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|
3149 delayed()->nop(); |
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|
3150 } else { |
3839 | 3151 brx(Assembler::notEqual, false, Assembler::pn, *L_failure); |
3152 delayed()->nop(); | |
3153 FINAL_JUMP(*L_slow_path); | |
644
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|
3154 } |
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|
3155 } else if (super_check_offset.as_constant() == sc_offset) { |
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|
3156 // Need a slow path; fast failure is impossible. |
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|
3157 if (L_slow_path == &L_fallthrough) { |
3839 | 3158 brx(Assembler::equal, false, Assembler::pt, *L_success); |
3159 delayed()->nop(); | |
644
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|
3160 } else { |
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|
3161 brx(Assembler::notEqual, false, Assembler::pn, *L_slow_path); |
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|
3162 delayed()->nop(); |
3839 | 3163 FINAL_JUMP(*L_success); |
644
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|
3164 } |
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|
3165 } else { |
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|
3166 // No slow path; it's a fast decision. |
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|
3167 if (L_failure == &L_fallthrough) { |
3839 | 3168 brx(Assembler::equal, false, Assembler::pt, *L_success); |
3169 delayed()->nop(); | |
644
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|
3170 } else { |
3839 | 3171 brx(Assembler::notEqual, false, Assembler::pn, *L_failure); |
3172 delayed()->nop(); | |
3173 FINAL_JUMP(*L_success); | |
644
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|
3174 } |
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|
3175 } |
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|
3176 |
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|
3177 bind(L_fallthrough); |
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|
3178 |
3839 | 3179 #undef FINAL_JUMP |
644
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|
3180 } |
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|
3181 |
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|
3182 |
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|
3183 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, |
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|
3184 Register super_klass, |
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|
3185 Register count_temp, |
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|
3186 Register scan_temp, |
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|
3187 Register scratch_reg, |
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|
3188 Register coop_reg, |
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|
3189 Label* L_success, |
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|
3190 Label* L_failure) { |
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|
3191 assert_different_registers(sub_klass, super_klass, |
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|
3192 count_temp, scan_temp, scratch_reg, coop_reg); |
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|
3193 |
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|
3194 Label L_fallthrough, L_loop; |
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|
3195 int label_nulls = 0; |
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|
3196 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
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|
3197 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
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|
3198 assert(label_nulls <= 1, "at most one NULL in the batch"); |
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|
3199 |
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|
3200 // a couple of useful fields in sub_klass: |
4762
069ab3f976d3
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|
3201 int ss_offset = in_bytes(Klass::secondary_supers_offset()); |
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|
3202 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); |
644
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|
3203 |
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|
3204 // Do a linear scan of the secondary super-klass chain. |
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|
3205 // This code is rarely used, so simplicity is a virtue here. |
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|
3206 |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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|
3207 #ifndef PRODUCT |
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diff
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|
3208 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; |
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diff
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|
3209 inc_counter((address) pst_counter, count_temp, scan_temp); |
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|
3210 #endif |
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|
3211 |
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|
3212 // We will consult the secondary-super array. |
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|
3213 ld_ptr(sub_klass, ss_offset, scan_temp); |
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|
3214 |
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|
3215 // Compress superclass if necessary. |
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|
3216 Register search_key = super_klass; |
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|
3217 bool decode_super_klass = false; |
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diff
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|
3218 if (UseCompressedOops) { |
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|
3219 if (coop_reg != noreg) { |
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diff
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|
3220 encode_heap_oop_not_null(super_klass, coop_reg); |
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diff
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|
3221 search_key = coop_reg; |
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diff
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|
3222 } else { |
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|
3223 encode_heap_oop_not_null(super_klass); |
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3224 decode_super_klass = true; // scarce temps! |
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|
3225 } |
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|
3226 // The superclass is never null; it would be a basic system error if a null |
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3227 // pointer were to sneak in here. Note that we have already loaded the |
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|
3228 // Klass::super_check_offset from the super_klass in the fast path, |
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|
3229 // so if there is a null in that register, we are already in the afterlife. |
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|
3230 } |
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|
3231 |
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|
3232 // Load the array length. (Positive movl does right thing on LP64.) |
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|
3233 lduw(scan_temp, arrayOopDesc::length_offset_in_bytes(), count_temp); |
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|
3234 |
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|
3235 // Check for empty secondary super list |
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|
3236 tst(count_temp); |
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|
3237 |
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diff
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|
3238 // Top of search loop |
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diff
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|
3239 bind(L_loop); |
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|
3240 br(Assembler::equal, false, Assembler::pn, *L_failure); |
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|
3241 delayed()->add(scan_temp, heapOopSize, scan_temp); |
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|
3242 assert(heapOopSize != 0, "heapOopSize should be initialized"); |
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|
3243 |
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3244 // Skip the array header in all array accesses. |
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3245 int elem_offset = arrayOopDesc::base_offset_in_bytes(T_OBJECT); |
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3246 elem_offset -= heapOopSize; // the scan pointer was pre-incremented also |
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|
3247 |
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|
3248 // Load next super to check |
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|
3249 if (UseCompressedOops) { |
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|
3250 // Don't use load_heap_oop; we don't want to decode the element. |
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3251 lduw( scan_temp, elem_offset, scratch_reg ); |
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|
3252 } else { |
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3253 ld_ptr( scan_temp, elem_offset, scratch_reg ); |
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|
3254 } |
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|
3255 |
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3256 // Look for Rsuper_klass on Rsub_klass's secondary super-class-overflow list |
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3257 cmp(scratch_reg, search_key); |
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|
3258 |
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3259 // A miss means we are NOT a subtype and need to keep looping |
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3260 brx(Assembler::notEqual, false, Assembler::pn, L_loop); |
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3261 delayed()->deccc(count_temp); // decrement trip counter in delay slot |
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|
3262 |
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|
3263 // Falling out the bottom means we found a hit; we ARE a subtype |
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|
3264 if (decode_super_klass) decode_heap_oop(super_klass); |
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|
3265 |
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3266 // Success. Cache the super we found and proceed in triumph. |
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|
3267 st_ptr(super_klass, sub_klass, sc_offset); |
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|
3268 |
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|
3269 if (L_success != &L_fallthrough) { |
3839 | 3270 ba(*L_success); |
644
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|
3271 delayed()->nop(); |
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|
3272 } |
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|
3273 |
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|
3274 bind(L_fallthrough); |
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|
3275 } |
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|
3276 |
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|
3277 |
710 | 3278 RegisterOrConstant MacroAssembler::argument_offset(RegisterOrConstant arg_slot, |
3442
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3249
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|
3279 Register temp_reg, |
710 | 3280 int extra_slot_offset) { |
3281 // cf. TemplateTable::prepare_invoke(), if (load_receiver). | |
1506 | 3282 int stackElementSize = Interpreter::stackElementSize; |
1503 | 3283 int offset = extra_slot_offset * stackElementSize; |
710 | 3284 if (arg_slot.is_constant()) { |
3285 offset += arg_slot.as_constant() * stackElementSize; | |
3286 return offset; | |
3287 } else { | |
3442
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parents:
3249
diff
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|
3288 assert(temp_reg != noreg, "must specify"); |
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parents:
3249
diff
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|
3289 sll_ptr(arg_slot.as_register(), exact_log2(stackElementSize), temp_reg); |
710 | 3290 if (offset != 0) |
3442
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parents:
3249
diff
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|
3291 add(temp_reg, offset, temp_reg); |
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parents:
3249
diff
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|
3292 return temp_reg; |
710 | 3293 } |
3294 } | |
3295 | |
3296 | |
1503 | 3297 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, |
3442
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3249
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|
3298 Register temp_reg, |
1503 | 3299 int extra_slot_offset) { |
3442
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|
3300 return Address(Gargs, argument_offset(arg_slot, temp_reg, extra_slot_offset)); |
1503 | 3301 } |
3302 | |
710 | 3303 |
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3304 void MacroAssembler::biased_locking_enter(Register obj_reg, Register mark_reg, |
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3305 Register temp_reg, |
0 | 3306 Label& done, Label* slow_case, |
3307 BiasedLockingCounters* counters) { | |
3308 assert(UseBiasedLocking, "why call this otherwise?"); | |
3309 | |
3310 if (PrintBiasedLockingStatistics) { | |
3311 assert_different_registers(obj_reg, mark_reg, temp_reg, O7); | |
3312 if (counters == NULL) | |
3313 counters = BiasedLocking::counters(); | |
3314 } | |
3315 | |
3316 Label cas_label; | |
3317 | |
3318 // Biased locking | |
3319 // See whether the lock is currently biased toward our thread and | |
3320 // whether the epoch is still valid | |
3321 // Note that the runtime guarantees sufficient alignment of JavaThread | |
3322 // pointers to allow age to be placed into low bits | |
3323 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); | |
3324 and3(mark_reg, markOopDesc::biased_lock_mask_in_place, temp_reg); | |
3839 | 3325 cmp_and_brx_short(temp_reg, markOopDesc::biased_lock_pattern, Assembler::notEqual, Assembler::pn, cas_label); |
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|
3326 |
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|
3327 load_klass(obj_reg, temp_reg); |
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069ab3f976d3
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|
3328 ld_ptr(Address(temp_reg, Klass::prototype_header_offset()), temp_reg); |
0 | 3329 or3(G2_thread, temp_reg, temp_reg); |
3330 xor3(mark_reg, temp_reg, temp_reg); | |
3331 andcc(temp_reg, ~((int) markOopDesc::age_mask_in_place), temp_reg); | |
3332 if (counters != NULL) { | |
3333 cond_inc(Assembler::equal, (address) counters->biased_lock_entry_count_addr(), mark_reg, temp_reg); | |
3334 // Reload mark_reg as we may need it later | |
727 | 3335 ld_ptr(Address(obj_reg, oopDesc::mark_offset_in_bytes()), mark_reg); |
0 | 3336 } |
3337 brx(Assembler::equal, true, Assembler::pt, done); | |
3338 delayed()->nop(); | |
3339 | |
3340 Label try_revoke_bias; | |
3341 Label try_rebias; | |
727 | 3342 Address mark_addr = Address(obj_reg, oopDesc::mark_offset_in_bytes()); |
0 | 3343 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); |
3344 | |
3345 // At this point we know that the header has the bias pattern and | |
3346 // that we are not the bias owner in the current epoch. We need to | |
3347 // figure out more details about the state of the header in order to | |
3348 // know what operations can be legally performed on the object's | |
3349 // header. | |
3350 | |
3351 // If the low three bits in the xor result aren't clear, that means | |
3352 // the prototype header is no longer biased and we have to revoke | |
3353 // the bias on this object. | |
3354 btst(markOopDesc::biased_lock_mask_in_place, temp_reg); | |
3355 brx(Assembler::notZero, false, Assembler::pn, try_revoke_bias); | |
3356 | |
3357 // Biasing is still enabled for this data type. See whether the | |
3358 // epoch of the current bias is still valid, meaning that the epoch | |
3359 // bits of the mark word are equal to the epoch bits of the | |
3360 // prototype header. (Note that the prototype header's epoch bits | |
3361 // only change at a safepoint.) If not, attempt to rebias the object | |
3362 // toward the current thread. Note that we must be absolutely sure | |
3363 // that the current epoch is invalid in order to do this because | |
3364 // otherwise the manipulations it performs on the mark word are | |
3365 // illegal. | |
3366 delayed()->btst(markOopDesc::epoch_mask_in_place, temp_reg); | |
3367 brx(Assembler::notZero, false, Assembler::pn, try_rebias); | |
3368 | |
3369 // The epoch of the current bias is still valid but we know nothing | |
3370 // about the owner; it might be set or it might be clear. Try to | |
3371 // acquire the bias of the object using an atomic operation. If this | |
3372 // fails we will go in to the runtime to revoke the object's bias. | |
3373 // Note that we first construct the presumed unbiased header so we | |
3374 // don't accidentally blow away another thread's valid bias. | |
3375 delayed()->and3(mark_reg, | |
3376 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place, | |
3377 mark_reg); | |
3378 or3(G2_thread, mark_reg, temp_reg); | |
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3379 casn(mark_addr.base(), mark_reg, temp_reg); |
0 | 3380 // If the biasing toward our thread failed, this means that |
3381 // another thread succeeded in biasing it toward itself and we | |
3382 // need to revoke that bias. The revocation will occur in the | |
3383 // interpreter runtime in the slow case. | |
3384 cmp(mark_reg, temp_reg); | |
3385 if (counters != NULL) { | |
3386 cond_inc(Assembler::zero, (address) counters->anonymously_biased_lock_entry_count_addr(), mark_reg, temp_reg); | |
3387 } | |
3388 if (slow_case != NULL) { | |
3389 brx(Assembler::notEqual, true, Assembler::pn, *slow_case); | |
3390 delayed()->nop(); | |
3391 } | |
3839 | 3392 ba_short(done); |
0 | 3393 |
3394 bind(try_rebias); | |
3395 // At this point we know the epoch has expired, meaning that the | |
3396 // current "bias owner", if any, is actually invalid. Under these | |
3397 // circumstances _only_, we are allowed to use the current header's | |
3398 // value as the comparison value when doing the cas to acquire the | |
3399 // bias in the current epoch. In other words, we allow transfer of | |
3400 // the bias from one thread to another directly in this situation. | |
3401 // | |
3402 // FIXME: due to a lack of registers we currently blow away the age | |
3403 // bits in this situation. Should attempt to preserve them. | |
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3404 load_klass(obj_reg, temp_reg); |
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3405 ld_ptr(Address(temp_reg, Klass::prototype_header_offset()), temp_reg); |
0 | 3406 or3(G2_thread, temp_reg, temp_reg); |
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3407 casn(mark_addr.base(), mark_reg, temp_reg); |
0 | 3408 // If the biasing toward our thread failed, this means that |
3409 // another thread succeeded in biasing it toward itself and we | |
3410 // need to revoke that bias. The revocation will occur in the | |
3411 // interpreter runtime in the slow case. | |
3412 cmp(mark_reg, temp_reg); | |
3413 if (counters != NULL) { | |
3414 cond_inc(Assembler::zero, (address) counters->rebiased_lock_entry_count_addr(), mark_reg, temp_reg); | |
3415 } | |
3416 if (slow_case != NULL) { | |
3417 brx(Assembler::notEqual, true, Assembler::pn, *slow_case); | |
3418 delayed()->nop(); | |
3419 } | |
3839 | 3420 ba_short(done); |
0 | 3421 |
3422 bind(try_revoke_bias); | |
3423 // The prototype mark in the klass doesn't have the bias bit set any | |
3424 // more, indicating that objects of this data type are not supposed | |
3425 // to be biased any more. We are going to try to reset the mark of | |
3426 // this object to the prototype value and fall through to the | |
3427 // CAS-based locking scheme. Note that if our CAS fails, it means | |
3428 // that another thread raced us for the privilege of revoking the | |
3429 // bias of this particular object, so it's okay to continue in the | |
3430 // normal locking code. | |
3431 // | |
3432 // FIXME: due to a lack of registers we currently blow away the age | |
3433 // bits in this situation. Should attempt to preserve them. | |
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3434 load_klass(obj_reg, temp_reg); |
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3435 ld_ptr(Address(temp_reg, Klass::prototype_header_offset()), temp_reg); |
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3436 casn(mark_addr.base(), mark_reg, temp_reg); |
0 | 3437 // Fall through to the normal CAS-based lock, because no matter what |
3438 // the result of the above CAS, some thread must have succeeded in | |
3439 // removing the bias bit from the object's header. | |
3440 if (counters != NULL) { | |
3441 cmp(mark_reg, temp_reg); | |
3442 cond_inc(Assembler::zero, (address) counters->revoked_lock_entry_count_addr(), mark_reg, temp_reg); | |
3443 } | |
3444 | |
3445 bind(cas_label); | |
3446 } | |
3447 | |
3448 void MacroAssembler::biased_locking_exit (Address mark_addr, Register temp_reg, Label& done, | |
3449 bool allow_delay_slot_filling) { | |
3450 // Check for biased locking unlock case, which is a no-op | |
3451 // Note: we do not have to check the thread ID for two reasons. | |
3452 // First, the interpreter checks for IllegalMonitorStateException at | |
3453 // a higher level. Second, if the bias was revoked while we held the | |
3454 // lock, the object could not be rebiased toward another thread, so | |
3455 // the bias bit would be clear. | |
3456 ld_ptr(mark_addr, temp_reg); | |
3457 and3(temp_reg, markOopDesc::biased_lock_mask_in_place, temp_reg); | |
3458 cmp(temp_reg, markOopDesc::biased_lock_pattern); | |
3459 brx(Assembler::equal, allow_delay_slot_filling, Assembler::pt, done); | |
3460 delayed(); | |
3461 if (!allow_delay_slot_filling) { | |
3462 nop(); | |
3463 } | |
3464 } | |
3465 | |
3466 | |
3467 // CASN -- 32-64 bit switch hitter similar to the synthetic CASN provided by | |
3468 // Solaris/SPARC's "as". Another apt name would be cas_ptr() | |
3469 | |
3470 void MacroAssembler::casn (Register addr_reg, Register cmp_reg, Register set_reg ) { | |
3839 | 3471 casx_under_lock (addr_reg, cmp_reg, set_reg, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); |
0 | 3472 } |
3473 | |
3474 | |
3475 | |
3476 // compiler_lock_object() and compiler_unlock_object() are direct transliterations | |
3477 // of i486.ad fast_lock() and fast_unlock(). See those methods for detailed comments. | |
3478 // The code could be tightened up considerably. | |
3479 // | |
3480 // box->dhw disposition - post-conditions at DONE_LABEL. | |
3481 // - Successful inflated lock: box->dhw != 0. | |
3482 // Any non-zero value suffices. | |
3483 // Consider G2_thread, rsp, boxReg, or unused_mark() | |
3484 // - Successful Stack-lock: box->dhw == mark. | |
3485 // box->dhw must contain the displaced mark word value | |
3486 // - Failure -- icc.ZFlag == 0 and box->dhw is undefined. | |
3487 // The slow-path fast_enter() and slow_enter() operators | |
3488 // are responsible for setting box->dhw = NonZero (typically ::unused_mark). | |
3489 // - Biased: box->dhw is undefined | |
3490 // | |
3491 // SPARC refworkload performance - specifically jetstream and scimark - are | |
3492 // extremely sensitive to the size of the code emitted by compiler_lock_object | |
3493 // and compiler_unlock_object. Critically, the key factor is code size, not path | |
3494 // length. (Simply experiments to pad CLO with unexecuted NOPs demonstrte the | |
3495 // effect). | |
3496 | |
3497 | |
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3498 void MacroAssembler::compiler_lock_object(Register Roop, Register Rmark, |
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3499 Register Rbox, Register Rscratch, |
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3500 BiasedLockingCounters* counters, |
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3501 bool try_bias) { |
727 | 3502 Address mark_addr(Roop, oopDesc::mark_offset_in_bytes()); |
0 | 3503 |
3504 verify_oop(Roop); | |
3505 Label done ; | |
3506 | |
3507 if (counters != NULL) { | |
3508 inc_counter((address) counters->total_entry_count_addr(), Rmark, Rscratch); | |
3509 } | |
3510 | |
3511 if (EmitSync & 1) { | |
3839 | 3512 mov(3, Rscratch); |
3513 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
3514 cmp(SP, G0); | |
0 | 3515 return ; |
3516 } | |
3517 | |
3518 if (EmitSync & 2) { | |
3519 | |
3520 // Fetch object's markword | |
3521 ld_ptr(mark_addr, Rmark); | |
3522 | |
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3523 if (try_bias) { |
0 | 3524 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters); |
3525 } | |
3526 | |
3527 // Save Rbox in Rscratch to be used for the cas operation | |
3528 mov(Rbox, Rscratch); | |
3529 | |
3530 // set Rmark to markOop | markOopDesc::unlocked_value | |
3531 or3(Rmark, markOopDesc::unlocked_value, Rmark); | |
3532 | |
3533 // Initialize the box. (Must happen before we update the object mark!) | |
3534 st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
3535 | |
3536 // compare object markOop with Rmark and if equal exchange Rscratch with object markOop | |
3537 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); | |
3538 casx_under_lock(mark_addr.base(), Rmark, Rscratch, | |
3539 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); | |
3540 | |
3541 // if compare/exchange succeeded we found an unlocked object and we now have locked it | |
3542 // hence we are done | |
3543 cmp(Rmark, Rscratch); | |
3544 #ifdef _LP64 | |
3545 sub(Rscratch, STACK_BIAS, Rscratch); | |
3546 #endif | |
3547 brx(Assembler::equal, false, Assembler::pt, done); | |
3548 delayed()->sub(Rscratch, SP, Rscratch); //pull next instruction into delay slot | |
3549 | |
3550 // we did not find an unlocked object so see if this is a recursive case | |
3551 // sub(Rscratch, SP, Rscratch); | |
3552 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant"); | |
3553 andcc(Rscratch, 0xfffff003, Rscratch); | |
3554 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
3839 | 3555 bind (done); |
0 | 3556 return ; |
3557 } | |
3558 | |
3559 Label Egress ; | |
3560 | |
3561 if (EmitSync & 256) { | |
3562 Label IsInflated ; | |
3563 | |
3839 | 3564 ld_ptr(mark_addr, Rmark); // fetch obj->mark |
0 | 3565 // Triage: biased, stack-locked, neutral, inflated |
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3566 if (try_bias) { |
0 | 3567 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters); |
3568 // Invariant: if control reaches this point in the emitted stream | |
3569 // then Rmark has not been modified. | |
3570 } | |
3571 | |
3572 // Store mark into displaced mark field in the on-stack basic-lock "box" | |
3573 // Critically, this must happen before the CAS | |
3574 // Maximize the ST-CAS distance to minimize the ST-before-CAS penalty. | |
3839 | 3575 st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes()); |
3576 andcc(Rmark, 2, G0); | |
3577 brx(Assembler::notZero, false, Assembler::pn, IsInflated); | |
3578 delayed()-> | |
0 | 3579 |
3580 // Try stack-lock acquisition. | |
3581 // Beware: the 1st instruction is in a delay slot | |
3839 | 3582 mov(Rbox, Rscratch); |
3583 or3(Rmark, markOopDesc::unlocked_value, Rmark); | |
3584 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); | |
3585 casn(mark_addr.base(), Rmark, Rscratch); | |
3586 cmp(Rmark, Rscratch); | |
3587 brx(Assembler::equal, false, Assembler::pt, done); | |
0 | 3588 delayed()->sub(Rscratch, SP, Rscratch); |
3589 | |
3590 // Stack-lock attempt failed - check for recursive stack-lock. | |
3591 // See the comments below about how we might remove this case. | |
3592 #ifdef _LP64 | |
3839 | 3593 sub(Rscratch, STACK_BIAS, Rscratch); |
0 | 3594 #endif |
3595 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant"); | |
3839 | 3596 andcc(Rscratch, 0xfffff003, Rscratch); |
3597 br(Assembler::always, false, Assembler::pt, done); | |
3598 delayed()-> st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
3599 | |
3600 bind(IsInflated); | |
0 | 3601 if (EmitSync & 64) { |
3602 // If m->owner != null goto IsLocked | |
3603 // Pessimistic form: Test-and-CAS vs CAS | |
3604 // The optimistic form avoids RTS->RTO cache line upgrades. | |
3839 | 3605 ld_ptr(Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch); |
3606 andcc(Rscratch, Rscratch, G0); | |
3607 brx(Assembler::notZero, false, Assembler::pn, done); | |
3608 delayed()->nop(); | |
0 | 3609 // m->owner == null : it's unlocked. |
3610 } | |
3611 | |
3612 // Try to CAS m->owner from null to Self | |
3613 // Invariant: if we acquire the lock then _recursions should be 0. | |
3839 | 3614 add(Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark); |
3615 mov(G2_thread, Rscratch); | |
3616 casn(Rmark, G0, Rscratch); | |
3617 cmp(Rscratch, G0); | |
0 | 3618 // Intentional fall-through into done |
3619 } else { | |
3620 // Aggressively avoid the Store-before-CAS penalty | |
3621 // Defer the store into box->dhw until after the CAS | |
3622 Label IsInflated, Recursive ; | |
3623 | |
3624 // Anticipate CAS -- Avoid RTS->RTO upgrade | |
3839 | 3625 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads); |
3626 | |
3627 ld_ptr(mark_addr, Rmark); // fetch obj->mark | |
0 | 3628 // Triage: biased, stack-locked, neutral, inflated |
3629 | |
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3630 if (try_bias) { |
0 | 3631 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters); |
3632 // Invariant: if control reaches this point in the emitted stream | |
3633 // then Rmark has not been modified. | |
3634 } | |
3839 | 3635 andcc(Rmark, 2, G0); |
3636 brx(Assembler::notZero, false, Assembler::pn, IsInflated); | |
0 | 3637 delayed()-> // Beware - dangling delay-slot |
3638 | |
3639 // Try stack-lock acquisition. | |
3640 // Transiently install BUSY (0) encoding in the mark word. | |
3641 // if the CAS of 0 into the mark was successful then we execute: | |
3642 // ST box->dhw = mark -- save fetched mark in on-stack basiclock box | |
3643 // ST obj->mark = box -- overwrite transient 0 value | |
3644 // This presumes TSO, of course. | |
3645 | |
3839 | 3646 mov(0, Rscratch); |
3647 or3(Rmark, markOopDesc::unlocked_value, Rmark); | |
3648 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); | |
3649 casn(mark_addr.base(), Rmark, Rscratch); | |
3650 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads); | |
3651 cmp(Rscratch, Rmark); | |
3652 brx(Assembler::notZero, false, Assembler::pn, Recursive); | |
3653 delayed()->st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
0 | 3654 if (counters != NULL) { |
3655 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch); | |
3656 } | |
3839 | 3657 ba(done); |
3658 delayed()->st_ptr(Rbox, mark_addr); | |
3659 | |
3660 bind(Recursive); | |
0 | 3661 // Stack-lock attempt failed - check for recursive stack-lock. |
3662 // Tests show that we can remove the recursive case with no impact | |
3663 // on refworkload 0.83. If we need to reduce the size of the code | |
3664 // emitted by compiler_lock_object() the recursive case is perfect | |
3665 // candidate. | |
3666 // | |
3667 // A more extreme idea is to always inflate on stack-lock recursion. | |
3668 // This lets us eliminate the recursive checks in compiler_lock_object | |
3669 // and compiler_unlock_object and the (box->dhw == 0) encoding. | |
3670 // A brief experiment - requiring changes to synchronizer.cpp, interpreter, | |
3671 // and showed a performance *increase*. In the same experiment I eliminated | |
3672 // the fast-path stack-lock code from the interpreter and always passed | |
3673 // control to the "slow" operators in synchronizer.cpp. | |
3674 | |
3675 // RScratch contains the fetched obj->mark value from the failed CASN. | |
3676 #ifdef _LP64 | |
3839 | 3677 sub(Rscratch, STACK_BIAS, Rscratch); |
0 | 3678 #endif |
3679 sub(Rscratch, SP, Rscratch); | |
3680 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant"); | |
3839 | 3681 andcc(Rscratch, 0xfffff003, Rscratch); |
0 | 3682 if (counters != NULL) { |
3683 // Accounting needs the Rscratch register | |
3839 | 3684 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); |
0 | 3685 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch); |
3839 | 3686 ba_short(done); |
0 | 3687 } else { |
3839 | 3688 ba(done); |
3689 delayed()->st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
0 | 3690 } |
3691 | |
3839 | 3692 bind (IsInflated); |
0 | 3693 if (EmitSync & 64) { |
3694 // If m->owner != null goto IsLocked | |
3695 // Test-and-CAS vs CAS | |
3696 // Pessimistic form avoids futile (doomed) CAS attempts | |
3697 // The optimistic form avoids RTS->RTO cache line upgrades. | |
3839 | 3698 ld_ptr(Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch); |
3699 andcc(Rscratch, Rscratch, G0); | |
3700 brx(Assembler::notZero, false, Assembler::pn, done); | |
3701 delayed()->nop(); | |
0 | 3702 // m->owner == null : it's unlocked. |
3703 } | |
3704 | |
3705 // Try to CAS m->owner from null to Self | |
3706 // Invariant: if we acquire the lock then _recursions should be 0. | |
3839 | 3707 add(Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark); |
3708 mov(G2_thread, Rscratch); | |
3709 casn(Rmark, G0, Rscratch); | |
3710 cmp(Rscratch, G0); | |
0 | 3711 // ST box->displaced_header = NonZero. |
3712 // Any non-zero value suffices: | |
3713 // unused_mark(), G2_thread, RBox, RScratch, rsp, etc. | |
3839 | 3714 st_ptr(Rbox, Rbox, BasicLock::displaced_header_offset_in_bytes()); |
0 | 3715 // Intentional fall-through into done |
3716 } | |
3717 | |
3839 | 3718 bind (done); |
0 | 3719 } |
3720 | |
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3721 void MacroAssembler::compiler_unlock_object(Register Roop, Register Rmark, |
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3722 Register Rbox, Register Rscratch, |
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3723 bool try_bias) { |
727 | 3724 Address mark_addr(Roop, oopDesc::mark_offset_in_bytes()); |
0 | 3725 |
3726 Label done ; | |
3727 | |
3728 if (EmitSync & 4) { | |
3839 | 3729 cmp(SP, G0); |
0 | 3730 return ; |
3731 } | |
3732 | |
3733 if (EmitSync & 8) { | |
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3734 if (try_bias) { |
0 | 3735 biased_locking_exit(mark_addr, Rscratch, done); |
3736 } | |
3737 | |
3738 // Test first if it is a fast recursive unlock | |
3739 ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rmark); | |
3839 | 3740 br_null_short(Rmark, Assembler::pt, done); |
0 | 3741 |
3742 // Check if it is still a light weight lock, this is is true if we see | |
3743 // the stack address of the basicLock in the markOop of the object | |
3744 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); | |
3745 casx_under_lock(mark_addr.base(), Rbox, Rmark, | |
3746 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); | |
3839 | 3747 ba(done); |
0 | 3748 delayed()->cmp(Rbox, Rmark); |
3839 | 3749 bind(done); |
0 | 3750 return ; |
3751 } | |
3752 | |
3753 // Beware ... If the aggregate size of the code emitted by CLO and CUO is | |
3754 // is too large performance rolls abruptly off a cliff. | |
3755 // This could be related to inlining policies, code cache management, or | |
3756 // I$ effects. | |
3757 Label LStacked ; | |
3758 | |
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3759 if (try_bias) { |
0 | 3760 // TODO: eliminate redundant LDs of obj->mark |
3761 biased_locking_exit(mark_addr, Rscratch, done); | |
3762 } | |
3763 | |
3839 | 3764 ld_ptr(Roop, oopDesc::mark_offset_in_bytes(), Rmark); |
3765 ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rscratch); | |
3766 andcc(Rscratch, Rscratch, G0); | |
3767 brx(Assembler::zero, false, Assembler::pn, done); | |
3768 delayed()->nop(); // consider: relocate fetch of mark, above, into this DS | |
3769 andcc(Rmark, 2, G0); | |
3770 brx(Assembler::zero, false, Assembler::pt, LStacked); | |
3771 delayed()->nop(); | |
0 | 3772 |
3773 // It's inflated | |
3774 // Conceptually we need a #loadstore|#storestore "release" MEMBAR before | |
3775 // the ST of 0 into _owner which releases the lock. This prevents loads | |
3776 // and stores within the critical section from reordering (floating) | |
3777 // past the store that releases the lock. But TSO is a strong memory model | |
3778 // and that particular flavor of barrier is a noop, so we can safely elide it. | |
3779 // Note that we use 1-0 locking by default for the inflated case. We | |
3780 // close the resultant (and rare) race by having contented threads in | |
3781 // monitorenter periodically poll _owner. | |
3839 | 3782 ld_ptr(Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch); |
3783 ld_ptr(Rmark, ObjectMonitor::recursions_offset_in_bytes() - 2, Rbox); | |
3784 xor3(Rscratch, G2_thread, Rscratch); | |
3785 orcc(Rbox, Rscratch, Rbox); | |
3786 brx(Assembler::notZero, false, Assembler::pn, done); | |
0 | 3787 delayed()-> |
3839 | 3788 ld_ptr(Rmark, ObjectMonitor::EntryList_offset_in_bytes() - 2, Rscratch); |
3789 ld_ptr(Rmark, ObjectMonitor::cxq_offset_in_bytes() - 2, Rbox); | |
3790 orcc(Rbox, Rscratch, G0); | |
0 | 3791 if (EmitSync & 65536) { |
3792 Label LSucc ; | |
3839 | 3793 brx(Assembler::notZero, false, Assembler::pn, LSucc); |
3794 delayed()->nop(); | |
3795 ba(done); | |
3796 delayed()->st_ptr(G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2); | |
3797 | |
3798 bind(LSucc); | |
3799 st_ptr(G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2); | |
3800 if (os::is_MP()) { membar (StoreLoad); } | |
3801 ld_ptr(Rmark, ObjectMonitor::succ_offset_in_bytes() - 2, Rscratch); | |
3802 andcc(Rscratch, Rscratch, G0); | |
3803 brx(Assembler::notZero, false, Assembler::pt, done); | |
3804 delayed()->andcc(G0, G0, G0); | |
3805 add(Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark); | |
3806 mov(G2_thread, Rscratch); | |
3807 casn(Rmark, G0, Rscratch); | |
0 | 3808 // invert icc.zf and goto done |
3839 | 3809 br_notnull(Rscratch, false, Assembler::pt, done); |
3810 delayed()->cmp(G0, G0); | |
3811 ba(done); | |
3812 delayed()->cmp(G0, 1); | |
0 | 3813 } else { |
3839 | 3814 brx(Assembler::notZero, false, Assembler::pn, done); |
3815 delayed()->nop(); | |
3816 ba(done); | |
3817 delayed()->st_ptr(G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2); | |
0 | 3818 } |
3819 | |
3839 | 3820 bind (LStacked); |
0 | 3821 // Consider: we could replace the expensive CAS in the exit |
3822 // path with a simple ST of the displaced mark value fetched from | |
3823 // the on-stack basiclock box. That admits a race where a thread T2 | |
3824 // in the slow lock path -- inflating with monitor M -- could race a | |
3825 // thread T1 in the fast unlock path, resulting in a missed wakeup for T2. | |
3826 // More precisely T1 in the stack-lock unlock path could "stomp" the | |
3827 // inflated mark value M installed by T2, resulting in an orphan | |
3828 // object monitor M and T2 becoming stranded. We can remedy that situation | |
3829 // by having T2 periodically poll the object's mark word using timed wait | |
3830 // operations. If T2 discovers that a stomp has occurred it vacates | |
3831 // the monitor M and wakes any other threads stranded on the now-orphan M. | |
3832 // In addition the monitor scavenger, which performs deflation, | |
3833 // would also need to check for orpan monitors and stranded threads. | |
3834 // | |
3835 // Finally, inflation is also used when T2 needs to assign a hashCode | |
3836 // to O and O is stack-locked by T1. The "stomp" race could cause | |
3837 // an assigned hashCode value to be lost. We can avoid that condition | |
3838 // and provide the necessary hashCode stability invariants by ensuring | |
3839 // that hashCode generation is idempotent between copying GCs. | |
3840 // For example we could compute the hashCode of an object O as | |
3841 // O's heap address XOR some high quality RNG value that is refreshed | |
3842 // at GC-time. The monitor scavenger would install the hashCode | |
3843 // found in any orphan monitors. Again, the mechanism admits a | |
3844 // lost-update "stomp" WAW race but detects and recovers as needed. | |
3845 // | |
3846 // A prototype implementation showed excellent results, although | |
3847 // the scavenger and timeout code was rather involved. | |
3848 | |
3839 | 3849 casn(mark_addr.base(), Rbox, Rscratch); |
3850 cmp(Rbox, Rscratch); | |
0 | 3851 // Intentional fall through into done ... |
3852 | |
3839 | 3853 bind(done); |
0 | 3854 } |
3855 | |
3856 | |
3857 | |
3858 void MacroAssembler::print_CPU_state() { | |
3859 // %%%%% need to implement this | |
3860 } | |
3861 | |
3862 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { | |
3863 // %%%%% need to implement this | |
3864 } | |
3865 | |
3866 void MacroAssembler::push_IU_state() { | |
3867 // %%%%% need to implement this | |
3868 } | |
3869 | |
3870 | |
3871 void MacroAssembler::pop_IU_state() { | |
3872 // %%%%% need to implement this | |
3873 } | |
3874 | |
3875 | |
3876 void MacroAssembler::push_FPU_state() { | |
3877 // %%%%% need to implement this | |
3878 } | |
3879 | |
3880 | |
3881 void MacroAssembler::pop_FPU_state() { | |
3882 // %%%%% need to implement this | |
3883 } | |
3884 | |
3885 | |
3886 void MacroAssembler::push_CPU_state() { | |
3887 // %%%%% need to implement this | |
3888 } | |
3889 | |
3890 | |
3891 void MacroAssembler::pop_CPU_state() { | |
3892 // %%%%% need to implement this | |
3893 } | |
3894 | |
3895 | |
3896 | |
3897 void MacroAssembler::verify_tlab() { | |
3898 #ifdef ASSERT | |
3899 if (UseTLAB && VerifyOops) { | |
3900 Label next, next2, ok; | |
3901 Register t1 = L0; | |
3902 Register t2 = L1; | |
3903 Register t3 = L2; | |
3904 | |
3905 save_frame(0); | |
3906 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1); | |
3907 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t2); | |
3908 or3(t1, t2, t3); | |
3839 | 3909 cmp_and_br_short(t1, t2, Assembler::greaterEqual, Assembler::pn, next); |
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3910 STOP("assert(top >= start)"); |
0 | 3911 should_not_reach_here(); |
3912 | |
3913 bind(next); | |
3914 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1); | |
3915 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t2); | |
3916 or3(t3, t2, t3); | |
3839 | 3917 cmp_and_br_short(t1, t2, Assembler::lessEqual, Assembler::pn, next2); |
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3918 STOP("assert(top <= end)"); |
0 | 3919 should_not_reach_here(); |
3920 | |
3921 bind(next2); | |
3922 and3(t3, MinObjAlignmentInBytesMask, t3); | |
3839 | 3923 cmp_and_br_short(t3, 0, Assembler::lessEqual, Assembler::pn, ok); |
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3924 STOP("assert(aligned)"); |
0 | 3925 should_not_reach_here(); |
3926 | |
3927 bind(ok); | |
3928 restore(); | |
3929 } | |
3930 #endif | |
3931 } | |
3932 | |
3933 | |
3934 void MacroAssembler::eden_allocate( | |
3935 Register obj, // result: pointer to object after successful allocation | |
3936 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise | |
3937 int con_size_in_bytes, // object size in bytes if known at compile time | |
3938 Register t1, // temp register | |
3939 Register t2, // temp register | |
3940 Label& slow_case // continuation point if fast allocation fails | |
3941 ){ | |
3942 // make sure arguments make sense | |
3943 assert_different_registers(obj, var_size_in_bytes, t1, t2); | |
3944 assert(0 <= con_size_in_bytes && Assembler::is_simm13(con_size_in_bytes), "illegal object size"); | |
3945 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment"); | |
3946 | |
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3947 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { |
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3948 // No allocation in the shared eden. |
3839 | 3949 ba_short(slow_case); |
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3950 } else { |
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3951 // get eden boundaries |
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3952 // note: we need both top & top_addr! |
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3953 const Register top_addr = t1; |
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3954 const Register end = t2; |
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3955 |
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3956 CollectedHeap* ch = Universe::heap(); |
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3957 set((intx)ch->top_addr(), top_addr); |
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3958 intx delta = (intx)ch->end_addr() - (intx)ch->top_addr(); |
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3959 ld_ptr(top_addr, delta, end); |
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3960 ld_ptr(top_addr, 0, obj); |
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3961 |
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3962 // try to allocate |
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3963 Label retry; |
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3964 bind(retry); |
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3965 #ifdef ASSERT |
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3966 // make sure eden top is properly aligned |
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3967 { |
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3968 Label L; |
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3969 btst(MinObjAlignmentInBytesMask, obj); |
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3970 br(Assembler::zero, false, Assembler::pt, L); |
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3971 delayed()->nop(); |
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3972 STOP("eden top is not properly aligned"); |
342
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3973 bind(L); |
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3974 } |
0 | 3975 #endif // ASSERT |
342
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3976 const Register free = end; |
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3977 sub(end, obj, free); // compute amount of free space |
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3978 if (var_size_in_bytes->is_valid()) { |
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3979 // size is unknown at compile time |
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3980 cmp(free, var_size_in_bytes); |
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3981 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case |
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3982 delayed()->add(obj, var_size_in_bytes, end); |
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3983 } else { |
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3984 // size is known at compile time |
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3985 cmp(free, con_size_in_bytes); |
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3986 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case |
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3987 delayed()->add(obj, con_size_in_bytes, end); |
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3988 } |
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3989 // Compare obj with the value at top_addr; if still equal, swap the value of |
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3990 // end with the value at top_addr. If not equal, read the value at top_addr |
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3991 // into end. |
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3992 casx_under_lock(top_addr, obj, end, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); |
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3993 // if someone beat us on the allocation, try again, otherwise continue |
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3994 cmp(obj, end); |
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3995 brx(Assembler::notEqual, false, Assembler::pn, retry); |
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3996 delayed()->mov(end, obj); // nop if successfull since obj == end |
0 | 3997 |
3998 #ifdef ASSERT | |
342
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3999 // make sure eden top is properly aligned |
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4000 { |
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4001 Label L; |
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4002 const Register top_addr = t1; |
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4003 |
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4004 set((intx)ch->top_addr(), top_addr); |
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4005 ld_ptr(top_addr, 0, top_addr); |
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4006 btst(MinObjAlignmentInBytesMask, top_addr); |
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4007 br(Assembler::zero, false, Assembler::pt, L); |
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4008 delayed()->nop(); |
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4009 STOP("eden top is not properly aligned"); |
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4010 bind(L); |
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4011 } |
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4012 #endif // ASSERT |
0 | 4013 } |
4014 } | |
4015 | |
4016 | |
4017 void MacroAssembler::tlab_allocate( | |
4018 Register obj, // result: pointer to object after successful allocation | |
4019 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise | |
4020 int con_size_in_bytes, // object size in bytes if known at compile time | |
4021 Register t1, // temp register | |
4022 Label& slow_case // continuation point if fast allocation fails | |
4023 ){ | |
4024 // make sure arguments make sense | |
4025 assert_different_registers(obj, var_size_in_bytes, t1); | |
4026 assert(0 <= con_size_in_bytes && is_simm13(con_size_in_bytes), "illegal object size"); | |
4027 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment"); | |
4028 | |
4029 const Register free = t1; | |
4030 | |
4031 verify_tlab(); | |
4032 | |
4033 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), obj); | |
4034 | |
4035 // calculate amount of free space | |
4036 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), free); | |
4037 sub(free, obj, free); | |
4038 | |
4039 Label done; | |
4040 if (var_size_in_bytes == noreg) { | |
4041 cmp(free, con_size_in_bytes); | |
4042 } else { | |
4043 cmp(free, var_size_in_bytes); | |
4044 } | |
4045 br(Assembler::less, false, Assembler::pn, slow_case); | |
4046 // calculate the new top pointer | |
4047 if (var_size_in_bytes == noreg) { | |
4048 delayed()->add(obj, con_size_in_bytes, free); | |
4049 } else { | |
4050 delayed()->add(obj, var_size_in_bytes, free); | |
4051 } | |
4052 | |
4053 bind(done); | |
4054 | |
4055 #ifdef ASSERT | |
4056 // make sure new free pointer is properly aligned | |
4057 { | |
4058 Label L; | |
4059 btst(MinObjAlignmentInBytesMask, free); | |
4060 br(Assembler::zero, false, Assembler::pt, L); | |
4061 delayed()->nop(); | |
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4062 STOP("updated TLAB free is not properly aligned"); |
0 | 4063 bind(L); |
4064 } | |
4065 #endif // ASSERT | |
4066 | |
4067 // update the tlab top pointer | |
4068 st_ptr(free, G2_thread, in_bytes(JavaThread::tlab_top_offset())); | |
4069 verify_tlab(); | |
4070 } | |
4071 | |
4072 | |
4073 void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) { | |
4074 Register top = O0; | |
4075 Register t1 = G1; | |
4076 Register t2 = G3; | |
4077 Register t3 = O1; | |
4078 assert_different_registers(top, t1, t2, t3, G4, G5 /* preserve G4 and G5 */); | |
4079 Label do_refill, discard_tlab; | |
4080 | |
4081 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { | |
4082 // No allocation in the shared eden. | |
3839 | 4083 ba_short(slow_case); |
0 | 4084 } |
4085 | |
4086 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), top); | |
4087 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t1); | |
4088 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()), t2); | |
4089 | |
4090 // calculate amount of free space | |
4091 sub(t1, top, t1); | |
4092 srl_ptr(t1, LogHeapWordSize, t1); | |
4093 | |
4094 // Retain tlab and allocate object in shared space if | |
4095 // the amount free in the tlab is too large to discard. | |
4096 cmp(t1, t2); | |
4097 brx(Assembler::lessEqual, false, Assembler::pt, discard_tlab); | |
4098 | |
4099 // increment waste limit to prevent getting stuck on this slow path | |
4100 delayed()->add(t2, ThreadLocalAllocBuffer::refill_waste_limit_increment(), t2); | |
4101 st_ptr(t2, G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset())); | |
4102 if (TLABStats) { | |
4103 // increment number of slow_allocations | |
4104 ld(G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset()), t2); | |
4105 add(t2, 1, t2); | |
4106 stw(t2, G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset())); | |
4107 } | |
3839 | 4108 ba_short(try_eden); |
0 | 4109 |
4110 bind(discard_tlab); | |
4111 if (TLABStats) { | |
4112 // increment number of refills | |
4113 ld(G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset()), t2); | |
4114 add(t2, 1, t2); | |
4115 stw(t2, G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset())); | |
4116 // accumulate wastage | |
4117 ld(G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset()), t2); | |
4118 add(t2, t1, t2); | |
4119 stw(t2, G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset())); | |
4120 } | |
4121 | |
4122 // if tlab is currently allocated (top or end != null) then | |
4123 // fill [top, end + alignment_reserve) with array object | |
3839 | 4124 br_null_short(top, Assembler::pn, do_refill); |
0 | 4125 |
4126 set((intptr_t)markOopDesc::prototype()->copy_set_hash(0x2), t2); | |
4127 st_ptr(t2, top, oopDesc::mark_offset_in_bytes()); // set up the mark word | |
4128 // set klass to intArrayKlass | |
4129 sub(t1, typeArrayOopDesc::header_size(T_INT), t1); | |
4130 add(t1, ThreadLocalAllocBuffer::alignment_reserve(), t1); | |
4131 sll_ptr(t1, log2_intptr(HeapWordSize/sizeof(jint)), t1); | |
4132 st(t1, top, arrayOopDesc::length_offset_in_bytes()); | |
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4133 set((intptr_t)Universe::intArrayKlassObj_addr(), t2); |
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4134 ld_ptr(t2, 0, t2); |
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4135 // store klass last. concurrent gcs assumes klass length is valid if |
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4136 // klass field is not null. |
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4137 store_klass(t2, top); |
0 | 4138 verify_oop(top); |
4139 | |
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4140 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t1); |
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4141 sub(top, t1, t1); // size of tlab's allocated portion |
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4142 incr_allocated_bytes(t1, t2, t3); |
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4143 |
0 | 4144 // refill the tlab with an eden allocation |
4145 bind(do_refill); | |
4146 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t1); | |
4147 sll_ptr(t1, LogHeapWordSize, t1); | |
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4148 // allocate new tlab, address returned in top |
0 | 4149 eden_allocate(top, t1, 0, t2, t3, slow_case); |
4150 | |
4151 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_start_offset())); | |
4152 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_top_offset())); | |
4153 #ifdef ASSERT | |
4154 // check that tlab_size (t1) is still valid | |
4155 { | |
4156 Label ok; | |
4157 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t2); | |
4158 sll_ptr(t2, LogHeapWordSize, t2); | |
3839 | 4159 cmp_and_br_short(t1, t2, Assembler::equal, Assembler::pt, ok); |
6266
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4160 STOP("assert(t1 == tlab_size)"); |
0 | 4161 should_not_reach_here(); |
4162 | |
4163 bind(ok); | |
4164 } | |
4165 #endif // ASSERT | |
4166 add(top, t1, top); // t1 is tlab_size | |
4167 sub(top, ThreadLocalAllocBuffer::alignment_reserve_in_bytes(), top); | |
4168 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_end_offset())); | |
4169 verify_tlab(); | |
3839 | 4170 ba_short(retry); |
0 | 4171 } |
4172 | |
2127
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4173 void MacroAssembler::incr_allocated_bytes(RegisterOrConstant size_in_bytes, |
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4174 Register t1, Register t2) { |
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4175 // Bump total bytes allocated by this thread |
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4176 assert(t1->is_global(), "must be global reg"); // so all 64 bits are saved on a context switch |
2127
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4177 assert_different_registers(size_in_bytes.register_or_noreg(), t1, t2); |
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4178 // v8 support has gone the way of the dodo |
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4179 ldx(G2_thread, in_bytes(JavaThread::allocated_bytes_offset()), t1); |
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4180 add(t1, ensure_simm13_or_reg(size_in_bytes, t2), t1); |
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4181 stx(t1, G2_thread, in_bytes(JavaThread::allocated_bytes_offset())); |
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4182 } |
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4183 |
0 | 4184 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { |
4185 switch (cond) { | |
4186 // Note some conditions are synonyms for others | |
4187 case Assembler::never: return Assembler::always; | |
4188 case Assembler::zero: return Assembler::notZero; | |
4189 case Assembler::lessEqual: return Assembler::greater; | |
4190 case Assembler::less: return Assembler::greaterEqual; | |
4191 case Assembler::lessEqualUnsigned: return Assembler::greaterUnsigned; | |
4192 case Assembler::lessUnsigned: return Assembler::greaterEqualUnsigned; | |
4193 case Assembler::negative: return Assembler::positive; | |
4194 case Assembler::overflowSet: return Assembler::overflowClear; | |
4195 case Assembler::always: return Assembler::never; | |
4196 case Assembler::notZero: return Assembler::zero; | |
4197 case Assembler::greater: return Assembler::lessEqual; | |
4198 case Assembler::greaterEqual: return Assembler::less; | |
4199 case Assembler::greaterUnsigned: return Assembler::lessEqualUnsigned; | |
4200 case Assembler::greaterEqualUnsigned: return Assembler::lessUnsigned; | |
4201 case Assembler::positive: return Assembler::negative; | |
4202 case Assembler::overflowClear: return Assembler::overflowSet; | |
4203 } | |
4204 | |
4205 ShouldNotReachHere(); return Assembler::overflowClear; | |
4206 } | |
4207 | |
4208 void MacroAssembler::cond_inc(Assembler::Condition cond, address counter_ptr, | |
4209 Register Rtmp1, Register Rtmp2 /*, Register Rtmp3, Register Rtmp4 */) { | |
4210 Condition negated_cond = negate_condition(cond); | |
4211 Label L; | |
4212 brx(negated_cond, false, Assembler::pt, L); | |
4213 delayed()->nop(); | |
4214 inc_counter(counter_ptr, Rtmp1, Rtmp2); | |
4215 bind(L); | |
4216 } | |
4217 | |
727 | 4218 void MacroAssembler::inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2) { |
4219 AddressLiteral addrlit(counter_addr); | |
4220 sethi(addrlit, Rtmp1); // Move hi22 bits into temporary register. | |
4221 Address addr(Rtmp1, addrlit.low10()); // Build an address with low10 bits. | |
4222 ld(addr, Rtmp2); | |
0 | 4223 inc(Rtmp2); |
727 | 4224 st(Rtmp2, addr); |
4225 } | |
4226 | |
4227 void MacroAssembler::inc_counter(int* counter_addr, Register Rtmp1, Register Rtmp2) { | |
4228 inc_counter((address) counter_addr, Rtmp1, Rtmp2); | |
0 | 4229 } |
4230 | |
4231 SkipIfEqual::SkipIfEqual( | |
4232 MacroAssembler* masm, Register temp, const bool* flag_addr, | |
4233 Assembler::Condition condition) { | |
4234 _masm = masm; | |
727 | 4235 AddressLiteral flag(flag_addr); |
4236 _masm->sethi(flag, temp); | |
4237 _masm->ldub(temp, flag.low10(), temp); | |
0 | 4238 _masm->tst(temp); |
4239 _masm->br(condition, false, Assembler::pt, _label); | |
4240 _masm->delayed()->nop(); | |
4241 } | |
4242 | |
4243 SkipIfEqual::~SkipIfEqual() { | |
4244 _masm->bind(_label); | |
4245 } | |
4246 | |
4247 | |
4248 // Writes to stack successive pages until offset reached to check for | |
4249 // stack overflow + shadow pages. This clobbers tsp and scratch. | |
4250 void MacroAssembler::bang_stack_size(Register Rsize, Register Rtsp, | |
4251 Register Rscratch) { | |
4252 // Use stack pointer in temp stack pointer | |
4253 mov(SP, Rtsp); | |
4254 | |
4255 // Bang stack for total size given plus stack shadow page size. | |
4256 // Bang one page at a time because a large size can overflow yellow and | |
4257 // red zones (the bang will fail but stack overflow handling can't tell that | |
4258 // it was a stack overflow bang vs a regular segv). | |
4259 int offset = os::vm_page_size(); | |
4260 Register Roffset = Rscratch; | |
4261 | |
4262 Label loop; | |
4263 bind(loop); | |
4264 set((-offset)+STACK_BIAS, Rscratch); | |
4265 st(G0, Rtsp, Rscratch); | |
4266 set(offset, Roffset); | |
4267 sub(Rsize, Roffset, Rsize); | |
4268 cmp(Rsize, G0); | |
4269 br(Assembler::greater, false, Assembler::pn, loop); | |
4270 delayed()->sub(Rtsp, Roffset, Rtsp); | |
4271 | |
4272 // Bang down shadow pages too. | |
4273 // The -1 because we already subtracted 1 page. | |
4274 for (int i = 0; i< StackShadowPages-1; i++) { | |
4275 set((-i*offset)+STACK_BIAS, Rscratch); | |
4276 st(G0, Rtsp, Rscratch); | |
4277 } | |
4278 } | |
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4279 |
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4280 /////////////////////////////////////////////////////////////////////////////////// |
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4281 #ifndef SERIALGC |
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4282 |
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4283 static address satb_log_enqueue_with_frame = NULL; |
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4284 static u_char* satb_log_enqueue_with_frame_end = NULL; |
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4285 |
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4286 static address satb_log_enqueue_frameless = NULL; |
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4287 static u_char* satb_log_enqueue_frameless_end = NULL; |
342
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4288 |
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4289 static int EnqueueCodeSize = 128 DEBUG_ONLY( + 256); // Instructions? |
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4290 |
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4291 static void generate_satb_log_enqueue(bool with_frame) { |
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4292 BufferBlob* bb = BufferBlob::create("enqueue_with_frame", EnqueueCodeSize); |
1748 | 4293 CodeBuffer buf(bb); |
342
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4294 MacroAssembler masm(&buf); |
3839 | 4295 |
4296 #define __ masm. | |
4297 | |
4298 address start = __ pc(); | |
342
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4299 Register pre_val; |
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4300 |
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4301 Label refill, restart; |
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4302 if (with_frame) { |
3839 | 4303 __ save_frame(0); |
342
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4304 pre_val = I0; // Was O0 before the save. |
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4305 } else { |
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4306 pre_val = O0; |
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4307 } |
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4308 |
342
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4309 int satb_q_index_byte_offset = |
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4310 in_bytes(JavaThread::satb_mark_queue_offset() + |
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4311 PtrQueue::byte_offset_of_index()); |
3888
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4312 |
342
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4313 int satb_q_buf_byte_offset = |
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4314 in_bytes(JavaThread::satb_mark_queue_offset() + |
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4315 PtrQueue::byte_offset_of_buf()); |
3888
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4316 |
342
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4317 assert(in_bytes(PtrQueue::byte_width_of_index()) == sizeof(intptr_t) && |
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4318 in_bytes(PtrQueue::byte_width_of_buf()) == sizeof(intptr_t), |
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4319 "check sizes in assembly below"); |
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4320 |
3839 | 4321 __ bind(restart); |
3888
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4322 |
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4323 // Load the index into the SATB buffer. PtrQueue::_index is a size_t |
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4324 // so ld_ptr is appropriate. |
3839 | 4325 __ ld_ptr(G2_thread, satb_q_index_byte_offset, L0); |
4326 | |
3888
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4327 // index == 0? |
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4328 __ cmp_and_brx_short(L0, G0, Assembler::equal, Assembler::pn, refill); |
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|
4329 |
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4330 __ ld_ptr(G2_thread, satb_q_buf_byte_offset, L1); |
3839 | 4331 __ sub(L0, oopSize, L0); |
4332 | |
4333 __ st_ptr(pre_val, L1, L0); // [_buf + index] := I0 | |
342
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4334 if (!with_frame) { |
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4335 // Use return-from-leaf |
3839 | 4336 __ retl(); |
4337 __ delayed()->st_ptr(L0, G2_thread, satb_q_index_byte_offset); | |
342
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4338 } else { |
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4339 // Not delayed. |
3839 | 4340 __ st_ptr(L0, G2_thread, satb_q_index_byte_offset); |
342
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4341 } |
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4342 if (with_frame) { |
3839 | 4343 __ ret(); |
4344 __ delayed()->restore(); | |
342
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4345 } |
3839 | 4346 __ bind(refill); |
342
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4347 |
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4348 address handle_zero = |
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4349 CAST_FROM_FN_PTR(address, |
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4350 &SATBMarkQueueSet::handle_zero_index_for_thread); |
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4351 // This should be rare enough that we can afford to save all the |
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4352 // scratch registers that the calling context might be using. |
3839 | 4353 __ mov(G1_scratch, L0); |
4354 __ mov(G3_scratch, L1); | |
4355 __ mov(G4, L2); | |
342
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4356 // We need the value of O0 above (for the write into the buffer), so we |
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4357 // save and restore it. |
3839 | 4358 __ mov(O0, L3); |
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4359 // Since the call will overwrite O7, we save and restore that, as well. |
3839 | 4360 __ mov(O7, L4); |
4361 __ call_VM_leaf(L5, handle_zero, G2_thread); | |
4362 __ mov(L0, G1_scratch); | |
4363 __ mov(L1, G3_scratch); | |
4364 __ mov(L2, G4); | |
4365 __ mov(L3, O0); | |
4366 __ br(Assembler::always, /*annul*/false, Assembler::pt, restart); | |
4367 __ delayed()->mov(L4, O7); | |
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4368 |
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4369 if (with_frame) { |
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4370 satb_log_enqueue_with_frame = start; |
3839 | 4371 satb_log_enqueue_with_frame_end = __ pc(); |
342
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4372 } else { |
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4373 satb_log_enqueue_frameless = start; |
3839 | 4374 satb_log_enqueue_frameless_end = __ pc(); |
342
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4375 } |
3839 | 4376 |
4377 #undef __ | |
342
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4378 } |
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4379 |
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4380 static inline void generate_satb_log_enqueue_if_necessary(bool with_frame) { |
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4381 if (with_frame) { |
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4382 if (satb_log_enqueue_with_frame == 0) { |
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4383 generate_satb_log_enqueue(with_frame); |
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4384 assert(satb_log_enqueue_with_frame != 0, "postcondition."); |
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|
4385 if (G1SATBPrintStubs) { |
37f87013dfd8
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|
4386 tty->print_cr("Generated with-frame satb enqueue:"); |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
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|
4387 Disassembler::decode((u_char*)satb_log_enqueue_with_frame, |
37f87013dfd8
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|
4388 satb_log_enqueue_with_frame_end, |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
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diff
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|
4389 tty); |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
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diff
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|
4390 } |
37f87013dfd8
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|
4391 } |
37f87013dfd8
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|
4392 } else { |
37f87013dfd8
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|
4393 if (satb_log_enqueue_frameless == 0) { |
37f87013dfd8
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|
4394 generate_satb_log_enqueue(with_frame); |
37f87013dfd8
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|
4395 assert(satb_log_enqueue_frameless != 0, "postcondition."); |
37f87013dfd8
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|
4396 if (G1SATBPrintStubs) { |
37f87013dfd8
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|
4397 tty->print_cr("Generated frameless satb enqueue:"); |
37f87013dfd8
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|
4398 Disassembler::decode((u_char*)satb_log_enqueue_frameless, |
37f87013dfd8
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diff
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|
4399 satb_log_enqueue_frameless_end, |
37f87013dfd8
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|
4400 tty); |
37f87013dfd8
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|
4401 } |
37f87013dfd8
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|
4402 } |
37f87013dfd8
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|
4403 } |
37f87013dfd8
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|
4404 } |
37f87013dfd8
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|
4405 |
3249
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7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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|
4406 void MacroAssembler::g1_write_barrier_pre(Register obj, |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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|
4407 Register index, |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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|
4408 int offset, |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
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|
4409 Register pre_val, |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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|
4410 Register tmp, |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
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|
4411 bool preserve_o_regs) { |
342
37f87013dfd8
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|
4412 Label filtered; |
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
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|
4413 |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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|
4414 if (obj == noreg) { |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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|
4415 // We are not loading the previous value so make |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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|
4416 // sure that we don't trash the value in pre_val |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
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|
4417 // with the code below. |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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|
4418 assert_different_registers(pre_val, tmp); |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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|
4419 } else { |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
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|
4420 // We will be loading the previous value |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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|
4421 // in this code so... |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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|
4422 assert(offset == 0 || index == noreg, "choose one"); |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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|
4423 assert(pre_val == noreg, "check this code"); |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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|
4424 } |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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diff
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|
4425 |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
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|
4426 // Is marking active? |
342
37f87013dfd8
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4427 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) { |
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|
4428 ld(G2, |
37f87013dfd8
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|
4429 in_bytes(JavaThread::satb_mark_queue_offset() + |
37f87013dfd8
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|
4430 PtrQueue::byte_offset_of_active()), |
37f87013dfd8
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|
4431 tmp); |
37f87013dfd8
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|
4432 } else { |
37f87013dfd8
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|
4433 guarantee(in_bytes(PtrQueue::byte_width_of_active()) == 1, |
37f87013dfd8
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|
4434 "Assumption"); |
37f87013dfd8
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|
4435 ldsb(G2, |
37f87013dfd8
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|
4436 in_bytes(JavaThread::satb_mark_queue_offset() + |
37f87013dfd8
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|
4437 PtrQueue::byte_offset_of_active()), |
37f87013dfd8
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|
4438 tmp); |
37f87013dfd8
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|
4439 } |
845
df6caf649ff7
6700789: G1: Enable use of compressed oops with G1 heaps
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794
diff
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|
4440 |
3888
4fe626cbf0bf
7066841: remove MacroAssembler::br_on_reg_cond() on sparc
johnc
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diff
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|
4441 // Is marking active? |
4fe626cbf0bf
7066841: remove MacroAssembler::br_on_reg_cond() on sparc
johnc
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3839
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|
4442 cmp_and_br_short(tmp, G0, Assembler::equal, Assembler::pt, filtered); |
342
37f87013dfd8
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|
4443 |
3249
e1162778c1c8
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diff
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|
4444 // Do we need to load the previous value? |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
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|
4445 if (obj != noreg) { |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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|
4446 // Load the previous value... |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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|
4447 if (index == noreg) { |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
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|
4448 if (Assembler::is_simm13(offset)) { |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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diff
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|
4449 load_heap_oop(obj, offset, tmp); |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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diff
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|
4450 } else { |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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diff
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|
4451 set(offset, tmp); |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
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|
4452 load_heap_oop(obj, tmp, tmp); |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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|
4453 } |
342
37f87013dfd8
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|
4454 } else { |
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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|
4455 load_heap_oop(obj, index, tmp); |
342
37f87013dfd8
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|
4456 } |
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
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diff
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|
4457 // Previous value has been loaded into tmp |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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|
4458 pre_val = tmp; |
342
37f87013dfd8
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|
4459 } |
37f87013dfd8
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|
4460 |
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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diff
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|
4461 assert(pre_val != noreg, "must have a real register"); |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
2357
diff
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|
4462 |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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diff
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|
4463 // Is the previous value null? |
3888
4fe626cbf0bf
7066841: remove MacroAssembler::br_on_reg_cond() on sparc
johnc
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3839
diff
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|
4464 cmp_and_brx_short(pre_val, G0, Assembler::equal, Assembler::pt, filtered); |
342
37f87013dfd8
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|
4465 |
37f87013dfd8
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|
4466 // OK, it's not filtered, so we'll need to call enqueue. In the normal |
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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diff
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|
4467 // case, pre_val will be a scratch G-reg, but there are some cases in |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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diff
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|
4468 // which it's an O-reg. In the first case, do a normal call. In the |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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diff
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|
4469 // latter, do a save here and call the frameless version. |
342
37f87013dfd8
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diff
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|
4470 |
37f87013dfd8
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|
4471 guarantee(pre_val->is_global() || pre_val->is_out(), |
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|
4472 "Or we need to think harder."); |
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
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diff
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|
4473 |
342
37f87013dfd8
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|
4474 if (pre_val->is_global() && !preserve_o_regs) { |
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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diff
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|
4475 generate_satb_log_enqueue_if_necessary(true); // with frame |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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|
4476 |
342
37f87013dfd8
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diff
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|
4477 call(satb_log_enqueue_with_frame); |
37f87013dfd8
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124
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|
4478 delayed()->mov(pre_val, O0); |
37f87013dfd8
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|
4479 } else { |
3249
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
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|
4480 generate_satb_log_enqueue_if_necessary(false); // frameless |
e1162778c1c8
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
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|
4481 |
342
37f87013dfd8
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|
4482 save_frame(0); |
37f87013dfd8
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|
4483 call(satb_log_enqueue_frameless); |
37f87013dfd8
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|
4484 delayed()->mov(pre_val->after_save(), O0); |
37f87013dfd8
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|
4485 restore(); |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
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|
4486 } |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
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|
4487 |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
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|
4488 bind(filtered); |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
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diff
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|
4489 } |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
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|
4490 |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
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|
4491 static address dirty_card_log_enqueue = 0; |
37f87013dfd8
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|
4492 static u_char* dirty_card_log_enqueue_end = 0; |
37f87013dfd8
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|
4493 |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
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|
4494 // This gets to assume that o0 contains the object address. |
37f87013dfd8
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|
4495 static void generate_dirty_card_log_enqueue(jbyte* byte_map_base) { |
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4496 BufferBlob* bb = BufferBlob::create("dirty_card_enqueue", EnqueueCodeSize*2); |
1748 | 4497 CodeBuffer buf(bb); |
342
37f87013dfd8
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|
4498 MacroAssembler masm(&buf); |
3839 | 4499 #define __ masm. |
4500 address start = __ pc(); | |
342
37f87013dfd8
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|
4501 |
37f87013dfd8
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4502 Label not_already_dirty, restart, refill; |
37f87013dfd8
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|
4503 |
37f87013dfd8
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|
4504 #ifdef _LP64 |
3839 | 4505 __ srlx(O0, CardTableModRefBS::card_shift, O0); |
342
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4506 #else |
3839 | 4507 __ srl(O0, CardTableModRefBS::card_shift, O0); |
342
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|
4508 #endif |
727 | 4509 AddressLiteral addrlit(byte_map_base); |
3839 | 4510 __ set(addrlit, O1); // O1 := <card table base> |
4511 __ ldub(O0, O1, O2); // O2 := [O0 + O1] | |
4512 | |
3888
4fe626cbf0bf
7066841: remove MacroAssembler::br_on_reg_cond() on sparc
johnc
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3839
diff
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|
4513 assert(CardTableModRefBS::dirty_card_val() == 0, "otherwise check this code"); |
4fe626cbf0bf
7066841: remove MacroAssembler::br_on_reg_cond() on sparc
johnc
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diff
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|
4514 __ cmp_and_br_short(O2, G0, Assembler::notEqual, Assembler::pt, not_already_dirty); |
342
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4515 |
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|
4516 // We didn't take the branch, so we're already dirty: return. |
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4517 // Use return-from-leaf |
3839 | 4518 __ retl(); |
4519 __ delayed()->nop(); | |
342
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4520 |
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4521 // Not dirty. |
3839 | 4522 __ bind(not_already_dirty); |
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4523 |
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4524 // Get O0 + O1 into a reg by itself |
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4525 __ add(O0, O1, O3); |
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4526 |
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4527 // First, dirty it. |
3839 | 4528 __ stb(G0, O3, G0); // [cardPtr] := 0 (i.e., dirty). |
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4529 |
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4530 int dirty_card_q_index_byte_offset = |
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4531 in_bytes(JavaThread::dirty_card_queue_offset() + |
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4532 PtrQueue::byte_offset_of_index()); |
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4533 int dirty_card_q_buf_byte_offset = |
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4534 in_bytes(JavaThread::dirty_card_queue_offset() + |
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4535 PtrQueue::byte_offset_of_buf()); |
3839 | 4536 __ bind(restart); |
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4537 |
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4538 // Load the index into the update buffer. PtrQueue::_index is |
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4539 // a size_t so ld_ptr is appropriate here. |
3839 | 4540 __ ld_ptr(G2_thread, dirty_card_q_index_byte_offset, L0); |
4541 | |
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4542 // index == 0? |
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4543 __ cmp_and_brx_short(L0, G0, Assembler::equal, Assembler::pn, refill); |
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4544 |
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4545 __ ld_ptr(G2_thread, dirty_card_q_buf_byte_offset, L1); |
3839 | 4546 __ sub(L0, oopSize, L0); |
4547 | |
4548 __ st_ptr(O3, L1, L0); // [_buf + index] := I0 | |
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4549 // Use return-from-leaf |
3839 | 4550 __ retl(); |
4551 __ delayed()->st_ptr(L0, G2_thread, dirty_card_q_index_byte_offset); | |
4552 | |
4553 __ bind(refill); | |
342
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4554 address handle_zero = |
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4555 CAST_FROM_FN_PTR(address, |
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4556 &DirtyCardQueueSet::handle_zero_index_for_thread); |
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4557 // This should be rare enough that we can afford to save all the |
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4558 // scratch registers that the calling context might be using. |
3839 | 4559 __ mov(G1_scratch, L3); |
4560 __ mov(G3_scratch, L5); | |
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4561 // We need the value of O3 above (for the write into the buffer), so we |
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4562 // save and restore it. |
3839 | 4563 __ mov(O3, L6); |
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4564 // Since the call will overwrite O7, we save and restore that, as well. |
3839 | 4565 __ mov(O7, L4); |
4566 | |
4567 __ call_VM_leaf(L7_thread_cache, handle_zero, G2_thread); | |
4568 __ mov(L3, G1_scratch); | |
4569 __ mov(L5, G3_scratch); | |
4570 __ mov(L6, O3); | |
4571 __ br(Assembler::always, /*annul*/false, Assembler::pt, restart); | |
4572 __ delayed()->mov(L4, O7); | |
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4573 |
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4574 dirty_card_log_enqueue = start; |
3839 | 4575 dirty_card_log_enqueue_end = __ pc(); |
342
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4576 // XXX Should have a guarantee here about not going off the end! |
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4577 // Does it already do so? Do an experiment... |
3839 | 4578 |
4579 #undef __ | |
4580 | |
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4581 } |
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4582 |
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4583 static inline void |
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4584 generate_dirty_card_log_enqueue_if_necessary(jbyte* byte_map_base) { |
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4585 if (dirty_card_log_enqueue == 0) { |
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4586 generate_dirty_card_log_enqueue(byte_map_base); |
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4587 assert(dirty_card_log_enqueue != 0, "postcondition."); |
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4588 if (G1SATBPrintStubs) { |
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4589 tty->print_cr("Generated dirty_card enqueue:"); |
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4590 Disassembler::decode((u_char*)dirty_card_log_enqueue, |
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4591 dirty_card_log_enqueue_end, |
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4592 tty); |
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4593 } |
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4594 } |
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4595 } |
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4596 |
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4597 |
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4598 void MacroAssembler::g1_write_barrier_post(Register store_addr, Register new_val, Register tmp) { |
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4599 |
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4600 Label filtered; |
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4601 MacroAssembler* post_filter_masm = this; |
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4602 |
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4603 if (new_val == G0) return; |
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4604 |
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4605 G1SATBCardTableModRefBS* bs = (G1SATBCardTableModRefBS*) Universe::heap()->barrier_set(); |
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4606 assert(bs->kind() == BarrierSet::G1SATBCT || |
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4607 bs->kind() == BarrierSet::G1SATBCTLogging, "wrong barrier"); |
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4608 |
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4609 if (G1RSBarrierRegionFilter) { |
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4610 xor3(store_addr, new_val, tmp); |
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4611 #ifdef _LP64 |
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4612 srlx(tmp, HeapRegion::LogOfHRGrainBytes, tmp); |
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4613 #else |
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4614 srl(tmp, HeapRegion::LogOfHRGrainBytes, tmp); |
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4615 #endif |
3249
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4616 |
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4617 // XXX Should I predict this taken or not? Does it matter? |
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4618 cmp_and_brx_short(tmp, G0, Assembler::equal, Assembler::pt, filtered); |
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4619 } |
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4620 |
794 | 4621 // If the "store_addr" register is an "in" or "local" register, move it to |
4622 // a scratch reg so we can pass it as an argument. | |
4623 bool use_scr = !(store_addr->is_global() || store_addr->is_out()); | |
4624 // Pick a scratch register different from "tmp". | |
4625 Register scr = (tmp == G1_scratch ? G3_scratch : G1_scratch); | |
4626 // Make sure we use up the delay slot! | |
4627 if (use_scr) { | |
4628 post_filter_masm->mov(store_addr, scr); | |
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4629 } else { |
794 | 4630 post_filter_masm->nop(); |
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4631 } |
794 | 4632 generate_dirty_card_log_enqueue_if_necessary(bs->byte_map_base); |
4633 save_frame(0); | |
4634 call(dirty_card_log_enqueue); | |
4635 if (use_scr) { | |
4636 delayed()->mov(scr, O0); | |
4637 } else { | |
4638 delayed()->mov(store_addr->after_save(), O0); | |
4639 } | |
4640 restore(); | |
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4641 |
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4642 bind(filtered); |
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4643 } |
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4644 |
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4645 #endif // SERIALGC |
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4646 /////////////////////////////////////////////////////////////////////////////////// |
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4647 |
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4648 void MacroAssembler::card_write_barrier_post(Register store_addr, Register new_val, Register tmp) { |
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4649 // If we're writing constant NULL, we can skip the write barrier. |
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4650 if (new_val == G0) return; |
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4651 CardTableModRefBS* bs = (CardTableModRefBS*) Universe::heap()->barrier_set(); |
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4652 assert(bs->kind() == BarrierSet::CardTableModRef || |
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4653 bs->kind() == BarrierSet::CardTableExtension, "wrong barrier"); |
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4654 card_table_write(bs->byte_map_base, tmp, store_addr); |
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4655 } |
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4656 |
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4657 void MacroAssembler::load_klass(Register src_oop, Register klass) { |
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4658 // The number of bytes in this code is used by |
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4659 // MachCallDynamicJavaNode::ret_addr_offset() |
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4660 // if this changes, change that. |
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4661 if (UseCompressedOops) { |
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4662 lduw(src_oop, oopDesc::klass_offset_in_bytes(), klass); |
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4663 decode_heap_oop_not_null(klass); |
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4664 } else { |
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4665 ld_ptr(src_oop, oopDesc::klass_offset_in_bytes(), klass); |
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4666 } |
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4667 } |
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4668 |
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4669 void MacroAssembler::store_klass(Register klass, Register dst_oop) { |
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4670 if (UseCompressedOops) { |
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4671 assert(dst_oop != klass, "not enough registers"); |
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4672 encode_heap_oop_not_null(klass); |
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4673 st(klass, dst_oop, oopDesc::klass_offset_in_bytes()); |
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4674 } else { |
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4675 st_ptr(klass, dst_oop, oopDesc::klass_offset_in_bytes()); |
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4676 } |
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parents:
0
diff
changeset
|
4677 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4678 |
167
feeb96a45707
6696264: assert("narrow oop can never be zero") for GCBasher & ParNewGC
coleenp
parents:
164
diff
changeset
|
4679 void MacroAssembler::store_klass_gap(Register s, Register d) { |
feeb96a45707
6696264: assert("narrow oop can never be zero") for GCBasher & ParNewGC
coleenp
parents:
164
diff
changeset
|
4680 if (UseCompressedOops) { |
feeb96a45707
6696264: assert("narrow oop can never be zero") for GCBasher & ParNewGC
coleenp
parents:
164
diff
changeset
|
4681 assert(s != d, "not enough registers"); |
feeb96a45707
6696264: assert("narrow oop can never be zero") for GCBasher & ParNewGC
coleenp
parents:
164
diff
changeset
|
4682 st(s, d, oopDesc::klass_gap_offset_in_bytes()); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4683 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4684 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4685 |
727 | 4686 void MacroAssembler::load_heap_oop(const Address& s, Register d) { |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4687 if (UseCompressedOops) { |
727 | 4688 lduw(s, d); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4689 decode_heap_oop(d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4690 } else { |
727 | 4691 ld_ptr(s, d); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4692 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4693 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4694 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4695 void MacroAssembler::load_heap_oop(Register s1, Register s2, Register d) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4696 if (UseCompressedOops) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4697 lduw(s1, s2, d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4698 decode_heap_oop(d, d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4699 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4700 ld_ptr(s1, s2, d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4701 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4702 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4703 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4704 void MacroAssembler::load_heap_oop(Register s1, int simm13a, Register d) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4705 if (UseCompressedOops) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4706 lduw(s1, simm13a, d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4707 decode_heap_oop(d, d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4708 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4709 ld_ptr(s1, simm13a, d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4710 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4711 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4712 |
1846 | 4713 void MacroAssembler::load_heap_oop(Register s1, RegisterOrConstant s2, Register d) { |
4714 if (s2.is_constant()) load_heap_oop(s1, s2.as_constant(), d); | |
4715 else load_heap_oop(s1, s2.as_register(), d); | |
4716 } | |
4717 | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4718 void MacroAssembler::store_heap_oop(Register d, Register s1, Register s2) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4719 if (UseCompressedOops) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4720 assert(s1 != d && s2 != d, "not enough registers"); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4721 encode_heap_oop(d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4722 st(d, s1, s2); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4723 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4724 st_ptr(d, s1, s2); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4725 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4726 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4727 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4728 void MacroAssembler::store_heap_oop(Register d, Register s1, int simm13a) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4729 if (UseCompressedOops) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4730 assert(s1 != d, "not enough registers"); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4731 encode_heap_oop(d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4732 st(d, s1, simm13a); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4733 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4734 st_ptr(d, s1, simm13a); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4735 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4736 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4737 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4738 void MacroAssembler::store_heap_oop(Register d, const Address& a, int offset) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4739 if (UseCompressedOops) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4740 assert(a.base() != d, "not enough registers"); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4741 encode_heap_oop(d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4742 st(d, a, offset); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4743 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4744 st_ptr(d, a, offset); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4745 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4746 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4747 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4748 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4749 void MacroAssembler::encode_heap_oop(Register src, Register dst) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4750 assert (UseCompressedOops, "must be compressed"); |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4751 assert (Universe::heap() != NULL, "java heap should be initialized"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4752 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
178
6d172e3548cb
6695819: verify_oopx rax: broken oop in decode_heap_oop
coleenp
parents:
124
diff
changeset
|
4753 verify_oop(src); |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4754 if (Universe::narrow_oop_base() == NULL) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4755 srlx(src, LogMinObjAlignmentInBytes, dst); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4756 return; |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4757 } |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4758 Label done; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4759 if (src == dst) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4760 // optimize for frequent case src == dst |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4761 bpr(rc_nz, true, Assembler::pt, src, done); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4762 delayed() -> sub(src, G6_heapbase, dst); // annuled if not taken |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4763 bind(done); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4764 srlx(src, LogMinObjAlignmentInBytes, dst); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4765 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4766 bpr(rc_z, false, Assembler::pn, src, done); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4767 delayed() -> mov(G0, dst); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4768 // could be moved before branch, and annulate delay, |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4769 // but may add some unneeded work decoding null |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4770 sub(src, G6_heapbase, dst); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4771 srlx(dst, LogMinObjAlignmentInBytes, dst); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4772 bind(done); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4773 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4774 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4775 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4776 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4777 void MacroAssembler::encode_heap_oop_not_null(Register r) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4778 assert (UseCompressedOops, "must be compressed"); |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4779 assert (Universe::heap() != NULL, "java heap should be initialized"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4780 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
178
6d172e3548cb
6695819: verify_oopx rax: broken oop in decode_heap_oop
coleenp
parents:
124
diff
changeset
|
4781 verify_oop(r); |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4782 if (Universe::narrow_oop_base() != NULL) |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4783 sub(r, G6_heapbase, r); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4784 srlx(r, LogMinObjAlignmentInBytes, r); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4785 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4786 |
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
4787 void MacroAssembler::encode_heap_oop_not_null(Register src, Register dst) { |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
4788 assert (UseCompressedOops, "must be compressed"); |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4789 assert (Universe::heap() != NULL, "java heap should be initialized"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4790 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
178
6d172e3548cb
6695819: verify_oopx rax: broken oop in decode_heap_oop
coleenp
parents:
124
diff
changeset
|
4791 verify_oop(src); |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4792 if (Universe::narrow_oop_base() == NULL) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4793 srlx(src, LogMinObjAlignmentInBytes, dst); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4794 } else { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4795 sub(src, G6_heapbase, dst); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4796 srlx(dst, LogMinObjAlignmentInBytes, dst); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4797 } |
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
4798 } |
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
4799 |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4800 // Same algorithm as oops.inline.hpp decode_heap_oop. |
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4801 void MacroAssembler::decode_heap_oop(Register src, Register dst) { |
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4802 assert (UseCompressedOops, "must be compressed"); |
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4803 assert (Universe::heap() != NULL, "java heap should be initialized"); |
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4804 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
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4805 sllx(src, LogMinObjAlignmentInBytes, dst); |
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4806 if (Universe::narrow_oop_base() != NULL) { |
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4807 Label done; |
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4808 bpr(rc_nz, true, Assembler::pt, dst, done); |
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4809 delayed() -> add(dst, G6_heapbase, dst); // annuled if not taken |
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4810 bind(done); |
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4811 } |
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4812 verify_oop(dst); |
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4813 } |
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4814 |
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4815 void MacroAssembler::decode_heap_oop_not_null(Register r) { |
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4816 // Do not add assert code to this unless you change vtableStubs_sparc.cpp |
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4817 // pd_code_size_limit. |
178
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4818 // Also do not verify_oop as this is called by verify_oop. |
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4819 assert (UseCompressedOops, "must be compressed"); |
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4820 assert (Universe::heap() != NULL, "java heap should be initialized"); |
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4821 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
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4822 sllx(r, LogMinObjAlignmentInBytes, r); |
642
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4823 if (Universe::narrow_oop_base() != NULL) |
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4824 add(r, G6_heapbase, r); |
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4825 } |
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4826 |
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4827 void MacroAssembler::decode_heap_oop_not_null(Register src, Register dst) { |
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4828 // Do not add assert code to this unless you change vtableStubs_sparc.cpp |
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4829 // pd_code_size_limit. |
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4830 // Also do not verify_oop as this is called by verify_oop. |
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4831 assert (UseCompressedOops, "must be compressed"); |
642
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4832 assert (Universe::heap() != NULL, "java heap should be initialized"); |
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4833 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
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4834 sllx(src, LogMinObjAlignmentInBytes, dst); |
642
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4835 if (Universe::narrow_oop_base() != NULL) |
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4836 add(dst, G6_heapbase, dst); |
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4837 } |
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4838 |
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4839 void MacroAssembler::reinit_heapbase() { |
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4840 if (UseCompressedOops) { |
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4841 // call indirectly to solve generation ordering problem |
727 | 4842 AddressLiteral base(Universe::narrow_oop_base_addr()); |
113
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4843 load_ptr_contents(base, G6_heapbase); |
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4844 } |
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4845 } |
986
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4846 |
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4847 // Compare char[] arrays aligned to 4 bytes. |
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4848 void MacroAssembler::char_arrays_equals(Register ary1, Register ary2, |
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4849 Register limit, Register result, |
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4850 Register chr1, Register chr2, Label& Ldone) { |
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4851 Label Lvector, Lloop; |
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4852 assert(chr1 == result, "should be the same"); |
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4853 |
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4854 // Note: limit contains number of bytes (2*char_elements) != 0. |
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4855 andcc(limit, 0x2, chr1); // trailing character ? |
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4856 br(Assembler::zero, false, Assembler::pt, Lvector); |
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4857 delayed()->nop(); |
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4858 |
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4859 // compare the trailing char |
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4860 sub(limit, sizeof(jchar), limit); |
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4861 lduh(ary1, limit, chr1); |
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4862 lduh(ary2, limit, chr2); |
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4863 cmp(chr1, chr2); |
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4864 br(Assembler::notEqual, true, Assembler::pt, Ldone); |
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4865 delayed()->mov(G0, result); // not equal |
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4866 |
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4867 // only one char ? |
3839 | 4868 cmp_zero_and_br(zero, limit, Ldone, true, Assembler::pn); |
986
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4869 delayed()->add(G0, 1, result); // zero-length arrays are equal |
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4870 |
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4871 // word by word compare, dont't need alignment check |
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4872 bind(Lvector); |
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4873 // Shift ary1 and ary2 to the end of the arrays, negate limit |
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4874 add(ary1, limit, ary1); |
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4875 add(ary2, limit, ary2); |
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4876 neg(limit, limit); |
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4877 |
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4878 lduw(ary1, limit, chr1); |
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4879 bind(Lloop); |
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4880 lduw(ary2, limit, chr2); |
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4881 cmp(chr1, chr2); |
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4882 br(Assembler::notEqual, true, Assembler::pt, Ldone); |
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4883 delayed()->mov(G0, result); // not equal |
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|
4884 inccc(limit, 2*sizeof(jchar)); |
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|
4885 // annul LDUW if branch is not taken to prevent access past end of array |
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4886 br(Assembler::notZero, true, Assembler::pt, Lloop); |
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4887 delayed()->lduw(ary1, limit, chr1); // hoisted |
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|
4888 |
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4889 // Caller should set it: |
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4890 // add(G0, 1, result); // equals |
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4891 } |
3892 | 4892 |
4893 // Use BIS for zeroing (count is in bytes). | |
4894 void MacroAssembler::bis_zeroing(Register to, Register count, Register temp, Label& Ldone) { | |
4895 assert(UseBlockZeroing && VM_Version::has_block_zeroing(), "only works with BIS zeroing"); | |
4896 Register end = count; | |
4897 int cache_line_size = VM_Version::prefetch_data_size(); | |
4898 // Minimum count when BIS zeroing can be used since | |
4899 // it needs membar which is expensive. | |
4900 int block_zero_size = MAX2(cache_line_size*3, (int)BlockZeroingLowLimit); | |
4901 | |
4902 Label small_loop; | |
4903 // Check if count is negative (dead code) or zero. | |
4904 // Note, count uses 64bit in 64 bit VM. | |
4905 cmp_and_brx_short(count, 0, Assembler::lessEqual, Assembler::pn, Ldone); | |
4906 | |
4907 // Use BIS zeroing only for big arrays since it requires membar. | |
4908 if (Assembler::is_simm13(block_zero_size)) { // < 4096 | |
4909 cmp(count, block_zero_size); | |
4910 } else { | |
4911 set(block_zero_size, temp); | |
4912 cmp(count, temp); | |
4913 } | |
4914 br(Assembler::lessUnsigned, false, Assembler::pt, small_loop); | |
4915 delayed()->add(to, count, end); | |
4916 | |
4917 // Note: size is >= three (32 bytes) cache lines. | |
4918 | |
4919 // Clean the beginning of space up to next cache line. | |
4920 for (int offs = 0; offs < cache_line_size; offs += 8) { | |
4921 stx(G0, to, offs); | |
4922 } | |
4923 | |
4924 // align to next cache line | |
4925 add(to, cache_line_size, to); | |
4926 and3(to, -cache_line_size, to); | |
4927 | |
4928 // Note: size left >= two (32 bytes) cache lines. | |
4929 | |
4930 // BIS should not be used to zero tail (64 bytes) | |
4931 // to avoid zeroing a header of the following object. | |
4932 sub(end, (cache_line_size*2)-8, end); | |
4933 | |
4934 Label bis_loop; | |
4935 bind(bis_loop); | |
4936 stxa(G0, to, G0, Assembler::ASI_ST_BLKINIT_PRIMARY); | |
4937 add(to, cache_line_size, to); | |
4938 cmp_and_brx_short(to, end, Assembler::lessUnsigned, Assembler::pt, bis_loop); | |
4939 | |
4940 // BIS needs membar. | |
4941 membar(Assembler::StoreLoad); | |
4942 | |
4943 add(end, (cache_line_size*2)-8, end); // restore end | |
4944 cmp_and_brx_short(to, end, Assembler::greaterEqualUnsigned, Assembler::pn, Ldone); | |
4945 | |
4946 // Clean the tail. | |
4947 bind(small_loop); | |
4948 stx(G0, to, 0); | |
4949 add(to, 8, to); | |
4950 cmp_and_brx_short(to, end, Assembler::lessUnsigned, Assembler::pt, small_loop); | |
4951 nop(); // Separate short branches | |
4952 } |