annotate src/cpu/x86/vm/vmreg_x86.inline.hpp @ 20504:6948da6d7c13

8052172: Evacuation failure handling in G1 does not evacuate all objects if -XX:-G1DeferredRSUpdate is set Summary: Remove -XX:-G1DeferredRSUpdate functionality as it is racy. During evacuation failure handling, threads where evacuation failure handling occurred may try to add remembered sets to regions which remembered sets are currently being scanned. The iterator to handle the remembered set scan does not support addition of entries during scan and so may skip valid references. Reviewed-by: iveresov, brutisso, mgerdin
author tschatzl
date Tue, 30 Sep 2014 09:44:36 +0200
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children
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1 /*
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2 * Copyright (c) 2006, 2012, Oracle and/or its affiliates. All rights reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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20 * or visit www.oracle.com if you need additional information or have any
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21 * questions.
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22 *
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23 */
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24
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25 #ifndef CPU_X86_VM_VMREG_X86_INLINE_HPP
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26 #define CPU_X86_VM_VMREG_X86_INLINE_HPP
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27
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28 inline VMReg RegisterImpl::as_VMReg() {
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29 if( this==noreg ) return VMRegImpl::Bad();
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30 #ifdef AMD64
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31 return VMRegImpl::as_VMReg(encoding() << 1 );
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32 #else
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33 return VMRegImpl::as_VMReg(encoding() );
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34 #endif // AMD64
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35 }
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36
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37 inline VMReg FloatRegisterImpl::as_VMReg() {
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38 return VMRegImpl::as_VMReg((encoding() << 1) + ConcreteRegisterImpl::max_gpr);
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39 }
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40
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41 inline VMReg XMMRegisterImpl::as_VMReg() {
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42 return VMRegImpl::as_VMReg((encoding() << 3) + ConcreteRegisterImpl::max_fpr);
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43 }
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44
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45
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46 inline bool VMRegImpl::is_Register() {
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47 return (unsigned int) value() < (unsigned int) ConcreteRegisterImpl::max_gpr;
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48 }
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49
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50 inline bool VMRegImpl::is_FloatRegister() {
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51 return value() >= ConcreteRegisterImpl::max_gpr && value() < ConcreteRegisterImpl::max_fpr;
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52 }
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53
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54 inline bool VMRegImpl::is_XMMRegister() {
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55 return value() >= ConcreteRegisterImpl::max_fpr && value() < ConcreteRegisterImpl::max_xmm;
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56 }
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57
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58 inline Register VMRegImpl::as_Register() {
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59
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60 assert( is_Register(), "must be");
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61 // Yuk
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62 #ifdef AMD64
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63 return ::as_Register(value() >> 1);
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64 #else
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65 return ::as_Register(value());
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66 #endif // AMD64
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67 }
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68
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69 inline FloatRegister VMRegImpl::as_FloatRegister() {
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70 assert( is_FloatRegister() && is_even(value()), "must be" );
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71 // Yuk
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72 return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) >> 1);
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73 }
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74
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75 inline XMMRegister VMRegImpl::as_XMMRegister() {
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76 assert( is_XMMRegister() && is_even(value()), "must be" );
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77 // Yuk
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78 return ::as_XMMRegister((value() - ConcreteRegisterImpl::max_fpr) >> 3);
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79 }
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80
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81 inline bool VMRegImpl::is_concrete() {
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82 assert(is_reg(), "must be");
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83 #ifndef AMD64
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84 if (is_Register()) return true;
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85 #endif // AMD64
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86 return is_even(value());
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87 }
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88
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89 #endif // CPU_X86_VM_VMREG_X86_INLINE_HPP