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1 /*
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2 * Copyright 2003 Sun Microsystems, Inc. All Rights Reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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20 * CA 95054 USA or visit www.sun.com if you need additional information or
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21 * have any questions.
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22 *
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23 */
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24
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25 // Memory Access Ordering Model
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26 //
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27 // This interface is based on the JSR-133 Cookbook for Compiler Writers
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28 // and on the IA64 memory model. It is the dynamic equivalent of the
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29 // C/C++ volatile specifier. I.e., volatility restricts compile-time
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30 // memory access reordering in a way similar to what we want to occur
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31 // at runtime.
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32 //
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33 // In the following, the terms 'previous', 'subsequent', 'before',
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34 // 'after', 'preceeding' and 'succeeding' refer to program order. The
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35 // terms 'down' and 'below' refer to forward load or store motion
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36 // relative to program order, while 'up' and 'above' refer to backward
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37 // motion.
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38 //
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39 //
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40 // We define four primitive memory barrier operations.
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41 //
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42 // LoadLoad: Load1(s); LoadLoad; Load2
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43 //
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44 // Ensures that Load1 completes (obtains the value it loads from memory)
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45 // before Load2 and any subsequent load operations. Loads before Load1
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46 // may *not* float below Load2 and any subsequent load operations.
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47 //
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48 // StoreStore: Store1(s); StoreStore; Store2
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49 //
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50 // Ensures that Store1 completes (the effect on memory of Store1 is made
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51 // visible to other processors) before Store2 and any subsequent store
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52 // operations. Stores before Store1 may *not* float below Store2 and any
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53 // subsequent store operations.
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54 //
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55 // LoadStore: Load1(s); LoadStore; Store2
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56 //
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57 // Ensures that Load1 completes before Store2 and any subsequent store
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58 // operations. Loads before Load1 may *not* float below Store2 and any
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59 // subseqeuent store operations.
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60 //
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61 // StoreLoad: Store1(s); StoreLoad; Load2
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62 //
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63 // Ensures that Store1 completes before Load2 and any subsequent load
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64 // operations. Stores before Store1 may *not* float below Load2 and any
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65 // subseqeuent load operations.
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66 //
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67 //
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68 // We define two further operations, 'release' and 'acquire'. They are
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69 // mirror images of each other.
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70 //
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71 // Execution by a processor of release makes the effect of all memory
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72 // accesses issued by it previous to the release visible to all
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73 // processors *before* the release completes. The effect of subsequent
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74 // memory accesses issued by it *may* be made visible *before* the
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75 // release. I.e., subsequent memory accesses may float above the
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76 // release, but prior ones may not float below it.
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77 //
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78 // Execution by a processor of acquire makes the effect of all memory
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79 // accesses issued by it subsequent to the acquire visible to all
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80 // processors *after* the acquire completes. The effect of prior memory
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81 // accesses issued by it *may* be made visible *after* the acquire.
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82 // I.e., prior memory accesses may float below the acquire, but
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83 // subsequent ones may not float above it.
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84 //
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85 // Finally, we define a 'fence' operation, which conceptually is a
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86 // release combined with an acquire. In the real world these operations
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87 // require one or more machine instructions which can float above and
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88 // below the release or acquire, so we usually can't just issue the
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89 // release-acquire back-to-back. All machines we know of implement some
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90 // sort of memory fence instruction.
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91 //
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92 //
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93 // The standalone implementations of release and acquire need an associated
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94 // dummy volatile store or load respectively. To avoid redundant operations,
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95 // we can define the composite operators: 'release_store', 'store_fence' and
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96 // 'load_acquire'. Here's a summary of the machine instructions corresponding
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97 // to each operation.
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98 //
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99 // sparc RMO ia64 x86
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100 // ---------------------------------------------------------------------
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101 // fence membar #LoadStore | mf lock addl 0,(sp)
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102 // #StoreStore |
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103 // #LoadLoad |
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104 // #StoreLoad
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105 //
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106 // release membar #LoadStore | st.rel [sp]=r0 movl $0,<dummy>
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107 // #StoreStore
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108 // st %g0,[]
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109 //
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110 // acquire ld [%sp],%g0 ld.acq <r>=[sp] movl (sp),<r>
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111 // membar #LoadLoad |
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112 // #LoadStore
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113 //
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114 // release_store membar #LoadStore | st.rel <store>
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115 // #StoreStore
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116 // st
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117 //
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118 // store_fence st st lock xchg
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119 // fence mf
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120 //
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121 // load_acquire ld ld.acq <load>
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122 // membar #LoadLoad |
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123 // #LoadStore
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124 //
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125 // Using only release_store and load_acquire, we can implement the
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126 // following ordered sequences.
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127 //
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128 // 1. load, load == load_acquire, load
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129 // or load_acquire, load_acquire
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130 // 2. load, store == load, release_store
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131 // or load_acquire, store
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132 // or load_acquire, release_store
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133 // 3. store, store == store, release_store
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134 // or release_store, release_store
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135 //
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136 // These require no membar instructions for sparc-TSO and no extra
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137 // instructions for ia64.
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138 //
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139 // Ordering a load relative to preceding stores requires a store_fence,
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140 // which implies a membar #StoreLoad between the store and load under
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141 // sparc-TSO. A fence is required by ia64. On x86, we use locked xchg.
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142 //
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143 // 4. store, load == store_fence, load
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144 //
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145 // Use store_fence to make sure all stores done in an 'interesting'
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146 // region are made visible prior to both subsequent loads and stores.
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147 //
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148 // Conventional usage is to issue a load_acquire for ordered loads. Use
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149 // release_store for ordered stores when you care only that prior stores
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150 // are visible before the release_store, but don't care exactly when the
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151 // store associated with the release_store becomes visible. Use
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152 // release_store_fence to update values like the thread state, where we
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153 // don't want the current thread to continue until all our prior memory
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154 // accesses (including the new thread state) are visible to other threads.
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155 //
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156 //
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157 // C++ Volatility
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158 //
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159 // C++ guarantees ordering at operations termed 'sequence points' (defined
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160 // to be volatile accesses and calls to library I/O functions). 'Side
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161 // effects' (defined as volatile accesses, calls to library I/O functions
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162 // and object modification) previous to a sequence point must be visible
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163 // at that sequence point. See the C++ standard, section 1.9, titled
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164 // "Program Execution". This means that all barrier implementations,
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165 // including standalone loadload, storestore, loadstore, storeload, acquire
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166 // and release must include a sequence point, usually via a volatile memory
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167 // access. Other ways to guarantee a sequence point are, e.g., use of
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168 // indirect calls and linux's __asm__ volatile.
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169 //
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170 //
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171 // os::is_MP Considered Redundant
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172 //
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173 // Callers of this interface do not need to test os::is_MP() before
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174 // issuing an operation. The test is taken care of by the implementation
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175 // of the interface (depending on the vm version and platform, the test
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176 // may or may not be actually done by the implementation).
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177 //
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178 //
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179 // A Note on Memory Ordering and Cache Coherency
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180 //
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181 // Cache coherency and memory ordering are orthogonal concepts, though they
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182 // interact. E.g., all existing itanium machines are cache-coherent, but
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183 // the hardware can freely reorder loads wrt other loads unless it sees a
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184 // load-acquire instruction. All existing sparc machines are cache-coherent
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185 // and, unlike itanium, TSO guarantees that the hardware orders loads wrt
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186 // loads and stores, and stores wrt to each other.
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187 //
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188 // Consider the implementation of loadload. *If* your platform *isn't*
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189 // cache-coherent, then loadload must not only prevent hardware load
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190 // instruction reordering, but it must *also* ensure that subsequent
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191 // loads from addresses that could be written by other processors (i.e.,
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192 // that are broadcast by other processors) go all the way to the first
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193 // level of memory shared by those processors and the one issuing
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194 // the loadload.
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195 //
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196 // So if we have a MP that has, say, a per-processor D$ that doesn't see
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197 // writes by other processors, and has a shared E$ that does, the loadload
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198 // barrier would have to make sure that either
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199 //
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200 // 1. cache lines in the issuing processor's D$ that contained data from
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201 // addresses that could be written by other processors are invalidated, so
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202 // subsequent loads from those addresses go to the E$, (it could do this
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203 // by tagging such cache lines as 'shared', though how to tell the hardware
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204 // to do the tagging is an interesting problem), or
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205 //
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206 // 2. there never are such cache lines in the issuing processor's D$, which
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207 // means all references to shared data (however identified: see above)
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208 // bypass the D$ (i.e., are satisfied from the E$).
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209 //
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210 // If your machine doesn't have an E$, substitute 'main memory' for 'E$'.
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211 //
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212 // Either of these alternatives is a pain, so no current machine we know of
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213 // has incoherent caches.
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214 //
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215 // If loadload didn't have these properties, the store-release sequence for
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216 // publishing a shared data structure wouldn't work, because a processor
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217 // trying to read data newly published by another processor might go to
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218 // its own incoherent caches to satisfy the read instead of to the newly
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219 // written shared memory.
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220 //
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221 //
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222 // NOTE WELL!!
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223 //
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224 // A Note on MutexLocker and Friends
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225 //
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226 // See mutexLocker.hpp. We assume throughout the VM that MutexLocker's
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227 // and friends' constructors do a fence, a lock and an acquire *in that
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228 // order*. And that their destructors do a release and unlock, in *that*
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229 // order. If their implementations change such that these assumptions
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230 // are violated, a whole lot of code will break.
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231
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232 class OrderAccess : AllStatic {
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233 public:
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234 static void loadload();
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235 static void storestore();
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236 static void loadstore();
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237 static void storeload();
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238
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239 static void acquire();
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240 static void release();
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241 static void fence();
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242
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243 static jbyte load_acquire(volatile jbyte* p);
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244 static jshort load_acquire(volatile jshort* p);
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245 static jint load_acquire(volatile jint* p);
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246 static jlong load_acquire(volatile jlong* p);
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247 static jubyte load_acquire(volatile jubyte* p);
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248 static jushort load_acquire(volatile jushort* p);
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249 static juint load_acquire(volatile juint* p);
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250 static julong load_acquire(volatile julong* p);
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251 static jfloat load_acquire(volatile jfloat* p);
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252 static jdouble load_acquire(volatile jdouble* p);
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253
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254 static intptr_t load_ptr_acquire(volatile intptr_t* p);
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255 static void* load_ptr_acquire(volatile void* p);
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256 static void* load_ptr_acquire(const volatile void* p);
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257
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258 static void release_store(volatile jbyte* p, jbyte v);
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259 static void release_store(volatile jshort* p, jshort v);
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260 static void release_store(volatile jint* p, jint v);
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261 static void release_store(volatile jlong* p, jlong v);
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262 static void release_store(volatile jubyte* p, jubyte v);
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263 static void release_store(volatile jushort* p, jushort v);
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264 static void release_store(volatile juint* p, juint v);
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265 static void release_store(volatile julong* p, julong v);
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266 static void release_store(volatile jfloat* p, jfloat v);
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267 static void release_store(volatile jdouble* p, jdouble v);
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268
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269 static void release_store_ptr(volatile intptr_t* p, intptr_t v);
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270 static void release_store_ptr(volatile void* p, void* v);
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271
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272 static void store_fence(jbyte* p, jbyte v);
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273 static void store_fence(jshort* p, jshort v);
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274 static void store_fence(jint* p, jint v);
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275 static void store_fence(jlong* p, jlong v);
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276 static void store_fence(jubyte* p, jubyte v);
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277 static void store_fence(jushort* p, jushort v);
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278 static void store_fence(juint* p, juint v);
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279 static void store_fence(julong* p, julong v);
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280 static void store_fence(jfloat* p, jfloat v);
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281 static void store_fence(jdouble* p, jdouble v);
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282
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283 static void store_ptr_fence(intptr_t* p, intptr_t v);
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284 static void store_ptr_fence(void** p, void* v);
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285
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286 static void release_store_fence(volatile jbyte* p, jbyte v);
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287 static void release_store_fence(volatile jshort* p, jshort v);
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288 static void release_store_fence(volatile jint* p, jint v);
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289 static void release_store_fence(volatile jlong* p, jlong v);
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290 static void release_store_fence(volatile jubyte* p, jubyte v);
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291 static void release_store_fence(volatile jushort* p, jushort v);
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292 static void release_store_fence(volatile juint* p, juint v);
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293 static void release_store_fence(volatile julong* p, julong v);
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294 static void release_store_fence(volatile jfloat* p, jfloat v);
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295 static void release_store_fence(volatile jdouble* p, jdouble v);
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296
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297 static void release_store_ptr_fence(volatile intptr_t* p, intptr_t v);
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298 static void release_store_ptr_fence(volatile void* p, void* v);
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299
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300 // In order to force a memory access, implementations may
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301 // need a volatile externally visible dummy variable.
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302 static volatile intptr_t dummy;
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303 };
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