annotate src/os_cpu/linux_x86/vm/orderAccess_linux_x86.inline.hpp @ 250:6ca61c728c2d

6712835: Server compiler fails with assertion (loop_count < K,"infinite loop in PhaseIterGVN::transform") Reviewed-by: kvn
author never
date Fri, 25 Jul 2008 11:32:56 -0700
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children d0994e5bebce
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1 /*
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2 * Copyright 2003 Sun Microsystems, Inc. All Rights Reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
a61af66fc99e Initial load
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
a61af66fc99e Initial load
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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20 * CA 95054 USA or visit www.sun.com if you need additional information or
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21 * have any questions.
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22 *
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23 */
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24
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25 // Implementation of class OrderAccess.
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26
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27 inline void OrderAccess::loadload() { acquire(); }
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28 inline void OrderAccess::storestore() { release(); }
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29 inline void OrderAccess::loadstore() { acquire(); }
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30 inline void OrderAccess::storeload() { fence(); }
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31
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32 inline void OrderAccess::acquire() {
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33 volatile intptr_t dummy;
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34 #ifdef AMD64
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35 __asm__ volatile ("movq 0(%%rsp), %0" : "=r" (dummy) : : "memory");
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36 #else
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37 __asm__ volatile ("movl 0(%%esp),%0" : "=r" (dummy) : : "memory");
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38 #endif // AMD64
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39 }
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40
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41 inline void OrderAccess::release() {
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42 dummy = 0;
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43 }
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44
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45 inline void OrderAccess::fence() {
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46 if (os::is_MP()) {
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47 #ifdef AMD64
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48 __asm__ __volatile__ ("mfence":::"memory");
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49 #else
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50 __asm__ volatile ("lock; addl $0,0(%%esp)" : : : "cc", "memory");
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51 #endif // AMD64
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52 }
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53 }
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54
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55 inline jbyte OrderAccess::load_acquire(volatile jbyte* p) { return *p; }
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56 inline jshort OrderAccess::load_acquire(volatile jshort* p) { return *p; }
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57 inline jint OrderAccess::load_acquire(volatile jint* p) { return *p; }
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58 inline jlong OrderAccess::load_acquire(volatile jlong* p) { return *p; }
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59 inline jubyte OrderAccess::load_acquire(volatile jubyte* p) { return *p; }
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60 inline jushort OrderAccess::load_acquire(volatile jushort* p) { return *p; }
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61 inline juint OrderAccess::load_acquire(volatile juint* p) { return *p; }
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62 inline julong OrderAccess::load_acquire(volatile julong* p) { return *p; }
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63 inline jfloat OrderAccess::load_acquire(volatile jfloat* p) { return *p; }
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64 inline jdouble OrderAccess::load_acquire(volatile jdouble* p) { return *p; }
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65
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66 inline intptr_t OrderAccess::load_ptr_acquire(volatile intptr_t* p) { return *p; }
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67 inline void* OrderAccess::load_ptr_acquire(volatile void* p) { return *(void* volatile *)p; }
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68 inline void* OrderAccess::load_ptr_acquire(const volatile void* p) { return *(void* const volatile *)p; }
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69
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70 inline void OrderAccess::release_store(volatile jbyte* p, jbyte v) { *p = v; }
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71 inline void OrderAccess::release_store(volatile jshort* p, jshort v) { *p = v; }
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72 inline void OrderAccess::release_store(volatile jint* p, jint v) { *p = v; }
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73 inline void OrderAccess::release_store(volatile jlong* p, jlong v) { *p = v; }
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74 inline void OrderAccess::release_store(volatile jubyte* p, jubyte v) { *p = v; }
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75 inline void OrderAccess::release_store(volatile jushort* p, jushort v) { *p = v; }
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76 inline void OrderAccess::release_store(volatile juint* p, juint v) { *p = v; }
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77 inline void OrderAccess::release_store(volatile julong* p, julong v) { *p = v; }
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78 inline void OrderAccess::release_store(volatile jfloat* p, jfloat v) { *p = v; }
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79 inline void OrderAccess::release_store(volatile jdouble* p, jdouble v) { *p = v; }
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80
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81 inline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { *p = v; }
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82 inline void OrderAccess::release_store_ptr(volatile void* p, void* v) { *(void* volatile *)p = v; }
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83
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84 inline void OrderAccess::store_fence(jbyte* p, jbyte v) {
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85 __asm__ volatile ( "xchgb (%2),%0"
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86 : "=r" (v)
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87 : "0" (v), "r" (p)
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88 : "memory");
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89 }
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90 inline void OrderAccess::store_fence(jshort* p, jshort v) {
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91 __asm__ volatile ( "xchgw (%2),%0"
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92 : "=r" (v)
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93 : "0" (v), "r" (p)
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94 : "memory");
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95 }
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96 inline void OrderAccess::store_fence(jint* p, jint v) {
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97 __asm__ volatile ( "xchgl (%2),%0"
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98 : "=r" (v)
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99 : "0" (v), "r" (p)
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100 : "memory");
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101 }
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102
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103 inline void OrderAccess::store_fence(jlong* p, jlong v) {
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104 #ifdef AMD64
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105 __asm__ __volatile__ ("xchgq (%2), %0"
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106 : "=r" (v)
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107 : "0" (v), "r" (p)
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108 : "memory");
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109 #else
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110 *p = v; fence();
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111 #endif // AMD64
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112 }
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113
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114 // AMD64 copied the bodies for the the signed version. 32bit did this. As long as the
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115 // compiler does the inlining this is simpler.
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116 inline void OrderAccess::store_fence(jubyte* p, jubyte v) { store_fence((jbyte*)p, (jbyte)v); }
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117 inline void OrderAccess::store_fence(jushort* p, jushort v) { store_fence((jshort*)p, (jshort)v); }
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118 inline void OrderAccess::store_fence(juint* p, juint v) { store_fence((jint*)p, (jint)v); }
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119 inline void OrderAccess::store_fence(julong* p, julong v) { store_fence((jlong*)p, (jlong)v); }
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120 inline void OrderAccess::store_fence(jfloat* p, jfloat v) { *p = v; fence(); }
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121 inline void OrderAccess::store_fence(jdouble* p, jdouble v) { *p = v; fence(); }
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122
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123 inline void OrderAccess::store_ptr_fence(intptr_t* p, intptr_t v) {
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124 #ifdef AMD64
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125 __asm__ __volatile__ ("xchgq (%2), %0"
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126 : "=r" (v)
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127 : "0" (v), "r" (p)
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128 : "memory");
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129 #else
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130 store_fence((jint*)p, (jint)v);
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131 #endif // AMD64
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132 }
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133
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134 inline void OrderAccess::store_ptr_fence(void** p, void* v) {
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135 #ifdef AMD64
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136 __asm__ __volatile__ ("xchgq (%2), %0"
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137 : "=r" (v)
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138 : "0" (v), "r" (p)
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139 : "memory");
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140 #else
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141 store_fence((jint*)p, (jint)v);
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142 #endif // AMD64
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143 }
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144
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145 // Must duplicate definitions instead of calling store_fence because we don't want to cast away volatile.
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146 inline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) {
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147 __asm__ volatile ( "xchgb (%2),%0"
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148 : "=r" (v)
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149 : "0" (v), "r" (p)
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150 : "memory");
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151 }
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152 inline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) {
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153 __asm__ volatile ( "xchgw (%2),%0"
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154 : "=r" (v)
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155 : "0" (v), "r" (p)
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156 : "memory");
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157 }
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158 inline void OrderAccess::release_store_fence(volatile jint* p, jint v) {
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159 __asm__ volatile ( "xchgl (%2),%0"
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160 : "=r" (v)
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161 : "0" (v), "r" (p)
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162 : "memory");
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163 }
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164
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165 inline void OrderAccess::release_store_fence(volatile jlong* p, jlong v) {
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166 #ifdef AMD64
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167 __asm__ __volatile__ ( "xchgq (%2), %0"
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168 : "=r" (v)
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169 : "0" (v), "r" (p)
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170 : "memory");
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171 #else
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172 *p = v; fence();
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173 #endif // AMD64
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174 }
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175
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176 inline void OrderAccess::release_store_fence(volatile jubyte* p, jubyte v) { release_store_fence((volatile jbyte*)p, (jbyte)v); }
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177 inline void OrderAccess::release_store_fence(volatile jushort* p, jushort v) { release_store_fence((volatile jshort*)p, (jshort)v); }
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178 inline void OrderAccess::release_store_fence(volatile juint* p, juint v) { release_store_fence((volatile jint*)p, (jint)v); }
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179 inline void OrderAccess::release_store_fence(volatile julong* p, julong v) { release_store_fence((volatile jlong*)p, (jlong)v); }
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180
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181 inline void OrderAccess::release_store_fence(volatile jfloat* p, jfloat v) { *p = v; fence(); }
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182 inline void OrderAccess::release_store_fence(volatile jdouble* p, jdouble v) { *p = v; fence(); }
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183
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184 inline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) {
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185 #ifdef AMD64
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186 __asm__ __volatile__ ( "xchgq (%2), %0"
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187 : "=r" (v)
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188 : "0" (v), "r" (p)
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189 : "memory");
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190 #else
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191 release_store_fence((volatile jint*)p, (jint)v);
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192 #endif // AMD64
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193 }
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194 inline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) {
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195 #ifdef AMD64
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196 __asm__ __volatile__ ( "xchgq (%2), %0"
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197 : "=r" (v)
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198 : "0" (v), "r" (p)
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199 : "memory");
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200 #else
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201 release_store_fence((volatile jint*)p, (jint)v);
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202 #endif // AMD64
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203 }