Mercurial > hg > truffle
annotate src/share/vm/c1/c1_FrameMap.hpp @ 1994:6cd6d394f280
7001033: assert(gch->gc_cause() == GCCause::_scavenge_alot || !gch->incremental_collection_failed())
7002546: regression on SpecJbb2005 on 7b118 comparing to 7b117 on small heaps
Summary: Relaxed assertion checking related to incremental_collection_failed flag to allow for ExplicitGCInvokesConcurrent behaviour where we do not want a failing scavenge to bail to a stop-world collection. Parameterized incremental_collection_will_fail() so we can selectively use, or not use, as appropriate, the statistical prediction at specific use sites. This essentially reverts the scavenge bail-out logic to what it was prior to some recent changes that had inadvertently started using the statistical prediction which can be noisy in the presence of bursty loads. Added some associated verbose non-product debugging messages.
Reviewed-by: johnc, tonyp
| author | ysr |
|---|---|
| date | Tue, 07 Dec 2010 21:55:53 -0800 |
| parents | f95d63e2154a |
| children | ac637b7220d1 |
| rev | line source |
|---|---|
| 0 | 1 /* |
| 1579 | 2 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #ifndef SHARE_VM_C1_C1_FRAMEMAP_HPP |
| 26 #define SHARE_VM_C1_C1_FRAMEMAP_HPP | |
| 27 | |
| 28 #include "asm/assembler.hpp" | |
| 29 #include "c1/c1_Defs.hpp" | |
| 30 #include "c1/c1_LIR.hpp" | |
| 31 #include "code/vmreg.hpp" | |
| 32 #include "memory/allocation.hpp" | |
| 33 #include "runtime/frame.hpp" | |
| 34 #include "runtime/synchronizer.hpp" | |
| 35 #include "utilities/globalDefinitions.hpp" | |
| 36 | |
| 0 | 37 class ciMethod; |
| 38 class CallingConvention; | |
| 39 class BasicTypeArray; | |
| 40 class BasicTypeList; | |
| 41 | |
| 42 //-------------------------------------------------------- | |
| 43 // FrameMap | |
| 44 //-------------------------------------------------------- | |
| 45 | |
| 46 // This class is responsible of mapping items (locals, monitors, spill | |
| 47 // slots and registers to their frame location | |
| 48 // | |
| 49 // The monitors are specified by a consecutive index, although each monitor entry | |
| 50 // occupies two words. The monitor_index is 0.._num_monitors | |
| 51 // The spill index is similar to local index; it is in range 0..(open) | |
| 52 // | |
| 53 // The CPU registers are mapped using a fixed table; register with number 0 | |
| 54 // is the most used one. | |
| 55 | |
| 56 | |
| 57 // stack grow direction --> SP | |
| 58 // +----------+---+----------+-------+------------------------+-----+ | |
| 59 // |arguments | x | monitors | spill | reserved argument area | ABI | | |
| 60 // +----------+---+----------+-------+------------------------+-----+ | |
| 61 // | |
| 62 // x = ABI area (SPARC) or return adress and link (i486) | |
| 63 // ABI = ABI area (SPARC) or nothing (i486) | |
| 64 | |
| 65 | |
| 66 class LIR_OprDesc; | |
| 67 typedef LIR_OprDesc* LIR_Opr; | |
| 68 | |
| 69 | |
| 70 class FrameMap : public CompilationResourceObj { | |
| 71 public: | |
| 72 enum { | |
| 73 nof_cpu_regs = pd_nof_cpu_regs_frame_map, | |
| 74 nof_fpu_regs = pd_nof_fpu_regs_frame_map, | |
| 75 | |
| 76 nof_cpu_regs_reg_alloc = pd_nof_cpu_regs_reg_alloc, | |
| 77 nof_fpu_regs_reg_alloc = pd_nof_fpu_regs_reg_alloc, | |
| 78 | |
| 79 nof_caller_save_cpu_regs = pd_nof_caller_save_cpu_regs_frame_map, | |
| 80 nof_caller_save_fpu_regs = pd_nof_caller_save_fpu_regs_frame_map, | |
| 81 | |
| 82 spill_slot_size_in_bytes = 4 | |
| 83 }; | |
| 84 | |
| 1972 | 85 #ifdef TARGET_ARCH_x86 |
| 86 # include "c1_FrameMap_x86.hpp" | |
| 87 #endif | |
| 88 #ifdef TARGET_ARCH_sparc | |
| 89 # include "c1_FrameMap_sparc.hpp" | |
| 90 #endif | |
| 91 | |
| 0 | 92 |
| 93 friend class LIR_OprDesc; | |
| 94 | |
| 95 private: | |
| 96 static bool _init_done; | |
| 97 static Register _cpu_rnr2reg [nof_cpu_regs]; | |
| 98 static int _cpu_reg2rnr [nof_cpu_regs]; | |
| 99 | |
| 100 static LIR_Opr _caller_save_cpu_regs [nof_caller_save_cpu_regs]; | |
| 101 static LIR_Opr _caller_save_fpu_regs [nof_caller_save_fpu_regs]; | |
| 102 | |
| 103 int _framesize; | |
| 104 int _argcount; | |
| 105 int _num_monitors; | |
| 106 int _num_spills; | |
| 107 int _reserved_argument_area_size; | |
| 108 int _oop_map_arg_count; | |
| 109 | |
| 110 CallingConvention* _incoming_arguments; | |
| 111 intArray* _argument_locations; | |
| 112 | |
| 113 void check_spill_index (int spill_index) const { assert(spill_index >= 0, "bad index"); } | |
| 114 void check_monitor_index (int monitor_index) const { assert(monitor_index >= 0 && | |
| 115 monitor_index < _num_monitors, "bad index"); } | |
| 116 | |
| 117 static Register cpu_rnr2reg (int rnr) { | |
| 118 assert(_init_done, "tables not initialized"); | |
| 119 debug_only(cpu_range_check(rnr);) | |
| 120 return _cpu_rnr2reg[rnr]; | |
| 121 } | |
| 122 | |
| 123 static int cpu_reg2rnr (Register reg) { | |
| 124 assert(_init_done, "tables not initialized"); | |
| 125 debug_only(cpu_range_check(reg->encoding());) | |
| 126 return _cpu_reg2rnr[reg->encoding()]; | |
| 127 } | |
| 128 | |
| 129 static void map_register(int rnr, Register reg) { | |
| 130 debug_only(cpu_range_check(rnr);) | |
| 131 debug_only(cpu_range_check(reg->encoding());) | |
| 132 _cpu_rnr2reg[rnr] = reg; | |
| 133 _cpu_reg2rnr[reg->encoding()] = rnr; | |
| 134 } | |
| 135 | |
| 136 void update_reserved_argument_area_size (int size) { | |
| 137 assert(size >= 0, "check"); | |
| 138 _reserved_argument_area_size = MAX2(_reserved_argument_area_size, size); | |
| 139 } | |
| 140 | |
| 141 protected: | |
| 142 #ifndef PRODUCT | |
| 143 static void cpu_range_check (int rnr) { assert(0 <= rnr && rnr < nof_cpu_regs, "cpu register number is too big"); } | |
| 144 static void fpu_range_check (int rnr) { assert(0 <= rnr && rnr < nof_fpu_regs, "fpu register number is too big"); } | |
| 145 #endif | |
| 146 | |
| 147 | |
| 148 ByteSize sp_offset_for_monitor_base(const int idx) const; | |
| 149 | |
| 150 Address make_new_address(ByteSize sp_offset) const; | |
| 151 | |
| 152 ByteSize sp_offset_for_slot(const int idx) const; | |
| 153 ByteSize sp_offset_for_double_slot(const int idx) const; | |
| 154 ByteSize sp_offset_for_spill(const int idx) const; | |
| 155 ByteSize sp_offset_for_monitor_lock(int monitor_index) const; | |
| 156 ByteSize sp_offset_for_monitor_object(int monitor_index) const; | |
| 157 | |
| 158 VMReg sp_offset2vmreg(ByteSize offset) const; | |
| 159 | |
| 160 // platform dependent hook used to check that frame is properly | |
| 161 // addressable on the platform. Used by sparc to verify that all | |
| 162 // stack addresses are expressable in a simm13. | |
| 163 bool validate_frame(); | |
| 164 | |
| 165 static LIR_Opr map_to_opr(BasicType type, VMRegPair* reg, bool incoming); | |
| 166 | |
| 167 public: | |
| 168 // Opr representing the stack_pointer on this platform | |
| 169 static LIR_Opr stack_pointer(); | |
| 170 | |
| 1564 | 171 // JSR 292 |
| 172 static LIR_Opr method_handle_invoke_SP_save_opr(); | |
| 173 | |
| 0 | 174 static BasicTypeArray* signature_type_array_for(const ciMethod* method); |
| 175 | |
| 176 // for outgoing calls, these also update the reserved area to | |
| 177 // include space for arguments and any ABI area. | |
| 178 CallingConvention* c_calling_convention (const BasicTypeArray* signature); | |
| 179 CallingConvention* java_calling_convention (const BasicTypeArray* signature, bool outgoing); | |
| 180 | |
| 181 // deopt support | |
| 182 ByteSize sp_offset_for_orig_pc() { return sp_offset_for_monitor_base(_num_monitors); } | |
| 183 | |
| 184 static LIR_Opr as_opr(Register r) { | |
| 185 return LIR_OprFact::single_cpu(cpu_reg2rnr(r)); | |
| 186 } | |
| 187 static LIR_Opr as_oop_opr(Register r) { | |
| 188 return LIR_OprFact::single_cpu_oop(cpu_reg2rnr(r)); | |
| 189 } | |
| 190 | |
| 191 FrameMap(ciMethod* method, int monitors, int reserved_argument_area_size); | |
| 192 bool finalize_frame(int nof_slots); | |
| 193 | |
| 194 int reserved_argument_area_size () const { return _reserved_argument_area_size; } | |
| 195 int framesize () const { assert(_framesize != -1, "hasn't been calculated"); return _framesize; } | |
| 196 ByteSize framesize_in_bytes () const { return in_ByteSize(framesize() * 4); } | |
| 197 int num_monitors () const { return _num_monitors; } | |
| 198 int num_spills () const { assert(_num_spills >= 0, "not set"); return _num_spills; } | |
| 199 int argcount () const { assert(_argcount >= 0, "not set"); return _argcount; } | |
| 200 | |
| 201 int oop_map_arg_count() const { return _oop_map_arg_count; } | |
| 202 | |
| 203 CallingConvention* incoming_arguments() const { return _incoming_arguments; } | |
| 204 | |
| 205 // convenience routines | |
| 206 Address address_for_slot(int index, int sp_adjust = 0) const { | |
| 207 return make_new_address(sp_offset_for_slot(index) + in_ByteSize(sp_adjust)); | |
| 208 } | |
| 209 Address address_for_double_slot(int index, int sp_adjust = 0) const { | |
| 210 return make_new_address(sp_offset_for_double_slot(index) + in_ByteSize(sp_adjust)); | |
| 211 } | |
| 212 Address address_for_monitor_lock(int monitor_index) const { | |
| 213 return make_new_address(sp_offset_for_monitor_lock(monitor_index)); | |
| 214 } | |
| 215 Address address_for_monitor_object(int monitor_index) const { | |
| 216 return make_new_address(sp_offset_for_monitor_object(monitor_index)); | |
| 217 } | |
| 218 | |
| 219 void print_frame_layout() const; | |
| 220 | |
| 221 // Creates Location describing desired slot and returns it via pointer | |
| 222 // to Location object. Returns true if the stack frame offset was legal | |
| 223 // (as defined by Location::legal_offset_in_bytes()), false otherwise. | |
| 224 // Do not use the returned location if this returns false. | |
| 225 bool location_for_sp_offset(ByteSize byte_offset_from_sp, | |
| 226 Location::Type loc_type, Location* loc) const; | |
| 227 | |
| 228 bool location_for_monitor_lock (int monitor_index, Location* loc) const { | |
| 229 return location_for_sp_offset(sp_offset_for_monitor_lock(monitor_index), Location::normal, loc); | |
| 230 } | |
| 231 bool location_for_monitor_object(int monitor_index, Location* loc) const { | |
| 232 return location_for_sp_offset(sp_offset_for_monitor_object(monitor_index), Location::oop, loc); | |
| 233 } | |
| 234 bool locations_for_slot (int index, Location::Type loc_type, | |
| 235 Location* loc, Location* second = NULL) const; | |
| 236 | |
| 237 VMReg slot_regname(int index) const { | |
| 238 return sp_offset2vmreg(sp_offset_for_slot(index)); | |
| 239 } | |
| 240 VMReg monitor_object_regname(int monitor_index) const { | |
| 241 return sp_offset2vmreg(sp_offset_for_monitor_object(monitor_index)); | |
| 242 } | |
| 243 VMReg regname(LIR_Opr opr) const; | |
| 244 | |
| 245 static LIR_Opr caller_save_cpu_reg_at(int i) { | |
| 246 assert(i >= 0 && i < nof_caller_save_cpu_regs, "out of bounds"); | |
| 247 return _caller_save_cpu_regs[i]; | |
| 248 } | |
| 249 | |
| 250 static LIR_Opr caller_save_fpu_reg_at(int i) { | |
| 251 assert(i >= 0 && i < nof_caller_save_fpu_regs, "out of bounds"); | |
| 252 return _caller_save_fpu_regs[i]; | |
| 253 } | |
| 254 | |
| 1584 | 255 static void initialize(); |
| 0 | 256 }; |
| 257 | |
| 258 // CallingConvention | |
| 259 //-------------------------------------------------------- | |
| 260 | |
| 261 class CallingConvention: public ResourceObj { | |
| 262 private: | |
| 263 LIR_OprList* _args; | |
| 264 int _reserved_stack_slots; | |
| 265 | |
| 266 public: | |
| 267 CallingConvention (LIR_OprList* args, int reserved_stack_slots) | |
| 268 : _args(args) | |
| 269 , _reserved_stack_slots(reserved_stack_slots) {} | |
| 270 | |
| 271 LIR_OprList* args() { return _args; } | |
| 272 | |
| 273 LIR_Opr at(int i) const { return _args->at(i); } | |
| 274 int length() const { return _args->length(); } | |
| 275 | |
| 276 // Indicates number of real frame slots used by arguments passed on stack. | |
| 277 int reserved_stack_slots() const { return _reserved_stack_slots; } | |
| 278 | |
| 279 #ifndef PRODUCT | |
| 280 void print () const { | |
| 281 for (int i = 0; i < length(); i++) { | |
| 282 at(i)->print(); | |
| 283 } | |
| 284 } | |
| 285 #endif // PRODUCT | |
| 286 }; | |
| 1972 | 287 |
| 288 #endif // SHARE_VM_C1_C1_FRAMEMAP_HPP |