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1 /*
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2 * Copyright 1997-2007 Sun Microsystems, Inc. All Rights Reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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20 * CA 95054 USA or visit www.sun.com if you need additional information or
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21 * have any questions.
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22 *
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23 */
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24
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25 class Compile;
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26 class Node;
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27 class MachNode;
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28 class MachTypeNode;
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29 class MachOper;
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30
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31 //---------------------------Matcher-------------------------------------------
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32 class Matcher : public PhaseTransform {
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33 friend class VMStructs;
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34 // Private arena of State objects
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35 ResourceArea _states_arena;
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36
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37 VectorSet _visited; // Visit bits
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38
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39 // Used to control the Label pass
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40 VectorSet _shared; // Shared Ideal Node
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41 VectorSet _dontcare; // Nothing the matcher cares about
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42
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43 // Private methods which perform the actual matching and reduction
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44 // Walks the label tree, generating machine nodes
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45 MachNode *ReduceInst( State *s, int rule, Node *&mem);
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46 void ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach);
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47 uint ReduceInst_Interior(State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds);
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48 void ReduceOper( State *s, int newrule, Node *&mem, MachNode *mach );
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49
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50 // If this node already matched using "rule", return the MachNode for it.
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51 MachNode* find_shared_constant(Node* con, uint rule);
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52
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53 // Convert a dense opcode number to an expanded rule number
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54 const int *_reduceOp;
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55 const int *_leftOp;
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56 const int *_rightOp;
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57
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58 // Map dense opcode number to info on when rule is swallowed constant.
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59 const bool *_swallowed;
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60
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61 // Map dense rule number to determine if this is an instruction chain rule
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62 const uint _begin_inst_chain_rule;
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63 const uint _end_inst_chain_rule;
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64
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65 // We want to clone constants and possible CmpI-variants.
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66 // If we do not clone CmpI, then we can have many instances of
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67 // condition codes alive at once. This is OK on some chips and
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68 // bad on others. Hence the machine-dependent table lookup.
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69 const char *_must_clone;
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70
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71 // Find shared Nodes, or Nodes that otherwise are Matcher roots
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72 void find_shared( Node *n );
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73
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74 // Debug and profile information for nodes in old space:
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75 GrowableArray<Node_Notes*>* _old_node_note_array;
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76
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77 // Node labeling iterator for instruction selection
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78 Node *Label_Root( const Node *n, State *svec, Node *control, const Node *mem );
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79
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80 Node *transform( Node *dummy );
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81
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82 Node_List &_proj_list; // For Machine nodes killing many values
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83
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84 Node_Array _shared_constants;
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85
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86 debug_only(Node_Array _old2new_map;) // Map roots of ideal-trees to machine-roots
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87
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88 // Accessors for the inherited field PhaseTransform::_nodes:
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89 void grow_new_node_array(uint idx_limit) {
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90 _nodes.map(idx_limit-1, NULL);
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91 }
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92 bool has_new_node(const Node* n) const {
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93 return _nodes.at(n->_idx) != NULL;
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94 }
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95 Node* new_node(const Node* n) const {
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96 assert(has_new_node(n), "set before get");
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97 return _nodes.at(n->_idx);
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98 }
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99 void set_new_node(const Node* n, Node *nn) {
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100 assert(!has_new_node(n), "set only once");
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101 _nodes.map(n->_idx, nn);
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102 }
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103
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104 #ifdef ASSERT
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105 // Make sure only new nodes are reachable from this node
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106 void verify_new_nodes_only(Node* root);
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107 #endif
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108
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109 public:
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110 int LabelRootDepth;
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111 static const int base2reg[]; // Map Types to machine register types
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112 // Convert ideal machine register to a register mask for spill-loads
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113 static const RegMask *idealreg2regmask[];
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114 RegMask *idealreg2spillmask[_last_machine_leaf];
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115 RegMask *idealreg2debugmask[_last_machine_leaf];
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116 void init_spill_mask( Node *ret );
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117 // Convert machine register number to register mask
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118 static uint mreg2regmask_max;
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119 static RegMask mreg2regmask[];
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120 static RegMask STACK_ONLY_mask;
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121
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122 bool is_shared( Node *n ) { return _shared.test(n->_idx) != 0; }
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123 void set_shared( Node *n ) { _shared.set(n->_idx); }
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124 bool is_visited( Node *n ) { return _visited.test(n->_idx) != 0; }
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125 void set_visited( Node *n ) { _visited.set(n->_idx); }
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126 bool is_dontcare( Node *n ) { return _dontcare.test(n->_idx) != 0; }
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127 void set_dontcare( Node *n ) { _dontcare.set(n->_idx); }
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128
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129 // Mode bit to tell DFA and expand rules whether we are running after
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130 // (or during) register selection. Usually, the matcher runs before,
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131 // but it will also get called to generate post-allocation spill code.
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132 // In this situation, it is a deadly error to attempt to allocate more
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133 // temporary registers.
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134 bool _allocation_started;
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135
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136 // Machine register names
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137 static const char *regName[];
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138 // Machine register encodings
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139 static const unsigned char _regEncode[];
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140 // Machine Node names
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141 const char **_ruleName;
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142 // Rules that are cheaper to rematerialize than to spill
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143 static const uint _begin_rematerialize;
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144 static const uint _end_rematerialize;
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145
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146 // An array of chars, from 0 to _last_Mach_Reg.
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147 // No Save = 'N' (for register windows)
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148 // Save on Entry = 'E'
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149 // Save on Call = 'C'
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150 // Always Save = 'A' (same as SOE + SOC)
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151 const char *_register_save_policy;
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152 const char *_c_reg_save_policy;
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153 // Convert a machine register to a machine register type, so-as to
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154 // properly match spill code.
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155 const int *_register_save_type;
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156 // Maps from machine register to boolean; true if machine register can
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157 // be holding a call argument in some signature.
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158 static bool can_be_java_arg( int reg );
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159 // Maps from machine register to boolean; true if machine register holds
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160 // a spillable argument.
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161 static bool is_spillable_arg( int reg );
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162
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163 // List of IfFalse or IfTrue Nodes that indicate a taken null test.
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164 // List is valid in the post-matching space.
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165 Node_List _null_check_tests;
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166 void collect_null_checks( Node *proj );
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167 void validate_null_checks( );
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168
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169 Matcher( Node_List &proj_list );
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170
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171 // Select instructions for entire method
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172 void match( );
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173 // Helper for match
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174 OptoReg::Name warp_incoming_stk_arg( VMReg reg );
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175
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176 // Transform, then walk. Does implicit DCE while walking.
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177 // Name changed from "transform" to avoid it being virtual.
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178 Node *xform( Node *old_space_node, int Nodes );
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179
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180 // Match a single Ideal Node - turn it into a 1-Node tree; Label & Reduce.
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181 MachNode *match_tree( const Node *n );
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182 MachNode *match_sfpt( SafePointNode *sfpt );
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183 // Helper for match_sfpt
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184 OptoReg::Name warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call );
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185
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186 // Initialize first stack mask and related masks.
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187 void init_first_stack_mask();
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188
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189 // If we should save-on-entry this register
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190 bool is_save_on_entry( int reg );
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191
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192 // Fixup the save-on-entry registers
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193 void Fixup_Save_On_Entry( );
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194
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195 // --- Frame handling ---
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196
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197 // Register number of the stack slot corresponding to the incoming SP.
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198 // Per the Big Picture in the AD file, it is:
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199 // SharedInfo::stack0 + locks + in_preserve_stack_slots + pad2.
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200 OptoReg::Name _old_SP;
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201
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202 // Register number of the stack slot corresponding to the highest incoming
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203 // argument on the stack. Per the Big Picture in the AD file, it is:
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204 // _old_SP + out_preserve_stack_slots + incoming argument size.
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205 OptoReg::Name _in_arg_limit;
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206
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207 // Register number of the stack slot corresponding to the new SP.
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208 // Per the Big Picture in the AD file, it is:
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209 // _in_arg_limit + pad0
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210 OptoReg::Name _new_SP;
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211
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212 // Register number of the stack slot corresponding to the highest outgoing
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213 // argument on the stack. Per the Big Picture in the AD file, it is:
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214 // _new_SP + max outgoing arguments of all calls
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215 OptoReg::Name _out_arg_limit;
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216
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217 OptoRegPair *_parm_regs; // Array of machine registers per argument
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218 RegMask *_calling_convention_mask; // Array of RegMasks per argument
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219
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220 // Does matcher support this ideal node?
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221 static const bool has_match_rule(int opcode);
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222 static const bool _hasMatchRule[_last_opcode];
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223
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224 // Used to determine if we have fast l2f conversion
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225 // USII has it, USIII doesn't
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226 static const bool convL2FSupported(void);
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227
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228 // Vector width in bytes
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229 static const uint vector_width_in_bytes(void);
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230
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231 // Vector ideal reg
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232 static const uint vector_ideal_reg(void);
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233
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234 // Used to determine a "low complexity" 64-bit constant. (Zero is simple.)
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235 // The standard of comparison is one (StoreL ConL) vs. two (StoreI ConI).
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236 // Depends on the details of 64-bit constant generation on the CPU.
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237 static const bool isSimpleConstant64(jlong con);
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238
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239 // These calls are all generated by the ADLC
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240
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241 // TRUE - grows up, FALSE - grows down (Intel)
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242 virtual bool stack_direction() const;
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243
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244 // Java-Java calling convention
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245 // (what you use when Java calls Java)
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246
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247 // Alignment of stack in bytes, standard Intel word alignment is 4.
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248 // Sparc probably wants at least double-word (8).
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249 static uint stack_alignment_in_bytes();
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250 // Alignment of stack, measured in stack slots.
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251 // The size of stack slots is defined by VMRegImpl::stack_slot_size.
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252 static uint stack_alignment_in_slots() {
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253 return stack_alignment_in_bytes() / (VMRegImpl::stack_slot_size);
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254 }
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255
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256 // Array mapping arguments to registers. Argument 0 is usually the 'this'
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257 // pointer. Registers can include stack-slots and regular registers.
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258 static void calling_convention( BasicType *, VMRegPair *, uint len, bool is_outgoing );
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259
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260 // Convert a sig into a calling convention register layout
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261 // and find interesting things about it.
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262 static OptoReg::Name find_receiver( bool is_outgoing );
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263 // Return address register. On Intel it is a stack-slot. On PowerPC
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264 // it is the Link register. On Sparc it is r31?
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265 virtual OptoReg::Name return_addr() const;
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266 RegMask _return_addr_mask;
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267 // Return value register. On Intel it is EAX. On Sparc i0/o0.
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268 static OptoRegPair return_value(int ideal_reg, bool is_outgoing);
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269 static OptoRegPair c_return_value(int ideal_reg, bool is_outgoing);
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270 RegMask _return_value_mask;
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271 // Inline Cache Register
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272 static OptoReg::Name inline_cache_reg();
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273 static const RegMask &inline_cache_reg_mask();
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274 static int inline_cache_reg_encode();
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275
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276 // Register for DIVI projection of divmodI
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277 static RegMask divI_proj_mask();
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278 // Register for MODI projection of divmodI
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279 static RegMask modI_proj_mask();
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280
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281 // Register for DIVL projection of divmodL
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282 static RegMask divL_proj_mask();
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283 // Register for MODL projection of divmodL
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284 static RegMask modL_proj_mask();
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285
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286 // Java-Interpreter calling convention
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287 // (what you use when calling between compiled-Java and Interpreted-Java
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288
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289 // Number of callee-save + always-save registers
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290 // Ignores frame pointer and "special" registers
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291 static int number_of_saved_registers();
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292
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293 // The Method-klass-holder may be passed in the inline_cache_reg
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294 // and then expanded into the inline_cache_reg and a method_oop register
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295
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296 static OptoReg::Name interpreter_method_oop_reg();
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297 static const RegMask &interpreter_method_oop_reg_mask();
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298 static int interpreter_method_oop_reg_encode();
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299
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300 static OptoReg::Name compiler_method_oop_reg();
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301 static const RegMask &compiler_method_oop_reg_mask();
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302 static int compiler_method_oop_reg_encode();
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303
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304 // Interpreter's Frame Pointer Register
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305 static OptoReg::Name interpreter_frame_pointer_reg();
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306 static const RegMask &interpreter_frame_pointer_reg_mask();
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307
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308 // Java-Native calling convention
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309 // (what you use when intercalling between Java and C++ code)
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310
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311 // Array mapping arguments to registers. Argument 0 is usually the 'this'
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312 // pointer. Registers can include stack-slots and regular registers.
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313 static void c_calling_convention( BasicType*, VMRegPair *, uint );
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314 // Frame pointer. The frame pointer is kept at the base of the stack
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315 // and so is probably the stack pointer for most machines. On Intel
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316 // it is ESP. On the PowerPC it is R1. On Sparc it is SP.
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317 OptoReg::Name c_frame_pointer() const;
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318 static RegMask c_frame_ptr_mask;
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319
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320 // !!!!! Special stuff for building ScopeDescs
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321 virtual int regnum_to_fpu_offset(int regnum);
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322
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323 // Is this branch offset small enough to be addressed by a short branch?
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324 bool is_short_branch_offset(int offset);
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325
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326 // Optional scaling for the parameter to the ClearArray/CopyArray node.
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327 static const bool init_array_count_is_in_bytes;
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328
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329 // Threshold small size (in bytes) for a ClearArray/CopyArray node.
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330 // Anything this size or smaller may get converted to discrete scalar stores.
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331 static const int init_array_short_size;
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332
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333 // Should the Matcher clone shifts on addressing modes, expecting them to
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334 // be subsumed into complex addressing expressions or compute them into
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335 // registers? True for Intel but false for most RISCs
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336 static const bool clone_shift_expressions;
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337
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338 // Is it better to copy float constants, or load them directly from memory?
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339 // Intel can load a float constant from a direct address, requiring no
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340 // extra registers. Most RISCs will have to materialize an address into a
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341 // register first, so they may as well materialize the constant immediately.
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342 static const bool rematerialize_float_constants;
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343
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344 // If CPU can load and store mis-aligned doubles directly then no fixup is
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345 // needed. Else we split the double into 2 integer pieces and move it
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346 // piece-by-piece. Only happens when passing doubles into C code or when
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347 // calling i2c adapters as the Java calling convention forces doubles to be
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348 // aligned.
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349 static const bool misaligned_doubles_ok;
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350
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351 // Perform a platform dependent implicit null fixup. This is needed
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352 // on windows95 to take care of some unusual register constraints.
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353 void pd_implicit_null_fixup(MachNode *load, uint idx);
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354
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355 // Advertise here if the CPU requires explicit rounding operations
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356 // to implement the UseStrictFP mode.
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357 static const bool strict_fp_requires_explicit_rounding;
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358
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359 // Do floats take an entire double register or just half?
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360 static const bool float_in_double;
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361 // Do ints take an entire long register or just half?
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362 static const bool int_in_long;
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363
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364 // This routine is run whenever a graph fails to match.
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365 // If it returns, the compiler should bailout to interpreter without error.
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366 // In non-product mode, SoftMatchFailure is false to detect non-canonical
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367 // graphs. Print a message and exit.
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368 static void soft_match_failure() {
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369 if( SoftMatchFailure ) return;
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370 else { fatal("SoftMatchFailure is not allowed except in product"); }
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371 }
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372
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373 // Used by the DFA in dfa_sparc.cpp. Check for a prior FastLock
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374 // acting as an Acquire and thus we don't need an Acquire here. We
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375 // retain the Node to act as a compiler ordering barrier.
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376 static bool prior_fast_lock( const Node *acq );
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377
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378 // Used by the DFA in dfa_sparc.cpp. Check for a following
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379 // FastUnLock acting as a Release and thus we don't need a Release
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380 // here. We retain the Node to act as a compiler ordering barrier.
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381 static bool post_fast_unlock( const Node *rel );
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382
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383 // Check for a following volatile memory barrier without an
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384 // intervening load and thus we don't need a barrier here. We
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385 // retain the Node to act as a compiler ordering barrier.
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386 static bool post_store_load_barrier(const Node* mb);
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387
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388
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389 #ifdef ASSERT
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390 void dump_old2new_map(); // machine-independent to machine-dependent
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391 #endif
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392 };
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