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1 //
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2 // Copyright 1999-2006 Sun Microsystems, Inc. All Rights Reserved.
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3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 //
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5 // This code is free software; you can redistribute it and/or modify it
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6 // under the terms of the GNU General Public License version 2 only, as
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7 // published by the Free Software Foundation.
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8 //
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9 // This code is distributed in the hope that it will be useful, but WITHOUT
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10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 // version 2 for more details (a copy is included in the LICENSE file that
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13 // accompanied this code).
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14 //
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15 // You should have received a copy of the GNU General Public License version
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16 // 2 along with this work; if not, write to the Free Software Foundation,
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17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 //
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19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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20 // CA 95054 USA or visit www.sun.com if you need additional information or
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21 // have any questions.
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22 //
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23 //
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24
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25 // X86 Win32 Architecture Description File
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26
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27 //----------OS-DEPENDENT ENCODING BLOCK-----------------------------------------------------
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28 // This block specifies the encoding classes used by the compiler to output
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29 // byte streams. Encoding classes generate functions which are called by
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30 // Machine Instruction Nodes in order to generate the bit encoding of the
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31 // instruction. Operands specify their base encoding interface with the
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32 // interface keyword. There are currently supported four interfaces,
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33 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
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34 // operand to generate a function which returns its register number when
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35 // queried. CONST_INTER causes an operand to generate a function which
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36 // returns the value of the constant when queried. MEMORY_INTER causes an
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37 // operand to generate four functions which return the Base Register, the
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38 // Index Register, the Scale Value, and the Offset Value of the operand when
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39 // queried. COND_INTER causes an operand to generate six functions which
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40 // return the encoding code (ie - encoding bits for the instruction)
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41 // associated with each basic boolean condition for a conditional instruction.
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42 // Instructions specify two basic values for encoding. They use the
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43 // ins_encode keyword to specify their encoding class (which must be one of
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44 // the class names specified in the encoding block), and they use the
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45 // opcode keyword to specify, in order, their primary, secondary, and
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46 // tertiary opcode. Only the opcode sections which a particular instruction
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47 // needs for encoding need to be specified.
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48 encode %{
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49 // Build emit functions for each basic byte or larger field in the intel
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50 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
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51 // code in the enc_class source block. Emit functions will live in the
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52 // main source block for now. In future, we can generalize this by
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53 // adding a syntax that specifies the sizes of fields in an order,
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54 // so that the adlc can build the emit functions automagically
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55
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56 enc_class tlsencode (eRegP dst, eRegP src) %{
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57 emit_rm(cbuf, 0x2, $dst$$reg, $src$$reg);
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58 emit_d32(cbuf, ThreadLocalStorage::get_thread_ptr_offset() );
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59 %}
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60
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61 enc_class call_epilog %{
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62 if( VerifyStackAtCalls ) {
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63 // Check that stack depth is unchanged: find majik cookie on stack
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64 int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP,-3*VMRegImpl::slots_per_word));
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65 if(framesize >= 128) {
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66 emit_opcode(cbuf, 0x81); // cmp [esp+0],0xbadb1ood
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67 emit_d8(cbuf,0xBC);
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68 emit_d8(cbuf,0x24);
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69 emit_d32(cbuf,framesize); // Find majik cookie from ESP
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70 emit_d32(cbuf, 0xbadb100d);
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71 }
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72 else {
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73 emit_opcode(cbuf, 0x81); // cmp [esp+0],0xbadb1ood
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74 emit_d8(cbuf,0x7C);
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75 emit_d8(cbuf,0x24);
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76 emit_d8(cbuf,framesize); // Find majik cookie from ESP
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77 emit_d32(cbuf, 0xbadb100d);
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78 }
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79 // jmp EQ around INT3
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80 emit_opcode(cbuf,0x74);
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81 emit_d8(cbuf,1);
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82 // Die if stack mismatch
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83 emit_opcode(cbuf,0xCC);
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84 }
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85 %}
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86
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87 %}
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88
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89 // INSTRUCTIONS -- Platform dependent
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90
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91
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92 //----------OS and Locking Instructions----------------------------------------
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93
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94 // The prefix of this name is KNOWN by the ADLC and cannot be changed.
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95 instruct tlsLoadP_prefixLoadP(eRegP t1) %{
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96 effect(DEF t1);
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97
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98 format %{ "MOV $t1,FS:[0x00] "%}
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99 opcode(0x8B, 0x64);
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100 ins_encode(OpcS, OpcP, conmemref(t1));
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101 ins_pipe( ialu_reg_fat );
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102 %}
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103
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104 // This name is KNOWN by the ADLC and cannot be changed.
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105 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
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106 // for this guy.
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107 // %%% Should do this with a clause like: bottom_type(TypeRawPtr::BOTTOM);
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108 instruct tlsLoadP(eRegP dst, eRegP t1) %{
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109 effect(DEF dst, USE t1);
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110
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111 format %{ "MOV $dst,[$t1 + TLS::thread_ptr_offset()]" %}
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112 opcode(0x8B);
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113 ins_encode(OpcP, tlsencode(dst, t1));
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114 ins_pipe( ialu_reg_reg_fat );
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115 %}
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116
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117 instruct TLS(eRegP dst) %{
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118 match(Set dst (ThreadLocal));
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119 expand %{
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120 eRegP t1;
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121 tlsLoadP_prefixLoadP(t1);
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122 tlsLoadP(dst, t1);
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123 %}
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124 %}
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125
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126 // Die now
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127 instruct ShouldNotReachHere( )
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128 %{
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129 match(Halt);
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130 // Use the following format syntax
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131 format %{ "INT3 ; ShouldNotReachHere" %}
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132 opcode(0xCC);
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133 ins_encode(OpcP);
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134 ins_pipe( pipe_slow );
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135 %}
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136
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137 //
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138 // Platform dependent source
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139 //
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140 source %{
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141
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142 // emit an interrupt that is caught by the debugger
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143 void emit_break(CodeBuffer &cbuf) {
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144 *(cbuf.code_end()) = (unsigned char)(0xcc);
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145 cbuf.set_code_end(cbuf.code_end() + 1);
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146 }
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147
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148 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
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149 emit_break(cbuf);
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150 }
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151
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152
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153 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
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154 return 1;
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155 }
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156
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157
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158 %}
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