Mercurial > hg > truffle
annotate src/os_cpu/aix_ppc/vm/orderAccess_aix_ppc.inline.hpp @ 18120:86ec7f6f71b3
refactored GraalCompilerTest API to be in terms of ResolvedJavaMethod instead of Method
author | Doug Simon <doug.simon@oracle.com> |
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date | Sat, 18 Oct 2014 00:08:19 +0200 |
parents | 67fa91961822 |
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rev | line source |
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1 /* |
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2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
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3 * Copyright 2012, 2013 SAP AG. All rights reserved. |
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4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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5 * |
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6 * This code is free software; you can redistribute it and/or modify it |
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7 * under the terms of the GNU General Public License version 2 only, as |
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8 * published by the Free Software Foundation. |
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9 * |
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10 * This code is distributed in the hope that it will be useful, but WITHOUT |
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11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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13 * version 2 for more details (a copy is included in the LICENSE file that |
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14 * accompanied this code). |
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15 * |
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16 * You should have received a copy of the GNU General Public License version |
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17 * 2 along with this work; if not, write to the Free Software Foundation, |
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18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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19 * |
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20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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21 * or visit www.oracle.com if you need additional information or have any |
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22 * questions. |
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23 * |
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24 */ |
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25 |
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26 #ifndef OS_CPU_AIX_OJDKPPC_VM_ORDERACCESS_AIX_PPC_INLINE_HPP |
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27 #define OS_CPU_AIX_OJDKPPC_VM_ORDERACCESS_AIX_PPC_INLINE_HPP |
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28 |
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29 #include "runtime/orderAccess.hpp" |
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30 #include "vm_version_ppc.hpp" |
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31 |
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32 // Implementation of class OrderAccess. |
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33 |
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34 // |
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35 // Machine barrier instructions: |
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36 // |
14445 | 37 // - sync Two-way memory barrier, aka fence. |
38 // - lwsync orders Store|Store, | |
39 // Load|Store, | |
40 // Load|Load, | |
41 // but not Store|Load | |
42 // - eieio orders Store|Store | |
43 // - isync Invalidates speculatively executed instructions, | |
44 // but isync may complete before storage accesses | |
45 // associated with instructions preceding isync have | |
46 // been performed. | |
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47 // |
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48 // Semantic barrier instructions: |
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49 // (as defined in orderAccess.hpp) |
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50 // |
14445 | 51 // - release orders Store|Store, (maps to lwsync) |
52 // Load|Store | |
53 // - acquire orders Load|Store, (maps to lwsync) | |
54 // Load|Load | |
55 // - fence orders Store|Store, (maps to sync) | |
56 // Load|Store, | |
57 // Load|Load, | |
58 // Store|Load | |
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59 // |
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60 |
14445 | 61 #define inlasm_sync() __asm__ __volatile__ ("sync" : : : "memory"); |
62 #define inlasm_lwsync() __asm__ __volatile__ ("lwsync" : : : "memory"); | |
63 #define inlasm_eieio() __asm__ __volatile__ ("eieio" : : : "memory"); | |
64 #define inlasm_isync() __asm__ __volatile__ ("isync" : : : "memory"); | |
65 #define inlasm_release() inlasm_lwsync(); | |
66 #define inlasm_acquire() inlasm_lwsync(); | |
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67 // Use twi-isync for load_acquire (faster than lwsync). |
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68 // ATTENTION: seems like xlC 10.1 has problems with this inline assembler macro (VerifyMethodHandles found "bad vminfo in AMH.conv"): |
14445 | 69 // #define inlasm_acquire_reg(X) __asm__ __volatile__ ("twi 0,%0,0\n isync\n" : : "r" (X) : "memory"); |
70 #define inlasm_acquire_reg(X) inlasm_lwsync(); | |
71 #define inlasm_fence() inlasm_sync(); | |
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72 |
14445 | 73 inline void OrderAccess::loadload() { inlasm_lwsync(); } |
74 inline void OrderAccess::storestore() { inlasm_lwsync(); } | |
75 inline void OrderAccess::loadstore() { inlasm_lwsync(); } | |
76 inline void OrderAccess::storeload() { inlasm_fence(); } | |
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77 |
14445 | 78 inline void OrderAccess::acquire() { inlasm_acquire(); } |
79 inline void OrderAccess::release() { inlasm_release(); } | |
80 inline void OrderAccess::fence() { inlasm_fence(); } | |
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81 |
14445 | 82 inline jbyte OrderAccess::load_acquire(volatile jbyte* p) { register jbyte t = *p; inlasm_acquire_reg(t); return t; } |
83 inline jshort OrderAccess::load_acquire(volatile jshort* p) { register jshort t = *p; inlasm_acquire_reg(t); return t; } | |
84 inline jint OrderAccess::load_acquire(volatile jint* p) { register jint t = *p; inlasm_acquire_reg(t); return t; } | |
85 inline jlong OrderAccess::load_acquire(volatile jlong* p) { register jlong t = *p; inlasm_acquire_reg(t); return t; } | |
86 inline jubyte OrderAccess::load_acquire(volatile jubyte* p) { register jubyte t = *p; inlasm_acquire_reg(t); return t; } | |
87 inline jushort OrderAccess::load_acquire(volatile jushort* p) { register jushort t = *p; inlasm_acquire_reg(t); return t; } | |
88 inline juint OrderAccess::load_acquire(volatile juint* p) { register juint t = *p; inlasm_acquire_reg(t); return t; } | |
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89 inline julong OrderAccess::load_acquire(volatile julong* p) { return (julong)load_acquire((volatile jlong*)p); } |
14445 | 90 inline jfloat OrderAccess::load_acquire(volatile jfloat* p) { register jfloat t = *p; inlasm_acquire(); return t; } |
91 inline jdouble OrderAccess::load_acquire(volatile jdouble* p) { register jdouble t = *p; inlasm_acquire(); return t; } | |
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92 |
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93 inline intptr_t OrderAccess::load_ptr_acquire(volatile intptr_t* p) { return (intptr_t)load_acquire((volatile jlong*)p); } |
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94 inline void* OrderAccess::load_ptr_acquire(volatile void* p) { return (void*) load_acquire((volatile jlong*)p); } |
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95 inline void* OrderAccess::load_ptr_acquire(const volatile void* p) { return (void*) load_acquire((volatile jlong*)p); } |
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96 |
14445 | 97 inline void OrderAccess::release_store(volatile jbyte* p, jbyte v) { inlasm_release(); *p = v; } |
98 inline void OrderAccess::release_store(volatile jshort* p, jshort v) { inlasm_release(); *p = v; } | |
99 inline void OrderAccess::release_store(volatile jint* p, jint v) { inlasm_release(); *p = v; } | |
100 inline void OrderAccess::release_store(volatile jlong* p, jlong v) { inlasm_release(); *p = v; } | |
101 inline void OrderAccess::release_store(volatile jubyte* p, jubyte v) { inlasm_release(); *p = v; } | |
102 inline void OrderAccess::release_store(volatile jushort* p, jushort v) { inlasm_release(); *p = v; } | |
103 inline void OrderAccess::release_store(volatile juint* p, juint v) { inlasm_release(); *p = v; } | |
104 inline void OrderAccess::release_store(volatile julong* p, julong v) { inlasm_release(); *p = v; } | |
105 inline void OrderAccess::release_store(volatile jfloat* p, jfloat v) { inlasm_release(); *p = v; } | |
106 inline void OrderAccess::release_store(volatile jdouble* p, jdouble v) { inlasm_release(); *p = v; } | |
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107 |
14445 | 108 inline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { inlasm_release(); *p = v; } |
109 inline void OrderAccess::release_store_ptr(volatile void* p, void* v) { inlasm_release(); *(void* volatile *)p = v; } | |
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110 |
14445 | 111 inline void OrderAccess::store_fence(jbyte* p, jbyte v) { *p = v; inlasm_fence(); } |
112 inline void OrderAccess::store_fence(jshort* p, jshort v) { *p = v; inlasm_fence(); } | |
113 inline void OrderAccess::store_fence(jint* p, jint v) { *p = v; inlasm_fence(); } | |
114 inline void OrderAccess::store_fence(jlong* p, jlong v) { *p = v; inlasm_fence(); } | |
115 inline void OrderAccess::store_fence(jubyte* p, jubyte v) { *p = v; inlasm_fence(); } | |
116 inline void OrderAccess::store_fence(jushort* p, jushort v) { *p = v; inlasm_fence(); } | |
117 inline void OrderAccess::store_fence(juint* p, juint v) { *p = v; inlasm_fence(); } | |
118 inline void OrderAccess::store_fence(julong* p, julong v) { *p = v; inlasm_fence(); } | |
119 inline void OrderAccess::store_fence(jfloat* p, jfloat v) { *p = v; inlasm_fence(); } | |
120 inline void OrderAccess::store_fence(jdouble* p, jdouble v) { *p = v; inlasm_fence(); } | |
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121 |
14445 | 122 inline void OrderAccess::store_ptr_fence(intptr_t* p, intptr_t v) { *p = v; inlasm_fence(); } |
123 inline void OrderAccess::store_ptr_fence(void** p, void* v) { *p = v; inlasm_fence(); } | |
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124 |
14445 | 125 inline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) { inlasm_release(); *p = v; inlasm_fence(); } |
126 inline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) { inlasm_release(); *p = v; inlasm_fence(); } | |
127 inline void OrderAccess::release_store_fence(volatile jint* p, jint v) { inlasm_release(); *p = v; inlasm_fence(); } | |
128 inline void OrderAccess::release_store_fence(volatile jlong* p, jlong v) { inlasm_release(); *p = v; inlasm_fence(); } | |
129 inline void OrderAccess::release_store_fence(volatile jubyte* p, jubyte v) { inlasm_release(); *p = v; inlasm_fence(); } | |
130 inline void OrderAccess::release_store_fence(volatile jushort* p, jushort v) { inlasm_release(); *p = v; inlasm_fence(); } | |
131 inline void OrderAccess::release_store_fence(volatile juint* p, juint v) { inlasm_release(); *p = v; inlasm_fence(); } | |
132 inline void OrderAccess::release_store_fence(volatile julong* p, julong v) { inlasm_release(); *p = v; inlasm_fence(); } | |
133 inline void OrderAccess::release_store_fence(volatile jfloat* p, jfloat v) { inlasm_release(); *p = v; inlasm_fence(); } | |
134 inline void OrderAccess::release_store_fence(volatile jdouble* p, jdouble v) { inlasm_release(); *p = v; inlasm_fence(); } | |
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135 |
14445 | 136 inline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) { inlasm_release(); *p = v; inlasm_fence(); } |
137 inline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) { inlasm_release(); *(void* volatile *)p = v; inlasm_fence(); } | |
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138 |
14445 | 139 #undef inlasm_sync |
140 #undef inlasm_lwsync | |
141 #undef inlasm_eieio | |
142 #undef inlasm_isync | |
143 #undef inlasm_release | |
144 #undef inlasm_acquire | |
145 #undef inlasm_fence | |
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146 |
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147 #endif // OS_CPU_AIX_OJDKPPC_VM_ORDERACCESS_AIX_PPC_INLINE_HPP |