Mercurial > hg > truffle
annotate src/cpu/sparc/vm/assembler_sparc.cpp @ 697:922aedc96ef5
Merge
author | ysr |
---|---|
date | Fri, 03 Apr 2009 15:59:19 -0700 |
parents | a80d48f6fde1 |
children | e5b0439ef4ae |
rev | line source |
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0 | 1 /* |
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2 * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
20 * CA 95054 USA or visit www.sun.com if you need additional information or | |
21 * have any questions. | |
22 * | |
23 */ | |
24 | |
25 #include "incls/_precompiled.incl" | |
26 #include "incls/_assembler_sparc.cpp.incl" | |
27 | |
28 // Implementation of Address | |
29 | |
30 Address::Address( addr_type t, int which ) { | |
31 switch (t) { | |
32 case extra_in_argument: | |
33 case extra_out_argument: | |
34 _base = t == extra_in_argument ? FP : SP; | |
35 _hi = 0; | |
36 // Warning: In LP64 mode, _disp will occupy more than 10 bits. | |
37 // This is inconsistent with the other constructors but op | |
38 // codes such as ld or ldx, only access disp() to get their | |
39 // simm13 argument. | |
40 _disp = ((which - Argument::n_register_parameters + frame::memory_parameter_word_sp_offset) * BytesPerWord) + STACK_BIAS; | |
41 break; | |
42 default: | |
43 ShouldNotReachHere(); | |
44 break; | |
45 } | |
46 } | |
47 | |
48 static const char* argumentNames[][2] = { | |
49 {"A0","P0"}, {"A1","P1"}, {"A2","P2"}, {"A3","P3"}, {"A4","P4"}, | |
50 {"A5","P5"}, {"A6","P6"}, {"A7","P7"}, {"A8","P8"}, {"A9","P9"}, | |
51 {"A(n>9)","P(n>9)"} | |
52 }; | |
53 | |
54 const char* Argument::name() const { | |
55 int nofArgs = sizeof argumentNames / sizeof argumentNames[0]; | |
56 int num = number(); | |
57 if (num >= nofArgs) num = nofArgs - 1; | |
58 return argumentNames[num][is_in() ? 1 : 0]; | |
59 } | |
60 | |
61 void Assembler::print_instruction(int inst) { | |
62 const char* s; | |
63 switch (inv_op(inst)) { | |
64 default: s = "????"; break; | |
65 case call_op: s = "call"; break; | |
66 case branch_op: | |
67 switch (inv_op2(inst)) { | |
68 case bpr_op2: s = "bpr"; break; | |
69 case fb_op2: s = "fb"; break; | |
70 case fbp_op2: s = "fbp"; break; | |
71 case br_op2: s = "br"; break; | |
72 case bp_op2: s = "bp"; break; | |
73 case cb_op2: s = "cb"; break; | |
74 default: s = "????"; break; | |
75 } | |
76 } | |
77 ::tty->print("%s", s); | |
78 } | |
79 | |
80 | |
81 // Patch instruction inst at offset inst_pos to refer to dest_pos | |
82 // and return the resulting instruction. | |
83 // We should have pcs, not offsets, but since all is relative, it will work out | |
84 // OK. | |
85 int Assembler::patched_branch(int dest_pos, int inst, int inst_pos) { | |
86 | |
87 int m; // mask for displacement field | |
88 int v; // new value for displacement field | |
89 const int word_aligned_ones = -4; | |
90 switch (inv_op(inst)) { | |
91 default: ShouldNotReachHere(); | |
92 case call_op: m = wdisp(word_aligned_ones, 0, 30); v = wdisp(dest_pos, inst_pos, 30); break; | |
93 case branch_op: | |
94 switch (inv_op2(inst)) { | |
95 case bpr_op2: m = wdisp16(word_aligned_ones, 0); v = wdisp16(dest_pos, inst_pos); break; | |
96 case fbp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break; | |
97 case bp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break; | |
98 case fb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break; | |
99 case br_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break; | |
100 case cb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break; | |
101 default: ShouldNotReachHere(); | |
102 } | |
103 } | |
104 return inst & ~m | v; | |
105 } | |
106 | |
107 // Return the offset of the branch destionation of instruction inst | |
108 // at offset pos. | |
109 // Should have pcs, but since all is relative, it works out. | |
110 int Assembler::branch_destination(int inst, int pos) { | |
111 int r; | |
112 switch (inv_op(inst)) { | |
113 default: ShouldNotReachHere(); | |
114 case call_op: r = inv_wdisp(inst, pos, 30); break; | |
115 case branch_op: | |
116 switch (inv_op2(inst)) { | |
117 case bpr_op2: r = inv_wdisp16(inst, pos); break; | |
118 case fbp_op2: r = inv_wdisp( inst, pos, 19); break; | |
119 case bp_op2: r = inv_wdisp( inst, pos, 19); break; | |
120 case fb_op2: r = inv_wdisp( inst, pos, 22); break; | |
121 case br_op2: r = inv_wdisp( inst, pos, 22); break; | |
122 case cb_op2: r = inv_wdisp( inst, pos, 22); break; | |
123 default: ShouldNotReachHere(); | |
124 } | |
125 } | |
126 return r; | |
127 } | |
128 | |
129 int AbstractAssembler::code_fill_byte() { | |
130 return 0x00; // illegal instruction 0x00000000 | |
131 } | |
132 | |
342
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133 Assembler::Condition Assembler::reg_cond_to_cc_cond(Assembler::RCondition in) { |
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134 switch (in) { |
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135 case rc_z: return equal; |
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136 case rc_lez: return lessEqual; |
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137 case rc_lz: return less; |
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138 case rc_nz: return notEqual; |
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139 case rc_gz: return greater; |
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140 case rc_gez: return greaterEqual; |
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141 default: |
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142 ShouldNotReachHere(); |
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143 } |
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144 return equal; |
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145 } |
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146 |
0 | 147 // Generate a bunch 'o stuff (including v9's |
148 #ifndef PRODUCT | |
149 void Assembler::test_v9() { | |
150 add( G0, G1, G2 ); | |
151 add( G3, 0, G4 ); | |
152 | |
153 addcc( G5, G6, G7 ); | |
154 addcc( I0, 1, I1 ); | |
155 addc( I2, I3, I4 ); | |
156 addc( I5, -1, I6 ); | |
157 addccc( I7, L0, L1 ); | |
158 addccc( L2, (1 << 12) - 2, L3 ); | |
159 | |
160 Label lbl1, lbl2, lbl3; | |
161 | |
162 bind(lbl1); | |
163 | |
164 bpr( rc_z, true, pn, L4, pc(), relocInfo::oop_type ); | |
165 delayed()->nop(); | |
166 bpr( rc_lez, false, pt, L5, lbl1); | |
167 delayed()->nop(); | |
168 | |
169 fb( f_never, true, pc() + 4, relocInfo::none); | |
170 delayed()->nop(); | |
171 fb( f_notEqual, false, lbl2 ); | |
172 delayed()->nop(); | |
173 | |
174 fbp( f_notZero, true, fcc0, pn, pc() - 4, relocInfo::none); | |
175 delayed()->nop(); | |
176 fbp( f_lessOrGreater, false, fcc1, pt, lbl3 ); | |
177 delayed()->nop(); | |
178 | |
179 br( equal, true, pc() + 1024, relocInfo::none); | |
180 delayed()->nop(); | |
181 br( lessEqual, false, lbl1 ); | |
182 delayed()->nop(); | |
183 br( never, false, lbl1 ); | |
184 delayed()->nop(); | |
185 | |
186 bp( less, true, icc, pn, pc(), relocInfo::none); | |
187 delayed()->nop(); | |
188 bp( lessEqualUnsigned, false, xcc, pt, lbl2 ); | |
189 delayed()->nop(); | |
190 | |
191 call( pc(), relocInfo::none); | |
192 delayed()->nop(); | |
193 call( lbl3 ); | |
194 delayed()->nop(); | |
195 | |
196 | |
197 casa( L6, L7, O0 ); | |
198 casxa( O1, O2, O3, 0 ); | |
199 | |
200 udiv( O4, O5, O7 ); | |
201 udiv( G0, (1 << 12) - 1, G1 ); | |
202 sdiv( G1, G2, G3 ); | |
203 sdiv( G4, -((1 << 12) - 1), G5 ); | |
204 udivcc( G6, G7, I0 ); | |
205 udivcc( I1, -((1 << 12) - 2), I2 ); | |
206 sdivcc( I3, I4, I5 ); | |
207 sdivcc( I6, -((1 << 12) - 0), I7 ); | |
208 | |
209 done(); | |
210 retry(); | |
211 | |
212 fadd( FloatRegisterImpl::S, F0, F1, F2 ); | |
213 fsub( FloatRegisterImpl::D, F34, F0, F62 ); | |
214 | |
215 fcmp( FloatRegisterImpl::Q, fcc0, F0, F60); | |
216 fcmpe( FloatRegisterImpl::S, fcc1, F31, F30); | |
217 | |
218 ftox( FloatRegisterImpl::D, F2, F4 ); | |
219 ftoi( FloatRegisterImpl::Q, F4, F8 ); | |
220 | |
221 ftof( FloatRegisterImpl::S, FloatRegisterImpl::Q, F3, F12 ); | |
222 | |
223 fxtof( FloatRegisterImpl::S, F4, F5 ); | |
224 fitof( FloatRegisterImpl::D, F6, F8 ); | |
225 | |
226 fmov( FloatRegisterImpl::Q, F16, F20 ); | |
227 fneg( FloatRegisterImpl::S, F6, F7 ); | |
228 fabs( FloatRegisterImpl::D, F10, F12 ); | |
229 | |
230 fmul( FloatRegisterImpl::Q, F24, F28, F32 ); | |
231 fmul( FloatRegisterImpl::S, FloatRegisterImpl::D, F8, F9, F14 ); | |
232 fdiv( FloatRegisterImpl::S, F10, F11, F12 ); | |
233 | |
234 fsqrt( FloatRegisterImpl::S, F13, F14 ); | |
235 | |
236 flush( L0, L1 ); | |
237 flush( L2, -1 ); | |
238 | |
239 flushw(); | |
240 | |
241 illtrap( (1 << 22) - 2); | |
242 | |
243 impdep1( 17, (1 << 19) - 1 ); | |
244 impdep2( 3, 0 ); | |
245 | |
246 jmpl( L3, L4, L5 ); | |
247 delayed()->nop(); | |
248 jmpl( L6, -1, L7, Relocation::spec_simple(relocInfo::none)); | |
249 delayed()->nop(); | |
250 | |
251 | |
252 ldf( FloatRegisterImpl::S, O0, O1, F15 ); | |
253 ldf( FloatRegisterImpl::D, O2, -1, F14 ); | |
254 | |
255 | |
256 ldfsr( O3, O4 ); | |
257 ldfsr( O5, -1 ); | |
258 ldxfsr( O6, O7 ); | |
259 ldxfsr( I0, -1 ); | |
260 | |
261 ldfa( FloatRegisterImpl::D, I1, I2, 1, F16 ); | |
262 ldfa( FloatRegisterImpl::Q, I3, -1, F36 ); | |
263 | |
264 ldsb( I4, I5, I6 ); | |
265 ldsb( I7, -1, G0 ); | |
266 ldsh( G1, G3, G4 ); | |
267 ldsh( G5, -1, G6 ); | |
268 ldsw( G7, L0, L1 ); | |
269 ldsw( L2, -1, L3 ); | |
270 ldub( L4, L5, L6 ); | |
271 ldub( L7, -1, O0 ); | |
272 lduh( O1, O2, O3 ); | |
273 lduh( O4, -1, O5 ); | |
274 lduw( O6, O7, G0 ); | |
275 lduw( G1, -1, G2 ); | |
276 ldx( G3, G4, G5 ); | |
277 ldx( G6, -1, G7 ); | |
278 ldd( I0, I1, I2 ); | |
279 ldd( I3, -1, I4 ); | |
280 | |
281 ldsba( I5, I6, 2, I7 ); | |
282 ldsba( L0, -1, L1 ); | |
283 ldsha( L2, L3, 3, L4 ); | |
284 ldsha( L5, -1, L6 ); | |
285 ldswa( L7, O0, (1 << 8) - 1, O1 ); | |
286 ldswa( O2, -1, O3 ); | |
287 lduba( O4, O5, 0, O6 ); | |
288 lduba( O7, -1, I0 ); | |
289 lduha( I1, I2, 1, I3 ); | |
290 lduha( I4, -1, I5 ); | |
291 lduwa( I6, I7, 2, L0 ); | |
292 lduwa( L1, -1, L2 ); | |
293 ldxa( L3, L4, 3, L5 ); | |
294 ldxa( L6, -1, L7 ); | |
295 ldda( G0, G1, 4, G2 ); | |
296 ldda( G3, -1, G4 ); | |
297 | |
298 ldstub( G5, G6, G7 ); | |
299 ldstub( O0, -1, O1 ); | |
300 | |
301 ldstuba( O2, O3, 5, O4 ); | |
302 ldstuba( O5, -1, O6 ); | |
303 | |
304 and3( I0, L0, O0 ); | |
305 and3( G7, -1, O7 ); | |
306 andcc( L2, I2, G2 ); | |
307 andcc( L4, -1, G4 ); | |
308 andn( I5, I6, I7 ); | |
309 andn( I6, -1, I7 ); | |
310 andncc( I5, I6, I7 ); | |
311 andncc( I7, -1, I6 ); | |
312 or3( I5, I6, I7 ); | |
313 or3( I7, -1, I6 ); | |
314 orcc( I5, I6, I7 ); | |
315 orcc( I7, -1, I6 ); | |
316 orn( I5, I6, I7 ); | |
317 orn( I7, -1, I6 ); | |
318 orncc( I5, I6, I7 ); | |
319 orncc( I7, -1, I6 ); | |
320 xor3( I5, I6, I7 ); | |
321 xor3( I7, -1, I6 ); | |
322 xorcc( I5, I6, I7 ); | |
323 xorcc( I7, -1, I6 ); | |
324 xnor( I5, I6, I7 ); | |
325 xnor( I7, -1, I6 ); | |
326 xnorcc( I5, I6, I7 ); | |
327 xnorcc( I7, -1, I6 ); | |
328 | |
329 membar( Membar_mask_bits(StoreStore | LoadStore | StoreLoad | LoadLoad | Sync | MemIssue | Lookaside ) ); | |
330 membar( StoreStore ); | |
331 membar( LoadStore ); | |
332 membar( StoreLoad ); | |
333 membar( LoadLoad ); | |
334 membar( Sync ); | |
335 membar( MemIssue ); | |
336 membar( Lookaside ); | |
337 | |
338 fmov( FloatRegisterImpl::S, f_ordered, true, fcc2, F16, F17 ); | |
339 fmov( FloatRegisterImpl::D, rc_lz, L5, F18, F20 ); | |
340 | |
341 movcc( overflowClear, false, icc, I6, L4 ); | |
342 movcc( f_unorderedOrEqual, true, fcc2, (1 << 10) - 1, O0 ); | |
343 | |
344 movr( rc_nz, I5, I6, I7 ); | |
345 movr( rc_gz, L1, -1, L2 ); | |
346 | |
347 mulx( I5, I6, I7 ); | |
348 mulx( I7, -1, I6 ); | |
349 sdivx( I5, I6, I7 ); | |
350 sdivx( I7, -1, I6 ); | |
351 udivx( I5, I6, I7 ); | |
352 udivx( I7, -1, I6 ); | |
353 | |
354 umul( I5, I6, I7 ); | |
355 umul( I7, -1, I6 ); | |
356 smul( I5, I6, I7 ); | |
357 smul( I7, -1, I6 ); | |
358 umulcc( I5, I6, I7 ); | |
359 umulcc( I7, -1, I6 ); | |
360 smulcc( I5, I6, I7 ); | |
361 smulcc( I7, -1, I6 ); | |
362 | |
363 mulscc( I5, I6, I7 ); | |
364 mulscc( I7, -1, I6 ); | |
365 | |
366 nop(); | |
367 | |
368 | |
369 popc( G0, G1); | |
370 popc( -1, G2); | |
371 | |
372 prefetch( L1, L2, severalReads ); | |
373 prefetch( L3, -1, oneRead ); | |
374 prefetcha( O3, O2, 6, severalWritesAndPossiblyReads ); | |
375 prefetcha( G2, -1, oneWrite ); | |
376 | |
377 rett( I7, I7); | |
378 delayed()->nop(); | |
379 rett( G0, -1, relocInfo::none); | |
380 delayed()->nop(); | |
381 | |
382 save( I5, I6, I7 ); | |
383 save( I7, -1, I6 ); | |
384 restore( I5, I6, I7 ); | |
385 restore( I7, -1, I6 ); | |
386 | |
387 saved(); | |
388 restored(); | |
389 | |
390 sethi( 0xaaaaaaaa, I3, Relocation::spec_simple(relocInfo::none)); | |
391 | |
392 sll( I5, I6, I7 ); | |
393 sll( I7, 31, I6 ); | |
394 srl( I5, I6, I7 ); | |
395 srl( I7, 0, I6 ); | |
396 sra( I5, I6, I7 ); | |
397 sra( I7, 30, I6 ); | |
398 sllx( I5, I6, I7 ); | |
399 sllx( I7, 63, I6 ); | |
400 srlx( I5, I6, I7 ); | |
401 srlx( I7, 0, I6 ); | |
402 srax( I5, I6, I7 ); | |
403 srax( I7, 62, I6 ); | |
404 | |
405 sir( -1 ); | |
406 | |
407 stbar(); | |
408 | |
409 stf( FloatRegisterImpl::Q, F40, G0, I7 ); | |
410 stf( FloatRegisterImpl::S, F18, I3, -1 ); | |
411 | |
412 stfsr( L1, L2 ); | |
413 stfsr( I7, -1 ); | |
414 stxfsr( I6, I5 ); | |
415 stxfsr( L4, -1 ); | |
416 | |
417 stfa( FloatRegisterImpl::D, F22, I6, I7, 7 ); | |
418 stfa( FloatRegisterImpl::Q, F44, G0, -1 ); | |
419 | |
420 stb( L5, O2, I7 ); | |
421 stb( I7, I6, -1 ); | |
422 sth( L5, O2, I7 ); | |
423 sth( I7, I6, -1 ); | |
424 stw( L5, O2, I7 ); | |
425 stw( I7, I6, -1 ); | |
426 stx( L5, O2, I7 ); | |
427 stx( I7, I6, -1 ); | |
428 std( L5, O2, I7 ); | |
429 std( I7, I6, -1 ); | |
430 | |
431 stba( L5, O2, I7, 8 ); | |
432 stba( I7, I6, -1 ); | |
433 stha( L5, O2, I7, 9 ); | |
434 stha( I7, I6, -1 ); | |
435 stwa( L5, O2, I7, 0 ); | |
436 stwa( I7, I6, -1 ); | |
437 stxa( L5, O2, I7, 11 ); | |
438 stxa( I7, I6, -1 ); | |
439 stda( L5, O2, I7, 12 ); | |
440 stda( I7, I6, -1 ); | |
441 | |
442 sub( I5, I6, I7 ); | |
443 sub( I7, -1, I6 ); | |
444 subcc( I5, I6, I7 ); | |
445 subcc( I7, -1, I6 ); | |
446 subc( I5, I6, I7 ); | |
447 subc( I7, -1, I6 ); | |
448 subccc( I5, I6, I7 ); | |
449 subccc( I7, -1, I6 ); | |
450 | |
451 swap( I5, I6, I7 ); | |
452 swap( I7, -1, I6 ); | |
453 | |
454 swapa( G0, G1, 13, G2 ); | |
455 swapa( I7, -1, I6 ); | |
456 | |
457 taddcc( I5, I6, I7 ); | |
458 taddcc( I7, -1, I6 ); | |
459 taddcctv( I5, I6, I7 ); | |
460 taddcctv( I7, -1, I6 ); | |
461 | |
462 tsubcc( I5, I6, I7 ); | |
463 tsubcc( I7, -1, I6 ); | |
464 tsubcctv( I5, I6, I7 ); | |
465 tsubcctv( I7, -1, I6 ); | |
466 | |
467 trap( overflowClear, xcc, G0, G1 ); | |
468 trap( lessEqual, icc, I7, 17 ); | |
469 | |
470 bind(lbl2); | |
471 bind(lbl3); | |
472 | |
473 code()->decode(); | |
474 } | |
475 | |
476 // Generate a bunch 'o stuff unique to V8 | |
477 void Assembler::test_v8_onlys() { | |
478 Label lbl1; | |
479 | |
480 cb( cp_0or1or2, false, pc() - 4, relocInfo::none); | |
481 delayed()->nop(); | |
482 cb( cp_never, true, lbl1); | |
483 delayed()->nop(); | |
484 | |
485 cpop1(1, 2, 3, 4); | |
486 cpop2(5, 6, 7, 8); | |
487 | |
488 ldc( I0, I1, 31); | |
489 ldc( I2, -1, 0); | |
490 | |
491 lddc( I4, I4, 30); | |
492 lddc( I6, 0, 1 ); | |
493 | |
494 ldcsr( L0, L1, 0); | |
495 ldcsr( L1, (1 << 12) - 1, 17 ); | |
496 | |
497 stc( 31, L4, L5); | |
498 stc( 30, L6, -(1 << 12) ); | |
499 | |
500 stdc( 0, L7, G0); | |
501 stdc( 1, G1, 0 ); | |
502 | |
503 stcsr( 16, G2, G3); | |
504 stcsr( 17, G4, 1 ); | |
505 | |
506 stdcq( 4, G5, G6); | |
507 stdcq( 5, G7, -1 ); | |
508 | |
509 bind(lbl1); | |
510 | |
511 code()->decode(); | |
512 } | |
513 #endif | |
514 | |
515 // Implementation of MacroAssembler | |
516 | |
517 void MacroAssembler::null_check(Register reg, int offset) { | |
518 if (needs_explicit_null_check((intptr_t)offset)) { | |
519 // provoke OS NULL exception if reg = NULL by | |
520 // accessing M[reg] w/o changing any registers | |
521 ld_ptr(reg, 0, G0); | |
522 } | |
523 else { | |
524 // nothing to do, (later) access of M[reg + offset] | |
525 // will provoke OS NULL exception if reg = NULL | |
526 } | |
527 } | |
528 | |
529 // Ring buffer jumps | |
530 | |
531 #ifndef PRODUCT | |
532 void MacroAssembler::ret( bool trace ) { if (trace) { | |
533 mov(I7, O7); // traceable register | |
534 JMP(O7, 2 * BytesPerInstWord); | |
535 } else { | |
536 jmpl( I7, 2 * BytesPerInstWord, G0 ); | |
537 } | |
538 } | |
539 | |
540 void MacroAssembler::retl( bool trace ) { if (trace) JMP(O7, 2 * BytesPerInstWord); | |
541 else jmpl( O7, 2 * BytesPerInstWord, G0 ); } | |
542 #endif /* PRODUCT */ | |
543 | |
544 | |
545 void MacroAssembler::jmp2(Register r1, Register r2, const char* file, int line ) { | |
546 assert_not_delayed(); | |
547 // This can only be traceable if r1 & r2 are visible after a window save | |
548 if (TraceJumps) { | |
549 #ifndef PRODUCT | |
550 save_frame(0); | |
551 verify_thread(); | |
552 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); | |
553 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); | |
554 sll(O0, exact_log2(4*sizeof(intptr_t)), O2); | |
555 add(O2, O1, O1); | |
556 | |
557 add(r1->after_save(), r2->after_save(), O2); | |
558 set((intptr_t)file, O3); | |
559 set(line, O4); | |
560 Label L; | |
561 // get nearby pc, store jmp target | |
562 call(L, relocInfo::none); // No relocation for call to pc+0x8 | |
563 delayed()->st(O2, O1, 0); | |
564 bind(L); | |
565 | |
566 // store nearby pc | |
567 st(O7, O1, sizeof(intptr_t)); | |
568 // store file | |
569 st(O3, O1, 2*sizeof(intptr_t)); | |
570 // store line | |
571 st(O4, O1, 3*sizeof(intptr_t)); | |
572 add(O0, 1, O0); | |
573 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); | |
574 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); | |
575 restore(); | |
576 #endif /* PRODUCT */ | |
577 } | |
578 jmpl(r1, r2, G0); | |
579 } | |
580 void MacroAssembler::jmp(Register r1, int offset, const char* file, int line ) { | |
581 assert_not_delayed(); | |
582 // This can only be traceable if r1 is visible after a window save | |
583 if (TraceJumps) { | |
584 #ifndef PRODUCT | |
585 save_frame(0); | |
586 verify_thread(); | |
587 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); | |
588 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); | |
589 sll(O0, exact_log2(4*sizeof(intptr_t)), O2); | |
590 add(O2, O1, O1); | |
591 | |
592 add(r1->after_save(), offset, O2); | |
593 set((intptr_t)file, O3); | |
594 set(line, O4); | |
595 Label L; | |
596 // get nearby pc, store jmp target | |
597 call(L, relocInfo::none); // No relocation for call to pc+0x8 | |
598 delayed()->st(O2, O1, 0); | |
599 bind(L); | |
600 | |
601 // store nearby pc | |
602 st(O7, O1, sizeof(intptr_t)); | |
603 // store file | |
604 st(O3, O1, 2*sizeof(intptr_t)); | |
605 // store line | |
606 st(O4, O1, 3*sizeof(intptr_t)); | |
607 add(O0, 1, O0); | |
608 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); | |
609 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); | |
610 restore(); | |
611 #endif /* PRODUCT */ | |
612 } | |
613 jmp(r1, offset); | |
614 } | |
615 | |
616 // This code sequence is relocatable to any address, even on LP64. | |
617 void MacroAssembler::jumpl( Address& a, Register d, int offset, const char* file, int line ) { | |
618 assert_not_delayed(); | |
619 // Force fixed length sethi because NativeJump and NativeFarCall don't handle | |
620 // variable length instruction streams. | |
621 sethi(a, /*ForceRelocatable=*/ true); | |
622 if (TraceJumps) { | |
623 #ifndef PRODUCT | |
624 // Must do the add here so relocation can find the remainder of the | |
625 // value to be relocated. | |
626 add(a.base(), a.disp() + offset, a.base(), a.rspec(offset)); | |
627 save_frame(0); | |
628 verify_thread(); | |
629 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); | |
630 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); | |
631 sll(O0, exact_log2(4*sizeof(intptr_t)), O2); | |
632 add(O2, O1, O1); | |
633 | |
634 set((intptr_t)file, O3); | |
635 set(line, O4); | |
636 Label L; | |
637 | |
638 // get nearby pc, store jmp target | |
639 call(L, relocInfo::none); // No relocation for call to pc+0x8 | |
640 delayed()->st(a.base()->after_save(), O1, 0); | |
641 bind(L); | |
642 | |
643 // store nearby pc | |
644 st(O7, O1, sizeof(intptr_t)); | |
645 // store file | |
646 st(O3, O1, 2*sizeof(intptr_t)); | |
647 // store line | |
648 st(O4, O1, 3*sizeof(intptr_t)); | |
649 add(O0, 1, O0); | |
650 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); | |
651 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); | |
652 restore(); | |
653 jmpl(a.base(), G0, d); | |
654 #else | |
655 jmpl(a, d, offset); | |
656 #endif /* PRODUCT */ | |
657 } else { | |
658 jmpl(a, d, offset); | |
659 } | |
660 } | |
661 | |
662 void MacroAssembler::jump( Address& a, int offset, const char* file, int line ) { | |
663 jumpl( a, G0, offset, file, line ); | |
664 } | |
665 | |
666 | |
667 // Convert to C varargs format | |
668 void MacroAssembler::set_varargs( Argument inArg, Register d ) { | |
669 // spill register-resident args to their memory slots | |
670 // (SPARC calling convention requires callers to have already preallocated these) | |
671 // Note that the inArg might in fact be an outgoing argument, | |
672 // if a leaf routine or stub does some tricky argument shuffling. | |
673 // This routine must work even though one of the saved arguments | |
674 // is in the d register (e.g., set_varargs(Argument(0, false), O0)). | |
675 for (Argument savePtr = inArg; | |
676 savePtr.is_register(); | |
677 savePtr = savePtr.successor()) { | |
678 st_ptr(savePtr.as_register(), savePtr.address_in_frame()); | |
679 } | |
680 // return the address of the first memory slot | |
681 add(inArg.address_in_frame(), d); | |
682 } | |
683 | |
684 // Conditional breakpoint (for assertion checks in assembly code) | |
685 void MacroAssembler::breakpoint_trap(Condition c, CC cc) { | |
686 trap(c, cc, G0, ST_RESERVED_FOR_USER_0); | |
687 } | |
688 | |
689 // We want to use ST_BREAKPOINT here, but the debugger is confused by it. | |
690 void MacroAssembler::breakpoint_trap() { | |
691 trap(ST_RESERVED_FOR_USER_0); | |
692 } | |
693 | |
694 // flush windows (except current) using flushw instruction if avail. | |
695 void MacroAssembler::flush_windows() { | |
696 if (VM_Version::v9_instructions_work()) flushw(); | |
697 else flush_windows_trap(); | |
698 } | |
699 | |
700 // Write serialization page so VM thread can do a pseudo remote membar | |
701 // We use the current thread pointer to calculate a thread specific | |
702 // offset to write to within the page. This minimizes bus traffic | |
703 // due to cache line collision. | |
704 void MacroAssembler::serialize_memory(Register thread, Register tmp1, Register tmp2) { | |
705 Address mem_serialize_page(tmp1, os::get_memory_serialize_page()); | |
706 srl(thread, os::get_serialize_page_shift_count(), tmp2); | |
707 if (Assembler::is_simm13(os::vm_page_size())) { | |
708 and3(tmp2, (os::vm_page_size() - sizeof(int)), tmp2); | |
709 } | |
710 else { | |
711 set((os::vm_page_size() - sizeof(int)), tmp1); | |
712 and3(tmp2, tmp1, tmp2); | |
713 } | |
714 load_address(mem_serialize_page); | |
715 st(G0, tmp1, tmp2); | |
716 } | |
717 | |
718 | |
719 | |
720 void MacroAssembler::enter() { | |
721 Unimplemented(); | |
722 } | |
723 | |
724 void MacroAssembler::leave() { | |
725 Unimplemented(); | |
726 } | |
727 | |
728 void MacroAssembler::mult(Register s1, Register s2, Register d) { | |
729 if(VM_Version::v9_instructions_work()) { | |
730 mulx (s1, s2, d); | |
731 } else { | |
732 smul (s1, s2, d); | |
733 } | |
734 } | |
735 | |
736 void MacroAssembler::mult(Register s1, int simm13a, Register d) { | |
737 if(VM_Version::v9_instructions_work()) { | |
738 mulx (s1, simm13a, d); | |
739 } else { | |
740 smul (s1, simm13a, d); | |
741 } | |
742 } | |
743 | |
744 | |
745 #ifdef ASSERT | |
746 void MacroAssembler::read_ccr_v8_assert(Register ccr_save) { | |
747 const Register s1 = G3_scratch; | |
748 const Register s2 = G4_scratch; | |
749 Label get_psr_test; | |
750 // Get the condition codes the V8 way. | |
751 read_ccr_trap(s1); | |
752 mov(ccr_save, s2); | |
753 // This is a test of V8 which has icc but not xcc | |
754 // so mask off the xcc bits | |
755 and3(s2, 0xf, s2); | |
756 // Compare condition codes from the V8 and V9 ways. | |
757 subcc(s2, s1, G0); | |
758 br(Assembler::notEqual, true, Assembler::pt, get_psr_test); | |
759 delayed()->breakpoint_trap(); | |
760 bind(get_psr_test); | |
761 } | |
762 | |
763 void MacroAssembler::write_ccr_v8_assert(Register ccr_save) { | |
764 const Register s1 = G3_scratch; | |
765 const Register s2 = G4_scratch; | |
766 Label set_psr_test; | |
767 // Write out the saved condition codes the V8 way | |
768 write_ccr_trap(ccr_save, s1, s2); | |
769 // Read back the condition codes using the V9 instruction | |
770 rdccr(s1); | |
771 mov(ccr_save, s2); | |
772 // This is a test of V8 which has icc but not xcc | |
773 // so mask off the xcc bits | |
774 and3(s2, 0xf, s2); | |
775 and3(s1, 0xf, s1); | |
776 // Compare the V8 way with the V9 way. | |
777 subcc(s2, s1, G0); | |
778 br(Assembler::notEqual, true, Assembler::pt, set_psr_test); | |
779 delayed()->breakpoint_trap(); | |
780 bind(set_psr_test); | |
781 } | |
782 #else | |
783 #define read_ccr_v8_assert(x) | |
784 #define write_ccr_v8_assert(x) | |
785 #endif // ASSERT | |
786 | |
787 void MacroAssembler::read_ccr(Register ccr_save) { | |
788 if (VM_Version::v9_instructions_work()) { | |
789 rdccr(ccr_save); | |
790 // Test code sequence used on V8. Do not move above rdccr. | |
791 read_ccr_v8_assert(ccr_save); | |
792 } else { | |
793 read_ccr_trap(ccr_save); | |
794 } | |
795 } | |
796 | |
797 void MacroAssembler::write_ccr(Register ccr_save) { | |
798 if (VM_Version::v9_instructions_work()) { | |
799 // Test code sequence used on V8. Do not move below wrccr. | |
800 write_ccr_v8_assert(ccr_save); | |
801 wrccr(ccr_save); | |
802 } else { | |
803 const Register temp_reg1 = G3_scratch; | |
804 const Register temp_reg2 = G4_scratch; | |
805 write_ccr_trap(ccr_save, temp_reg1, temp_reg2); | |
806 } | |
807 } | |
808 | |
809 | |
810 // Calls to C land | |
811 | |
812 #ifdef ASSERT | |
813 // a hook for debugging | |
814 static Thread* reinitialize_thread() { | |
815 return ThreadLocalStorage::thread(); | |
816 } | |
817 #else | |
818 #define reinitialize_thread ThreadLocalStorage::thread | |
819 #endif | |
820 | |
821 #ifdef ASSERT | |
822 address last_get_thread = NULL; | |
823 #endif | |
824 | |
825 // call this when G2_thread is not known to be valid | |
826 void MacroAssembler::get_thread() { | |
827 save_frame(0); // to avoid clobbering O0 | |
828 mov(G1, L0); // avoid clobbering G1 | |
829 mov(G5_method, L1); // avoid clobbering G5 | |
830 mov(G3, L2); // avoid clobbering G3 also | |
831 mov(G4, L5); // avoid clobbering G4 | |
832 #ifdef ASSERT | |
833 Address last_get_thread_addr(L3, (address)&last_get_thread); | |
834 sethi(last_get_thread_addr); | |
835 inc(L4, get_pc(L4) + 2 * BytesPerInstWord); // skip getpc() code + inc + st_ptr to point L4 at call | |
836 st_ptr(L4, last_get_thread_addr); | |
837 #endif | |
838 call(CAST_FROM_FN_PTR(address, reinitialize_thread), relocInfo::runtime_call_type); | |
839 delayed()->nop(); | |
840 mov(L0, G1); | |
841 mov(L1, G5_method); | |
842 mov(L2, G3); | |
843 mov(L5, G4); | |
844 restore(O0, 0, G2_thread); | |
845 } | |
846 | |
847 static Thread* verify_thread_subroutine(Thread* gthread_value) { | |
848 Thread* correct_value = ThreadLocalStorage::thread(); | |
849 guarantee(gthread_value == correct_value, "G2_thread value must be the thread"); | |
850 return correct_value; | |
851 } | |
852 | |
853 void MacroAssembler::verify_thread() { | |
854 if (VerifyThread) { | |
855 // NOTE: this chops off the heads of the 64-bit O registers. | |
856 #ifdef CC_INTERP | |
857 save_frame(0); | |
858 #else | |
859 // make sure G2_thread contains the right value | |
860 save_frame_and_mov(0, Lmethod, Lmethod); // to avoid clobbering O0 (and propagate Lmethod for -Xprof) | |
861 mov(G1, L1); // avoid clobbering G1 | |
862 // G2 saved below | |
863 mov(G3, L3); // avoid clobbering G3 | |
864 mov(G4, L4); // avoid clobbering G4 | |
865 mov(G5_method, L5); // avoid clobbering G5_method | |
866 #endif /* CC_INTERP */ | |
867 #if defined(COMPILER2) && !defined(_LP64) | |
868 // Save & restore possible 64-bit Long arguments in G-regs | |
869 srlx(G1,32,L0); | |
870 srlx(G4,32,L6); | |
871 #endif | |
872 call(CAST_FROM_FN_PTR(address,verify_thread_subroutine), relocInfo::runtime_call_type); | |
873 delayed()->mov(G2_thread, O0); | |
874 | |
875 mov(L1, G1); // Restore G1 | |
876 // G2 restored below | |
877 mov(L3, G3); // restore G3 | |
878 mov(L4, G4); // restore G4 | |
879 mov(L5, G5_method); // restore G5_method | |
880 #if defined(COMPILER2) && !defined(_LP64) | |
881 // Save & restore possible 64-bit Long arguments in G-regs | |
882 sllx(L0,32,G2); // Move old high G1 bits high in G2 | |
883 sllx(G1, 0,G1); // Clear current high G1 bits | |
884 or3 (G1,G2,G1); // Recover 64-bit G1 | |
885 sllx(L6,32,G2); // Move old high G4 bits high in G2 | |
886 sllx(G4, 0,G4); // Clear current high G4 bits | |
887 or3 (G4,G2,G4); // Recover 64-bit G4 | |
888 #endif | |
889 restore(O0, 0, G2_thread); | |
890 } | |
891 } | |
892 | |
893 | |
894 void MacroAssembler::save_thread(const Register thread_cache) { | |
895 verify_thread(); | |
896 if (thread_cache->is_valid()) { | |
897 assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile"); | |
898 mov(G2_thread, thread_cache); | |
899 } | |
900 if (VerifyThread) { | |
901 // smash G2_thread, as if the VM were about to anyway | |
902 set(0x67676767, G2_thread); | |
903 } | |
904 } | |
905 | |
906 | |
907 void MacroAssembler::restore_thread(const Register thread_cache) { | |
908 if (thread_cache->is_valid()) { | |
909 assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile"); | |
910 mov(thread_cache, G2_thread); | |
911 verify_thread(); | |
912 } else { | |
913 // do it the slow way | |
914 get_thread(); | |
915 } | |
916 } | |
917 | |
918 | |
919 // %%% maybe get rid of [re]set_last_Java_frame | |
920 void MacroAssembler::set_last_Java_frame(Register last_java_sp, Register last_Java_pc) { | |
921 assert_not_delayed(); | |
922 Address flags(G2_thread, | |
923 0, | |
924 in_bytes(JavaThread::frame_anchor_offset()) + | |
925 in_bytes(JavaFrameAnchor::flags_offset())); | |
926 Address pc_addr(G2_thread, | |
927 0, | |
928 in_bytes(JavaThread::last_Java_pc_offset())); | |
929 | |
930 // Always set last_Java_pc and flags first because once last_Java_sp is visible | |
931 // has_last_Java_frame is true and users will look at the rest of the fields. | |
932 // (Note: flags should always be zero before we get here so doesn't need to be set.) | |
933 | |
934 #ifdef ASSERT | |
935 // Verify that flags was zeroed on return to Java | |
936 Label PcOk; | |
937 save_frame(0); // to avoid clobbering O0 | |
938 ld_ptr(pc_addr, L0); | |
939 tst(L0); | |
940 #ifdef _LP64 | |
941 brx(Assembler::zero, false, Assembler::pt, PcOk); | |
942 #else | |
943 br(Assembler::zero, false, Assembler::pt, PcOk); | |
944 #endif // _LP64 | |
945 delayed() -> nop(); | |
946 stop("last_Java_pc not zeroed before leaving Java"); | |
947 bind(PcOk); | |
948 | |
949 // Verify that flags was zeroed on return to Java | |
950 Label FlagsOk; | |
951 ld(flags, L0); | |
952 tst(L0); | |
953 br(Assembler::zero, false, Assembler::pt, FlagsOk); | |
954 delayed() -> restore(); | |
955 stop("flags not zeroed before leaving Java"); | |
956 bind(FlagsOk); | |
957 #endif /* ASSERT */ | |
958 // | |
959 // When returning from calling out from Java mode the frame anchor's last_Java_pc | |
960 // will always be set to NULL. It is set here so that if we are doing a call to | |
961 // native (not VM) that we capture the known pc and don't have to rely on the | |
962 // native call having a standard frame linkage where we can find the pc. | |
963 | |
964 if (last_Java_pc->is_valid()) { | |
965 st_ptr(last_Java_pc, pc_addr); | |
966 } | |
967 | |
968 #ifdef _LP64 | |
969 #ifdef ASSERT | |
970 // Make sure that we have an odd stack | |
971 Label StackOk; | |
972 andcc(last_java_sp, 0x01, G0); | |
973 br(Assembler::notZero, false, Assembler::pt, StackOk); | |
974 delayed() -> nop(); | |
975 stop("Stack Not Biased in set_last_Java_frame"); | |
976 bind(StackOk); | |
977 #endif // ASSERT | |
978 assert( last_java_sp != G4_scratch, "bad register usage in set_last_Java_frame"); | |
979 add( last_java_sp, STACK_BIAS, G4_scratch ); | |
980 st_ptr(G4_scratch, Address(G2_thread, 0, in_bytes(JavaThread::last_Java_sp_offset()))); | |
981 #else | |
982 st_ptr(last_java_sp, Address(G2_thread, 0, in_bytes(JavaThread::last_Java_sp_offset()))); | |
983 #endif // _LP64 | |
984 } | |
985 | |
986 void MacroAssembler::reset_last_Java_frame(void) { | |
987 assert_not_delayed(); | |
988 | |
989 Address sp_addr(G2_thread, 0, in_bytes(JavaThread::last_Java_sp_offset())); | |
990 Address pc_addr(G2_thread, | |
991 0, | |
992 in_bytes(JavaThread::frame_anchor_offset()) + in_bytes(JavaFrameAnchor::last_Java_pc_offset())); | |
993 Address flags(G2_thread, | |
994 0, | |
995 in_bytes(JavaThread::frame_anchor_offset()) + in_bytes(JavaFrameAnchor::flags_offset())); | |
996 | |
997 #ifdef ASSERT | |
998 // check that it WAS previously set | |
999 #ifdef CC_INTERP | |
1000 save_frame(0); | |
1001 #else | |
1002 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod to helper frame for -Xprof | |
1003 #endif /* CC_INTERP */ | |
1004 ld_ptr(sp_addr, L0); | |
1005 tst(L0); | |
1006 breakpoint_trap(Assembler::zero, Assembler::ptr_cc); | |
1007 restore(); | |
1008 #endif // ASSERT | |
1009 | |
1010 st_ptr(G0, sp_addr); | |
1011 // Always return last_Java_pc to zero | |
1012 st_ptr(G0, pc_addr); | |
1013 // Always null flags after return to Java | |
1014 st(G0, flags); | |
1015 } | |
1016 | |
1017 | |
1018 void MacroAssembler::call_VM_base( | |
1019 Register oop_result, | |
1020 Register thread_cache, | |
1021 Register last_java_sp, | |
1022 address entry_point, | |
1023 int number_of_arguments, | |
1024 bool check_exceptions) | |
1025 { | |
1026 assert_not_delayed(); | |
1027 | |
1028 // determine last_java_sp register | |
1029 if (!last_java_sp->is_valid()) { | |
1030 last_java_sp = SP; | |
1031 } | |
1032 // debugging support | |
1033 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); | |
1034 | |
1035 // 64-bit last_java_sp is biased! | |
1036 set_last_Java_frame(last_java_sp, noreg); | |
1037 if (VerifyThread) mov(G2_thread, O0); // about to be smashed; pass early | |
1038 save_thread(thread_cache); | |
1039 // do the call | |
1040 call(entry_point, relocInfo::runtime_call_type); | |
1041 if (!VerifyThread) | |
1042 delayed()->mov(G2_thread, O0); // pass thread as first argument | |
1043 else | |
1044 delayed()->nop(); // (thread already passed) | |
1045 restore_thread(thread_cache); | |
1046 reset_last_Java_frame(); | |
1047 | |
1048 // check for pending exceptions. use Gtemp as scratch register. | |
1049 if (check_exceptions) { | |
1050 check_and_forward_exception(Gtemp); | |
1051 } | |
1052 | |
1053 // get oop result if there is one and reset the value in the thread | |
1054 if (oop_result->is_valid()) { | |
1055 get_vm_result(oop_result); | |
1056 } | |
1057 } | |
1058 | |
1059 void MacroAssembler::check_and_forward_exception(Register scratch_reg) | |
1060 { | |
1061 Label L; | |
1062 | |
1063 check_and_handle_popframe(scratch_reg); | |
1064 check_and_handle_earlyret(scratch_reg); | |
1065 | |
1066 Address exception_addr(G2_thread, 0, in_bytes(Thread::pending_exception_offset())); | |
1067 ld_ptr(exception_addr, scratch_reg); | |
1068 br_null(scratch_reg,false,pt,L); | |
1069 delayed()->nop(); | |
1070 // we use O7 linkage so that forward_exception_entry has the issuing PC | |
1071 call(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type); | |
1072 delayed()->nop(); | |
1073 bind(L); | |
1074 } | |
1075 | |
1076 | |
1077 void MacroAssembler::check_and_handle_popframe(Register scratch_reg) { | |
1078 } | |
1079 | |
1080 | |
1081 void MacroAssembler::check_and_handle_earlyret(Register scratch_reg) { | |
1082 } | |
1083 | |
1084 | |
1085 void MacroAssembler::call_VM(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { | |
1086 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions); | |
1087 } | |
1088 | |
1089 | |
1090 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions) { | |
1091 // O0 is reserved for the thread | |
1092 mov(arg_1, O1); | |
1093 call_VM(oop_result, entry_point, 1, check_exceptions); | |
1094 } | |
1095 | |
1096 | |
1097 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) { | |
1098 // O0 is reserved for the thread | |
1099 mov(arg_1, O1); | |
1100 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); | |
1101 call_VM(oop_result, entry_point, 2, check_exceptions); | |
1102 } | |
1103 | |
1104 | |
1105 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) { | |
1106 // O0 is reserved for the thread | |
1107 mov(arg_1, O1); | |
1108 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); | |
1109 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument"); | |
1110 call_VM(oop_result, entry_point, 3, check_exceptions); | |
1111 } | |
1112 | |
1113 | |
1114 | |
1115 // Note: The following call_VM overloadings are useful when a "save" | |
1116 // has already been performed by a stub, and the last Java frame is | |
1117 // the previous one. In that case, last_java_sp must be passed as FP | |
1118 // instead of SP. | |
1119 | |
1120 | |
1121 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments, bool check_exceptions) { | |
1122 call_VM_base(oop_result, noreg, last_java_sp, entry_point, number_of_arguments, check_exceptions); | |
1123 } | |
1124 | |
1125 | |
1126 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions) { | |
1127 // O0 is reserved for the thread | |
1128 mov(arg_1, O1); | |
1129 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); | |
1130 } | |
1131 | |
1132 | |
1133 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) { | |
1134 // O0 is reserved for the thread | |
1135 mov(arg_1, O1); | |
1136 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); | |
1137 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); | |
1138 } | |
1139 | |
1140 | |
1141 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) { | |
1142 // O0 is reserved for the thread | |
1143 mov(arg_1, O1); | |
1144 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); | |
1145 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument"); | |
1146 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); | |
1147 } | |
1148 | |
1149 | |
1150 | |
1151 void MacroAssembler::call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments) { | |
1152 assert_not_delayed(); | |
1153 save_thread(thread_cache); | |
1154 // do the call | |
1155 call(entry_point, relocInfo::runtime_call_type); | |
1156 delayed()->nop(); | |
1157 restore_thread(thread_cache); | |
1158 } | |
1159 | |
1160 | |
1161 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments) { | |
1162 call_VM_leaf_base(thread_cache, entry_point, number_of_arguments); | |
1163 } | |
1164 | |
1165 | |
1166 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1) { | |
1167 mov(arg_1, O0); | |
1168 call_VM_leaf(thread_cache, entry_point, 1); | |
1169 } | |
1170 | |
1171 | |
1172 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2) { | |
1173 mov(arg_1, O0); | |
1174 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument"); | |
1175 call_VM_leaf(thread_cache, entry_point, 2); | |
1176 } | |
1177 | |
1178 | |
1179 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3) { | |
1180 mov(arg_1, O0); | |
1181 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument"); | |
1182 mov(arg_3, O2); assert(arg_3 != O0 && arg_3 != O1, "smashed argument"); | |
1183 call_VM_leaf(thread_cache, entry_point, 3); | |
1184 } | |
1185 | |
1186 | |
1187 void MacroAssembler::get_vm_result(Register oop_result) { | |
1188 verify_thread(); | |
1189 Address vm_result_addr(G2_thread, 0, in_bytes(JavaThread::vm_result_offset())); | |
1190 ld_ptr( vm_result_addr, oop_result); | |
1191 st_ptr(G0, vm_result_addr); | |
1192 verify_oop(oop_result); | |
1193 } | |
1194 | |
1195 | |
1196 void MacroAssembler::get_vm_result_2(Register oop_result) { | |
1197 verify_thread(); | |
1198 Address vm_result_addr_2(G2_thread, 0, in_bytes(JavaThread::vm_result_2_offset())); | |
1199 ld_ptr(vm_result_addr_2, oop_result); | |
1200 st_ptr(G0, vm_result_addr_2); | |
1201 verify_oop(oop_result); | |
1202 } | |
1203 | |
1204 | |
1205 // We require that C code which does not return a value in vm_result will | |
1206 // leave it undisturbed. | |
1207 void MacroAssembler::set_vm_result(Register oop_result) { | |
1208 verify_thread(); | |
1209 Address vm_result_addr(G2_thread, 0, in_bytes(JavaThread::vm_result_offset())); | |
1210 verify_oop(oop_result); | |
1211 | |
1212 # ifdef ASSERT | |
1213 // Check that we are not overwriting any other oop. | |
1214 #ifdef CC_INTERP | |
1215 save_frame(0); | |
1216 #else | |
1217 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod for -Xprof | |
1218 #endif /* CC_INTERP */ | |
1219 ld_ptr(vm_result_addr, L0); | |
1220 tst(L0); | |
1221 restore(); | |
1222 breakpoint_trap(notZero, Assembler::ptr_cc); | |
1223 // } | |
1224 # endif | |
1225 | |
1226 st_ptr(oop_result, vm_result_addr); | |
1227 } | |
1228 | |
1229 | |
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1230 void MacroAssembler::card_table_write(jbyte* byte_map_base, |
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1231 Register tmp, Register obj) { |
0 | 1232 #ifdef _LP64 |
1233 srlx(obj, CardTableModRefBS::card_shift, obj); | |
1234 #else | |
1235 srl(obj, CardTableModRefBS::card_shift, obj); | |
1236 #endif | |
1237 assert( tmp != obj, "need separate temp reg"); | |
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1238 Address rs(tmp, (address)byte_map_base); |
0 | 1239 load_address(rs); |
1240 stb(G0, rs.base(), obj); | |
1241 } | |
1242 | |
1243 // %%% Note: The following six instructions have been moved, | |
1244 // unchanged, from assembler_sparc.inline.hpp. | |
1245 // They will be refactored at a later date. | |
1246 | |
1247 void MacroAssembler::sethi(intptr_t imm22a, | |
1248 Register d, | |
1249 bool ForceRelocatable, | |
1250 RelocationHolder const& rspec) { | |
1251 Address adr( d, (address)imm22a, rspec ); | |
1252 MacroAssembler::sethi( adr, ForceRelocatable ); | |
1253 } | |
1254 | |
1255 | |
1256 void MacroAssembler::sethi(Address& a, bool ForceRelocatable) { | |
1257 address save_pc; | |
1258 int shiftcnt; | |
1259 // if addr of local, do not need to load it | |
1260 assert(a.base() != FP && a.base() != SP, "just use ld or st for locals"); | |
1261 #ifdef _LP64 | |
1262 # ifdef CHECK_DELAY | |
1263 assert_not_delayed( (char *)"cannot put two instructions in delay slot" ); | |
1264 # endif | |
1265 v9_dep(); | |
1266 // ForceRelocatable = 1; | |
1267 save_pc = pc(); | |
1268 if (a.hi32() == 0 && a.low32() >= 0) { | |
1269 Assembler::sethi(a.low32(), a.base(), a.rspec()); | |
1270 } | |
1271 else if (a.hi32() == -1) { | |
1272 Assembler::sethi(~a.low32(), a.base(), a.rspec()); | |
1273 xor3(a.base(), ~low10(~0), a.base()); | |
1274 } | |
1275 else { | |
1276 Assembler::sethi(a.hi32(), a.base(), a.rspec() ); // 22 | |
1277 if ( a.hi32() & 0x3ff ) // Any bits? | |
1278 or3( a.base(), a.hi32() & 0x3ff ,a.base() ); // High 32 bits are now in low 32 | |
1279 if ( a.low32() & 0xFFFFFC00 ) { // done? | |
1280 if( (a.low32() >> 20) & 0xfff ) { // Any bits set? | |
1281 sllx(a.base(), 12, a.base()); // Make room for next 12 bits | |
1282 or3( a.base(), (a.low32() >> 20) & 0xfff,a.base() ); // Or in next 12 | |
1283 shiftcnt = 0; // We already shifted | |
1284 } | |
1285 else | |
1286 shiftcnt = 12; | |
1287 if( (a.low32() >> 10) & 0x3ff ) { | |
1288 sllx(a.base(), shiftcnt+10, a.base());// Make room for last 10 bits | |
1289 or3( a.base(), (a.low32() >> 10) & 0x3ff,a.base() ); // Or in next 10 | |
1290 shiftcnt = 0; | |
1291 } | |
1292 else | |
1293 shiftcnt = 10; | |
1294 sllx(a.base(), shiftcnt+10 , a.base()); // Shift leaving disp field 0'd | |
1295 } | |
1296 else | |
1297 sllx( a.base(), 32, a.base() ); | |
1298 } | |
1299 // Pad out the instruction sequence so it can be | |
1300 // patched later. | |
1301 if ( ForceRelocatable || (a.rtype() != relocInfo::none && | |
1302 a.rtype() != relocInfo::runtime_call_type) ) { | |
1303 while ( pc() < (save_pc + (7 * BytesPerInstWord )) ) | |
1304 nop(); | |
1305 } | |
1306 #else | |
1307 Assembler::sethi(a.hi(), a.base(), a.rspec()); | |
1308 #endif | |
1309 | |
1310 } | |
1311 | |
1312 int MacroAssembler::size_of_sethi(address a, bool worst_case) { | |
1313 #ifdef _LP64 | |
1314 if (worst_case) return 7; | |
1315 intptr_t iaddr = (intptr_t)a; | |
1316 int hi32 = (int)(iaddr >> 32); | |
1317 int lo32 = (int)(iaddr); | |
1318 int inst_count; | |
1319 if (hi32 == 0 && lo32 >= 0) | |
1320 inst_count = 1; | |
1321 else if (hi32 == -1) | |
1322 inst_count = 2; | |
1323 else { | |
1324 inst_count = 2; | |
1325 if ( hi32 & 0x3ff ) | |
1326 inst_count++; | |
1327 if ( lo32 & 0xFFFFFC00 ) { | |
1328 if( (lo32 >> 20) & 0xfff ) inst_count += 2; | |
1329 if( (lo32 >> 10) & 0x3ff ) inst_count += 2; | |
1330 } | |
1331 } | |
1332 return BytesPerInstWord * inst_count; | |
1333 #else | |
1334 return BytesPerInstWord; | |
1335 #endif | |
1336 } | |
1337 | |
1338 int MacroAssembler::worst_case_size_of_set() { | |
1339 return size_of_sethi(NULL, true) + 1; | |
1340 } | |
1341 | |
1342 void MacroAssembler::set(intptr_t value, Register d, | |
1343 RelocationHolder const& rspec) { | |
1344 Address val( d, (address)value, rspec); | |
1345 | |
1346 if ( rspec.type() == relocInfo::none ) { | |
1347 // can optimize | |
1348 if (-4096 <= value && value <= 4095) { | |
1349 or3(G0, value, d); // setsw (this leaves upper 32 bits sign-extended) | |
1350 return; | |
1351 } | |
1352 if (inv_hi22(hi22(value)) == value) { | |
1353 sethi(val); | |
1354 return; | |
1355 } | |
1356 } | |
1357 assert_not_delayed( (char *)"cannot put two instructions in delay slot" ); | |
1358 sethi( val ); | |
1359 if (rspec.type() != relocInfo::none || (value & 0x3ff) != 0) { | |
1360 add( d, value & 0x3ff, d, rspec); | |
1361 } | |
1362 } | |
1363 | |
1364 void MacroAssembler::setsw(int value, Register d, | |
1365 RelocationHolder const& rspec) { | |
1366 Address val( d, (address)value, rspec); | |
1367 if ( rspec.type() == relocInfo::none ) { | |
1368 // can optimize | |
1369 if (-4096 <= value && value <= 4095) { | |
1370 or3(G0, value, d); | |
1371 return; | |
1372 } | |
1373 if (inv_hi22(hi22(value)) == value) { | |
1374 sethi( val ); | |
1375 #ifndef _LP64 | |
1376 if ( value < 0 ) { | |
1377 assert_not_delayed(); | |
1378 sra (d, G0, d); | |
1379 } | |
1380 #endif | |
1381 return; | |
1382 } | |
1383 } | |
1384 assert_not_delayed(); | |
1385 sethi( val ); | |
1386 add( d, value & 0x3ff, d, rspec); | |
1387 | |
1388 // (A negative value could be loaded in 2 insns with sethi/xor, | |
1389 // but it would take a more complex relocation.) | |
1390 #ifndef _LP64 | |
1391 if ( value < 0) | |
1392 sra(d, G0, d); | |
1393 #endif | |
1394 } | |
1395 | |
1396 // %%% End of moved six set instructions. | |
1397 | |
1398 | |
1399 void MacroAssembler::set64(jlong value, Register d, Register tmp) { | |
1400 assert_not_delayed(); | |
1401 v9_dep(); | |
1402 | |
1403 int hi = (int)(value >> 32); | |
1404 int lo = (int)(value & ~0); | |
1405 // (Matcher::isSimpleConstant64 knows about the following optimizations.) | |
1406 if (Assembler::is_simm13(lo) && value == lo) { | |
1407 or3(G0, lo, d); | |
1408 } else if (hi == 0) { | |
1409 Assembler::sethi(lo, d); // hardware version zero-extends to upper 32 | |
1410 if (low10(lo) != 0) | |
1411 or3(d, low10(lo), d); | |
1412 } | |
1413 else if (hi == -1) { | |
1414 Assembler::sethi(~lo, d); // hardware version zero-extends to upper 32 | |
1415 xor3(d, low10(lo) ^ ~low10(~0), d); | |
1416 } | |
1417 else if (lo == 0) { | |
1418 if (Assembler::is_simm13(hi)) { | |
1419 or3(G0, hi, d); | |
1420 } else { | |
1421 Assembler::sethi(hi, d); // hardware version zero-extends to upper 32 | |
1422 if (low10(hi) != 0) | |
1423 or3(d, low10(hi), d); | |
1424 } | |
1425 sllx(d, 32, d); | |
1426 } | |
1427 else { | |
1428 Assembler::sethi(hi, tmp); | |
1429 Assembler::sethi(lo, d); // macro assembler version sign-extends | |
1430 if (low10(hi) != 0) | |
1431 or3 (tmp, low10(hi), tmp); | |
1432 if (low10(lo) != 0) | |
1433 or3 ( d, low10(lo), d); | |
1434 sllx(tmp, 32, tmp); | |
1435 or3 (d, tmp, d); | |
1436 } | |
1437 } | |
1438 | |
1439 // compute size in bytes of sparc frame, given | |
1440 // number of extraWords | |
1441 int MacroAssembler::total_frame_size_in_bytes(int extraWords) { | |
1442 | |
1443 int nWords = frame::memory_parameter_word_sp_offset; | |
1444 | |
1445 nWords += extraWords; | |
1446 | |
1447 if (nWords & 1) ++nWords; // round up to double-word | |
1448 | |
1449 return nWords * BytesPerWord; | |
1450 } | |
1451 | |
1452 | |
1453 // save_frame: given number of "extra" words in frame, | |
1454 // issue approp. save instruction (p 200, v8 manual) | |
1455 | |
1456 void MacroAssembler::save_frame(int extraWords = 0) { | |
1457 int delta = -total_frame_size_in_bytes(extraWords); | |
1458 if (is_simm13(delta)) { | |
1459 save(SP, delta, SP); | |
1460 } else { | |
1461 set(delta, G3_scratch); | |
1462 save(SP, G3_scratch, SP); | |
1463 } | |
1464 } | |
1465 | |
1466 | |
1467 void MacroAssembler::save_frame_c1(int size_in_bytes) { | |
1468 if (is_simm13(-size_in_bytes)) { | |
1469 save(SP, -size_in_bytes, SP); | |
1470 } else { | |
1471 set(-size_in_bytes, G3_scratch); | |
1472 save(SP, G3_scratch, SP); | |
1473 } | |
1474 } | |
1475 | |
1476 | |
1477 void MacroAssembler::save_frame_and_mov(int extraWords, | |
1478 Register s1, Register d1, | |
1479 Register s2, Register d2) { | |
1480 assert_not_delayed(); | |
1481 | |
1482 // The trick here is to use precisely the same memory word | |
1483 // that trap handlers also use to save the register. | |
1484 // This word cannot be used for any other purpose, but | |
1485 // it works fine to save the register's value, whether or not | |
1486 // an interrupt flushes register windows at any given moment! | |
1487 Address s1_addr; | |
1488 if (s1->is_valid() && (s1->is_in() || s1->is_local())) { | |
1489 s1_addr = s1->address_in_saved_window(); | |
1490 st_ptr(s1, s1_addr); | |
1491 } | |
1492 | |
1493 Address s2_addr; | |
1494 if (s2->is_valid() && (s2->is_in() || s2->is_local())) { | |
1495 s2_addr = s2->address_in_saved_window(); | |
1496 st_ptr(s2, s2_addr); | |
1497 } | |
1498 | |
1499 save_frame(extraWords); | |
1500 | |
1501 if (s1_addr.base() == SP) { | |
1502 ld_ptr(s1_addr.after_save(), d1); | |
1503 } else if (s1->is_valid()) { | |
1504 mov(s1->after_save(), d1); | |
1505 } | |
1506 | |
1507 if (s2_addr.base() == SP) { | |
1508 ld_ptr(s2_addr.after_save(), d2); | |
1509 } else if (s2->is_valid()) { | |
1510 mov(s2->after_save(), d2); | |
1511 } | |
1512 } | |
1513 | |
1514 | |
1515 Address MacroAssembler::allocate_oop_address(jobject obj, Register d) { | |
1516 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); | |
1517 int oop_index = oop_recorder()->allocate_index(obj); | |
1518 return Address(d, address(obj), oop_Relocation::spec(oop_index)); | |
1519 } | |
1520 | |
1521 | |
1522 Address MacroAssembler::constant_oop_address(jobject obj, Register d) { | |
1523 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); | |
1524 int oop_index = oop_recorder()->find_index(obj); | |
1525 return Address(d, address(obj), oop_Relocation::spec(oop_index)); | |
1526 } | |
1527 | |
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1528 void MacroAssembler::set_narrow_oop(jobject obj, Register d) { |
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1529 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
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1530 int oop_index = oop_recorder()->find_index(obj); |
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1531 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
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1533 assert_not_delayed(); |
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1534 // Relocation with special format (see relocInfo_sparc.hpp). |
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1535 relocate(rspec, 1); |
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1536 // Assembler::sethi(0x3fffff, d); |
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1537 emit_long( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(0x3fffff) ); |
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1538 // Don't add relocation for 'add'. Do patching during 'sethi' processing. |
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1539 add(d, 0x3ff, d); |
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1540 |
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1541 } |
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1542 |
0 | 1543 |
1544 void MacroAssembler::align(int modulus) { | |
1545 while (offset() % modulus != 0) nop(); | |
1546 } | |
1547 | |
1548 | |
1549 void MacroAssembler::safepoint() { | |
1550 relocate(breakpoint_Relocation::spec(breakpoint_Relocation::safepoint)); | |
1551 } | |
1552 | |
1553 | |
1554 void RegistersForDebugging::print(outputStream* s) { | |
1555 int j; | |
1556 for ( j = 0; j < 8; ++j ) | |
1557 if ( j != 6 ) s->print_cr("i%d = 0x%.16lx", j, i[j]); | |
1558 else s->print_cr( "fp = 0x%.16lx", i[j]); | |
1559 s->cr(); | |
1560 | |
1561 for ( j = 0; j < 8; ++j ) | |
1562 s->print_cr("l%d = 0x%.16lx", j, l[j]); | |
1563 s->cr(); | |
1564 | |
1565 for ( j = 0; j < 8; ++j ) | |
1566 if ( j != 6 ) s->print_cr("o%d = 0x%.16lx", j, o[j]); | |
1567 else s->print_cr( "sp = 0x%.16lx", o[j]); | |
1568 s->cr(); | |
1569 | |
1570 for ( j = 0; j < 8; ++j ) | |
1571 s->print_cr("g%d = 0x%.16lx", j, g[j]); | |
1572 s->cr(); | |
1573 | |
1574 // print out floats with compression | |
1575 for (j = 0; j < 32; ) { | |
1576 jfloat val = f[j]; | |
1577 int last = j; | |
1578 for ( ; last+1 < 32; ++last ) { | |
1579 char b1[1024], b2[1024]; | |
1580 sprintf(b1, "%f", val); | |
1581 sprintf(b2, "%f", f[last+1]); | |
1582 if (strcmp(b1, b2)) | |
1583 break; | |
1584 } | |
1585 s->print("f%d", j); | |
1586 if ( j != last ) s->print(" - f%d", last); | |
1587 s->print(" = %f", val); | |
1588 s->fill_to(25); | |
1589 s->print_cr(" (0x%x)", val); | |
1590 j = last + 1; | |
1591 } | |
1592 s->cr(); | |
1593 | |
1594 // and doubles (evens only) | |
1595 for (j = 0; j < 32; ) { | |
1596 jdouble val = d[j]; | |
1597 int last = j; | |
1598 for ( ; last+1 < 32; ++last ) { | |
1599 char b1[1024], b2[1024]; | |
1600 sprintf(b1, "%f", val); | |
1601 sprintf(b2, "%f", d[last+1]); | |
1602 if (strcmp(b1, b2)) | |
1603 break; | |
1604 } | |
1605 s->print("d%d", 2 * j); | |
1606 if ( j != last ) s->print(" - d%d", last); | |
1607 s->print(" = %f", val); | |
1608 s->fill_to(30); | |
1609 s->print("(0x%x)", *(int*)&val); | |
1610 s->fill_to(42); | |
1611 s->print_cr("(0x%x)", *(1 + (int*)&val)); | |
1612 j = last + 1; | |
1613 } | |
1614 s->cr(); | |
1615 } | |
1616 | |
1617 void RegistersForDebugging::save_registers(MacroAssembler* a) { | |
1618 a->sub(FP, round_to(sizeof(RegistersForDebugging), sizeof(jdouble)) - STACK_BIAS, O0); | |
1619 a->flush_windows(); | |
1620 int i; | |
1621 for (i = 0; i < 8; ++i) { | |
1622 a->ld_ptr(as_iRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, i_offset(i)); | |
1623 a->ld_ptr(as_lRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, l_offset(i)); | |
1624 a->st_ptr(as_oRegister(i)->after_save(), O0, o_offset(i)); | |
1625 a->st_ptr(as_gRegister(i)->after_save(), O0, g_offset(i)); | |
1626 } | |
1627 for (i = 0; i < 32; ++i) { | |
1628 a->stf(FloatRegisterImpl::S, as_FloatRegister(i), O0, f_offset(i)); | |
1629 } | |
1630 for (i = 0; i < (VM_Version::v9_instructions_work() ? 64 : 32); i += 2) { | |
1631 a->stf(FloatRegisterImpl::D, as_FloatRegister(i), O0, d_offset(i)); | |
1632 } | |
1633 } | |
1634 | |
1635 void RegistersForDebugging::restore_registers(MacroAssembler* a, Register r) { | |
1636 for (int i = 1; i < 8; ++i) { | |
1637 a->ld_ptr(r, g_offset(i), as_gRegister(i)); | |
1638 } | |
1639 for (int j = 0; j < 32; ++j) { | |
1640 a->ldf(FloatRegisterImpl::S, O0, f_offset(j), as_FloatRegister(j)); | |
1641 } | |
1642 for (int k = 0; k < (VM_Version::v9_instructions_work() ? 64 : 32); k += 2) { | |
1643 a->ldf(FloatRegisterImpl::D, O0, d_offset(k), as_FloatRegister(k)); | |
1644 } | |
1645 } | |
1646 | |
1647 | |
1648 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack | |
1649 void MacroAssembler::push_fTOS() { | |
1650 // %%%%%% need to implement this | |
1651 } | |
1652 | |
1653 // pops double TOS element from CPU stack and pushes on FPU stack | |
1654 void MacroAssembler::pop_fTOS() { | |
1655 // %%%%%% need to implement this | |
1656 } | |
1657 | |
1658 void MacroAssembler::empty_FPU_stack() { | |
1659 // %%%%%% need to implement this | |
1660 } | |
1661 | |
1662 void MacroAssembler::_verify_oop(Register reg, const char* msg, const char * file, int line) { | |
1663 // plausibility check for oops | |
1664 if (!VerifyOops) return; | |
1665 | |
1666 if (reg == G0) return; // always NULL, which is always an oop | |
1667 | |
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1668 char buffer[64]; |
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1669 #ifdef COMPILER1 |
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1670 if (CommentedAssembly) { |
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1671 snprintf(buffer, sizeof(buffer), "verify_oop at %d", offset()); |
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1672 block_comment(buffer); |
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1673 } |
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1674 #endif |
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1675 |
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1676 int len = strlen(file) + strlen(msg) + 1 + 4; |
0 | 1677 sprintf(buffer, "%d", line); |
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1678 len += strlen(buffer); |
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1679 sprintf(buffer, " at offset %d ", offset()); |
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1680 len += strlen(buffer); |
0 | 1681 char * real_msg = new char[len]; |
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1682 sprintf(real_msg, "%s%s(%s:%d)", msg, buffer, file, line); |
0 | 1683 |
1684 // Call indirectly to solve generation ordering problem | |
1685 Address a(O7, (address)StubRoutines::verify_oop_subroutine_entry_address()); | |
1686 | |
1687 // Make some space on stack above the current register window. | |
1688 // Enough to hold 8 64-bit registers. | |
1689 add(SP,-8*8,SP); | |
1690 | |
1691 // Save some 64-bit registers; a normal 'save' chops the heads off | |
1692 // of 64-bit longs in the 32-bit build. | |
1693 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8); | |
1694 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8); | |
1695 mov(reg,O0); // Move arg into O0; arg might be in O7 which is about to be crushed | |
1696 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8); | |
1697 | |
1698 set((intptr_t)real_msg, O1); | |
1699 // Load address to call to into O7 | |
1700 load_ptr_contents(a, O7); | |
1701 // Register call to verify_oop_subroutine | |
1702 callr(O7, G0); | |
1703 delayed()->nop(); | |
1704 // recover frame size | |
1705 add(SP, 8*8,SP); | |
1706 } | |
1707 | |
1708 void MacroAssembler::_verify_oop_addr(Address addr, const char* msg, const char * file, int line) { | |
1709 // plausibility check for oops | |
1710 if (!VerifyOops) return; | |
1711 | |
1712 char buffer[64]; | |
1713 sprintf(buffer, "%d", line); | |
1714 int len = strlen(file) + strlen(msg) + 1 + 4 + strlen(buffer); | |
1715 sprintf(buffer, " at SP+%d ", addr.disp()); | |
1716 len += strlen(buffer); | |
1717 char * real_msg = new char[len]; | |
1718 sprintf(real_msg, "%s at SP+%d (%s:%d)", msg, addr.disp(), file, line); | |
1719 | |
1720 // Call indirectly to solve generation ordering problem | |
1721 Address a(O7, (address)StubRoutines::verify_oop_subroutine_entry_address()); | |
1722 | |
1723 // Make some space on stack above the current register window. | |
1724 // Enough to hold 8 64-bit registers. | |
1725 add(SP,-8*8,SP); | |
1726 | |
1727 // Save some 64-bit registers; a normal 'save' chops the heads off | |
1728 // of 64-bit longs in the 32-bit build. | |
1729 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8); | |
1730 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8); | |
1731 ld_ptr(addr.base(), addr.disp() + 8*8, O0); // Load arg into O0; arg might be in O7 which is about to be crushed | |
1732 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8); | |
1733 | |
1734 set((intptr_t)real_msg, O1); | |
1735 // Load address to call to into O7 | |
1736 load_ptr_contents(a, O7); | |
1737 // Register call to verify_oop_subroutine | |
1738 callr(O7, G0); | |
1739 delayed()->nop(); | |
1740 // recover frame size | |
1741 add(SP, 8*8,SP); | |
1742 } | |
1743 | |
1744 // side-door communication with signalHandler in os_solaris.cpp | |
1745 address MacroAssembler::_verify_oop_implicit_branch[3] = { NULL }; | |
1746 | |
1747 // This macro is expanded just once; it creates shared code. Contract: | |
1748 // receives an oop in O0. Must restore O0 & O7 from TLS. Must not smash ANY | |
1749 // registers, including flags. May not use a register 'save', as this blows | |
1750 // the high bits of the O-regs if they contain Long values. Acts as a 'leaf' | |
1751 // call. | |
1752 void MacroAssembler::verify_oop_subroutine() { | |
1753 assert( VM_Version::v9_instructions_work(), "VerifyOops not supported for V8" ); | |
1754 | |
1755 // Leaf call; no frame. | |
1756 Label succeed, fail, null_or_fail; | |
1757 | |
1758 // O0 and O7 were saved already (O0 in O0's TLS home, O7 in O5's TLS home). | |
1759 // O0 is now the oop to be checked. O7 is the return address. | |
1760 Register O0_obj = O0; | |
1761 | |
1762 // Save some more registers for temps. | |
1763 stx(O2,SP,frame::register_save_words*wordSize+STACK_BIAS+2*8); | |
1764 stx(O3,SP,frame::register_save_words*wordSize+STACK_BIAS+3*8); | |
1765 stx(O4,SP,frame::register_save_words*wordSize+STACK_BIAS+4*8); | |
1766 stx(O5,SP,frame::register_save_words*wordSize+STACK_BIAS+5*8); | |
1767 | |
1768 // Save flags | |
1769 Register O5_save_flags = O5; | |
1770 rdccr( O5_save_flags ); | |
1771 | |
1772 { // count number of verifies | |
1773 Register O2_adr = O2; | |
1774 Register O3_accum = O3; | |
1775 Address count_addr( O2_adr, (address) StubRoutines::verify_oop_count_addr() ); | |
1776 sethi(count_addr); | |
1777 ld(count_addr, O3_accum); | |
1778 inc(O3_accum); | |
1779 st(O3_accum, count_addr); | |
1780 } | |
1781 | |
1782 Register O2_mask = O2; | |
1783 Register O3_bits = O3; | |
1784 Register O4_temp = O4; | |
1785 | |
1786 // mark lower end of faulting range | |
1787 assert(_verify_oop_implicit_branch[0] == NULL, "set once"); | |
1788 _verify_oop_implicit_branch[0] = pc(); | |
1789 | |
1790 // We can't check the mark oop because it could be in the process of | |
1791 // locking or unlocking while this is running. | |
1792 set(Universe::verify_oop_mask (), O2_mask); | |
1793 set(Universe::verify_oop_bits (), O3_bits); | |
1794 | |
1795 // assert((obj & oop_mask) == oop_bits); | |
1796 and3(O0_obj, O2_mask, O4_temp); | |
1797 cmp(O4_temp, O3_bits); | |
1798 brx(notEqual, false, pn, null_or_fail); | |
1799 delayed()->nop(); | |
1800 | |
1801 if ((NULL_WORD & Universe::verify_oop_mask()) == Universe::verify_oop_bits()) { | |
1802 // the null_or_fail case is useless; must test for null separately | |
1803 br_null(O0_obj, false, pn, succeed); | |
1804 delayed()->nop(); | |
1805 } | |
1806 | |
1807 // Check the klassOop of this object for being in the right area of memory. | |
1808 // Cannot do the load in the delay above slot in case O0 is null | |
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1809 load_klass(O0_obj, O0_obj); |
0 | 1810 // assert((klass & klass_mask) == klass_bits); |
1811 if( Universe::verify_klass_mask() != Universe::verify_oop_mask() ) | |
1812 set(Universe::verify_klass_mask(), O2_mask); | |
1813 if( Universe::verify_klass_bits() != Universe::verify_oop_bits() ) | |
1814 set(Universe::verify_klass_bits(), O3_bits); | |
1815 and3(O0_obj, O2_mask, O4_temp); | |
1816 cmp(O4_temp, O3_bits); | |
1817 brx(notEqual, false, pn, fail); | |
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1818 delayed()->nop(); |
0 | 1819 // Check the klass's klass |
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1820 load_klass(O0_obj, O0_obj); |
0 | 1821 and3(O0_obj, O2_mask, O4_temp); |
1822 cmp(O4_temp, O3_bits); | |
1823 brx(notEqual, false, pn, fail); | |
1824 delayed()->wrccr( O5_save_flags ); // Restore CCR's | |
1825 | |
1826 // mark upper end of faulting range | |
1827 _verify_oop_implicit_branch[1] = pc(); | |
1828 | |
1829 //----------------------- | |
1830 // all tests pass | |
1831 bind(succeed); | |
1832 | |
1833 // Restore prior 64-bit registers | |
1834 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+0*8,O0); | |
1835 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+1*8,O1); | |
1836 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+2*8,O2); | |
1837 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+3*8,O3); | |
1838 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+4*8,O4); | |
1839 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+5*8,O5); | |
1840 | |
1841 retl(); // Leaf return; restore prior O7 in delay slot | |
1842 delayed()->ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+7*8,O7); | |
1843 | |
1844 //----------------------- | |
1845 bind(null_or_fail); // nulls are less common but OK | |
1846 br_null(O0_obj, false, pt, succeed); | |
1847 delayed()->wrccr( O5_save_flags ); // Restore CCR's | |
1848 | |
1849 //----------------------- | |
1850 // report failure: | |
1851 bind(fail); | |
1852 _verify_oop_implicit_branch[2] = pc(); | |
1853 | |
1854 wrccr( O5_save_flags ); // Restore CCR's | |
1855 | |
1856 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2)); | |
1857 | |
1858 // stop_subroutine expects message pointer in I1. | |
1859 mov(I1, O1); | |
1860 | |
1861 // Restore prior 64-bit registers | |
1862 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+0*8,I0); | |
1863 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+1*8,I1); | |
1864 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+2*8,I2); | |
1865 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+3*8,I3); | |
1866 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+4*8,I4); | |
1867 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+5*8,I5); | |
1868 | |
1869 // factor long stop-sequence into subroutine to save space | |
1870 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet"); | |
1871 | |
1872 // call indirectly to solve generation ordering problem | |
1873 Address a(O5, (address)StubRoutines::Sparc::stop_subroutine_entry_address()); | |
1874 load_ptr_contents(a, O5); | |
1875 jmpl(O5, 0, O7); | |
1876 delayed()->nop(); | |
1877 } | |
1878 | |
1879 | |
1880 void MacroAssembler::stop(const char* msg) { | |
1881 // save frame first to get O7 for return address | |
1882 // add one word to size in case struct is odd number of words long | |
1883 // It must be doubleword-aligned for storing doubles into it. | |
1884 | |
1885 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2)); | |
1886 | |
1887 // stop_subroutine expects message pointer in I1. | |
1888 set((intptr_t)msg, O1); | |
1889 | |
1890 // factor long stop-sequence into subroutine to save space | |
1891 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet"); | |
1892 | |
1893 // call indirectly to solve generation ordering problem | |
1894 Address a(O5, (address)StubRoutines::Sparc::stop_subroutine_entry_address()); | |
1895 load_ptr_contents(a, O5); | |
1896 jmpl(O5, 0, O7); | |
1897 delayed()->nop(); | |
1898 | |
1899 breakpoint_trap(); // make stop actually stop rather than writing | |
1900 // unnoticeable results in the output files. | |
1901 | |
1902 // restore(); done in callee to save space! | |
1903 } | |
1904 | |
1905 | |
1906 void MacroAssembler::warn(const char* msg) { | |
1907 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2)); | |
1908 RegistersForDebugging::save_registers(this); | |
1909 mov(O0, L0); | |
1910 set((intptr_t)msg, O0); | |
1911 call( CAST_FROM_FN_PTR(address, warning) ); | |
1912 delayed()->nop(); | |
1913 // ret(); | |
1914 // delayed()->restore(); | |
1915 RegistersForDebugging::restore_registers(this, L0); | |
1916 restore(); | |
1917 } | |
1918 | |
1919 | |
1920 void MacroAssembler::untested(const char* what) { | |
1921 // We must be able to turn interactive prompting off | |
1922 // in order to run automated test scripts on the VM | |
1923 // Use the flag ShowMessageBoxOnError | |
1924 | |
1925 char* b = new char[1024]; | |
1926 sprintf(b, "untested: %s", what); | |
1927 | |
1928 if ( ShowMessageBoxOnError ) stop(b); | |
1929 else warn(b); | |
1930 } | |
1931 | |
1932 | |
1933 void MacroAssembler::stop_subroutine() { | |
1934 RegistersForDebugging::save_registers(this); | |
1935 | |
1936 // for the sake of the debugger, stick a PC on the current frame | |
1937 // (this assumes that the caller has performed an extra "save") | |
1938 mov(I7, L7); | |
1939 add(O7, -7 * BytesPerInt, I7); | |
1940 | |
1941 save_frame(); // one more save to free up another O7 register | |
1942 mov(I0, O1); // addr of reg save area | |
1943 | |
1944 // We expect pointer to message in I1. Caller must set it up in O1 | |
1945 mov(I1, O0); // get msg | |
1946 call (CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type); | |
1947 delayed()->nop(); | |
1948 | |
1949 restore(); | |
1950 | |
1951 RegistersForDebugging::restore_registers(this, O0); | |
1952 | |
1953 save_frame(0); | |
1954 call(CAST_FROM_FN_PTR(address,breakpoint)); | |
1955 delayed()->nop(); | |
1956 restore(); | |
1957 | |
1958 mov(L7, I7); | |
1959 retl(); | |
1960 delayed()->restore(); // see stop above | |
1961 } | |
1962 | |
1963 | |
1964 void MacroAssembler::debug(char* msg, RegistersForDebugging* regs) { | |
1965 if ( ShowMessageBoxOnError ) { | |
1966 JavaThreadState saved_state = JavaThread::current()->thread_state(); | |
1967 JavaThread::current()->set_thread_state(_thread_in_vm); | |
1968 { | |
1969 // In order to get locks work, we need to fake a in_VM state | |
1970 ttyLocker ttyl; | |
1971 ::tty->print_cr("EXECUTION STOPPED: %s\n", msg); | |
1972 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { | |
1973 ::tty->print_cr("Interpreter::bytecode_counter = %d", BytecodeCounter::counter_value()); | |
1974 } | |
1975 if (os::message_box(msg, "Execution stopped, print registers?")) | |
1976 regs->print(::tty); | |
1977 } | |
1978 ThreadStateTransition::transition(JavaThread::current(), _thread_in_vm, saved_state); | |
1979 } | |
1980 else | |
1981 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); | |
1982 assert(false, "error"); | |
1983 } | |
1984 | |
1985 | |
1986 #ifndef PRODUCT | |
1987 void MacroAssembler::test() { | |
1988 ResourceMark rm; | |
1989 | |
1990 CodeBuffer cb("test", 10000, 10000); | |
1991 MacroAssembler* a = new MacroAssembler(&cb); | |
1992 VM_Version::allow_all(); | |
1993 a->test_v9(); | |
1994 a->test_v8_onlys(); | |
1995 VM_Version::revert(); | |
1996 | |
1997 StubRoutines::Sparc::test_stop_entry()(); | |
1998 } | |
1999 #endif | |
2000 | |
2001 | |
2002 void MacroAssembler::calc_mem_param_words(Register Rparam_words, Register Rresult) { | |
2003 subcc( Rparam_words, Argument::n_register_parameters, Rresult); // how many mem words? | |
2004 Label no_extras; | |
2005 br( negative, true, pt, no_extras ); // if neg, clear reg | |
2006 delayed()->set( 0, Rresult); // annuled, so only if taken | |
2007 bind( no_extras ); | |
2008 } | |
2009 | |
2010 | |
2011 void MacroAssembler::calc_frame_size(Register Rextra_words, Register Rresult) { | |
2012 #ifdef _LP64 | |
2013 add(Rextra_words, frame::memory_parameter_word_sp_offset, Rresult); | |
2014 #else | |
2015 add(Rextra_words, frame::memory_parameter_word_sp_offset + 1, Rresult); | |
2016 #endif | |
2017 bclr(1, Rresult); | |
2018 sll(Rresult, LogBytesPerWord, Rresult); // Rresult has total frame bytes | |
2019 } | |
2020 | |
2021 | |
2022 void MacroAssembler::calc_frame_size_and_save(Register Rextra_words, Register Rresult) { | |
2023 calc_frame_size(Rextra_words, Rresult); | |
2024 neg(Rresult); | |
2025 save(SP, Rresult, SP); | |
2026 } | |
2027 | |
2028 | |
2029 // --------------------------------------------------------- | |
2030 Assembler::RCondition cond2rcond(Assembler::Condition c) { | |
2031 switch (c) { | |
2032 /*case zero: */ | |
2033 case Assembler::equal: return Assembler::rc_z; | |
2034 case Assembler::lessEqual: return Assembler::rc_lez; | |
2035 case Assembler::less: return Assembler::rc_lz; | |
2036 /*case notZero:*/ | |
2037 case Assembler::notEqual: return Assembler::rc_nz; | |
2038 case Assembler::greater: return Assembler::rc_gz; | |
2039 case Assembler::greaterEqual: return Assembler::rc_gez; | |
2040 } | |
2041 ShouldNotReachHere(); | |
2042 return Assembler::rc_z; | |
2043 } | |
2044 | |
2045 // compares register with zero and branches. NOT FOR USE WITH 64-bit POINTERS | |
2046 void MacroAssembler::br_zero( Condition c, bool a, Predict p, Register s1, Label& L) { | |
2047 tst(s1); | |
2048 br (c, a, p, L); | |
2049 } | |
2050 | |
2051 | |
2052 // Compares a pointer register with zero and branches on null. | |
2053 // Does a test & branch on 32-bit systems and a register-branch on 64-bit. | |
2054 void MacroAssembler::br_null( Register s1, bool a, Predict p, Label& L ) { | |
2055 assert_not_delayed(); | |
2056 #ifdef _LP64 | |
2057 bpr( rc_z, a, p, s1, L ); | |
2058 #else | |
2059 tst(s1); | |
2060 br ( zero, a, p, L ); | |
2061 #endif | |
2062 } | |
2063 | |
2064 void MacroAssembler::br_notnull( Register s1, bool a, Predict p, Label& L ) { | |
2065 assert_not_delayed(); | |
2066 #ifdef _LP64 | |
2067 bpr( rc_nz, a, p, s1, L ); | |
2068 #else | |
2069 tst(s1); | |
2070 br ( notZero, a, p, L ); | |
2071 #endif | |
2072 } | |
2073 | |
342
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2074 void MacroAssembler::br_on_reg_cond( RCondition rc, bool a, Predict p, |
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2075 Register s1, address d, |
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2076 relocInfo::relocType rt ) { |
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2077 if (VM_Version::v9_instructions_work()) { |
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2078 bpr(rc, a, p, s1, d, rt); |
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2079 } else { |
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2080 tst(s1); |
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2081 br(reg_cond_to_cc_cond(rc), a, p, d, rt); |
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2082 } |
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2083 } |
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2084 |
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2085 void MacroAssembler::br_on_reg_cond( RCondition rc, bool a, Predict p, |
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2086 Register s1, Label& L ) { |
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2087 if (VM_Version::v9_instructions_work()) { |
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2088 bpr(rc, a, p, s1, L); |
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2089 } else { |
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2090 tst(s1); |
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2091 br(reg_cond_to_cc_cond(rc), a, p, L); |
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2092 } |
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2093 } |
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2094 |
0 | 2095 |
2096 // instruction sequences factored across compiler & interpreter | |
2097 | |
2098 | |
2099 void MacroAssembler::lcmp( Register Ra_hi, Register Ra_low, | |
2100 Register Rb_hi, Register Rb_low, | |
2101 Register Rresult) { | |
2102 | |
2103 Label check_low_parts, done; | |
2104 | |
2105 cmp(Ra_hi, Rb_hi ); // compare hi parts | |
2106 br(equal, true, pt, check_low_parts); | |
2107 delayed()->cmp(Ra_low, Rb_low); // test low parts | |
2108 | |
2109 // And, with an unsigned comparison, it does not matter if the numbers | |
2110 // are negative or not. | |
2111 // E.g., -2 cmp -1: the low parts are 0xfffffffe and 0xffffffff. | |
2112 // The second one is bigger (unsignedly). | |
2113 | |
2114 // Other notes: The first move in each triplet can be unconditional | |
2115 // (and therefore probably prefetchable). | |
2116 // And the equals case for the high part does not need testing, | |
2117 // since that triplet is reached only after finding the high halves differ. | |
2118 | |
2119 if (VM_Version::v9_instructions_work()) { | |
2120 | |
2121 mov ( -1, Rresult); | |
2122 ba( false, done ); delayed()-> movcc(greater, false, icc, 1, Rresult); | |
2123 } | |
2124 else { | |
2125 br(less, true, pt, done); delayed()-> set(-1, Rresult); | |
2126 br(greater, true, pt, done); delayed()-> set( 1, Rresult); | |
2127 } | |
2128 | |
2129 bind( check_low_parts ); | |
2130 | |
2131 if (VM_Version::v9_instructions_work()) { | |
2132 mov( -1, Rresult); | |
2133 movcc(equal, false, icc, 0, Rresult); | |
2134 movcc(greaterUnsigned, false, icc, 1, Rresult); | |
2135 } | |
2136 else { | |
2137 set(-1, Rresult); | |
2138 br(equal, true, pt, done); delayed()->set( 0, Rresult); | |
2139 br(greaterUnsigned, true, pt, done); delayed()->set( 1, Rresult); | |
2140 } | |
2141 bind( done ); | |
2142 } | |
2143 | |
2144 void MacroAssembler::lneg( Register Rhi, Register Rlow ) { | |
2145 subcc( G0, Rlow, Rlow ); | |
2146 subc( G0, Rhi, Rhi ); | |
2147 } | |
2148 | |
2149 void MacroAssembler::lshl( Register Rin_high, Register Rin_low, | |
2150 Register Rcount, | |
2151 Register Rout_high, Register Rout_low, | |
2152 Register Rtemp ) { | |
2153 | |
2154 | |
2155 Register Ralt_count = Rtemp; | |
2156 Register Rxfer_bits = Rtemp; | |
2157 | |
2158 assert( Ralt_count != Rin_high | |
2159 && Ralt_count != Rin_low | |
2160 && Ralt_count != Rcount | |
2161 && Rxfer_bits != Rin_low | |
2162 && Rxfer_bits != Rin_high | |
2163 && Rxfer_bits != Rcount | |
2164 && Rxfer_bits != Rout_low | |
2165 && Rout_low != Rin_high, | |
2166 "register alias checks"); | |
2167 | |
2168 Label big_shift, done; | |
2169 | |
2170 // This code can be optimized to use the 64 bit shifts in V9. | |
2171 // Here we use the 32 bit shifts. | |
2172 | |
2173 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits | |
2174 subcc(Rcount, 31, Ralt_count); | |
2175 br(greater, true, pn, big_shift); | |
2176 delayed()-> | |
2177 dec(Ralt_count); | |
2178 | |
2179 // shift < 32 bits, Ralt_count = Rcount-31 | |
2180 | |
2181 // We get the transfer bits by shifting right by 32-count the low | |
2182 // register. This is done by shifting right by 31-count and then by one | |
2183 // more to take care of the special (rare) case where count is zero | |
2184 // (shifting by 32 would not work). | |
2185 | |
2186 neg( Ralt_count ); | |
2187 | |
2188 // The order of the next two instructions is critical in the case where | |
2189 // Rin and Rout are the same and should not be reversed. | |
2190 | |
2191 srl( Rin_low, Ralt_count, Rxfer_bits ); // shift right by 31-count | |
2192 if (Rcount != Rout_low) { | |
2193 sll( Rin_low, Rcount, Rout_low ); // low half | |
2194 } | |
2195 sll( Rin_high, Rcount, Rout_high ); | |
2196 if (Rcount == Rout_low) { | |
2197 sll( Rin_low, Rcount, Rout_low ); // low half | |
2198 } | |
2199 srl( Rxfer_bits, 1, Rxfer_bits ); // shift right by one more | |
2200 ba (false, done); | |
2201 delayed()-> | |
2202 or3( Rout_high, Rxfer_bits, Rout_high); // new hi value: or in shifted old hi part and xfer from low | |
2203 | |
2204 // shift >= 32 bits, Ralt_count = Rcount-32 | |
2205 bind(big_shift); | |
2206 sll( Rin_low, Ralt_count, Rout_high ); | |
2207 clr( Rout_low ); | |
2208 | |
2209 bind(done); | |
2210 } | |
2211 | |
2212 | |
2213 void MacroAssembler::lshr( Register Rin_high, Register Rin_low, | |
2214 Register Rcount, | |
2215 Register Rout_high, Register Rout_low, | |
2216 Register Rtemp ) { | |
2217 | |
2218 Register Ralt_count = Rtemp; | |
2219 Register Rxfer_bits = Rtemp; | |
2220 | |
2221 assert( Ralt_count != Rin_high | |
2222 && Ralt_count != Rin_low | |
2223 && Ralt_count != Rcount | |
2224 && Rxfer_bits != Rin_low | |
2225 && Rxfer_bits != Rin_high | |
2226 && Rxfer_bits != Rcount | |
2227 && Rxfer_bits != Rout_high | |
2228 && Rout_high != Rin_low, | |
2229 "register alias checks"); | |
2230 | |
2231 Label big_shift, done; | |
2232 | |
2233 // This code can be optimized to use the 64 bit shifts in V9. | |
2234 // Here we use the 32 bit shifts. | |
2235 | |
2236 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits | |
2237 subcc(Rcount, 31, Ralt_count); | |
2238 br(greater, true, pn, big_shift); | |
2239 delayed()->dec(Ralt_count); | |
2240 | |
2241 // shift < 32 bits, Ralt_count = Rcount-31 | |
2242 | |
2243 // We get the transfer bits by shifting left by 32-count the high | |
2244 // register. This is done by shifting left by 31-count and then by one | |
2245 // more to take care of the special (rare) case where count is zero | |
2246 // (shifting by 32 would not work). | |
2247 | |
2248 neg( Ralt_count ); | |
2249 if (Rcount != Rout_low) { | |
2250 srl( Rin_low, Rcount, Rout_low ); | |
2251 } | |
2252 | |
2253 // The order of the next two instructions is critical in the case where | |
2254 // Rin and Rout are the same and should not be reversed. | |
2255 | |
2256 sll( Rin_high, Ralt_count, Rxfer_bits ); // shift left by 31-count | |
2257 sra( Rin_high, Rcount, Rout_high ); // high half | |
2258 sll( Rxfer_bits, 1, Rxfer_bits ); // shift left by one more | |
2259 if (Rcount == Rout_low) { | |
2260 srl( Rin_low, Rcount, Rout_low ); | |
2261 } | |
2262 ba (false, done); | |
2263 delayed()-> | |
2264 or3( Rout_low, Rxfer_bits, Rout_low ); // new low value: or shifted old low part and xfer from high | |
2265 | |
2266 // shift >= 32 bits, Ralt_count = Rcount-32 | |
2267 bind(big_shift); | |
2268 | |
2269 sra( Rin_high, Ralt_count, Rout_low ); | |
2270 sra( Rin_high, 31, Rout_high ); // sign into hi | |
2271 | |
2272 bind( done ); | |
2273 } | |
2274 | |
2275 | |
2276 | |
2277 void MacroAssembler::lushr( Register Rin_high, Register Rin_low, | |
2278 Register Rcount, | |
2279 Register Rout_high, Register Rout_low, | |
2280 Register Rtemp ) { | |
2281 | |
2282 Register Ralt_count = Rtemp; | |
2283 Register Rxfer_bits = Rtemp; | |
2284 | |
2285 assert( Ralt_count != Rin_high | |
2286 && Ralt_count != Rin_low | |
2287 && Ralt_count != Rcount | |
2288 && Rxfer_bits != Rin_low | |
2289 && Rxfer_bits != Rin_high | |
2290 && Rxfer_bits != Rcount | |
2291 && Rxfer_bits != Rout_high | |
2292 && Rout_high != Rin_low, | |
2293 "register alias checks"); | |
2294 | |
2295 Label big_shift, done; | |
2296 | |
2297 // This code can be optimized to use the 64 bit shifts in V9. | |
2298 // Here we use the 32 bit shifts. | |
2299 | |
2300 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits | |
2301 subcc(Rcount, 31, Ralt_count); | |
2302 br(greater, true, pn, big_shift); | |
2303 delayed()->dec(Ralt_count); | |
2304 | |
2305 // shift < 32 bits, Ralt_count = Rcount-31 | |
2306 | |
2307 // We get the transfer bits by shifting left by 32-count the high | |
2308 // register. This is done by shifting left by 31-count and then by one | |
2309 // more to take care of the special (rare) case where count is zero | |
2310 // (shifting by 32 would not work). | |
2311 | |
2312 neg( Ralt_count ); | |
2313 if (Rcount != Rout_low) { | |
2314 srl( Rin_low, Rcount, Rout_low ); | |
2315 } | |
2316 | |
2317 // The order of the next two instructions is critical in the case where | |
2318 // Rin and Rout are the same and should not be reversed. | |
2319 | |
2320 sll( Rin_high, Ralt_count, Rxfer_bits ); // shift left by 31-count | |
2321 srl( Rin_high, Rcount, Rout_high ); // high half | |
2322 sll( Rxfer_bits, 1, Rxfer_bits ); // shift left by one more | |
2323 if (Rcount == Rout_low) { | |
2324 srl( Rin_low, Rcount, Rout_low ); | |
2325 } | |
2326 ba (false, done); | |
2327 delayed()-> | |
2328 or3( Rout_low, Rxfer_bits, Rout_low ); // new low value: or shifted old low part and xfer from high | |
2329 | |
2330 // shift >= 32 bits, Ralt_count = Rcount-32 | |
2331 bind(big_shift); | |
2332 | |
2333 srl( Rin_high, Ralt_count, Rout_low ); | |
2334 clr( Rout_high ); | |
2335 | |
2336 bind( done ); | |
2337 } | |
2338 | |
2339 #ifdef _LP64 | |
2340 void MacroAssembler::lcmp( Register Ra, Register Rb, Register Rresult) { | |
2341 cmp(Ra, Rb); | |
2342 mov( -1, Rresult); | |
2343 movcc(equal, false, xcc, 0, Rresult); | |
2344 movcc(greater, false, xcc, 1, Rresult); | |
2345 } | |
2346 #endif | |
2347 | |
2348 | |
2349 void MacroAssembler::float_cmp( bool is_float, int unordered_result, | |
2350 FloatRegister Fa, FloatRegister Fb, | |
2351 Register Rresult) { | |
2352 | |
2353 fcmp(is_float ? FloatRegisterImpl::S : FloatRegisterImpl::D, fcc0, Fa, Fb); | |
2354 | |
2355 Condition lt = unordered_result == -1 ? f_unorderedOrLess : f_less; | |
2356 Condition eq = f_equal; | |
2357 Condition gt = unordered_result == 1 ? f_unorderedOrGreater : f_greater; | |
2358 | |
2359 if (VM_Version::v9_instructions_work()) { | |
2360 | |
2361 mov( -1, Rresult ); | |
2362 movcc( eq, true, fcc0, 0, Rresult ); | |
2363 movcc( gt, true, fcc0, 1, Rresult ); | |
2364 | |
2365 } else { | |
2366 Label done; | |
2367 | |
2368 set( -1, Rresult ); | |
2369 //fb(lt, true, pn, done); delayed()->set( -1, Rresult ); | |
2370 fb( eq, true, pn, done); delayed()->set( 0, Rresult ); | |
2371 fb( gt, true, pn, done); delayed()->set( 1, Rresult ); | |
2372 | |
2373 bind (done); | |
2374 } | |
2375 } | |
2376 | |
2377 | |
2378 void MacroAssembler::fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) | |
2379 { | |
2380 if (VM_Version::v9_instructions_work()) { | |
2381 Assembler::fneg(w, s, d); | |
2382 } else { | |
2383 if (w == FloatRegisterImpl::S) { | |
2384 Assembler::fneg(w, s, d); | |
2385 } else if (w == FloatRegisterImpl::D) { | |
2386 // number() does a sanity check on the alignment. | |
2387 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) && | |
2388 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check"); | |
2389 | |
2390 Assembler::fneg(FloatRegisterImpl::S, s, d); | |
2391 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); | |
2392 } else { | |
2393 assert(w == FloatRegisterImpl::Q, "Invalid float register width"); | |
2394 | |
2395 // number() does a sanity check on the alignment. | |
2396 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) && | |
2397 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check"); | |
2398 | |
2399 Assembler::fneg(FloatRegisterImpl::S, s, d); | |
2400 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); | |
2401 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor()); | |
2402 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor()); | |
2403 } | |
2404 } | |
2405 } | |
2406 | |
2407 void MacroAssembler::fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) | |
2408 { | |
2409 if (VM_Version::v9_instructions_work()) { | |
2410 Assembler::fmov(w, s, d); | |
2411 } else { | |
2412 if (w == FloatRegisterImpl::S) { | |
2413 Assembler::fmov(w, s, d); | |
2414 } else if (w == FloatRegisterImpl::D) { | |
2415 // number() does a sanity check on the alignment. | |
2416 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) && | |
2417 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check"); | |
2418 | |
2419 Assembler::fmov(FloatRegisterImpl::S, s, d); | |
2420 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); | |
2421 } else { | |
2422 assert(w == FloatRegisterImpl::Q, "Invalid float register width"); | |
2423 | |
2424 // number() does a sanity check on the alignment. | |
2425 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) && | |
2426 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check"); | |
2427 | |
2428 Assembler::fmov(FloatRegisterImpl::S, s, d); | |
2429 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); | |
2430 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor()); | |
2431 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor()); | |
2432 } | |
2433 } | |
2434 } | |
2435 | |
2436 void MacroAssembler::fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) | |
2437 { | |
2438 if (VM_Version::v9_instructions_work()) { | |
2439 Assembler::fabs(w, s, d); | |
2440 } else { | |
2441 if (w == FloatRegisterImpl::S) { | |
2442 Assembler::fabs(w, s, d); | |
2443 } else if (w == FloatRegisterImpl::D) { | |
2444 // number() does a sanity check on the alignment. | |
2445 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) && | |
2446 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check"); | |
2447 | |
2448 Assembler::fabs(FloatRegisterImpl::S, s, d); | |
2449 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); | |
2450 } else { | |
2451 assert(w == FloatRegisterImpl::Q, "Invalid float register width"); | |
2452 | |
2453 // number() does a sanity check on the alignment. | |
2454 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) && | |
2455 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check"); | |
2456 | |
2457 Assembler::fabs(FloatRegisterImpl::S, s, d); | |
2458 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); | |
2459 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor()); | |
2460 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor()); | |
2461 } | |
2462 } | |
2463 } | |
2464 | |
2465 void MacroAssembler::save_all_globals_into_locals() { | |
2466 mov(G1,L1); | |
2467 mov(G2,L2); | |
2468 mov(G3,L3); | |
2469 mov(G4,L4); | |
2470 mov(G5,L5); | |
2471 mov(G6,L6); | |
2472 mov(G7,L7); | |
2473 } | |
2474 | |
2475 void MacroAssembler::restore_globals_from_locals() { | |
2476 mov(L1,G1); | |
2477 mov(L2,G2); | |
2478 mov(L3,G3); | |
2479 mov(L4,G4); | |
2480 mov(L5,G5); | |
2481 mov(L6,G6); | |
2482 mov(L7,G7); | |
2483 } | |
2484 | |
2485 // Use for 64 bit operation. | |
2486 void MacroAssembler::casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm) | |
2487 { | |
2488 // store ptr_reg as the new top value | |
2489 #ifdef _LP64 | |
2490 casx(top_ptr_reg, top_reg, ptr_reg); | |
2491 #else | |
2492 cas_under_lock(top_ptr_reg, top_reg, ptr_reg, lock_addr, use_call_vm); | |
2493 #endif // _LP64 | |
2494 } | |
2495 | |
2496 // [RGV] This routine does not handle 64 bit operations. | |
2497 // use casx_under_lock() or casx directly!!! | |
2498 void MacroAssembler::cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm) | |
2499 { | |
2500 // store ptr_reg as the new top value | |
2501 if (VM_Version::v9_instructions_work()) { | |
2502 cas(top_ptr_reg, top_reg, ptr_reg); | |
2503 } else { | |
2504 | |
2505 // If the register is not an out nor global, it is not visible | |
2506 // after the save. Allocate a register for it, save its | |
2507 // value in the register save area (the save may not flush | |
2508 // registers to the save area). | |
2509 | |
2510 Register top_ptr_reg_after_save; | |
2511 Register top_reg_after_save; | |
2512 Register ptr_reg_after_save; | |
2513 | |
2514 if (top_ptr_reg->is_out() || top_ptr_reg->is_global()) { | |
2515 top_ptr_reg_after_save = top_ptr_reg->after_save(); | |
2516 } else { | |
2517 Address reg_save_addr = top_ptr_reg->address_in_saved_window(); | |
2518 top_ptr_reg_after_save = L0; | |
2519 st(top_ptr_reg, reg_save_addr); | |
2520 } | |
2521 | |
2522 if (top_reg->is_out() || top_reg->is_global()) { | |
2523 top_reg_after_save = top_reg->after_save(); | |
2524 } else { | |
2525 Address reg_save_addr = top_reg->address_in_saved_window(); | |
2526 top_reg_after_save = L1; | |
2527 st(top_reg, reg_save_addr); | |
2528 } | |
2529 | |
2530 if (ptr_reg->is_out() || ptr_reg->is_global()) { | |
2531 ptr_reg_after_save = ptr_reg->after_save(); | |
2532 } else { | |
2533 Address reg_save_addr = ptr_reg->address_in_saved_window(); | |
2534 ptr_reg_after_save = L2; | |
2535 st(ptr_reg, reg_save_addr); | |
2536 } | |
2537 | |
2538 const Register& lock_reg = L3; | |
2539 const Register& lock_ptr_reg = L4; | |
2540 const Register& value_reg = L5; | |
2541 const Register& yield_reg = L6; | |
2542 const Register& yieldall_reg = L7; | |
2543 | |
2544 save_frame(); | |
2545 | |
2546 if (top_ptr_reg_after_save == L0) { | |
2547 ld(top_ptr_reg->address_in_saved_window().after_save(), top_ptr_reg_after_save); | |
2548 } | |
2549 | |
2550 if (top_reg_after_save == L1) { | |
2551 ld(top_reg->address_in_saved_window().after_save(), top_reg_after_save); | |
2552 } | |
2553 | |
2554 if (ptr_reg_after_save == L2) { | |
2555 ld(ptr_reg->address_in_saved_window().after_save(), ptr_reg_after_save); | |
2556 } | |
2557 | |
2558 Label(retry_get_lock); | |
2559 Label(not_same); | |
2560 Label(dont_yield); | |
2561 | |
2562 assert(lock_addr, "lock_address should be non null for v8"); | |
2563 set((intptr_t)lock_addr, lock_ptr_reg); | |
2564 // Initialize yield counter | |
2565 mov(G0,yield_reg); | |
2566 mov(G0, yieldall_reg); | |
2567 set(StubRoutines::Sparc::locked, lock_reg); | |
2568 | |
2569 bind(retry_get_lock); | |
2570 cmp(yield_reg, V8AtomicOperationUnderLockSpinCount); | |
2571 br(Assembler::less, false, Assembler::pt, dont_yield); | |
2572 delayed()->nop(); | |
2573 | |
2574 if(use_call_vm) { | |
2575 Untested("Need to verify global reg consistancy"); | |
2576 call_VM(noreg, CAST_FROM_FN_PTR(address, SharedRuntime::yield_all), yieldall_reg); | |
2577 } else { | |
2578 // Save the regs and make space for a C call | |
2579 save(SP, -96, SP); | |
2580 save_all_globals_into_locals(); | |
2581 call(CAST_FROM_FN_PTR(address,os::yield_all)); | |
2582 delayed()->mov(yieldall_reg, O0); | |
2583 restore_globals_from_locals(); | |
2584 restore(); | |
2585 } | |
2586 | |
2587 // reset the counter | |
2588 mov(G0,yield_reg); | |
2589 add(yieldall_reg, 1, yieldall_reg); | |
2590 | |
2591 bind(dont_yield); | |
2592 // try to get lock | |
2593 swap(lock_ptr_reg, 0, lock_reg); | |
2594 | |
2595 // did we get the lock? | |
2596 cmp(lock_reg, StubRoutines::Sparc::unlocked); | |
2597 br(Assembler::notEqual, true, Assembler::pn, retry_get_lock); | |
2598 delayed()->add(yield_reg,1,yield_reg); | |
2599 | |
2600 // yes, got lock. do we have the same top? | |
2601 ld(top_ptr_reg_after_save, 0, value_reg); | |
2602 cmp(value_reg, top_reg_after_save); | |
2603 br(Assembler::notEqual, false, Assembler::pn, not_same); | |
2604 delayed()->nop(); | |
2605 | |
2606 // yes, same top. | |
2607 st(ptr_reg_after_save, top_ptr_reg_after_save, 0); | |
2608 membar(Assembler::StoreStore); | |
2609 | |
2610 bind(not_same); | |
2611 mov(value_reg, ptr_reg_after_save); | |
2612 st(lock_reg, lock_ptr_reg, 0); // unlock | |
2613 | |
2614 restore(); | |
2615 } | |
2616 } | |
2617 | |
665
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2618 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, |
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2619 Register tmp, |
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2620 int offset) { |
622
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2621 intptr_t value = *delayed_value_addr; |
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2622 if (value != 0) |
665
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2623 return RegisterOrConstant(value + offset); |
622
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2624 |
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2625 // load indirectly to solve generation ordering problem |
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2626 Address a(tmp, (address) delayed_value_addr); |
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2627 load_ptr_contents(a, tmp); |
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|
2628 |
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2629 #ifdef ASSERT |
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|
2630 tst(tmp); |
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|
2631 breakpoint_trap(zero, xcc); |
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2632 #endif |
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|
2633 |
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2634 if (offset != 0) |
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|
2635 add(tmp, offset, tmp); |
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2636 |
665
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2637 return RegisterOrConstant(tmp); |
622
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2638 } |
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|
2639 |
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|
2640 |
665
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2641 void MacroAssembler::regcon_inc_ptr( RegisterOrConstant& dest, RegisterOrConstant src, Register temp ) { |
623
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2642 assert(dest.register_or_noreg() != G0, "lost side effect"); |
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2643 if ((src.is_constant() && src.as_constant() == 0) || |
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2644 (src.is_register() && src.as_register() == G0)) { |
9adddb8c0fc8
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|
2645 // do nothing |
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|
2646 } else if (dest.is_register()) { |
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|
2647 add(dest.as_register(), ensure_rs2(src, temp), dest.as_register()); |
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2648 } else if (src.is_constant()) { |
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2649 intptr_t res = dest.as_constant() + src.as_constant(); |
665
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2650 dest = RegisterOrConstant(res); // side effect seen by caller |
623
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|
2651 } else { |
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|
2652 assert(temp != noreg, "cannot handle constant += register"); |
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2653 add(src.as_register(), ensure_rs2(dest, temp), temp); |
665
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2654 dest = RegisterOrConstant(temp); // side effect seen by caller |
623
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|
2655 } |
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|
2656 } |
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|
2657 |
665
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2658 void MacroAssembler::regcon_sll_ptr( RegisterOrConstant& dest, RegisterOrConstant src, Register temp ) { |
623
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2659 assert(dest.register_or_noreg() != G0, "lost side effect"); |
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2660 if (!is_simm13(src.constant_or_zero())) |
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|
2661 src = (src.as_constant() & 0xFF); |
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2662 if ((src.is_constant() && src.as_constant() == 0) || |
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|
2663 (src.is_register() && src.as_register() == G0)) { |
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|
2664 // do nothing |
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|
2665 } else if (dest.is_register()) { |
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|
2666 sll_ptr(dest.as_register(), src, dest.as_register()); |
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|
2667 } else if (src.is_constant()) { |
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|
2668 intptr_t res = dest.as_constant() << src.as_constant(); |
665
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|
2669 dest = RegisterOrConstant(res); // side effect seen by caller |
623
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|
2670 } else { |
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|
2671 assert(temp != noreg, "cannot handle constant <<= register"); |
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|
2672 set(dest.as_constant(), temp); |
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|
2673 sll_ptr(temp, src, temp); |
665
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|
2674 dest = RegisterOrConstant(temp); // side effect seen by caller |
623
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|
2675 } |
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|
2676 } |
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|
2677 |
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|
2678 |
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|
2679 // Look up the method for a megamorphic invokeinterface call. |
9adddb8c0fc8
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2680 // The target method is determined by <intf_klass, itable_index>. |
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|
2681 // The receiver klass is in recv_klass. |
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2682 // On success, the result will be in method_result, and execution falls through. |
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2683 // On failure, execution transfers to the given label. |
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|
2684 void MacroAssembler::lookup_interface_method(Register recv_klass, |
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|
2685 Register intf_klass, |
665
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|
2686 RegisterOrConstant itable_index, |
623
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|
2687 Register method_result, |
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changeset
|
2688 Register scan_temp, |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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diff
changeset
|
2689 Register sethi_temp, |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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diff
changeset
|
2690 Label& L_no_such_interface) { |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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diff
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|
2691 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2692 assert(itable_index.is_constant() || itable_index.as_register() == method_result, |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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diff
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|
2693 "caller must use same register for non-constant itable index as for method"); |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2694 |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2695 // Compute start of first itableOffsetEntry (which is at the end of the vtable) |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2696 int vtable_base = instanceKlass::vtable_start_offset() * wordSize; |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2697 int scan_step = itableOffsetEntry::size() * wordSize; |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2698 int vte_size = vtableEntry::size() * wordSize; |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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diff
changeset
|
2699 |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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diff
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|
2700 lduw(recv_klass, instanceKlass::vtable_length_offset() * wordSize, scan_temp); |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2701 // %%% We should store the aligned, prescaled offset in the klassoop. |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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diff
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|
2702 // Then the next several instructions would fold away. |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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622
diff
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|
2703 |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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diff
changeset
|
2704 int round_to_unit = ((HeapWordsPerLong > 1) ? BytesPerLong : 0); |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2705 int itb_offset = vtable_base; |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2706 if (round_to_unit != 0) { |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2707 // hoist first instruction of round_to(scan_temp, BytesPerLong): |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2708 itb_offset += round_to_unit - wordSize; |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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diff
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|
2709 } |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2710 int itb_scale = exact_log2(vtableEntry::size() * wordSize); |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2711 sll(scan_temp, itb_scale, scan_temp); |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2712 add(scan_temp, itb_offset, scan_temp); |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2713 if (round_to_unit != 0) { |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2714 // Round up to align_object_offset boundary |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2715 // see code for instanceKlass::start_of_itable! |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2716 // Was: round_to(scan_temp, BytesPerLong); |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2717 // Hoisted: add(scan_temp, BytesPerLong-1, scan_temp); |
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|
2718 and3(scan_temp, -round_to_unit, scan_temp); |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2719 } |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2720 add(recv_klass, scan_temp, scan_temp); |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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diff
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|
2721 |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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changeset
|
2722 // Adjust recv_klass by scaled itable_index, so we can free itable_index. |
665
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6814659: separable cleanups and subroutines for 6655638
jrose
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changeset
|
2723 RegisterOrConstant itable_offset = itable_index; |
623
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|
2724 regcon_sll_ptr(itable_offset, exact_log2(itableMethodEntry::size() * wordSize)); |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2725 regcon_inc_ptr(itable_offset, itableMethodEntry::method_offset_in_bytes()); |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2726 add(recv_klass, ensure_rs2(itable_offset, sethi_temp), recv_klass); |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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changeset
|
2727 |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2728 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2729 // if (scan->interface() == intf) { |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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changeset
|
2730 // result = (klass + scan->offset() + itable_index); |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2731 // } |
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|
2732 // } |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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changeset
|
2733 Label search, found_method; |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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diff
changeset
|
2734 |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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diff
changeset
|
2735 for (int peel = 1; peel >= 0; peel--) { |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2736 // %%%% Could load both offset and interface in one ldx, if they were |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
2737 // in the opposite order. This would save a load. |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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changeset
|
2738 ld_ptr(scan_temp, itableOffsetEntry::interface_offset_in_bytes(), method_result); |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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diff
changeset
|
2739 |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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diff
changeset
|
2740 // Check that this entry is non-null. A null entry means that |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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diff
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|
2741 // the receiver class doesn't implement the interface, and wasn't the |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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diff
changeset
|
2742 // same as when the caller was compiled. |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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diff
changeset
|
2743 bpr(Assembler::rc_z, false, Assembler::pn, method_result, L_no_such_interface); |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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diff
changeset
|
2744 delayed()->cmp(method_result, intf_klass); |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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622
diff
changeset
|
2745 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
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622
diff
changeset
|
2746 if (peel) { |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
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diff
changeset
|
2747 brx(Assembler::equal, false, Assembler::pt, found_method); |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
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diff
changeset
|
2748 } else { |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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622
diff
changeset
|
2749 brx(Assembler::notEqual, false, Assembler::pn, search); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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parents:
622
diff
changeset
|
2750 // (invert the test to fall through to found_method...) |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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622
diff
changeset
|
2751 } |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
2752 delayed()->add(scan_temp, scan_step, scan_temp); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
2753 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
2754 if (!peel) break; |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
2755 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
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622
diff
changeset
|
2756 bind(search); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
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622
diff
changeset
|
2757 } |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
2758 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
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622
diff
changeset
|
2759 bind(found_method); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
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622
diff
changeset
|
2760 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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622
diff
changeset
|
2761 // Got a hit. |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
2762 int ito_offset = itableOffsetEntry::offset_offset_in_bytes(); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
2763 // scan_temp[-scan_step] points to the vtable offset we need |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
2764 ito_offset -= scan_step; |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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parents:
622
diff
changeset
|
2765 lduw(scan_temp, ito_offset, scan_temp); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
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622
diff
changeset
|
2766 ld_ptr(recv_klass, scan_temp, method_result); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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622
diff
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|
2767 } |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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622
diff
changeset
|
2768 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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622
diff
changeset
|
2769 |
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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642
diff
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|
2770 void MacroAssembler::check_klass_subtype(Register sub_klass, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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642
diff
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|
2771 Register super_klass, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
642
diff
changeset
|
2772 Register temp_reg, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2773 Register temp2_reg, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
642
diff
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|
2774 Label& L_success) { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
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642
diff
changeset
|
2775 Label L_failure, L_pop_to_failure; |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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642
diff
changeset
|
2776 check_klass_subtype_fast_path(sub_klass, super_klass, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2777 temp_reg, temp2_reg, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2778 &L_success, &L_failure, NULL); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
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642
diff
changeset
|
2779 Register sub_2 = sub_klass; |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2780 Register sup_2 = super_klass; |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2781 if (!sub_2->is_global()) sub_2 = L0; |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2782 if (!sup_2->is_global()) sup_2 = L1; |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
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642
diff
changeset
|
2783 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2784 save_frame_and_mov(0, sub_klass, sub_2, super_klass, sup_2); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
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642
diff
changeset
|
2785 check_klass_subtype_slow_path(sub_2, sup_2, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
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642
diff
changeset
|
2786 L2, L3, L4, L5, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
642
diff
changeset
|
2787 NULL, &L_pop_to_failure); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
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642
diff
changeset
|
2788 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
2789 // on success: |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
642
diff
changeset
|
2790 restore(); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2791 ba(false, L_success); |
c517646eef23
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jrose
parents:
642
diff
changeset
|
2792 delayed()->nop(); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2793 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
2794 // on failure: |
c517646eef23
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jrose
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642
diff
changeset
|
2795 bind(L_pop_to_failure); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2796 restore(); |
c517646eef23
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jrose
parents:
642
diff
changeset
|
2797 bind(L_failure); |
c517646eef23
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parents:
642
diff
changeset
|
2798 } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
642
diff
changeset
|
2799 |
c517646eef23
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642
diff
changeset
|
2800 |
c517646eef23
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diff
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|
2801 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, |
c517646eef23
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642
diff
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|
2802 Register super_klass, |
c517646eef23
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diff
changeset
|
2803 Register temp_reg, |
c517646eef23
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642
diff
changeset
|
2804 Register temp2_reg, |
c517646eef23
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diff
changeset
|
2805 Label* L_success, |
c517646eef23
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diff
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|
2806 Label* L_failure, |
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|
2807 Label* L_slow_path, |
665
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|
2808 RegisterOrConstant super_check_offset, |
644
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diff
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|
2809 Register instanceof_hack) { |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
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|
2810 int sc_offset = (klassOopDesc::header_size() * HeapWordSize + |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
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|
2811 Klass::secondary_super_cache_offset_in_bytes()); |
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diff
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|
2812 int sco_offset = (klassOopDesc::header_size() * HeapWordSize + |
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diff
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|
2813 Klass::super_check_offset_offset_in_bytes()); |
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|
2814 |
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diff
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|
2815 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); |
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|
2816 bool need_slow_path = (must_load_sco || |
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|
2817 super_check_offset.constant_or_zero() == sco_offset); |
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|
2818 |
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diff
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|
2819 assert_different_registers(sub_klass, super_klass, temp_reg); |
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|
2820 if (super_check_offset.is_register()) { |
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diff
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|
2821 assert_different_registers(sub_klass, super_klass, |
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diff
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|
2822 super_check_offset.as_register()); |
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|
2823 } else if (must_load_sco) { |
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diff
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|
2824 assert(temp2_reg != noreg, "supply either a temp or a register offset"); |
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|
2825 } |
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|
2826 |
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diff
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|
2827 Label L_fallthrough; |
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diff
changeset
|
2828 int label_nulls = 0; |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
2829 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
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|
2830 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
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|
2831 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } |
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|
2832 assert(label_nulls <= 1 || instanceof_hack != noreg || |
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|
2833 (L_slow_path == &L_fallthrough && label_nulls <= 2 && !need_slow_path), |
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|
2834 "at most one NULL in the batch, usually"); |
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diff
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|
2835 |
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diff
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|
2836 // Support for the instanceof hack, which uses delay slots to |
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diff
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|
2837 // set a destination register to zero or one. |
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diff
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|
2838 bool do_bool_sets = (instanceof_hack != noreg); |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
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|
2839 #define BOOL_SET(bool_value) \ |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
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|
2840 if (do_bool_sets && bool_value >= 0) \ |
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diff
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|
2841 set(bool_value, instanceof_hack) |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
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|
2842 #define DELAYED_BOOL_SET(bool_value) \ |
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diff
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|
2843 if (do_bool_sets && bool_value >= 0) \ |
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642
diff
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|
2844 delayed()->set(bool_value, instanceof_hack); \ |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
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|
2845 else delayed()->nop() |
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diff
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|
2846 // Hacked ba(), which may only be used just before L_fallthrough. |
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diff
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|
2847 #define FINAL_JUMP(label, bool_value) \ |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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642
diff
changeset
|
2848 if (&(label) == &L_fallthrough) { \ |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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642
diff
changeset
|
2849 BOOL_SET(bool_value); \ |
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parents:
642
diff
changeset
|
2850 } else { \ |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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642
diff
changeset
|
2851 ba((do_bool_sets && bool_value >= 0), label); \ |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
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diff
changeset
|
2852 DELAYED_BOOL_SET(bool_value); \ |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
2853 } |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
2854 |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
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|
2855 // If the pointers are equal, we are done (e.g., String[] elements). |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
2856 // This self-check enables sharing of secondary supertype arrays among |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
642
diff
changeset
|
2857 // non-primary types such as array-of-interface. Otherwise, each such |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
642
diff
changeset
|
2858 // type would need its own customized SSA. |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2859 // We move this check to the front of the fast path because many |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
642
diff
changeset
|
2860 // type checks are in fact trivially successful in this manner, |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
642
diff
changeset
|
2861 // so we get a nicely predicted branch right at the start of the check. |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
642
diff
changeset
|
2862 cmp(super_klass, sub_klass); |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2863 brx(Assembler::equal, do_bool_sets, Assembler::pn, *L_success); |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2864 DELAYED_BOOL_SET(1); |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2865 |
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parents:
642
diff
changeset
|
2866 // Check the supertype display: |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
642
diff
changeset
|
2867 if (must_load_sco) { |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2868 // The super check offset is always positive... |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2869 lduw(super_klass, sco_offset, temp2_reg); |
665
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6814659: separable cleanups and subroutines for 6655638
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644
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|
2870 super_check_offset = RegisterOrConstant(temp2_reg); |
644
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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642
diff
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|
2871 } |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
642
diff
changeset
|
2872 ld_ptr(sub_klass, super_check_offset, temp_reg); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
642
diff
changeset
|
2873 cmp(super_klass, temp_reg); |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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642
diff
changeset
|
2874 |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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642
diff
changeset
|
2875 // This check has worked decisively for primary supers. |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
642
diff
changeset
|
2876 // Secondary supers are sought in the super_cache ('super_cache_addr'). |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
642
diff
changeset
|
2877 // (Secondary supers are interfaces and very deeply nested subtypes.) |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
642
diff
changeset
|
2878 // This works in the same check above because of a tricky aliasing |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
642
diff
changeset
|
2879 // between the super_cache and the primary super display elements. |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
642
diff
changeset
|
2880 // (The 'super_check_addr' can address either, as the case requires.) |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
642
diff
changeset
|
2881 // Note that the cache is updated below if it does not help us find |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2882 // what we need immediately. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2883 // So if it was a primary super, we can just fail immediately. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2884 // Otherwise, it's the slow path for us (no success at this point). |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2885 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
642
diff
changeset
|
2886 if (super_check_offset.is_register()) { |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2887 brx(Assembler::equal, do_bool_sets, Assembler::pn, *L_success); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2888 delayed(); if (do_bool_sets) BOOL_SET(1); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2889 // if !do_bool_sets, sneak the next cmp into the delay slot: |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2890 cmp(super_check_offset.as_register(), sc_offset); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2891 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
642
diff
changeset
|
2892 if (L_failure == &L_fallthrough) { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2893 brx(Assembler::equal, do_bool_sets, Assembler::pt, *L_slow_path); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2894 delayed()->nop(); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2895 BOOL_SET(0); // fallthrough on failure |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2896 } else { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2897 brx(Assembler::notEqual, do_bool_sets, Assembler::pn, *L_failure); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2898 DELAYED_BOOL_SET(0); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
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642
diff
changeset
|
2899 FINAL_JUMP(*L_slow_path, -1); // -1 => vanilla delay slot |
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642
diff
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|
2900 } |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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642
diff
changeset
|
2901 } else if (super_check_offset.as_constant() == sc_offset) { |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
642
diff
changeset
|
2902 // Need a slow path; fast failure is impossible. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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642
diff
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|
2903 if (L_slow_path == &L_fallthrough) { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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642
diff
changeset
|
2904 brx(Assembler::equal, do_bool_sets, Assembler::pt, *L_success); |
c517646eef23
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jrose
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diff
changeset
|
2905 DELAYED_BOOL_SET(1); |
c517646eef23
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jrose
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642
diff
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|
2906 } else { |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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642
diff
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|
2907 brx(Assembler::notEqual, false, Assembler::pn, *L_slow_path); |
c517646eef23
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jrose
parents:
642
diff
changeset
|
2908 delayed()->nop(); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
642
diff
changeset
|
2909 FINAL_JUMP(*L_success, 1); |
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jrose
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642
diff
changeset
|
2910 } |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
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|
2911 } else { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
642
diff
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|
2912 // No slow path; it's a fast decision. |
c517646eef23
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642
diff
changeset
|
2913 if (L_failure == &L_fallthrough) { |
c517646eef23
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642
diff
changeset
|
2914 brx(Assembler::equal, do_bool_sets, Assembler::pt, *L_success); |
c517646eef23
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jrose
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diff
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|
2915 DELAYED_BOOL_SET(1); |
c517646eef23
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642
diff
changeset
|
2916 BOOL_SET(0); |
c517646eef23
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642
diff
changeset
|
2917 } else { |
c517646eef23
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642
diff
changeset
|
2918 brx(Assembler::notEqual, do_bool_sets, Assembler::pn, *L_failure); |
c517646eef23
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diff
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|
2919 DELAYED_BOOL_SET(0); |
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diff
changeset
|
2920 FINAL_JUMP(*L_success, 1); |
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642
diff
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|
2921 } |
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diff
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|
2922 } |
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diff
changeset
|
2923 |
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jrose
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diff
changeset
|
2924 bind(L_fallthrough); |
c517646eef23
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jrose
parents:
642
diff
changeset
|
2925 |
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jrose
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642
diff
changeset
|
2926 #undef final_jump |
c517646eef23
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jrose
parents:
642
diff
changeset
|
2927 #undef bool_set |
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|
2928 #undef DELAYED_BOOL_SET |
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diff
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|
2929 #undef final_jump |
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diff
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|
2930 } |
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|
2931 |
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diff
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|
2932 |
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|
2933 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, |
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|
2934 Register super_klass, |
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diff
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|
2935 Register count_temp, |
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diff
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|
2936 Register scan_temp, |
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|
2937 Register scratch_reg, |
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diff
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|
2938 Register coop_reg, |
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diff
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|
2939 Label* L_success, |
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|
2940 Label* L_failure) { |
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|
2941 assert_different_registers(sub_klass, super_klass, |
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|
2942 count_temp, scan_temp, scratch_reg, coop_reg); |
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|
2943 |
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|
2944 Label L_fallthrough, L_loop; |
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diff
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|
2945 int label_nulls = 0; |
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|
2946 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
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|
2947 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
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|
2948 assert(label_nulls <= 1, "at most one NULL in the batch"); |
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|
2949 |
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|
2950 // a couple of useful fields in sub_klass: |
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|
2951 int ss_offset = (klassOopDesc::header_size() * HeapWordSize + |
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|
2952 Klass::secondary_supers_offset_in_bytes()); |
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|
2953 int sc_offset = (klassOopDesc::header_size() * HeapWordSize + |
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|
2954 Klass::secondary_super_cache_offset_in_bytes()); |
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diff
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|
2955 |
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diff
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|
2956 // Do a linear scan of the secondary super-klass chain. |
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2957 // This code is rarely used, so simplicity is a virtue here. |
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|
2958 |
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diff
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|
2959 #ifndef PRODUCT |
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diff
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|
2960 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; |
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|
2961 inc_counter((address) pst_counter, count_temp, scan_temp); |
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diff
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|
2962 #endif |
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diff
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|
2963 |
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|
2964 // We will consult the secondary-super array. |
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|
2965 ld_ptr(sub_klass, ss_offset, scan_temp); |
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|
2966 |
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|
2967 // Compress superclass if necessary. |
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|
2968 Register search_key = super_klass; |
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|
2969 bool decode_super_klass = false; |
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|
2970 if (UseCompressedOops) { |
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|
2971 if (coop_reg != noreg) { |
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|
2972 encode_heap_oop_not_null(super_klass, coop_reg); |
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|
2973 search_key = coop_reg; |
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|
2974 } else { |
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|
2975 encode_heap_oop_not_null(super_klass); |
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2976 decode_super_klass = true; // scarce temps! |
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|
2977 } |
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2978 // The superclass is never null; it would be a basic system error if a null |
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2979 // pointer were to sneak in here. Note that we have already loaded the |
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2980 // Klass::super_check_offset from the super_klass in the fast path, |
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2981 // so if there is a null in that register, we are already in the afterlife. |
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|
2982 } |
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|
2983 |
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|
2984 // Load the array length. (Positive movl does right thing on LP64.) |
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2985 lduw(scan_temp, arrayOopDesc::length_offset_in_bytes(), count_temp); |
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|
2986 |
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|
2987 // Check for empty secondary super list |
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|
2988 tst(count_temp); |
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diff
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|
2989 |
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|
2990 // Top of search loop |
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|
2991 bind(L_loop); |
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|
2992 br(Assembler::equal, false, Assembler::pn, *L_failure); |
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2993 delayed()->add(scan_temp, heapOopSize, scan_temp); |
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|
2994 assert(heapOopSize != 0, "heapOopSize should be initialized"); |
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|
2995 |
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|
2996 // Skip the array header in all array accesses. |
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|
2997 int elem_offset = arrayOopDesc::base_offset_in_bytes(T_OBJECT); |
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2998 elem_offset -= heapOopSize; // the scan pointer was pre-incremented also |
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|
2999 |
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|
3000 // Load next super to check |
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|
3001 if (UseCompressedOops) { |
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diff
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|
3002 // Don't use load_heap_oop; we don't want to decode the element. |
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|
3003 lduw( scan_temp, elem_offset, scratch_reg ); |
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diff
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|
3004 } else { |
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|
3005 ld_ptr( scan_temp, elem_offset, scratch_reg ); |
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|
3006 } |
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|
3007 |
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|
3008 // Look for Rsuper_klass on Rsub_klass's secondary super-class-overflow list |
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diff
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|
3009 cmp(scratch_reg, search_key); |
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diff
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|
3010 |
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diff
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|
3011 // A miss means we are NOT a subtype and need to keep looping |
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|
3012 brx(Assembler::notEqual, false, Assembler::pn, L_loop); |
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|
3013 delayed()->deccc(count_temp); // decrement trip counter in delay slot |
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diff
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|
3014 |
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diff
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|
3015 // Falling out the bottom means we found a hit; we ARE a subtype |
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diff
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|
3016 if (decode_super_klass) decode_heap_oop(super_klass); |
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|
3017 |
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|
3018 // Success. Cache the super we found and proceed in triumph. |
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|
3019 st_ptr(super_klass, sub_klass, sc_offset); |
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|
3020 |
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|
3021 if (L_success != &L_fallthrough) { |
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|
3022 ba(false, *L_success); |
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|
3023 delayed()->nop(); |
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diff
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|
3024 } |
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|
3025 |
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|
3026 bind(L_fallthrough); |
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|
3027 } |
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|
3028 |
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|
3029 |
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|
3030 |
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|
3031 |
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
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|
3032 void MacroAssembler::biased_locking_enter(Register obj_reg, Register mark_reg, |
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3033 Register temp_reg, |
0 | 3034 Label& done, Label* slow_case, |
3035 BiasedLockingCounters* counters) { | |
3036 assert(UseBiasedLocking, "why call this otherwise?"); | |
3037 | |
3038 if (PrintBiasedLockingStatistics) { | |
3039 assert_different_registers(obj_reg, mark_reg, temp_reg, O7); | |
3040 if (counters == NULL) | |
3041 counters = BiasedLocking::counters(); | |
3042 } | |
3043 | |
3044 Label cas_label; | |
3045 | |
3046 // Biased locking | |
3047 // See whether the lock is currently biased toward our thread and | |
3048 // whether the epoch is still valid | |
3049 // Note that the runtime guarantees sufficient alignment of JavaThread | |
3050 // pointers to allow age to be placed into low bits | |
3051 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); | |
3052 and3(mark_reg, markOopDesc::biased_lock_mask_in_place, temp_reg); | |
3053 cmp(temp_reg, markOopDesc::biased_lock_pattern); | |
3054 brx(Assembler::notEqual, false, Assembler::pn, cas_label); | |
113
ba764ed4b6f2
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diff
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|
3055 delayed()->nop(); |
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|
3056 |
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|
3057 load_klass(obj_reg, temp_reg); |
0 | 3058 ld_ptr(Address(temp_reg, 0, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg); |
3059 or3(G2_thread, temp_reg, temp_reg); | |
3060 xor3(mark_reg, temp_reg, temp_reg); | |
3061 andcc(temp_reg, ~((int) markOopDesc::age_mask_in_place), temp_reg); | |
3062 if (counters != NULL) { | |
3063 cond_inc(Assembler::equal, (address) counters->biased_lock_entry_count_addr(), mark_reg, temp_reg); | |
3064 // Reload mark_reg as we may need it later | |
3065 ld_ptr(Address(obj_reg, 0, oopDesc::mark_offset_in_bytes()), mark_reg); | |
3066 } | |
3067 brx(Assembler::equal, true, Assembler::pt, done); | |
3068 delayed()->nop(); | |
3069 | |
3070 Label try_revoke_bias; | |
3071 Label try_rebias; | |
3072 Address mark_addr = Address(obj_reg, 0, oopDesc::mark_offset_in_bytes()); | |
3073 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); | |
3074 | |
3075 // At this point we know that the header has the bias pattern and | |
3076 // that we are not the bias owner in the current epoch. We need to | |
3077 // figure out more details about the state of the header in order to | |
3078 // know what operations can be legally performed on the object's | |
3079 // header. | |
3080 | |
3081 // If the low three bits in the xor result aren't clear, that means | |
3082 // the prototype header is no longer biased and we have to revoke | |
3083 // the bias on this object. | |
3084 btst(markOopDesc::biased_lock_mask_in_place, temp_reg); | |
3085 brx(Assembler::notZero, false, Assembler::pn, try_revoke_bias); | |
3086 | |
3087 // Biasing is still enabled for this data type. See whether the | |
3088 // epoch of the current bias is still valid, meaning that the epoch | |
3089 // bits of the mark word are equal to the epoch bits of the | |
3090 // prototype header. (Note that the prototype header's epoch bits | |
3091 // only change at a safepoint.) If not, attempt to rebias the object | |
3092 // toward the current thread. Note that we must be absolutely sure | |
3093 // that the current epoch is invalid in order to do this because | |
3094 // otherwise the manipulations it performs on the mark word are | |
3095 // illegal. | |
3096 delayed()->btst(markOopDesc::epoch_mask_in_place, temp_reg); | |
3097 brx(Assembler::notZero, false, Assembler::pn, try_rebias); | |
3098 | |
3099 // The epoch of the current bias is still valid but we know nothing | |
3100 // about the owner; it might be set or it might be clear. Try to | |
3101 // acquire the bias of the object using an atomic operation. If this | |
3102 // fails we will go in to the runtime to revoke the object's bias. | |
3103 // Note that we first construct the presumed unbiased header so we | |
3104 // don't accidentally blow away another thread's valid bias. | |
3105 delayed()->and3(mark_reg, | |
3106 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place, | |
3107 mark_reg); | |
3108 or3(G2_thread, mark_reg, temp_reg); | |
420
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3109 casn(mark_addr.base(), mark_reg, temp_reg); |
0 | 3110 // If the biasing toward our thread failed, this means that |
3111 // another thread succeeded in biasing it toward itself and we | |
3112 // need to revoke that bias. The revocation will occur in the | |
3113 // interpreter runtime in the slow case. | |
3114 cmp(mark_reg, temp_reg); | |
3115 if (counters != NULL) { | |
3116 cond_inc(Assembler::zero, (address) counters->anonymously_biased_lock_entry_count_addr(), mark_reg, temp_reg); | |
3117 } | |
3118 if (slow_case != NULL) { | |
3119 brx(Assembler::notEqual, true, Assembler::pn, *slow_case); | |
3120 delayed()->nop(); | |
3121 } | |
3122 br(Assembler::always, false, Assembler::pt, done); | |
3123 delayed()->nop(); | |
3124 | |
3125 bind(try_rebias); | |
3126 // At this point we know the epoch has expired, meaning that the | |
3127 // current "bias owner", if any, is actually invalid. Under these | |
3128 // circumstances _only_, we are allowed to use the current header's | |
3129 // value as the comparison value when doing the cas to acquire the | |
3130 // bias in the current epoch. In other words, we allow transfer of | |
3131 // the bias from one thread to another directly in this situation. | |
3132 // | |
3133 // FIXME: due to a lack of registers we currently blow away the age | |
3134 // bits in this situation. Should attempt to preserve them. | |
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3135 load_klass(obj_reg, temp_reg); |
0 | 3136 ld_ptr(Address(temp_reg, 0, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg); |
3137 or3(G2_thread, temp_reg, temp_reg); | |
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3138 casn(mark_addr.base(), mark_reg, temp_reg); |
0 | 3139 // If the biasing toward our thread failed, this means that |
3140 // another thread succeeded in biasing it toward itself and we | |
3141 // need to revoke that bias. The revocation will occur in the | |
3142 // interpreter runtime in the slow case. | |
3143 cmp(mark_reg, temp_reg); | |
3144 if (counters != NULL) { | |
3145 cond_inc(Assembler::zero, (address) counters->rebiased_lock_entry_count_addr(), mark_reg, temp_reg); | |
3146 } | |
3147 if (slow_case != NULL) { | |
3148 brx(Assembler::notEqual, true, Assembler::pn, *slow_case); | |
3149 delayed()->nop(); | |
3150 } | |
3151 br(Assembler::always, false, Assembler::pt, done); | |
3152 delayed()->nop(); | |
3153 | |
3154 bind(try_revoke_bias); | |
3155 // The prototype mark in the klass doesn't have the bias bit set any | |
3156 // more, indicating that objects of this data type are not supposed | |
3157 // to be biased any more. We are going to try to reset the mark of | |
3158 // this object to the prototype value and fall through to the | |
3159 // CAS-based locking scheme. Note that if our CAS fails, it means | |
3160 // that another thread raced us for the privilege of revoking the | |
3161 // bias of this particular object, so it's okay to continue in the | |
3162 // normal locking code. | |
3163 // | |
3164 // FIXME: due to a lack of registers we currently blow away the age | |
3165 // bits in this situation. Should attempt to preserve them. | |
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3166 load_klass(obj_reg, temp_reg); |
0 | 3167 ld_ptr(Address(temp_reg, 0, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg); |
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3168 casn(mark_addr.base(), mark_reg, temp_reg); |
0 | 3169 // Fall through to the normal CAS-based lock, because no matter what |
3170 // the result of the above CAS, some thread must have succeeded in | |
3171 // removing the bias bit from the object's header. | |
3172 if (counters != NULL) { | |
3173 cmp(mark_reg, temp_reg); | |
3174 cond_inc(Assembler::zero, (address) counters->revoked_lock_entry_count_addr(), mark_reg, temp_reg); | |
3175 } | |
3176 | |
3177 bind(cas_label); | |
3178 } | |
3179 | |
3180 void MacroAssembler::biased_locking_exit (Address mark_addr, Register temp_reg, Label& done, | |
3181 bool allow_delay_slot_filling) { | |
3182 // Check for biased locking unlock case, which is a no-op | |
3183 // Note: we do not have to check the thread ID for two reasons. | |
3184 // First, the interpreter checks for IllegalMonitorStateException at | |
3185 // a higher level. Second, if the bias was revoked while we held the | |
3186 // lock, the object could not be rebiased toward another thread, so | |
3187 // the bias bit would be clear. | |
3188 ld_ptr(mark_addr, temp_reg); | |
3189 and3(temp_reg, markOopDesc::biased_lock_mask_in_place, temp_reg); | |
3190 cmp(temp_reg, markOopDesc::biased_lock_pattern); | |
3191 brx(Assembler::equal, allow_delay_slot_filling, Assembler::pt, done); | |
3192 delayed(); | |
3193 if (!allow_delay_slot_filling) { | |
3194 nop(); | |
3195 } | |
3196 } | |
3197 | |
3198 | |
3199 // CASN -- 32-64 bit switch hitter similar to the synthetic CASN provided by | |
3200 // Solaris/SPARC's "as". Another apt name would be cas_ptr() | |
3201 | |
3202 void MacroAssembler::casn (Register addr_reg, Register cmp_reg, Register set_reg ) { | |
3203 casx_under_lock (addr_reg, cmp_reg, set_reg, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()) ; | |
3204 } | |
3205 | |
3206 | |
3207 | |
3208 // compiler_lock_object() and compiler_unlock_object() are direct transliterations | |
3209 // of i486.ad fast_lock() and fast_unlock(). See those methods for detailed comments. | |
3210 // The code could be tightened up considerably. | |
3211 // | |
3212 // box->dhw disposition - post-conditions at DONE_LABEL. | |
3213 // - Successful inflated lock: box->dhw != 0. | |
3214 // Any non-zero value suffices. | |
3215 // Consider G2_thread, rsp, boxReg, or unused_mark() | |
3216 // - Successful Stack-lock: box->dhw == mark. | |
3217 // box->dhw must contain the displaced mark word value | |
3218 // - Failure -- icc.ZFlag == 0 and box->dhw is undefined. | |
3219 // The slow-path fast_enter() and slow_enter() operators | |
3220 // are responsible for setting box->dhw = NonZero (typically ::unused_mark). | |
3221 // - Biased: box->dhw is undefined | |
3222 // | |
3223 // SPARC refworkload performance - specifically jetstream and scimark - are | |
3224 // extremely sensitive to the size of the code emitted by compiler_lock_object | |
3225 // and compiler_unlock_object. Critically, the key factor is code size, not path | |
3226 // length. (Simply experiments to pad CLO with unexecuted NOPs demonstrte the | |
3227 // effect). | |
3228 | |
3229 | |
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3230 void MacroAssembler::compiler_lock_object(Register Roop, Register Rmark, |
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3231 Register Rbox, Register Rscratch, |
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3232 BiasedLockingCounters* counters, |
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3233 bool try_bias) { |
0 | 3234 Address mark_addr(Roop, 0, oopDesc::mark_offset_in_bytes()); |
3235 | |
3236 verify_oop(Roop); | |
3237 Label done ; | |
3238 | |
3239 if (counters != NULL) { | |
3240 inc_counter((address) counters->total_entry_count_addr(), Rmark, Rscratch); | |
3241 } | |
3242 | |
3243 if (EmitSync & 1) { | |
3244 mov (3, Rscratch) ; | |
3245 st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
3246 cmp (SP, G0) ; | |
3247 return ; | |
3248 } | |
3249 | |
3250 if (EmitSync & 2) { | |
3251 | |
3252 // Fetch object's markword | |
3253 ld_ptr(mark_addr, Rmark); | |
3254 | |
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3255 if (try_bias) { |
0 | 3256 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters); |
3257 } | |
3258 | |
3259 // Save Rbox in Rscratch to be used for the cas operation | |
3260 mov(Rbox, Rscratch); | |
3261 | |
3262 // set Rmark to markOop | markOopDesc::unlocked_value | |
3263 or3(Rmark, markOopDesc::unlocked_value, Rmark); | |
3264 | |
3265 // Initialize the box. (Must happen before we update the object mark!) | |
3266 st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
3267 | |
3268 // compare object markOop with Rmark and if equal exchange Rscratch with object markOop | |
3269 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); | |
3270 casx_under_lock(mark_addr.base(), Rmark, Rscratch, | |
3271 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); | |
3272 | |
3273 // if compare/exchange succeeded we found an unlocked object and we now have locked it | |
3274 // hence we are done | |
3275 cmp(Rmark, Rscratch); | |
3276 #ifdef _LP64 | |
3277 sub(Rscratch, STACK_BIAS, Rscratch); | |
3278 #endif | |
3279 brx(Assembler::equal, false, Assembler::pt, done); | |
3280 delayed()->sub(Rscratch, SP, Rscratch); //pull next instruction into delay slot | |
3281 | |
3282 // we did not find an unlocked object so see if this is a recursive case | |
3283 // sub(Rscratch, SP, Rscratch); | |
3284 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant"); | |
3285 andcc(Rscratch, 0xfffff003, Rscratch); | |
3286 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
3287 bind (done) ; | |
3288 return ; | |
3289 } | |
3290 | |
3291 Label Egress ; | |
3292 | |
3293 if (EmitSync & 256) { | |
3294 Label IsInflated ; | |
3295 | |
3296 ld_ptr (mark_addr, Rmark); // fetch obj->mark | |
3297 // Triage: biased, stack-locked, neutral, inflated | |
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3298 if (try_bias) { |
0 | 3299 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters); |
3300 // Invariant: if control reaches this point in the emitted stream | |
3301 // then Rmark has not been modified. | |
3302 } | |
3303 | |
3304 // Store mark into displaced mark field in the on-stack basic-lock "box" | |
3305 // Critically, this must happen before the CAS | |
3306 // Maximize the ST-CAS distance to minimize the ST-before-CAS penalty. | |
3307 st_ptr (Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
3308 andcc (Rmark, 2, G0) ; | |
3309 brx (Assembler::notZero, false, Assembler::pn, IsInflated) ; | |
3310 delayed() -> | |
3311 | |
3312 // Try stack-lock acquisition. | |
3313 // Beware: the 1st instruction is in a delay slot | |
3314 mov (Rbox, Rscratch); | |
3315 or3 (Rmark, markOopDesc::unlocked_value, Rmark); | |
3316 assert (mark_addr.disp() == 0, "cas must take a zero displacement"); | |
3317 casn (mark_addr.base(), Rmark, Rscratch) ; | |
3318 cmp (Rmark, Rscratch); | |
3319 brx (Assembler::equal, false, Assembler::pt, done); | |
3320 delayed()->sub(Rscratch, SP, Rscratch); | |
3321 | |
3322 // Stack-lock attempt failed - check for recursive stack-lock. | |
3323 // See the comments below about how we might remove this case. | |
3324 #ifdef _LP64 | |
3325 sub (Rscratch, STACK_BIAS, Rscratch); | |
3326 #endif | |
3327 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant"); | |
3328 andcc (Rscratch, 0xfffff003, Rscratch); | |
3329 br (Assembler::always, false, Assembler::pt, done) ; | |
3330 delayed()-> st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
3331 | |
3332 bind (IsInflated) ; | |
3333 if (EmitSync & 64) { | |
3334 // If m->owner != null goto IsLocked | |
3335 // Pessimistic form: Test-and-CAS vs CAS | |
3336 // The optimistic form avoids RTS->RTO cache line upgrades. | |
3337 ld_ptr (Address (Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2), Rscratch) ; | |
3338 andcc (Rscratch, Rscratch, G0) ; | |
3339 brx (Assembler::notZero, false, Assembler::pn, done) ; | |
3340 delayed()->nop() ; | |
3341 // m->owner == null : it's unlocked. | |
3342 } | |
3343 | |
3344 // Try to CAS m->owner from null to Self | |
3345 // Invariant: if we acquire the lock then _recursions should be 0. | |
3346 add (Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark) ; | |
3347 mov (G2_thread, Rscratch) ; | |
3348 casn (Rmark, G0, Rscratch) ; | |
3349 cmp (Rscratch, G0) ; | |
3350 // Intentional fall-through into done | |
3351 } else { | |
3352 // Aggressively avoid the Store-before-CAS penalty | |
3353 // Defer the store into box->dhw until after the CAS | |
3354 Label IsInflated, Recursive ; | |
3355 | |
3356 // Anticipate CAS -- Avoid RTS->RTO upgrade | |
3357 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads) ; | |
3358 | |
3359 ld_ptr (mark_addr, Rmark); // fetch obj->mark | |
3360 // Triage: biased, stack-locked, neutral, inflated | |
3361 | |
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3362 if (try_bias) { |
0 | 3363 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters); |
3364 // Invariant: if control reaches this point in the emitted stream | |
3365 // then Rmark has not been modified. | |
3366 } | |
3367 andcc (Rmark, 2, G0) ; | |
3368 brx (Assembler::notZero, false, Assembler::pn, IsInflated) ; | |
3369 delayed()-> // Beware - dangling delay-slot | |
3370 | |
3371 // Try stack-lock acquisition. | |
3372 // Transiently install BUSY (0) encoding in the mark word. | |
3373 // if the CAS of 0 into the mark was successful then we execute: | |
3374 // ST box->dhw = mark -- save fetched mark in on-stack basiclock box | |
3375 // ST obj->mark = box -- overwrite transient 0 value | |
3376 // This presumes TSO, of course. | |
3377 | |
3378 mov (0, Rscratch) ; | |
3379 or3 (Rmark, markOopDesc::unlocked_value, Rmark); | |
3380 assert (mark_addr.disp() == 0, "cas must take a zero displacement"); | |
3381 casn (mark_addr.base(), Rmark, Rscratch) ; | |
3382 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads) ; | |
3383 cmp (Rscratch, Rmark) ; | |
3384 brx (Assembler::notZero, false, Assembler::pn, Recursive) ; | |
3385 delayed() -> | |
3386 st_ptr (Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
3387 if (counters != NULL) { | |
3388 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch); | |
3389 } | |
3390 br (Assembler::always, false, Assembler::pt, done); | |
3391 delayed() -> | |
3392 st_ptr (Rbox, mark_addr) ; | |
3393 | |
3394 bind (Recursive) ; | |
3395 // Stack-lock attempt failed - check for recursive stack-lock. | |
3396 // Tests show that we can remove the recursive case with no impact | |
3397 // on refworkload 0.83. If we need to reduce the size of the code | |
3398 // emitted by compiler_lock_object() the recursive case is perfect | |
3399 // candidate. | |
3400 // | |
3401 // A more extreme idea is to always inflate on stack-lock recursion. | |
3402 // This lets us eliminate the recursive checks in compiler_lock_object | |
3403 // and compiler_unlock_object and the (box->dhw == 0) encoding. | |
3404 // A brief experiment - requiring changes to synchronizer.cpp, interpreter, | |
3405 // and showed a performance *increase*. In the same experiment I eliminated | |
3406 // the fast-path stack-lock code from the interpreter and always passed | |
3407 // control to the "slow" operators in synchronizer.cpp. | |
3408 | |
3409 // RScratch contains the fetched obj->mark value from the failed CASN. | |
3410 #ifdef _LP64 | |
3411 sub (Rscratch, STACK_BIAS, Rscratch); | |
3412 #endif | |
3413 sub(Rscratch, SP, Rscratch); | |
3414 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant"); | |
3415 andcc (Rscratch, 0xfffff003, Rscratch); | |
3416 if (counters != NULL) { | |
3417 // Accounting needs the Rscratch register | |
3418 st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
3419 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch); | |
3420 br (Assembler::always, false, Assembler::pt, done) ; | |
3421 delayed()->nop() ; | |
3422 } else { | |
3423 br (Assembler::always, false, Assembler::pt, done) ; | |
3424 delayed()-> st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
3425 } | |
3426 | |
3427 bind (IsInflated) ; | |
3428 if (EmitSync & 64) { | |
3429 // If m->owner != null goto IsLocked | |
3430 // Test-and-CAS vs CAS | |
3431 // Pessimistic form avoids futile (doomed) CAS attempts | |
3432 // The optimistic form avoids RTS->RTO cache line upgrades. | |
3433 ld_ptr (Address (Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2), Rscratch) ; | |
3434 andcc (Rscratch, Rscratch, G0) ; | |
3435 brx (Assembler::notZero, false, Assembler::pn, done) ; | |
3436 delayed()->nop() ; | |
3437 // m->owner == null : it's unlocked. | |
3438 } | |
3439 | |
3440 // Try to CAS m->owner from null to Self | |
3441 // Invariant: if we acquire the lock then _recursions should be 0. | |
3442 add (Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark) ; | |
3443 mov (G2_thread, Rscratch) ; | |
3444 casn (Rmark, G0, Rscratch) ; | |
3445 cmp (Rscratch, G0) ; | |
3446 // ST box->displaced_header = NonZero. | |
3447 // Any non-zero value suffices: | |
3448 // unused_mark(), G2_thread, RBox, RScratch, rsp, etc. | |
3449 st_ptr (Rbox, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
3450 // Intentional fall-through into done | |
3451 } | |
3452 | |
3453 bind (done) ; | |
3454 } | |
3455 | |
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3456 void MacroAssembler::compiler_unlock_object(Register Roop, Register Rmark, |
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3457 Register Rbox, Register Rscratch, |
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3458 bool try_bias) { |
0 | 3459 Address mark_addr(Roop, 0, oopDesc::mark_offset_in_bytes()); |
3460 | |
3461 Label done ; | |
3462 | |
3463 if (EmitSync & 4) { | |
3464 cmp (SP, G0) ; | |
3465 return ; | |
3466 } | |
3467 | |
3468 if (EmitSync & 8) { | |
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3469 if (try_bias) { |
0 | 3470 biased_locking_exit(mark_addr, Rscratch, done); |
3471 } | |
3472 | |
3473 // Test first if it is a fast recursive unlock | |
3474 ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rmark); | |
3475 cmp(Rmark, G0); | |
3476 brx(Assembler::equal, false, Assembler::pt, done); | |
3477 delayed()->nop(); | |
3478 | |
3479 // Check if it is still a light weight lock, this is is true if we see | |
3480 // the stack address of the basicLock in the markOop of the object | |
3481 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); | |
3482 casx_under_lock(mark_addr.base(), Rbox, Rmark, | |
3483 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); | |
3484 br (Assembler::always, false, Assembler::pt, done); | |
3485 delayed()->cmp(Rbox, Rmark); | |
3486 bind (done) ; | |
3487 return ; | |
3488 } | |
3489 | |
3490 // Beware ... If the aggregate size of the code emitted by CLO and CUO is | |
3491 // is too large performance rolls abruptly off a cliff. | |
3492 // This could be related to inlining policies, code cache management, or | |
3493 // I$ effects. | |
3494 Label LStacked ; | |
3495 | |
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3496 if (try_bias) { |
0 | 3497 // TODO: eliminate redundant LDs of obj->mark |
3498 biased_locking_exit(mark_addr, Rscratch, done); | |
3499 } | |
3500 | |
3501 ld_ptr (Roop, oopDesc::mark_offset_in_bytes(), Rmark) ; | |
3502 ld_ptr (Rbox, BasicLock::displaced_header_offset_in_bytes(), Rscratch); | |
3503 andcc (Rscratch, Rscratch, G0); | |
3504 brx (Assembler::zero, false, Assembler::pn, done); | |
3505 delayed()-> nop() ; // consider: relocate fetch of mark, above, into this DS | |
3506 andcc (Rmark, 2, G0) ; | |
3507 brx (Assembler::zero, false, Assembler::pt, LStacked) ; | |
3508 delayed()-> nop() ; | |
3509 | |
3510 // It's inflated | |
3511 // Conceptually we need a #loadstore|#storestore "release" MEMBAR before | |
3512 // the ST of 0 into _owner which releases the lock. This prevents loads | |
3513 // and stores within the critical section from reordering (floating) | |
3514 // past the store that releases the lock. But TSO is a strong memory model | |
3515 // and that particular flavor of barrier is a noop, so we can safely elide it. | |
3516 // Note that we use 1-0 locking by default for the inflated case. We | |
3517 // close the resultant (and rare) race by having contented threads in | |
3518 // monitorenter periodically poll _owner. | |
3519 ld_ptr (Address(Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2), Rscratch) ; | |
3520 ld_ptr (Address(Rmark, 0, ObjectMonitor::recursions_offset_in_bytes()-2), Rbox) ; | |
3521 xor3 (Rscratch, G2_thread, Rscratch) ; | |
3522 orcc (Rbox, Rscratch, Rbox) ; | |
3523 brx (Assembler::notZero, false, Assembler::pn, done) ; | |
3524 delayed()-> | |
3525 ld_ptr (Address (Rmark, 0, ObjectMonitor::EntryList_offset_in_bytes()-2), Rscratch) ; | |
3526 ld_ptr (Address (Rmark, 0, ObjectMonitor::cxq_offset_in_bytes()-2), Rbox) ; | |
3527 orcc (Rbox, Rscratch, G0) ; | |
3528 if (EmitSync & 65536) { | |
3529 Label LSucc ; | |
3530 brx (Assembler::notZero, false, Assembler::pn, LSucc) ; | |
3531 delayed()->nop() ; | |
3532 br (Assembler::always, false, Assembler::pt, done) ; | |
3533 delayed()-> | |
3534 st_ptr (G0, Address (Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
3535 | |
3536 bind (LSucc) ; | |
3537 st_ptr (G0, Address (Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
3538 if (os::is_MP()) { membar (StoreLoad) ; } | |
3539 ld_ptr (Address (Rmark, 0, ObjectMonitor::succ_offset_in_bytes()-2), Rscratch) ; | |
3540 andcc (Rscratch, Rscratch, G0) ; | |
3541 brx (Assembler::notZero, false, Assembler::pt, done) ; | |
3542 delayed()-> andcc (G0, G0, G0) ; | |
3543 add (Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark) ; | |
3544 mov (G2_thread, Rscratch) ; | |
3545 casn (Rmark, G0, Rscratch) ; | |
3546 cmp (Rscratch, G0) ; | |
3547 // invert icc.zf and goto done | |
3548 brx (Assembler::notZero, false, Assembler::pt, done) ; | |
3549 delayed() -> cmp (G0, G0) ; | |
3550 br (Assembler::always, false, Assembler::pt, done); | |
3551 delayed() -> cmp (G0, 1) ; | |
3552 } else { | |
3553 brx (Assembler::notZero, false, Assembler::pn, done) ; | |
3554 delayed()->nop() ; | |
3555 br (Assembler::always, false, Assembler::pt, done) ; | |
3556 delayed()-> | |
3557 st_ptr (G0, Address (Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
3558 } | |
3559 | |
3560 bind (LStacked) ; | |
3561 // Consider: we could replace the expensive CAS in the exit | |
3562 // path with a simple ST of the displaced mark value fetched from | |
3563 // the on-stack basiclock box. That admits a race where a thread T2 | |
3564 // in the slow lock path -- inflating with monitor M -- could race a | |
3565 // thread T1 in the fast unlock path, resulting in a missed wakeup for T2. | |
3566 // More precisely T1 in the stack-lock unlock path could "stomp" the | |
3567 // inflated mark value M installed by T2, resulting in an orphan | |
3568 // object monitor M and T2 becoming stranded. We can remedy that situation | |
3569 // by having T2 periodically poll the object's mark word using timed wait | |
3570 // operations. If T2 discovers that a stomp has occurred it vacates | |
3571 // the monitor M and wakes any other threads stranded on the now-orphan M. | |
3572 // In addition the monitor scavenger, which performs deflation, | |
3573 // would also need to check for orpan monitors and stranded threads. | |
3574 // | |
3575 // Finally, inflation is also used when T2 needs to assign a hashCode | |
3576 // to O and O is stack-locked by T1. The "stomp" race could cause | |
3577 // an assigned hashCode value to be lost. We can avoid that condition | |
3578 // and provide the necessary hashCode stability invariants by ensuring | |
3579 // that hashCode generation is idempotent between copying GCs. | |
3580 // For example we could compute the hashCode of an object O as | |
3581 // O's heap address XOR some high quality RNG value that is refreshed | |
3582 // at GC-time. The monitor scavenger would install the hashCode | |
3583 // found in any orphan monitors. Again, the mechanism admits a | |
3584 // lost-update "stomp" WAW race but detects and recovers as needed. | |
3585 // | |
3586 // A prototype implementation showed excellent results, although | |
3587 // the scavenger and timeout code was rather involved. | |
3588 | |
3589 casn (mark_addr.base(), Rbox, Rscratch) ; | |
3590 cmp (Rbox, Rscratch); | |
3591 // Intentional fall through into done ... | |
3592 | |
3593 bind (done) ; | |
3594 } | |
3595 | |
3596 | |
3597 | |
3598 void MacroAssembler::print_CPU_state() { | |
3599 // %%%%% need to implement this | |
3600 } | |
3601 | |
3602 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { | |
3603 // %%%%% need to implement this | |
3604 } | |
3605 | |
3606 void MacroAssembler::push_IU_state() { | |
3607 // %%%%% need to implement this | |
3608 } | |
3609 | |
3610 | |
3611 void MacroAssembler::pop_IU_state() { | |
3612 // %%%%% need to implement this | |
3613 } | |
3614 | |
3615 | |
3616 void MacroAssembler::push_FPU_state() { | |
3617 // %%%%% need to implement this | |
3618 } | |
3619 | |
3620 | |
3621 void MacroAssembler::pop_FPU_state() { | |
3622 // %%%%% need to implement this | |
3623 } | |
3624 | |
3625 | |
3626 void MacroAssembler::push_CPU_state() { | |
3627 // %%%%% need to implement this | |
3628 } | |
3629 | |
3630 | |
3631 void MacroAssembler::pop_CPU_state() { | |
3632 // %%%%% need to implement this | |
3633 } | |
3634 | |
3635 | |
3636 | |
3637 void MacroAssembler::verify_tlab() { | |
3638 #ifdef ASSERT | |
3639 if (UseTLAB && VerifyOops) { | |
3640 Label next, next2, ok; | |
3641 Register t1 = L0; | |
3642 Register t2 = L1; | |
3643 Register t3 = L2; | |
3644 | |
3645 save_frame(0); | |
3646 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1); | |
3647 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t2); | |
3648 or3(t1, t2, t3); | |
3649 cmp(t1, t2); | |
3650 br(Assembler::greaterEqual, false, Assembler::pn, next); | |
3651 delayed()->nop(); | |
3652 stop("assert(top >= start)"); | |
3653 should_not_reach_here(); | |
3654 | |
3655 bind(next); | |
3656 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1); | |
3657 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t2); | |
3658 or3(t3, t2, t3); | |
3659 cmp(t1, t2); | |
3660 br(Assembler::lessEqual, false, Assembler::pn, next2); | |
3661 delayed()->nop(); | |
3662 stop("assert(top <= end)"); | |
3663 should_not_reach_here(); | |
3664 | |
3665 bind(next2); | |
3666 and3(t3, MinObjAlignmentInBytesMask, t3); | |
3667 cmp(t3, 0); | |
3668 br(Assembler::lessEqual, false, Assembler::pn, ok); | |
3669 delayed()->nop(); | |
3670 stop("assert(aligned)"); | |
3671 should_not_reach_here(); | |
3672 | |
3673 bind(ok); | |
3674 restore(); | |
3675 } | |
3676 #endif | |
3677 } | |
3678 | |
3679 | |
3680 void MacroAssembler::eden_allocate( | |
3681 Register obj, // result: pointer to object after successful allocation | |
3682 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise | |
3683 int con_size_in_bytes, // object size in bytes if known at compile time | |
3684 Register t1, // temp register | |
3685 Register t2, // temp register | |
3686 Label& slow_case // continuation point if fast allocation fails | |
3687 ){ | |
3688 // make sure arguments make sense | |
3689 assert_different_registers(obj, var_size_in_bytes, t1, t2); | |
3690 assert(0 <= con_size_in_bytes && Assembler::is_simm13(con_size_in_bytes), "illegal object size"); | |
3691 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment"); | |
3692 | |
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3693 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { |
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3694 // No allocation in the shared eden. |
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3695 br(Assembler::always, false, Assembler::pt, slow_case); |
0 | 3696 delayed()->nop(); |
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3697 } else { |
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3698 // get eden boundaries |
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3699 // note: we need both top & top_addr! |
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3700 const Register top_addr = t1; |
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3701 const Register end = t2; |
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3702 |
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3703 CollectedHeap* ch = Universe::heap(); |
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3704 set((intx)ch->top_addr(), top_addr); |
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3705 intx delta = (intx)ch->end_addr() - (intx)ch->top_addr(); |
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3706 ld_ptr(top_addr, delta, end); |
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3707 ld_ptr(top_addr, 0, obj); |
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3708 |
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3709 // try to allocate |
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3710 Label retry; |
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3711 bind(retry); |
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3712 #ifdef ASSERT |
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3713 // make sure eden top is properly aligned |
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3714 { |
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3715 Label L; |
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3716 btst(MinObjAlignmentInBytesMask, obj); |
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3717 br(Assembler::zero, false, Assembler::pt, L); |
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3718 delayed()->nop(); |
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3719 stop("eden top is not properly aligned"); |
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3720 bind(L); |
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3721 } |
0 | 3722 #endif // ASSERT |
342
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3723 const Register free = end; |
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3724 sub(end, obj, free); // compute amount of free space |
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3725 if (var_size_in_bytes->is_valid()) { |
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3726 // size is unknown at compile time |
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3727 cmp(free, var_size_in_bytes); |
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3728 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case |
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3729 delayed()->add(obj, var_size_in_bytes, end); |
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3730 } else { |
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3731 // size is known at compile time |
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3732 cmp(free, con_size_in_bytes); |
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3733 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case |
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3734 delayed()->add(obj, con_size_in_bytes, end); |
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3735 } |
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3736 // Compare obj with the value at top_addr; if still equal, swap the value of |
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3737 // end with the value at top_addr. If not equal, read the value at top_addr |
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3738 // into end. |
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3739 casx_under_lock(top_addr, obj, end, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); |
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3740 // if someone beat us on the allocation, try again, otherwise continue |
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3741 cmp(obj, end); |
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3742 brx(Assembler::notEqual, false, Assembler::pn, retry); |
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3743 delayed()->mov(end, obj); // nop if successfull since obj == end |
0 | 3744 |
3745 #ifdef ASSERT | |
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3746 // make sure eden top is properly aligned |
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3747 { |
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3748 Label L; |
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3749 const Register top_addr = t1; |
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3750 |
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3751 set((intx)ch->top_addr(), top_addr); |
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3752 ld_ptr(top_addr, 0, top_addr); |
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3753 btst(MinObjAlignmentInBytesMask, top_addr); |
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3754 br(Assembler::zero, false, Assembler::pt, L); |
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3755 delayed()->nop(); |
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3756 stop("eden top is not properly aligned"); |
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3757 bind(L); |
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3758 } |
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3759 #endif // ASSERT |
0 | 3760 } |
3761 } | |
3762 | |
3763 | |
3764 void MacroAssembler::tlab_allocate( | |
3765 Register obj, // result: pointer to object after successful allocation | |
3766 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise | |
3767 int con_size_in_bytes, // object size in bytes if known at compile time | |
3768 Register t1, // temp register | |
3769 Label& slow_case // continuation point if fast allocation fails | |
3770 ){ | |
3771 // make sure arguments make sense | |
3772 assert_different_registers(obj, var_size_in_bytes, t1); | |
3773 assert(0 <= con_size_in_bytes && is_simm13(con_size_in_bytes), "illegal object size"); | |
3774 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment"); | |
3775 | |
3776 const Register free = t1; | |
3777 | |
3778 verify_tlab(); | |
3779 | |
3780 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), obj); | |
3781 | |
3782 // calculate amount of free space | |
3783 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), free); | |
3784 sub(free, obj, free); | |
3785 | |
3786 Label done; | |
3787 if (var_size_in_bytes == noreg) { | |
3788 cmp(free, con_size_in_bytes); | |
3789 } else { | |
3790 cmp(free, var_size_in_bytes); | |
3791 } | |
3792 br(Assembler::less, false, Assembler::pn, slow_case); | |
3793 // calculate the new top pointer | |
3794 if (var_size_in_bytes == noreg) { | |
3795 delayed()->add(obj, con_size_in_bytes, free); | |
3796 } else { | |
3797 delayed()->add(obj, var_size_in_bytes, free); | |
3798 } | |
3799 | |
3800 bind(done); | |
3801 | |
3802 #ifdef ASSERT | |
3803 // make sure new free pointer is properly aligned | |
3804 { | |
3805 Label L; | |
3806 btst(MinObjAlignmentInBytesMask, free); | |
3807 br(Assembler::zero, false, Assembler::pt, L); | |
3808 delayed()->nop(); | |
3809 stop("updated TLAB free is not properly aligned"); | |
3810 bind(L); | |
3811 } | |
3812 #endif // ASSERT | |
3813 | |
3814 // update the tlab top pointer | |
3815 st_ptr(free, G2_thread, in_bytes(JavaThread::tlab_top_offset())); | |
3816 verify_tlab(); | |
3817 } | |
3818 | |
3819 | |
3820 void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) { | |
3821 Register top = O0; | |
3822 Register t1 = G1; | |
3823 Register t2 = G3; | |
3824 Register t3 = O1; | |
3825 assert_different_registers(top, t1, t2, t3, G4, G5 /* preserve G4 and G5 */); | |
3826 Label do_refill, discard_tlab; | |
3827 | |
3828 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { | |
3829 // No allocation in the shared eden. | |
3830 br(Assembler::always, false, Assembler::pt, slow_case); | |
3831 delayed()->nop(); | |
3832 } | |
3833 | |
3834 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), top); | |
3835 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t1); | |
3836 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()), t2); | |
3837 | |
3838 // calculate amount of free space | |
3839 sub(t1, top, t1); | |
3840 srl_ptr(t1, LogHeapWordSize, t1); | |
3841 | |
3842 // Retain tlab and allocate object in shared space if | |
3843 // the amount free in the tlab is too large to discard. | |
3844 cmp(t1, t2); | |
3845 brx(Assembler::lessEqual, false, Assembler::pt, discard_tlab); | |
3846 | |
3847 // increment waste limit to prevent getting stuck on this slow path | |
3848 delayed()->add(t2, ThreadLocalAllocBuffer::refill_waste_limit_increment(), t2); | |
3849 st_ptr(t2, G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset())); | |
3850 if (TLABStats) { | |
3851 // increment number of slow_allocations | |
3852 ld(G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset()), t2); | |
3853 add(t2, 1, t2); | |
3854 stw(t2, G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset())); | |
3855 } | |
3856 br(Assembler::always, false, Assembler::pt, try_eden); | |
3857 delayed()->nop(); | |
3858 | |
3859 bind(discard_tlab); | |
3860 if (TLABStats) { | |
3861 // increment number of refills | |
3862 ld(G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset()), t2); | |
3863 add(t2, 1, t2); | |
3864 stw(t2, G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset())); | |
3865 // accumulate wastage | |
3866 ld(G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset()), t2); | |
3867 add(t2, t1, t2); | |
3868 stw(t2, G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset())); | |
3869 } | |
3870 | |
3871 // if tlab is currently allocated (top or end != null) then | |
3872 // fill [top, end + alignment_reserve) with array object | |
3873 br_null(top, false, Assembler::pn, do_refill); | |
3874 delayed()->nop(); | |
3875 | |
3876 set((intptr_t)markOopDesc::prototype()->copy_set_hash(0x2), t2); | |
3877 st_ptr(t2, top, oopDesc::mark_offset_in_bytes()); // set up the mark word | |
3878 // set klass to intArrayKlass | |
3879 sub(t1, typeArrayOopDesc::header_size(T_INT), t1); | |
3880 add(t1, ThreadLocalAllocBuffer::alignment_reserve(), t1); | |
3881 sll_ptr(t1, log2_intptr(HeapWordSize/sizeof(jint)), t1); | |
3882 st(t1, top, arrayOopDesc::length_offset_in_bytes()); | |
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3883 set((intptr_t)Universe::intArrayKlassObj_addr(), t2); |
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3884 ld_ptr(t2, 0, t2); |
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3885 // store klass last. concurrent gcs assumes klass length is valid if |
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3886 // klass field is not null. |
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3887 store_klass(t2, top); |
0 | 3888 verify_oop(top); |
3889 | |
3890 // refill the tlab with an eden allocation | |
3891 bind(do_refill); | |
3892 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t1); | |
3893 sll_ptr(t1, LogHeapWordSize, t1); | |
3894 // add object_size ?? | |
3895 eden_allocate(top, t1, 0, t2, t3, slow_case); | |
3896 | |
3897 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_start_offset())); | |
3898 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_top_offset())); | |
3899 #ifdef ASSERT | |
3900 // check that tlab_size (t1) is still valid | |
3901 { | |
3902 Label ok; | |
3903 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t2); | |
3904 sll_ptr(t2, LogHeapWordSize, t2); | |
3905 cmp(t1, t2); | |
3906 br(Assembler::equal, false, Assembler::pt, ok); | |
3907 delayed()->nop(); | |
3908 stop("assert(t1 == tlab_size)"); | |
3909 should_not_reach_here(); | |
3910 | |
3911 bind(ok); | |
3912 } | |
3913 #endif // ASSERT | |
3914 add(top, t1, top); // t1 is tlab_size | |
3915 sub(top, ThreadLocalAllocBuffer::alignment_reserve_in_bytes(), top); | |
3916 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_end_offset())); | |
3917 verify_tlab(); | |
3918 br(Assembler::always, false, Assembler::pt, retry); | |
3919 delayed()->nop(); | |
3920 } | |
3921 | |
3922 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { | |
3923 switch (cond) { | |
3924 // Note some conditions are synonyms for others | |
3925 case Assembler::never: return Assembler::always; | |
3926 case Assembler::zero: return Assembler::notZero; | |
3927 case Assembler::lessEqual: return Assembler::greater; | |
3928 case Assembler::less: return Assembler::greaterEqual; | |
3929 case Assembler::lessEqualUnsigned: return Assembler::greaterUnsigned; | |
3930 case Assembler::lessUnsigned: return Assembler::greaterEqualUnsigned; | |
3931 case Assembler::negative: return Assembler::positive; | |
3932 case Assembler::overflowSet: return Assembler::overflowClear; | |
3933 case Assembler::always: return Assembler::never; | |
3934 case Assembler::notZero: return Assembler::zero; | |
3935 case Assembler::greater: return Assembler::lessEqual; | |
3936 case Assembler::greaterEqual: return Assembler::less; | |
3937 case Assembler::greaterUnsigned: return Assembler::lessEqualUnsigned; | |
3938 case Assembler::greaterEqualUnsigned: return Assembler::lessUnsigned; | |
3939 case Assembler::positive: return Assembler::negative; | |
3940 case Assembler::overflowClear: return Assembler::overflowSet; | |
3941 } | |
3942 | |
3943 ShouldNotReachHere(); return Assembler::overflowClear; | |
3944 } | |
3945 | |
3946 void MacroAssembler::cond_inc(Assembler::Condition cond, address counter_ptr, | |
3947 Register Rtmp1, Register Rtmp2 /*, Register Rtmp3, Register Rtmp4 */) { | |
3948 Condition negated_cond = negate_condition(cond); | |
3949 Label L; | |
3950 brx(negated_cond, false, Assembler::pt, L); | |
3951 delayed()->nop(); | |
3952 inc_counter(counter_ptr, Rtmp1, Rtmp2); | |
3953 bind(L); | |
3954 } | |
3955 | |
3956 void MacroAssembler::inc_counter(address counter_ptr, Register Rtmp1, Register Rtmp2) { | |
3957 Address counter_addr(Rtmp1, counter_ptr); | |
3958 load_contents(counter_addr, Rtmp2); | |
3959 inc(Rtmp2); | |
3960 store_contents(Rtmp2, counter_addr); | |
3961 } | |
3962 | |
3963 SkipIfEqual::SkipIfEqual( | |
3964 MacroAssembler* masm, Register temp, const bool* flag_addr, | |
3965 Assembler::Condition condition) { | |
3966 _masm = masm; | |
3967 Address flag(temp, (address)flag_addr, relocInfo::none); | |
3968 _masm->sethi(flag); | |
3969 _masm->ldub(flag, temp); | |
3970 _masm->tst(temp); | |
3971 _masm->br(condition, false, Assembler::pt, _label); | |
3972 _masm->delayed()->nop(); | |
3973 } | |
3974 | |
3975 SkipIfEqual::~SkipIfEqual() { | |
3976 _masm->bind(_label); | |
3977 } | |
3978 | |
3979 | |
3980 // Writes to stack successive pages until offset reached to check for | |
3981 // stack overflow + shadow pages. This clobbers tsp and scratch. | |
3982 void MacroAssembler::bang_stack_size(Register Rsize, Register Rtsp, | |
3983 Register Rscratch) { | |
3984 // Use stack pointer in temp stack pointer | |
3985 mov(SP, Rtsp); | |
3986 | |
3987 // Bang stack for total size given plus stack shadow page size. | |
3988 // Bang one page at a time because a large size can overflow yellow and | |
3989 // red zones (the bang will fail but stack overflow handling can't tell that | |
3990 // it was a stack overflow bang vs a regular segv). | |
3991 int offset = os::vm_page_size(); | |
3992 Register Roffset = Rscratch; | |
3993 | |
3994 Label loop; | |
3995 bind(loop); | |
3996 set((-offset)+STACK_BIAS, Rscratch); | |
3997 st(G0, Rtsp, Rscratch); | |
3998 set(offset, Roffset); | |
3999 sub(Rsize, Roffset, Rsize); | |
4000 cmp(Rsize, G0); | |
4001 br(Assembler::greater, false, Assembler::pn, loop); | |
4002 delayed()->sub(Rtsp, Roffset, Rtsp); | |
4003 | |
4004 // Bang down shadow pages too. | |
4005 // The -1 because we already subtracted 1 page. | |
4006 for (int i = 0; i< StackShadowPages-1; i++) { | |
4007 set((-i*offset)+STACK_BIAS, Rscratch); | |
4008 st(G0, Rtsp, Rscratch); | |
4009 } | |
4010 } | |
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4011 |
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4012 /////////////////////////////////////////////////////////////////////////////////// |
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4013 #ifndef SERIALGC |
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4014 |
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4015 static uint num_stores = 0; |
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4016 static uint num_null_pre_stores = 0; |
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4017 |
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4018 static void count_null_pre_vals(void* pre_val) { |
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4019 num_stores++; |
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4020 if (pre_val == NULL) num_null_pre_stores++; |
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4021 if ((num_stores % 1000000) == 0) { |
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4022 tty->print_cr(UINT32_FORMAT " stores, " UINT32_FORMAT " (%5.2f%%) with null pre-vals.", |
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4023 num_stores, num_null_pre_stores, |
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4024 100.0*(float)num_null_pre_stores/(float)num_stores); |
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4025 } |
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4026 } |
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4027 |
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4028 static address satb_log_enqueue_with_frame = 0; |
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4029 static u_char* satb_log_enqueue_with_frame_end = 0; |
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4030 |
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4031 static address satb_log_enqueue_frameless = 0; |
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4032 static u_char* satb_log_enqueue_frameless_end = 0; |
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4033 |
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4034 static int EnqueueCodeSize = 128 DEBUG_ONLY( + 256); // Instructions? |
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4035 |
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4036 // The calls to this don't work. We'd need to do a fair amount of work to |
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4037 // make it work. |
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4038 static void check_index(int ind) { |
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4039 assert(0 <= ind && ind <= 64*K && ((ind % oopSize) == 0), |
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4040 "Invariants.") |
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4041 } |
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4042 |
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4043 static void generate_satb_log_enqueue(bool with_frame) { |
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4044 BufferBlob* bb = BufferBlob::create("enqueue_with_frame", EnqueueCodeSize); |
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4045 CodeBuffer buf(bb->instructions_begin(), bb->instructions_size()); |
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4046 MacroAssembler masm(&buf); |
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4047 address start = masm.pc(); |
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4048 Register pre_val; |
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4049 |
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4050 Label refill, restart; |
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4051 if (with_frame) { |
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4052 masm.save_frame(0); |
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4053 pre_val = I0; // Was O0 before the save. |
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4054 } else { |
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4055 pre_val = O0; |
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4056 } |
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4057 int satb_q_index_byte_offset = |
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4058 in_bytes(JavaThread::satb_mark_queue_offset() + |
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4059 PtrQueue::byte_offset_of_index()); |
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4060 int satb_q_buf_byte_offset = |
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4061 in_bytes(JavaThread::satb_mark_queue_offset() + |
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4062 PtrQueue::byte_offset_of_buf()); |
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4063 assert(in_bytes(PtrQueue::byte_width_of_index()) == sizeof(intptr_t) && |
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4064 in_bytes(PtrQueue::byte_width_of_buf()) == sizeof(intptr_t), |
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4065 "check sizes in assembly below"); |
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4066 |
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4067 masm.bind(restart); |
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4068 masm.ld_ptr(G2_thread, satb_q_index_byte_offset, L0); |
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4069 |
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4070 masm.br_on_reg_cond(Assembler::rc_z, /*annul*/false, Assembler::pn, L0, refill); |
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4071 // If the branch is taken, no harm in executing this in the delay slot. |
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4072 masm.delayed()->ld_ptr(G2_thread, satb_q_buf_byte_offset, L1); |
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4073 masm.sub(L0, oopSize, L0); |
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4074 |
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4075 masm.st_ptr(pre_val, L1, L0); // [_buf + index] := I0 |
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4076 if (!with_frame) { |
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4077 // Use return-from-leaf |
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4078 masm.retl(); |
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4079 masm.delayed()->st_ptr(L0, G2_thread, satb_q_index_byte_offset); |
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4080 } else { |
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4081 // Not delayed. |
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4082 masm.st_ptr(L0, G2_thread, satb_q_index_byte_offset); |
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4083 } |
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4084 if (with_frame) { |
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4085 masm.ret(); |
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4086 masm.delayed()->restore(); |
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4087 } |
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4088 masm.bind(refill); |
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4089 |
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4090 address handle_zero = |
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4091 CAST_FROM_FN_PTR(address, |
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4092 &SATBMarkQueueSet::handle_zero_index_for_thread); |
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4093 // This should be rare enough that we can afford to save all the |
37f87013dfd8
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diff
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|
4094 // scratch registers that the calling context might be using. |
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diff
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|
4095 masm.mov(G1_scratch, L0); |
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diff
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|
4096 masm.mov(G3_scratch, L1); |
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diff
changeset
|
4097 masm.mov(G4, L2); |
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|
4098 // We need the value of O0 above (for the write into the buffer), so we |
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|
4099 // save and restore it. |
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diff
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|
4100 masm.mov(O0, L3); |
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diff
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|
4101 // Since the call will overwrite O7, we save and restore that, as well. |
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|
4102 masm.mov(O7, L4); |
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|
4103 masm.call_VM_leaf(L5, handle_zero, G2_thread); |
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|
4104 masm.mov(L0, G1_scratch); |
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diff
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|
4105 masm.mov(L1, G3_scratch); |
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124
diff
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|
4106 masm.mov(L2, G4); |
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124
diff
changeset
|
4107 masm.mov(L3, O0); |
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|
4108 masm.br(Assembler::always, /*annul*/false, Assembler::pt, restart); |
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|
4109 masm.delayed()->mov(L4, O7); |
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diff
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|
4110 |
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|
4111 if (with_frame) { |
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|
4112 satb_log_enqueue_with_frame = start; |
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|
4113 satb_log_enqueue_with_frame_end = masm.pc(); |
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|
4114 } else { |
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|
4115 satb_log_enqueue_frameless = start; |
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|
4116 satb_log_enqueue_frameless_end = masm.pc(); |
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|
4117 } |
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124
diff
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|
4118 } |
37f87013dfd8
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diff
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|
4119 |
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|
4120 static inline void generate_satb_log_enqueue_if_necessary(bool with_frame) { |
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4121 if (with_frame) { |
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|
4122 if (satb_log_enqueue_with_frame == 0) { |
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|
4123 generate_satb_log_enqueue(with_frame); |
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|
4124 assert(satb_log_enqueue_with_frame != 0, "postcondition."); |
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|
4125 if (G1SATBPrintStubs) { |
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|
4126 tty->print_cr("Generated with-frame satb enqueue:"); |
37f87013dfd8
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4127 Disassembler::decode((u_char*)satb_log_enqueue_with_frame, |
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|
4128 satb_log_enqueue_with_frame_end, |
37f87013dfd8
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124
diff
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|
4129 tty); |
37f87013dfd8
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diff
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|
4130 } |
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diff
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|
4131 } |
37f87013dfd8
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124
diff
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|
4132 } else { |
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|
4133 if (satb_log_enqueue_frameless == 0) { |
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|
4134 generate_satb_log_enqueue(with_frame); |
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|
4135 assert(satb_log_enqueue_frameless != 0, "postcondition."); |
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|
4136 if (G1SATBPrintStubs) { |
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|
4137 tty->print_cr("Generated frameless satb enqueue:"); |
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|
4138 Disassembler::decode((u_char*)satb_log_enqueue_frameless, |
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|
4139 satb_log_enqueue_frameless_end, |
37f87013dfd8
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|
4140 tty); |
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|
4141 } |
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diff
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|
4142 } |
37f87013dfd8
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diff
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|
4143 } |
37f87013dfd8
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124
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|
4144 } |
37f87013dfd8
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|
4145 |
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|
4146 void MacroAssembler::g1_write_barrier_pre(Register obj, Register index, int offset, Register tmp, bool preserve_o_regs) { |
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4147 assert(offset == 0 || index == noreg, "choose one"); |
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|
4148 |
37f87013dfd8
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|
4149 if (G1DisablePreBarrier) return; |
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|
4150 // satb_log_barrier(tmp, obj, offset, preserve_o_regs); |
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|
4151 Label filtered; |
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|
4152 // satb_log_barrier_work0(tmp, filtered); |
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|
4153 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) { |
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|
4154 ld(G2, |
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changeset
|
4155 in_bytes(JavaThread::satb_mark_queue_offset() + |
37f87013dfd8
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|
4156 PtrQueue::byte_offset_of_active()), |
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|
4157 tmp); |
37f87013dfd8
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|
4158 } else { |
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|
4159 guarantee(in_bytes(PtrQueue::byte_width_of_active()) == 1, |
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|
4160 "Assumption"); |
37f87013dfd8
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|
4161 ldsb(G2, |
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|
4162 in_bytes(JavaThread::satb_mark_queue_offset() + |
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|
4163 PtrQueue::byte_offset_of_active()), |
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diff
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|
4164 tmp); |
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|
4165 } |
37f87013dfd8
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|
4166 // Check on whether to annul. |
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|
4167 br_on_reg_cond(rc_z, /*annul*/false, Assembler::pt, tmp, filtered); |
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|
4168 delayed() -> nop(); |
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|
4169 |
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|
4170 // satb_log_barrier_work1(tmp, offset); |
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|
4171 if (index == noreg) { |
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|
4172 if (Assembler::is_simm13(offset)) { |
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|
4173 ld_ptr(obj, offset, tmp); |
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|
4174 } else { |
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|
4175 set(offset, tmp); |
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|
4176 ld_ptr(obj, tmp, tmp); |
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|
4177 } |
37f87013dfd8
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|
4178 } else { |
37f87013dfd8
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|
4179 ld_ptr(obj, index, tmp); |
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|
4180 } |
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|
4181 |
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|
4182 // satb_log_barrier_work2(obj, tmp, offset); |
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|
4183 |
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|
4184 // satb_log_barrier_work3(tmp, filtered, preserve_o_regs); |
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|
4185 |
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|
4186 const Register pre_val = tmp; |
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|
4187 |
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|
4188 if (G1SATBBarrierPrintNullPreVals) { |
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|
4189 save_frame(0); |
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|
4190 mov(pre_val, O0); |
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|
4191 // Save G-regs that target may use. |
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|
4192 mov(G1, L1); |
37f87013dfd8
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|
4193 mov(G2, L2); |
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|
4194 mov(G3, L3); |
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|
4195 mov(G4, L4); |
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|
4196 mov(G5, L5); |
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|
4197 call(CAST_FROM_FN_PTR(address, &count_null_pre_vals)); |
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|
4198 delayed()->nop(); |
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|
4199 // Restore G-regs that target may have used. |
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|
4200 mov(L1, G1); |
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|
4201 mov(L2, G2); |
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|
4202 mov(L3, G3); |
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|
4203 mov(L4, G4); |
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|
4204 mov(L5, G5); |
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|
4205 restore(G0, G0, G0); |
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|
4206 } |
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|
4207 |
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4208 // Check on whether to annul. |
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4209 br_on_reg_cond(rc_z, /*annul*/false, Assembler::pt, pre_val, filtered); |
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|
4210 delayed() -> nop(); |
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|
4211 |
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4212 // OK, it's not filtered, so we'll need to call enqueue. In the normal |
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4213 // case, pre_val will be a scratch G-reg, but there's some cases in which |
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4214 // it's an O-reg. In the first case, do a normal call. In the latter, |
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4215 // do a save here and call the frameless version. |
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|
4216 |
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4217 guarantee(pre_val->is_global() || pre_val->is_out(), |
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4218 "Or we need to think harder."); |
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4219 if (pre_val->is_global() && !preserve_o_regs) { |
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4220 generate_satb_log_enqueue_if_necessary(true); // with frame. |
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|
4221 call(satb_log_enqueue_with_frame); |
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|
4222 delayed()->mov(pre_val, O0); |
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|
4223 } else { |
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|
4224 generate_satb_log_enqueue_if_necessary(false); // with frameless. |
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4225 save_frame(0); |
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4226 call(satb_log_enqueue_frameless); |
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4227 delayed()->mov(pre_val->after_save(), O0); |
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4228 restore(); |
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|
4229 } |
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|
4230 |
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|
4231 bind(filtered); |
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|
4232 } |
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|
4233 |
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4234 static jint num_ct_writes = 0; |
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4235 static jint num_ct_writes_filtered_in_hr = 0; |
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4236 static jint num_ct_writes_filtered_null = 0; |
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4237 static G1CollectedHeap* g1 = NULL; |
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|
4238 |
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4239 static Thread* count_ct_writes(void* filter_val, void* new_val) { |
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4240 Atomic::inc(&num_ct_writes); |
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|
4241 if (filter_val == NULL) { |
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|
4242 Atomic::inc(&num_ct_writes_filtered_in_hr); |
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4243 } else if (new_val == NULL) { |
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4244 Atomic::inc(&num_ct_writes_filtered_null); |
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|
4245 } else { |
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|
4246 if (g1 == NULL) { |
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|
4247 g1 = G1CollectedHeap::heap(); |
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|
4248 } |
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|
4249 } |
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4250 if ((num_ct_writes % 1000000) == 0) { |
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4251 jint num_ct_writes_filtered = |
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4252 num_ct_writes_filtered_in_hr + |
677 | 4253 num_ct_writes_filtered_null; |
342
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4254 |
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|
4255 tty->print_cr("%d potential CT writes: %5.2f%% filtered\n" |
677 | 4256 " (%5.2f%% intra-HR, %5.2f%% null).", |
342
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|
4257 num_ct_writes, |
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4258 100.0*(float)num_ct_writes_filtered/(float)num_ct_writes, |
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4259 100.0*(float)num_ct_writes_filtered_in_hr/ |
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|
4260 (float)num_ct_writes, |
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|
4261 100.0*(float)num_ct_writes_filtered_null/ |
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4262 (float)num_ct_writes); |
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|
4263 } |
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4264 return Thread::current(); |
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|
4265 } |
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|
4266 |
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4267 static address dirty_card_log_enqueue = 0; |
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4268 static u_char* dirty_card_log_enqueue_end = 0; |
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4269 |
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4270 // This gets to assume that o0 contains the object address. |
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4271 static void generate_dirty_card_log_enqueue(jbyte* byte_map_base) { |
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4272 BufferBlob* bb = BufferBlob::create("dirty_card_enqueue", EnqueueCodeSize*2); |
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4273 CodeBuffer buf(bb->instructions_begin(), bb->instructions_size()); |
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4274 MacroAssembler masm(&buf); |
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4275 address start = masm.pc(); |
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|
4276 |
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|
4277 Label not_already_dirty, restart, refill; |
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|
4278 |
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|
4279 #ifdef _LP64 |
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4280 masm.srlx(O0, CardTableModRefBS::card_shift, O0); |
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4281 #else |
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|
4282 masm.srl(O0, CardTableModRefBS::card_shift, O0); |
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4283 #endif |
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4284 Address rs(O1, (address)byte_map_base); |
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4285 masm.load_address(rs); // O1 := <card table base> |
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4286 masm.ldub(O0, O1, O2); // O2 := [O0 + O1] |
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|
4287 |
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4288 masm.br_on_reg_cond(Assembler::rc_nz, /*annul*/false, Assembler::pt, |
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|
4289 O2, not_already_dirty); |
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4290 // Get O1 + O2 into a reg by itself -- useful in the take-the-branch |
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4291 // case, harmless if not. |
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4292 masm.delayed()->add(O0, O1, O3); |
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|
4293 |
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4294 // We didn't take the branch, so we're already dirty: return. |
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|
4295 // Use return-from-leaf |
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|
4296 masm.retl(); |
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|
4297 masm.delayed()->nop(); |
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|
4298 |
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|
4299 // Not dirty. |
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|
4300 masm.bind(not_already_dirty); |
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|
4301 // First, dirty it. |
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4302 masm.stb(G0, O3, G0); // [cardPtr] := 0 (i.e., dirty). |
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|
4303 int dirty_card_q_index_byte_offset = |
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|
4304 in_bytes(JavaThread::dirty_card_queue_offset() + |
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|
4305 PtrQueue::byte_offset_of_index()); |
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|
4306 int dirty_card_q_buf_byte_offset = |
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|
4307 in_bytes(JavaThread::dirty_card_queue_offset() + |
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|
4308 PtrQueue::byte_offset_of_buf()); |
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|
4309 masm.bind(restart); |
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|
4310 masm.ld_ptr(G2_thread, dirty_card_q_index_byte_offset, L0); |
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|
4311 |
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4312 masm.br_on_reg_cond(Assembler::rc_z, /*annul*/false, Assembler::pn, |
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4313 L0, refill); |
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4314 // If the branch is taken, no harm in executing this in the delay slot. |
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4315 masm.delayed()->ld_ptr(G2_thread, dirty_card_q_buf_byte_offset, L1); |
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4316 masm.sub(L0, oopSize, L0); |
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|
4317 |
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4318 masm.st_ptr(O3, L1, L0); // [_buf + index] := I0 |
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4319 // Use return-from-leaf |
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|
4320 masm.retl(); |
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4321 masm.delayed()->st_ptr(L0, G2_thread, dirty_card_q_index_byte_offset); |
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|
4322 |
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|
4323 masm.bind(refill); |
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|
4324 address handle_zero = |
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|
4325 CAST_FROM_FN_PTR(address, |
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|
4326 &DirtyCardQueueSet::handle_zero_index_for_thread); |
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|
4327 // This should be rare enough that we can afford to save all the |
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4328 // scratch registers that the calling context might be using. |
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|
4329 masm.mov(G1_scratch, L3); |
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|
4330 masm.mov(G3_scratch, L5); |
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4331 // We need the value of O3 above (for the write into the buffer), so we |
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|
4332 // save and restore it. |
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|
4333 masm.mov(O3, L6); |
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|
4334 // Since the call will overwrite O7, we save and restore that, as well. |
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|
4335 masm.mov(O7, L4); |
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|
4336 |
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4337 masm.call_VM_leaf(L7_thread_cache, handle_zero, G2_thread); |
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4338 masm.mov(L3, G1_scratch); |
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|
4339 masm.mov(L5, G3_scratch); |
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|
4340 masm.mov(L6, O3); |
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4341 masm.br(Assembler::always, /*annul*/false, Assembler::pt, restart); |
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4342 masm.delayed()->mov(L4, O7); |
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|
4343 |
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4344 dirty_card_log_enqueue = start; |
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4345 dirty_card_log_enqueue_end = masm.pc(); |
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4346 // XXX Should have a guarantee here about not going off the end! |
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4347 // Does it already do so? Do an experiment... |
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|
4348 } |
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|
4349 |
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|
4350 static inline void |
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4351 generate_dirty_card_log_enqueue_if_necessary(jbyte* byte_map_base) { |
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4352 if (dirty_card_log_enqueue == 0) { |
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4353 generate_dirty_card_log_enqueue(byte_map_base); |
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4354 assert(dirty_card_log_enqueue != 0, "postcondition."); |
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4355 if (G1SATBPrintStubs) { |
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4356 tty->print_cr("Generated dirty_card enqueue:"); |
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4357 Disassembler::decode((u_char*)dirty_card_log_enqueue, |
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4358 dirty_card_log_enqueue_end, |
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|
4359 tty); |
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|
4360 } |
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4361 } |
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|
4362 } |
37f87013dfd8
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diff
changeset
|
4363 |
37f87013dfd8
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diff
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|
4364 |
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|
4365 void MacroAssembler::g1_write_barrier_post(Register store_addr, Register new_val, Register tmp) { |
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|
4366 |
37f87013dfd8
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diff
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|
4367 Label filtered; |
37f87013dfd8
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|
4368 MacroAssembler* post_filter_masm = this; |
37f87013dfd8
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|
4369 |
37f87013dfd8
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|
4370 if (new_val == G0) return; |
37f87013dfd8
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diff
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|
4371 if (G1DisablePostBarrier) return; |
37f87013dfd8
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|
4372 |
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|
4373 G1SATBCardTableModRefBS* bs = (G1SATBCardTableModRefBS*) Universe::heap()->barrier_set(); |
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|
4374 assert(bs->kind() == BarrierSet::G1SATBCT || |
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|
4375 bs->kind() == BarrierSet::G1SATBCTLogging, "wrong barrier"); |
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|
4376 if (G1RSBarrierRegionFilter) { |
37f87013dfd8
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diff
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|
4377 xor3(store_addr, new_val, tmp); |
37f87013dfd8
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diff
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|
4378 #ifdef _LP64 |
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|
4379 srlx(tmp, HeapRegion::LogOfHRGrainBytes, tmp); |
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diff
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|
4380 #else |
37f87013dfd8
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|
4381 srl(tmp, HeapRegion::LogOfHRGrainBytes, tmp); |
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diff
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|
4382 #endif |
37f87013dfd8
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diff
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|
4383 if (G1PrintCTFilterStats) { |
37f87013dfd8
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diff
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|
4384 guarantee(tmp->is_global(), "Or stats won't work..."); |
37f87013dfd8
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|
4385 // This is a sleazy hack: I'm temporarily hijacking G2, which I |
37f87013dfd8
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diff
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|
4386 // promise to restore. |
37f87013dfd8
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diff
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|
4387 mov(new_val, G2); |
37f87013dfd8
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diff
changeset
|
4388 save_frame(0); |
37f87013dfd8
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diff
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|
4389 mov(tmp, O0); |
37f87013dfd8
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diff
changeset
|
4390 mov(G2, O1); |
37f87013dfd8
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diff
changeset
|
4391 // Save G-regs that target may use. |
37f87013dfd8
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diff
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|
4392 mov(G1, L1); |
37f87013dfd8
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124
diff
changeset
|
4393 mov(G2, L2); |
37f87013dfd8
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124
diff
changeset
|
4394 mov(G3, L3); |
37f87013dfd8
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124
diff
changeset
|
4395 mov(G4, L4); |
37f87013dfd8
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124
diff
changeset
|
4396 mov(G5, L5); |
37f87013dfd8
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diff
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|
4397 call(CAST_FROM_FN_PTR(address, &count_ct_writes)); |
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|
4398 delayed()->nop(); |
37f87013dfd8
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124
diff
changeset
|
4399 mov(O0, G2); |
37f87013dfd8
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124
diff
changeset
|
4400 // Restore G-regs that target may have used. |
37f87013dfd8
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124
diff
changeset
|
4401 mov(L1, G1); |
37f87013dfd8
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124
diff
changeset
|
4402 mov(L3, G3); |
37f87013dfd8
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parents:
124
diff
changeset
|
4403 mov(L4, G4); |
37f87013dfd8
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parents:
124
diff
changeset
|
4404 mov(L5, G5); |
37f87013dfd8
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124
diff
changeset
|
4405 restore(G0, G0, G0); |
37f87013dfd8
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diff
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|
4406 } |
37f87013dfd8
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diff
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|
4407 // XXX Should I predict this taken or not? Does it mattern? |
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|
4408 br_on_reg_cond(rc_z, /*annul*/false, Assembler::pt, tmp, filtered); |
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|
4409 delayed()->nop(); |
37f87013dfd8
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124
diff
changeset
|
4410 } |
37f87013dfd8
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124
diff
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|
4411 |
37f87013dfd8
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|
4412 // Now we decide how to generate the card table write. If we're |
37f87013dfd8
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|
4413 // enqueueing, we call out to a generated function. Otherwise, we do it |
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diff
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|
4414 // inline here. |
37f87013dfd8
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diff
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|
4415 |
37f87013dfd8
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124
diff
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|
4416 if (G1RSBarrierUseQueue) { |
37f87013dfd8
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diff
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|
4417 // If the "store_addr" register is an "in" or "local" register, move it to |
37f87013dfd8
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diff
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|
4418 // a scratch reg so we can pass it as an argument. |
37f87013dfd8
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|
4419 bool use_scr = !(store_addr->is_global() || store_addr->is_out()); |
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|
4420 // Pick a scratch register different from "tmp". |
37f87013dfd8
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diff
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|
4421 Register scr = (tmp == G1_scratch ? G3_scratch : G1_scratch); |
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diff
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|
4422 // Make sure we use up the delay slot! |
37f87013dfd8
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124
diff
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|
4423 if (use_scr) { |
37f87013dfd8
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124
diff
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|
4424 post_filter_masm->mov(store_addr, scr); |
37f87013dfd8
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diff
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|
4425 } else { |
37f87013dfd8
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124
diff
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|
4426 post_filter_masm->nop(); |
37f87013dfd8
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124
diff
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|
4427 } |
37f87013dfd8
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|
4428 generate_dirty_card_log_enqueue_if_necessary(bs->byte_map_base); |
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diff
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|
4429 save_frame(0); |
37f87013dfd8
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124
diff
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|
4430 call(dirty_card_log_enqueue); |
37f87013dfd8
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parents:
124
diff
changeset
|
4431 if (use_scr) { |
37f87013dfd8
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124
diff
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|
4432 delayed()->mov(scr, O0); |
37f87013dfd8
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124
diff
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|
4433 } else { |
37f87013dfd8
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diff
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|
4434 delayed()->mov(store_addr->after_save(), O0); |
37f87013dfd8
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diff
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|
4435 } |
37f87013dfd8
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124
diff
changeset
|
4436 restore(); |
37f87013dfd8
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124
diff
changeset
|
4437 |
37f87013dfd8
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124
diff
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|
4438 } else { |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
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124
diff
changeset
|
4439 |
37f87013dfd8
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124
diff
changeset
|
4440 #ifdef _LP64 |
37f87013dfd8
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|
4441 post_filter_masm->srlx(store_addr, CardTableModRefBS::card_shift, store_addr); |
37f87013dfd8
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diff
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|
4442 #else |
37f87013dfd8
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124
diff
changeset
|
4443 post_filter_masm->srl(store_addr, CardTableModRefBS::card_shift, store_addr); |
37f87013dfd8
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124
diff
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|
4444 #endif |
37f87013dfd8
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124
diff
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|
4445 assert( tmp != store_addr, "need separate temp reg"); |
37f87013dfd8
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124
diff
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|
4446 Address rs(tmp, (address)bs->byte_map_base); |
37f87013dfd8
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diff
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|
4447 load_address(rs); |
37f87013dfd8
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124
diff
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|
4448 stb(G0, rs.base(), store_addr); |
37f87013dfd8
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124
diff
changeset
|
4449 } |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
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124
diff
changeset
|
4450 |
37f87013dfd8
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124
diff
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|
4451 bind(filtered); |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
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124
diff
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|
4452 |
37f87013dfd8
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124
diff
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|
4453 } |
37f87013dfd8
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124
diff
changeset
|
4454 |
37f87013dfd8
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diff
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|
4455 #endif // SERIALGC |
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|
4456 /////////////////////////////////////////////////////////////////////////////////// |
37f87013dfd8
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diff
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|
4457 |
37f87013dfd8
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|
4458 void MacroAssembler::card_write_barrier_post(Register store_addr, Register new_val, Register tmp) { |
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diff
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|
4459 // If we're writing constant NULL, we can skip the write barrier. |
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diff
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|
4460 if (new_val == G0) return; |
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|
4461 CardTableModRefBS* bs = (CardTableModRefBS*) Universe::heap()->barrier_set(); |
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|
4462 assert(bs->kind() == BarrierSet::CardTableModRef || |
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diff
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|
4463 bs->kind() == BarrierSet::CardTableExtension, "wrong barrier"); |
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|
4464 card_table_write(bs->byte_map_base, tmp, store_addr); |
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|
4465 } |
37f87013dfd8
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|
4466 |
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
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420
diff
changeset
|
4467 // Loading values by size and signed-ness |
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
644
diff
changeset
|
4468 void MacroAssembler::load_sized_value(Register s1, RegisterOrConstant s2, Register d, |
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
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420
diff
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|
4469 int size_in_bytes, bool is_signed) { |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
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420
diff
changeset
|
4470 switch (size_in_bytes ^ (is_signed ? -1 : 0)) { |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
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420
diff
changeset
|
4471 case ~8: // fall through: |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
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420
diff
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|
4472 case 8: ld_long( s1, s2, d ); break; |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
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420
diff
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|
4473 case ~4: ldsw( s1, s2, d ); break; |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
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420
diff
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|
4474 case 4: lduw( s1, s2, d ); break; |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
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420
diff
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|
4475 case ~2: ldsh( s1, s2, d ); break; |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
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420
diff
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|
4476 case 2: lduh( s1, s2, d ); break; |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
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420
diff
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|
4477 case ~1: ldsb( s1, s2, d ); break; |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
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420
diff
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|
4478 case 1: ldub( s1, s2, d ); break; |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
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420
diff
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|
4479 default: ShouldNotReachHere(); |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
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420
diff
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|
4480 } |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
4481 } |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
4482 |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
420
diff
changeset
|
4483 |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
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420
diff
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|
4484 |
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
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124
diff
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|
4485 void MacroAssembler::load_klass(Register src_oop, Register klass) { |
113
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coleenp
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0
diff
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|
4486 // The number of bytes in this code is used by |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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0
diff
changeset
|
4487 // MachCallDynamicJavaNode::ret_addr_offset() |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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0
diff
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|
4488 // if this changes, change that. |
ba764ed4b6f2
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0
diff
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|
4489 if (UseCompressedOops) { |
164
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|
4490 lduw(src_oop, oopDesc::klass_offset_in_bytes(), klass); |
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|
4491 decode_heap_oop_not_null(klass); |
113
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|
4492 } else { |
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
124
diff
changeset
|
4493 ld_ptr(src_oop, oopDesc::klass_offset_in_bytes(), klass); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4494 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4495 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4496 |
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
124
diff
changeset
|
4497 void MacroAssembler::store_klass(Register klass, Register dst_oop) { |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4498 if (UseCompressedOops) { |
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
124
diff
changeset
|
4499 assert(dst_oop != klass, "not enough registers"); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
124
diff
changeset
|
4500 encode_heap_oop_not_null(klass); |
167
feeb96a45707
6696264: assert("narrow oop can never be zero") for GCBasher & ParNewGC
coleenp
parents:
164
diff
changeset
|
4501 st(klass, dst_oop, oopDesc::klass_offset_in_bytes()); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4502 } else { |
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
124
diff
changeset
|
4503 st_ptr(klass, dst_oop, oopDesc::klass_offset_in_bytes()); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4504 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4505 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4506 |
167
feeb96a45707
6696264: assert("narrow oop can never be zero") for GCBasher & ParNewGC
coleenp
parents:
164
diff
changeset
|
4507 void MacroAssembler::store_klass_gap(Register s, Register d) { |
feeb96a45707
6696264: assert("narrow oop can never be zero") for GCBasher & ParNewGC
coleenp
parents:
164
diff
changeset
|
4508 if (UseCompressedOops) { |
feeb96a45707
6696264: assert("narrow oop can never be zero") for GCBasher & ParNewGC
coleenp
parents:
164
diff
changeset
|
4509 assert(s != d, "not enough registers"); |
feeb96a45707
6696264: assert("narrow oop can never be zero") for GCBasher & ParNewGC
coleenp
parents:
164
diff
changeset
|
4510 st(s, d, oopDesc::klass_gap_offset_in_bytes()); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4511 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4512 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4513 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4514 void MacroAssembler::load_heap_oop(const Address& s, Register d, int offset) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4515 if (UseCompressedOops) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4516 lduw(s, d, offset); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4517 decode_heap_oop(d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4518 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4519 ld_ptr(s, d, offset); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4520 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4521 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4522 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4523 void MacroAssembler::load_heap_oop(Register s1, Register s2, Register d) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4524 if (UseCompressedOops) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4525 lduw(s1, s2, d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4526 decode_heap_oop(d, d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4527 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4528 ld_ptr(s1, s2, d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4529 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4530 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4531 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4532 void MacroAssembler::load_heap_oop(Register s1, int simm13a, Register d) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4533 if (UseCompressedOops) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4534 lduw(s1, simm13a, d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4535 decode_heap_oop(d, d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4536 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4537 ld_ptr(s1, simm13a, d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4538 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4539 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4540 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4541 void MacroAssembler::store_heap_oop(Register d, Register s1, Register s2) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4542 if (UseCompressedOops) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4543 assert(s1 != d && s2 != d, "not enough registers"); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4544 encode_heap_oop(d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4545 st(d, s1, s2); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4546 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4547 st_ptr(d, s1, s2); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4548 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4549 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4550 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4551 void MacroAssembler::store_heap_oop(Register d, Register s1, int simm13a) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4552 if (UseCompressedOops) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4553 assert(s1 != d, "not enough registers"); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4554 encode_heap_oop(d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4555 st(d, s1, simm13a); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4556 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4557 st_ptr(d, s1, simm13a); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4558 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4559 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4560 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4561 void MacroAssembler::store_heap_oop(Register d, const Address& a, int offset) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4562 if (UseCompressedOops) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4563 assert(a.base() != d, "not enough registers"); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4564 encode_heap_oop(d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4565 st(d, a, offset); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4566 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4567 st_ptr(d, a, offset); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4568 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4569 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4570 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4571 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4572 void MacroAssembler::encode_heap_oop(Register src, Register dst) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4573 assert (UseCompressedOops, "must be compressed"); |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4574 assert (Universe::heap() != NULL, "java heap should be initialized"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4575 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
178
6d172e3548cb
6695819: verify_oopx rax: broken oop in decode_heap_oop
coleenp
parents:
124
diff
changeset
|
4576 verify_oop(src); |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4577 if (Universe::narrow_oop_base() == NULL) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4578 srlx(src, LogMinObjAlignmentInBytes, dst); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4579 return; |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4580 } |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4581 Label done; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4582 if (src == dst) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4583 // optimize for frequent case src == dst |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4584 bpr(rc_nz, true, Assembler::pt, src, done); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4585 delayed() -> sub(src, G6_heapbase, dst); // annuled if not taken |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4586 bind(done); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4587 srlx(src, LogMinObjAlignmentInBytes, dst); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4588 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4589 bpr(rc_z, false, Assembler::pn, src, done); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4590 delayed() -> mov(G0, dst); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4591 // could be moved before branch, and annulate delay, |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4592 // but may add some unneeded work decoding null |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4593 sub(src, G6_heapbase, dst); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4594 srlx(dst, LogMinObjAlignmentInBytes, dst); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4595 bind(done); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4596 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4597 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4598 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4599 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4600 void MacroAssembler::encode_heap_oop_not_null(Register r) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4601 assert (UseCompressedOops, "must be compressed"); |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4602 assert (Universe::heap() != NULL, "java heap should be initialized"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4603 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
178
6d172e3548cb
6695819: verify_oopx rax: broken oop in decode_heap_oop
coleenp
parents:
124
diff
changeset
|
4604 verify_oop(r); |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4605 if (Universe::narrow_oop_base() != NULL) |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
623
diff
changeset
|
4606 sub(r, G6_heapbase, r); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4607 srlx(r, LogMinObjAlignmentInBytes, r); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4608 } |
ba764ed4b6f2
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4609 |
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4610 void MacroAssembler::encode_heap_oop_not_null(Register src, Register dst) { |
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4611 assert (UseCompressedOops, "must be compressed"); |
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4612 assert (Universe::heap() != NULL, "java heap should be initialized"); |
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4613 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
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4614 verify_oop(src); |
642
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4615 if (Universe::narrow_oop_base() == NULL) { |
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4616 srlx(src, LogMinObjAlignmentInBytes, dst); |
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4617 } else { |
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4618 sub(src, G6_heapbase, dst); |
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4619 srlx(dst, LogMinObjAlignmentInBytes, dst); |
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4620 } |
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4621 } |
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4622 |
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4623 // Same algorithm as oops.inline.hpp decode_heap_oop. |
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4624 void MacroAssembler::decode_heap_oop(Register src, Register dst) { |
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4625 assert (UseCompressedOops, "must be compressed"); |
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4626 assert (Universe::heap() != NULL, "java heap should be initialized"); |
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4627 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
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4628 sllx(src, LogMinObjAlignmentInBytes, dst); |
642
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4629 if (Universe::narrow_oop_base() != NULL) { |
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4630 Label done; |
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4631 bpr(rc_nz, true, Assembler::pt, dst, done); |
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4632 delayed() -> add(dst, G6_heapbase, dst); // annuled if not taken |
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4633 bind(done); |
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4634 } |
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4635 verify_oop(dst); |
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4636 } |
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4637 |
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4638 void MacroAssembler::decode_heap_oop_not_null(Register r) { |
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4639 // Do not add assert code to this unless you change vtableStubs_sparc.cpp |
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4640 // pd_code_size_limit. |
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4641 // Also do not verify_oop as this is called by verify_oop. |
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4642 assert (UseCompressedOops, "must be compressed"); |
642
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4643 assert (Universe::heap() != NULL, "java heap should be initialized"); |
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4644 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
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4645 sllx(r, LogMinObjAlignmentInBytes, r); |
642
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4646 if (Universe::narrow_oop_base() != NULL) |
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4647 add(r, G6_heapbase, r); |
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4648 } |
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4649 |
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4650 void MacroAssembler::decode_heap_oop_not_null(Register src, Register dst) { |
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4651 // Do not add assert code to this unless you change vtableStubs_sparc.cpp |
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4652 // pd_code_size_limit. |
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4653 // Also do not verify_oop as this is called by verify_oop. |
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4654 assert (UseCompressedOops, "must be compressed"); |
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4655 assert (Universe::heap() != NULL, "java heap should be initialized"); |
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4656 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
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4657 sllx(src, LogMinObjAlignmentInBytes, dst); |
642
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4658 if (Universe::narrow_oop_base() != NULL) |
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4659 add(dst, G6_heapbase, dst); |
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4660 } |
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4661 |
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4662 void MacroAssembler::reinit_heapbase() { |
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4663 if (UseCompressedOops) { |
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4664 // call indirectly to solve generation ordering problem |
642
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4665 Address base(G6_heapbase, (address)Universe::narrow_oop_base_addr()); |
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4666 load_ptr_contents(base, G6_heapbase); |
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4667 } |
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4668 } |