Mercurial > hg > truffle
annotate src/cpu/x86/vm/c1_LinearScan_x86.hpp @ 1683:99ceb0e99c9e
Merge
author | never |
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date | Mon, 26 Jul 2010 15:58:07 -0700 |
parents | c18cbe5936b8 |
children | f95d63e2154a |
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0 | 1 /* |
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2 * Copyright (c) 2005, 2008, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
25 inline bool LinearScan::is_processed_reg_num(int reg_num) { | |
304 | 26 #ifndef _LP64 |
0 | 27 // rsp and rbp (numbers 6 ancd 7) are ignored |
28 assert(FrameMap::rsp_opr->cpu_regnr() == 6, "wrong assumption below"); | |
29 assert(FrameMap::rbp_opr->cpu_regnr() == 7, "wrong assumption below"); | |
30 assert(reg_num >= 0, "invalid reg_num"); | |
31 | |
32 return reg_num < 6 || reg_num > 7; | |
304 | 33 #else |
34 // rsp and rbp, r10, r15 (numbers 6 ancd 7) are ignored | |
35 assert(FrameMap::r10_opr->cpu_regnr() == 12, "wrong assumption below"); | |
36 assert(FrameMap::r15_opr->cpu_regnr() == 13, "wrong assumption below"); | |
37 assert(FrameMap::rsp_opr->cpu_regnrLo() == 14, "wrong assumption below"); | |
38 assert(FrameMap::rbp_opr->cpu_regnrLo() == 15, "wrong assumption below"); | |
39 assert(reg_num >= 0, "invalid reg_num"); | |
40 | |
41 return reg_num < 12 || reg_num > 15; | |
42 #endif // _LP64 | |
0 | 43 } |
44 | |
45 inline int LinearScan::num_physical_regs(BasicType type) { | |
46 // Intel requires two cpu registers for long, | |
47 // but requires only one fpu register for double | |
304 | 48 if (LP64_ONLY(false &&) type == T_LONG) { |
0 | 49 return 2; |
50 } | |
51 return 1; | |
52 } | |
53 | |
54 | |
55 inline bool LinearScan::requires_adjacent_regs(BasicType type) { | |
56 return false; | |
57 } | |
58 | |
59 inline bool LinearScan::is_caller_save(int assigned_reg) { | |
60 assert(assigned_reg >= 0 && assigned_reg < nof_regs, "should call this only for registers"); | |
61 return true; // no callee-saved registers on Intel | |
62 | |
63 } | |
64 | |
65 | |
66 inline void LinearScan::pd_add_temps(LIR_Op* op) { | |
67 switch (op->code()) { | |
68 case lir_tan: | |
69 case lir_sin: | |
70 case lir_cos: { | |
71 // The slow path for these functions may need to save and | |
72 // restore all live registers but we don't want to save and | |
73 // restore everything all the time, so mark the xmms as being | |
74 // killed. If the slow path were explicit or we could propagate | |
75 // live register masks down to the assembly we could do better | |
76 // but we don't have any easy way to do that right now. We | |
77 // could also consider not killing all xmm registers if we | |
78 // assume that slow paths are uncommon but it's not clear that | |
79 // would be a good idea. | |
80 if (UseSSE > 0) { | |
81 #ifndef PRODUCT | |
82 if (TraceLinearScanLevel >= 2) { | |
83 tty->print_cr("killing XMMs for trig"); | |
84 } | |
85 #endif | |
86 int op_id = op->id(); | |
87 for (int xmm = 0; xmm < FrameMap::nof_caller_save_xmm_regs; xmm++) { | |
88 LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(xmm); | |
89 add_temp(reg_num(opr), op_id, noUse, T_ILLEGAL); | |
90 } | |
91 } | |
92 break; | |
93 } | |
94 } | |
95 } | |
96 | |
97 | |
98 // Implementation of LinearScanWalker | |
99 | |
100 inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur) { | |
101 if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::byte_reg)) { | |
102 assert(cur->type() != T_FLOAT && cur->type() != T_DOUBLE, "cpu regs only"); | |
103 _first_reg = pd_first_byte_reg; | |
104 _last_reg = pd_last_byte_reg; | |
105 return true; | |
106 } else if ((UseSSE >= 1 && cur->type() == T_FLOAT) || (UseSSE >= 2 && cur->type() == T_DOUBLE)) { | |
107 _first_reg = pd_first_xmm_reg; | |
108 _last_reg = pd_last_xmm_reg; | |
109 return true; | |
110 } | |
111 | |
112 return false; | |
113 } | |
114 | |
115 | |
116 class FpuStackAllocator VALUE_OBJ_CLASS_SPEC { | |
117 private: | |
118 Compilation* _compilation; | |
119 LinearScan* _allocator; | |
120 | |
121 LIR_OpVisitState visitor; | |
122 | |
123 LIR_List* _lir; | |
124 int _pos; | |
125 FpuStackSim _sim; | |
126 FpuStackSim _temp_sim; | |
127 | |
128 bool _debug_information_computed; | |
129 | |
130 LinearScan* allocator() { return _allocator; } | |
131 Compilation* compilation() const { return _compilation; } | |
132 | |
133 // unified bailout support | |
134 void bailout(const char* msg) const { compilation()->bailout(msg); } | |
135 bool bailed_out() const { return compilation()->bailed_out(); } | |
136 | |
137 int pos() { return _pos; } | |
138 void set_pos(int pos) { _pos = pos; } | |
139 LIR_Op* cur_op() { return lir()->instructions_list()->at(pos()); } | |
140 LIR_List* lir() { return _lir; } | |
141 void set_lir(LIR_List* lir) { _lir = lir; } | |
142 FpuStackSim* sim() { return &_sim; } | |
143 FpuStackSim* temp_sim() { return &_temp_sim; } | |
144 | |
145 int fpu_num(LIR_Opr opr); | |
146 int tos_offset(LIR_Opr opr); | |
147 LIR_Opr to_fpu_stack_top(LIR_Opr opr, bool dont_check_offset = false); | |
148 | |
149 // Helper functions for handling operations | |
150 void insert_op(LIR_Op* op); | |
151 void insert_exchange(int offset); | |
152 void insert_exchange(LIR_Opr opr); | |
153 void insert_free(int offset); | |
154 void insert_free_if_dead(LIR_Opr opr); | |
155 void insert_free_if_dead(LIR_Opr opr, LIR_Opr ignore); | |
156 void insert_copy(LIR_Opr from, LIR_Opr to); | |
157 void do_rename(LIR_Opr from, LIR_Opr to); | |
158 void do_push(LIR_Opr opr); | |
159 void pop_if_last_use(LIR_Op* op, LIR_Opr opr); | |
160 void pop_always(LIR_Op* op, LIR_Opr opr); | |
161 void clear_fpu_stack(LIR_Opr preserve); | |
162 void handle_op1(LIR_Op1* op1); | |
163 void handle_op2(LIR_Op2* op2); | |
164 void handle_opCall(LIR_OpCall* opCall); | |
165 void compute_debug_information(LIR_Op* op); | |
166 void allocate_exception_handler(XHandler* xhandler); | |
167 void allocate_block(BlockBegin* block); | |
168 | |
169 #ifndef PRODUCT | |
170 void check_invalid_lir_op(LIR_Op* op); | |
171 #endif | |
172 | |
173 // Helper functions for merging of fpu stacks | |
174 void merge_insert_add(LIR_List* instrs, FpuStackSim* cur_sim, int reg); | |
175 void merge_insert_xchg(LIR_List* instrs, FpuStackSim* cur_sim, int slot); | |
176 void merge_insert_pop(LIR_List* instrs, FpuStackSim* cur_sim); | |
177 bool merge_rename(FpuStackSim* cur_sim, FpuStackSim* sux_sim, int start_slot, int change_slot); | |
178 void merge_fpu_stack(LIR_List* instrs, FpuStackSim* cur_sim, FpuStackSim* sux_sim); | |
179 void merge_cleanup_fpu_stack(LIR_List* instrs, FpuStackSim* cur_sim, BitMap& live_fpu_regs); | |
180 bool merge_fpu_stack_with_successors(BlockBegin* block); | |
181 | |
182 public: | |
183 LIR_Opr to_fpu_stack(LIR_Opr opr); // used by LinearScan for creation of debug information | |
184 | |
185 FpuStackAllocator(Compilation* compilation, LinearScan* allocator); | |
186 void allocate(); | |
187 }; |