Mercurial > hg > truffle
annotate src/share/vm/opto/ifg.cpp @ 16405:9bfc4247262f
send log output to native tty
author | Lukas Stadler <lukas.stadler@oracle.com> |
---|---|
date | Fri, 04 Jul 2014 16:06:44 +0200 |
parents | 4ca6dc0799b6 |
children | 89152779163c |
rev | line source |
---|---|
0 | 1 /* |
14909 | 2 * Copyright (c) 1998, 2012, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1212
diff
changeset
|
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1212
diff
changeset
|
20 * or visit www.oracle.com if you need additional information or have any |
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1212
diff
changeset
|
21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
26 #include "compiler/oopMap.hpp" | |
27 #include "memory/allocation.inline.hpp" | |
28 #include "opto/addnode.hpp" | |
29 #include "opto/block.hpp" | |
30 #include "opto/callnode.hpp" | |
31 #include "opto/cfgnode.hpp" | |
32 #include "opto/chaitin.hpp" | |
33 #include "opto/coalesce.hpp" | |
34 #include "opto/connode.hpp" | |
35 #include "opto/indexSet.hpp" | |
36 #include "opto/machnode.hpp" | |
37 #include "opto/memnode.hpp" | |
38 #include "opto/opcodes.hpp" | |
0 | 39 |
40 PhaseIFG::PhaseIFG( Arena *arena ) : Phase(Interference_Graph), _arena(arena) { | |
41 } | |
42 | |
43 void PhaseIFG::init( uint maxlrg ) { | |
44 _maxlrg = maxlrg; | |
45 _yanked = new (_arena) VectorSet(_arena); | |
46 _is_square = false; | |
47 // Make uninitialized adjacency lists | |
48 _adjs = (IndexSet*)_arena->Amalloc(sizeof(IndexSet)*maxlrg); | |
49 // Also make empty live range structures | |
50 _lrgs = (LRG *)_arena->Amalloc( maxlrg * sizeof(LRG) ); | |
51 memset(_lrgs,0,sizeof(LRG)*maxlrg); | |
52 // Init all to empty | |
53 for( uint i = 0; i < maxlrg; i++ ) { | |
54 _adjs[i].initialize(maxlrg); | |
55 _lrgs[i].Set_All(); | |
56 } | |
57 } | |
58 | |
59 // Add edge between vertices a & b. These are sorted (triangular matrix), | |
60 // then the smaller number is inserted in the larger numbered array. | |
61 int PhaseIFG::add_edge( uint a, uint b ) { | |
62 lrgs(a).invalid_degree(); | |
63 lrgs(b).invalid_degree(); | |
64 // Sort a and b, so that a is bigger | |
65 assert( !_is_square, "only on triangular" ); | |
66 if( a < b ) { uint tmp = a; a = b; b = tmp; } | |
67 return _adjs[a].insert( b ); | |
68 } | |
69 | |
70 // Add an edge between 'a' and everything in the vector. | |
71 void PhaseIFG::add_vector( uint a, IndexSet *vec ) { | |
72 // IFG is triangular, so do the inserts where 'a' < 'b'. | |
73 assert( !_is_square, "only on triangular" ); | |
74 IndexSet *adjs_a = &_adjs[a]; | |
75 if( !vec->count() ) return; | |
76 | |
77 IndexSetIterator elements(vec); | |
78 uint neighbor; | |
79 while ((neighbor = elements.next()) != 0) { | |
80 add_edge( a, neighbor ); | |
81 } | |
82 } | |
83 | |
84 // Is there an edge between a and b? | |
85 int PhaseIFG::test_edge( uint a, uint b ) const { | |
86 // Sort a and b, so that a is larger | |
87 assert( !_is_square, "only on triangular" ); | |
88 if( a < b ) { uint tmp = a; a = b; b = tmp; } | |
89 return _adjs[a].member(b); | |
90 } | |
91 | |
92 // Convert triangular matrix to square matrix | |
93 void PhaseIFG::SquareUp() { | |
94 assert( !_is_square, "only on triangular" ); | |
95 | |
96 // Simple transpose | |
97 for( uint i = 0; i < _maxlrg; i++ ) { | |
98 IndexSetIterator elements(&_adjs[i]); | |
99 uint datum; | |
100 while ((datum = elements.next()) != 0) { | |
101 _adjs[datum].insert( i ); | |
102 } | |
103 } | |
104 _is_square = true; | |
105 } | |
106 | |
107 // Compute effective degree in bulk | |
108 void PhaseIFG::Compute_Effective_Degree() { | |
109 assert( _is_square, "only on square" ); | |
110 | |
111 for( uint i = 0; i < _maxlrg; i++ ) | |
112 lrgs(i).set_degree(effective_degree(i)); | |
113 } | |
114 | |
115 int PhaseIFG::test_edge_sq( uint a, uint b ) const { | |
116 assert( _is_square, "only on square" ); | |
117 // Swap, so that 'a' has the lesser count. Then binary search is on | |
118 // the smaller of a's list and b's list. | |
119 if( neighbor_cnt(a) > neighbor_cnt(b) ) { uint tmp = a; a = b; b = tmp; } | |
120 //return _adjs[a].unordered_member(b); | |
121 return _adjs[a].member(b); | |
122 } | |
123 | |
124 // Union edges of B into A | |
125 void PhaseIFG::Union( uint a, uint b ) { | |
126 assert( _is_square, "only on square" ); | |
127 IndexSet *A = &_adjs[a]; | |
128 IndexSetIterator b_elements(&_adjs[b]); | |
129 uint datum; | |
130 while ((datum = b_elements.next()) != 0) { | |
131 if(A->insert(datum)) { | |
132 _adjs[datum].insert(a); | |
133 lrgs(a).invalid_degree(); | |
134 lrgs(datum).invalid_degree(); | |
135 } | |
136 } | |
137 } | |
138 | |
139 // Yank a Node and all connected edges from the IFG. Return a | |
140 // list of neighbors (edges) yanked. | |
141 IndexSet *PhaseIFG::remove_node( uint a ) { | |
142 assert( _is_square, "only on square" ); | |
143 assert( !_yanked->test(a), "" ); | |
144 _yanked->set(a); | |
145 | |
146 // I remove the LRG from all neighbors. | |
147 IndexSetIterator elements(&_adjs[a]); | |
148 LRG &lrg_a = lrgs(a); | |
149 uint datum; | |
150 while ((datum = elements.next()) != 0) { | |
151 _adjs[datum].remove(a); | |
152 lrgs(datum).inc_degree( -lrg_a.compute_degree(lrgs(datum)) ); | |
153 } | |
154 return neighbors(a); | |
155 } | |
156 | |
157 // Re-insert a yanked Node. | |
158 void PhaseIFG::re_insert( uint a ) { | |
159 assert( _is_square, "only on square" ); | |
160 assert( _yanked->test(a), "" ); | |
161 (*_yanked) >>= a; | |
162 | |
163 IndexSetIterator elements(&_adjs[a]); | |
164 uint datum; | |
165 while ((datum = elements.next()) != 0) { | |
166 _adjs[datum].insert(a); | |
167 lrgs(datum).invalid_degree(); | |
168 } | |
169 } | |
170 | |
171 // Compute the degree between 2 live ranges. If both live ranges are | |
172 // aligned-adjacent powers-of-2 then we use the MAX size. If either is | |
173 // mis-aligned (or for Fat-Projections, not-adjacent) then we have to | |
174 // MULTIPLY the sizes. Inspect Brigg's thesis on register pairs to see why | |
175 // this is so. | |
176 int LRG::compute_degree( LRG &l ) const { | |
177 int tmp; | |
178 int num_regs = _num_regs; | |
179 int nregs = l.num_regs(); | |
180 tmp = (_fat_proj || l._fat_proj) // either is a fat-proj? | |
181 ? (num_regs * nregs) // then use product | |
182 : MAX2(num_regs,nregs); // else use max | |
183 return tmp; | |
184 } | |
185 | |
186 // Compute effective degree for this live range. If both live ranges are | |
187 // aligned-adjacent powers-of-2 then we use the MAX size. If either is | |
188 // mis-aligned (or for Fat-Projections, not-adjacent) then we have to | |
189 // MULTIPLY the sizes. Inspect Brigg's thesis on register pairs to see why | |
190 // this is so. | |
191 int PhaseIFG::effective_degree( uint lidx ) const { | |
192 int eff = 0; | |
193 int num_regs = lrgs(lidx).num_regs(); | |
194 int fat_proj = lrgs(lidx)._fat_proj; | |
195 IndexSet *s = neighbors(lidx); | |
196 IndexSetIterator elements(s); | |
197 uint nidx; | |
198 while((nidx = elements.next()) != 0) { | |
199 LRG &lrgn = lrgs(nidx); | |
200 int nregs = lrgn.num_regs(); | |
201 eff += (fat_proj || lrgn._fat_proj) // either is a fat-proj? | |
202 ? (num_regs * nregs) // then use product | |
203 : MAX2(num_regs,nregs); // else use max | |
204 } | |
205 return eff; | |
206 } | |
207 | |
208 | |
209 #ifndef PRODUCT | |
210 void PhaseIFG::dump() const { | |
211 tty->print_cr("-- Interference Graph --%s--", | |
212 _is_square ? "square" : "triangular" ); | |
213 if( _is_square ) { | |
214 for( uint i = 0; i < _maxlrg; i++ ) { | |
215 tty->print( (*_yanked)[i] ? "XX " : " "); | |
216 tty->print("L%d: { ",i); | |
217 IndexSetIterator elements(&_adjs[i]); | |
218 uint datum; | |
219 while ((datum = elements.next()) != 0) { | |
220 tty->print("L%d ", datum); | |
221 } | |
222 tty->print_cr("}"); | |
223 | |
224 } | |
225 return; | |
226 } | |
227 | |
228 // Triangular | |
229 for( uint i = 0; i < _maxlrg; i++ ) { | |
230 uint j; | |
231 tty->print( (*_yanked)[i] ? "XX " : " "); | |
232 tty->print("L%d: { ",i); | |
233 for( j = _maxlrg; j > i; j-- ) | |
234 if( test_edge(j - 1,i) ) { | |
235 tty->print("L%d ",j - 1); | |
236 } | |
237 tty->print("| "); | |
238 IndexSetIterator elements(&_adjs[i]); | |
239 uint datum; | |
240 while ((datum = elements.next()) != 0) { | |
241 tty->print("L%d ", datum); | |
242 } | |
243 tty->print("}\n"); | |
244 } | |
245 tty->print("\n"); | |
246 } | |
247 | |
248 void PhaseIFG::stats() const { | |
249 ResourceMark rm; | |
250 int *h_cnt = NEW_RESOURCE_ARRAY(int,_maxlrg*2); | |
251 memset( h_cnt, 0, sizeof(int)*_maxlrg*2 ); | |
252 uint i; | |
253 for( i = 0; i < _maxlrg; i++ ) { | |
254 h_cnt[neighbor_cnt(i)]++; | |
255 } | |
256 tty->print_cr("--Histogram of counts--"); | |
257 for( i = 0; i < _maxlrg*2; i++ ) | |
258 if( h_cnt[i] ) | |
259 tty->print("%d/%d ",i,h_cnt[i]); | |
260 tty->print_cr(""); | |
261 } | |
262 | |
263 void PhaseIFG::verify( const PhaseChaitin *pc ) const { | |
264 // IFG is square, sorted and no need for Find | |
265 for( uint i = 0; i < _maxlrg; i++ ) { | |
266 assert(!((*_yanked)[i]) || !neighbor_cnt(i), "Is removed completely" ); | |
267 IndexSet *set = &_adjs[i]; | |
268 IndexSetIterator elements(set); | |
269 uint idx; | |
270 uint last = 0; | |
271 while ((idx = elements.next()) != 0) { | |
10111 | 272 assert(idx != i, "Must have empty diagonal"); |
273 assert(pc->_lrg_map.find_const(idx) == idx, "Must not need Find"); | |
274 assert(_adjs[idx].member(i), "IFG not square"); | |
275 assert(!(*_yanked)[idx], "No yanked neighbors"); | |
276 assert(last < idx, "not sorted increasing"); | |
0 | 277 last = idx; |
278 } | |
10111 | 279 assert(!lrgs(i)._degree_valid || effective_degree(i) == lrgs(i).degree(), "degree is valid but wrong"); |
0 | 280 } |
281 } | |
282 #endif | |
283 | |
14909 | 284 // Interfere this register with everything currently live. Use the RegMasks |
285 // to trim the set of possible interferences. Return a count of register-only | |
286 // interferences as an estimate of register pressure. | |
287 void PhaseChaitin::interfere_with_live( uint r, IndexSet *liveout ) { | |
288 uint retval = 0; | |
289 // Interfere with everything live. | |
290 const RegMask &rm = lrgs(r).mask(); | |
291 // Check for interference by checking overlap of regmasks. | |
292 // Only interfere if acceptable register masks overlap. | |
0 | 293 IndexSetIterator elements(liveout); |
14909 | 294 uint l; |
295 while( (l = elements.next()) != 0 ) | |
296 if( rm.overlap( lrgs(l).mask() ) ) | |
297 _ifg->add_edge( r, l ); | |
0 | 298 } |
299 | |
300 // Actually build the interference graph. Uses virtual registers only, no | |
301 // physical register masks. This allows me to be very aggressive when | |
302 // coalescing copies. Some of this aggressiveness will have to be undone | |
303 // later, but I'd rather get all the copies I can now (since unremoved copies | |
304 // at this point can end up in bad places). Copies I re-insert later I have | |
305 // more opportunity to insert them in low-frequency locations. | |
306 void PhaseChaitin::build_ifg_virtual( ) { | |
307 | |
308 // For all blocks (in any order) do... | |
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
309 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
310 Block* block = _cfg.get_block(i); |
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
311 IndexSet* liveout = _live->live(block); |
0 | 312 |
313 // The IFG is built by a single reverse pass over each basic block. | |
314 // Starting with the known live-out set, we remove things that get | |
315 // defined and add things that become live (essentially executing one | |
316 // pass of a standard LIVE analysis). Just before a Node defines a value | |
317 // (and removes it from the live-ness set) that value is certainly live. | |
318 // The defined value interferes with everything currently live. The | |
319 // value is then removed from the live-ness set and it's inputs are | |
320 // added to the live-ness set. | |
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
321 for (uint j = block->end_idx() + 1; j > 1; j--) { |
12167
650868c062a9
8023691: Create interface for nodes in class Block
adlertz
parents:
12071
diff
changeset
|
322 Node* n = block->get_node(j - 1); |
0 | 323 |
324 // Get value being defined | |
10111 | 325 uint r = _lrg_map.live_range_id(n); |
0 | 326 |
327 // Some special values do not allocate | |
10111 | 328 if (r) { |
0 | 329 |
330 // Remove from live-out set | |
331 liveout->remove(r); | |
332 | |
333 // Copies do not define a new value and so do not interfere. | |
334 // Remove the copies source from the liveout set before interfering. | |
335 uint idx = n->is_Copy(); | |
14909 | 336 if (idx) { |
10111 | 337 liveout->remove(_lrg_map.live_range_id(n->in(idx))); |
338 } | |
0 | 339 |
340 // Interfere with everything live | |
10111 | 341 interfere_with_live(r, liveout); |
0 | 342 } |
343 | |
344 // Make all inputs live | |
10111 | 345 if (!n->is_Phi()) { // Phi function uses come from prior block |
346 for(uint k = 1; k < n->req(); k++) { | |
347 liveout->insert(_lrg_map.live_range_id(n->in(k))); | |
348 } | |
0 | 349 } |
350 | |
351 // 2-address instructions always have the defined value live | |
352 // on entry to the instruction, even though it is being defined | |
353 // by the instruction. We pretend a virtual copy sits just prior | |
354 // to the instruction and kills the src-def'd register. | |
355 // In other words, for 2-address instructions the defined value | |
356 // interferes with all inputs. | |
357 uint idx; | |
358 if( n->is_Mach() && (idx = n->as_Mach()->two_adr()) ) { | |
359 const MachNode *mach = n->as_Mach(); | |
360 // Sometimes my 2-address ADDs are commuted in a bad way. | |
361 // We generally want the USE-DEF register to refer to the | |
362 // loop-varying quantity, to avoid a copy. | |
363 uint op = mach->ideal_Opcode(); | |
364 // Check that mach->num_opnds() == 3 to ensure instruction is | |
365 // not subsuming constants, effectively excludes addI_cin_imm | |
366 // Can NOT swap for instructions like addI_cin_imm since it | |
367 // is adding zero to yhi + carry and the second ideal-input | |
368 // points to the result of adding low-halves. | |
369 // Checking req() and num_opnds() does NOT distinguish addI_cout from addI_cout_imm | |
370 if( (op == Op_AddI && mach->req() == 3 && mach->num_opnds() == 3) && | |
371 n->in(1)->bottom_type()->base() == Type::Int && | |
372 // See if the ADD is involved in a tight data loop the wrong way | |
373 n->in(2)->is_Phi() && | |
374 n->in(2)->in(2) == n ) { | |
375 Node *tmp = n->in(1); | |
376 n->set_req( 1, n->in(2) ); | |
377 n->set_req( 2, tmp ); | |
378 } | |
379 // Defined value interferes with all inputs | |
10111 | 380 uint lidx = _lrg_map.live_range_id(n->in(idx)); |
381 for (uint k = 1; k < n->req(); k++) { | |
382 uint kidx = _lrg_map.live_range_id(n->in(k)); | |
383 if (kidx != lidx) { | |
384 _ifg->add_edge(r, kidx); | |
385 } | |
0 | 386 } |
387 } | |
388 } // End of forall instructions in block | |
389 } // End of forall blocks | |
390 } | |
391 | |
14909 | 392 uint PhaseChaitin::count_int_pressure( IndexSet *liveout ) { |
0 | 393 IndexSetIterator elements(liveout); |
14909 | 394 uint lidx; |
0 | 395 uint cnt = 0; |
14909 | 396 while ((lidx = elements.next()) != 0) { |
397 if( lrgs(lidx).mask().is_UP() && | |
398 lrgs(lidx).mask_size() && | |
399 !lrgs(lidx)._is_float && | |
400 !lrgs(lidx)._is_vector && | |
401 lrgs(lidx).mask().overlap(*Matcher::idealreg2regmask[Op_RegI]) ) | |
402 cnt += lrgs(lidx).reg_pressure(); | |
0 | 403 } |
404 return cnt; | |
405 } | |
406 | |
14909 | 407 uint PhaseChaitin::count_float_pressure( IndexSet *liveout ) { |
0 | 408 IndexSetIterator elements(liveout); |
14909 | 409 uint lidx; |
0 | 410 uint cnt = 0; |
14909 | 411 while ((lidx = elements.next()) != 0) { |
412 if( lrgs(lidx).mask().is_UP() && | |
413 lrgs(lidx).mask_size() && | |
414 (lrgs(lidx)._is_float || lrgs(lidx)._is_vector)) | |
415 cnt += lrgs(lidx).reg_pressure(); | |
0 | 416 } |
417 return cnt; | |
418 } | |
419 | |
14909 | 420 // Adjust register pressure down by 1. Capture last hi-to-low transition, |
421 static void lower_pressure( LRG *lrg, uint where, Block *b, uint *pressure, uint *hrp_index ) { | |
422 if (lrg->mask().is_UP() && lrg->mask_size()) { | |
423 if (lrg->_is_float || lrg->_is_vector) { | |
424 pressure[1] -= lrg->reg_pressure(); | |
425 if( pressure[1] == (uint)FLOATPRESSURE ) { | |
426 hrp_index[1] = where; | |
427 if( pressure[1] > b->_freg_pressure ) | |
428 b->_freg_pressure = pressure[1]+1; | |
0 | 429 } |
14909 | 430 } else if( lrg->mask().overlap(*Matcher::idealreg2regmask[Op_RegI]) ) { |
431 pressure[0] -= lrg->reg_pressure(); | |
432 if( pressure[0] == (uint)INTPRESSURE ) { | |
433 hrp_index[0] = where; | |
434 if( pressure[0] > b->_reg_pressure ) | |
435 b->_reg_pressure = pressure[0]+1; | |
0 | 436 } |
437 } | |
438 } | |
439 } | |
440 | |
14909 | 441 // Build the interference graph using physical registers when available. |
442 // That is, if 2 live ranges are simultaneously alive but in their acceptable | |
443 // register sets do not overlap, then they do not interfere. | |
444 uint PhaseChaitin::build_ifg_physical( ResourceArea *a ) { | |
445 NOT_PRODUCT( Compile::TracePhase t3("buildIFG", &_t_buildIFGphysical, TimeCompiler); ) | |
0 | 446 |
14909 | 447 uint must_spill = 0; |
14388
c84312468f5c
8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical
adlertz
parents:
14223
diff
changeset
|
448 |
14909 | 449 // For all blocks (in any order) do... |
450 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { | |
451 Block* block = _cfg.get_block(i); | |
452 // Clone (rather than smash in place) the liveout info, so it is alive | |
453 // for the "collect_gc_info" phase later. | |
454 IndexSet liveout(_live->live(block)); | |
455 uint last_inst = block->end_idx(); | |
456 // Compute first nonphi node index | |
457 uint first_inst; | |
458 for (first_inst = 1; first_inst < last_inst; first_inst++) { | |
459 if (!block->get_node(first_inst)->is_Phi()) { | |
460 break; | |
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
461 } |
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
462 } |
0 | 463 |
14909 | 464 // Spills could be inserted before CreateEx node which should be |
465 // first instruction in block after Phis. Move CreateEx up. | |
466 for (uint insidx = first_inst; insidx < last_inst; insidx++) { | |
467 Node *ex = block->get_node(insidx); | |
468 if (ex->is_SpillCopy()) { | |
469 continue; | |
470 } | |
471 if (insidx > first_inst && ex->is_Mach() && ex->as_Mach()->ideal_Opcode() == Op_CreateEx) { | |
472 // If the CreateEx isn't above all the MachSpillCopies | |
473 // then move it to the top. | |
474 block->remove_node(insidx); | |
475 block->insert_node(ex, first_inst); | |
476 } | |
477 // Stop once a CreateEx or any other node is found | |
478 break; | |
566
91263420e1c6
6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents:
380
diff
changeset
|
479 } |
91263420e1c6
6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents:
380
diff
changeset
|
480 |
14909 | 481 // Reset block's register pressure values for each ifg construction |
482 uint pressure[2], hrp_index[2]; | |
483 pressure[0] = pressure[1] = 0; | |
484 hrp_index[0] = hrp_index[1] = last_inst+1; | |
485 block->_reg_pressure = block->_freg_pressure = 0; | |
486 // Liveout things are presumed live for the whole block. We accumulate | |
487 // 'area' accordingly. If they get killed in the block, we'll subtract | |
488 // the unused part of the block from the area. | |
566
91263420e1c6
6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly")
kvn
parents:
380
diff
changeset
|
489 int inst_count = last_inst - first_inst; |
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
490 double cost = (inst_count <= 0) ? 0.0 : block->_freq * double(inst_count); |
14909 | 491 assert(!(cost < 0.0), "negative spill cost" ); |
492 IndexSetIterator elements(&liveout); | |
493 uint lidx; | |
494 while ((lidx = elements.next()) != 0) { | |
495 LRG &lrg = lrgs(lidx); | |
496 lrg._area += cost; | |
497 // Compute initial register pressure | |
498 if (lrg.mask().is_UP() && lrg.mask_size()) { | |
499 if (lrg._is_float || lrg._is_vector) { // Count float pressure | |
500 pressure[1] += lrg.reg_pressure(); | |
501 if (pressure[1] > block->_freg_pressure) { | |
502 block->_freg_pressure = pressure[1]; | |
503 } | |
504 // Count int pressure, but do not count the SP, flags | |
505 } else if(lrgs(lidx).mask().overlap(*Matcher::idealreg2regmask[Op_RegI])) { | |
506 pressure[0] += lrg.reg_pressure(); | |
507 if (pressure[0] > block->_reg_pressure) { | |
508 block->_reg_pressure = pressure[0]; | |
509 } | |
510 } | |
511 } | |
512 } | |
513 assert( pressure[0] == count_int_pressure (&liveout), "" ); | |
514 assert( pressure[1] == count_float_pressure(&liveout), "" ); | |
0 | 515 |
14909 | 516 // The IFG is built by a single reverse pass over each basic block. |
517 // Starting with the known live-out set, we remove things that get | |
518 // defined and add things that become live (essentially executing one | |
519 // pass of a standard LIVE analysis). Just before a Node defines a value | |
520 // (and removes it from the live-ness set) that value is certainly live. | |
521 // The defined value interferes with everything currently live. The | |
522 // value is then removed from the live-ness set and it's inputs are added | |
523 // to the live-ness set. | |
524 uint j; | |
525 for (j = last_inst + 1; j > 1; j--) { | |
526 Node* n = block->get_node(j - 1); | |
0 | 527 |
14909 | 528 // Get value being defined |
529 uint r = _lrg_map.live_range_id(n); | |
0 | 530 |
14909 | 531 // Some special values do not allocate |
532 if(r) { | |
0 | 533 // A DEF normally costs block frequency; rematerialized values are |
534 // removed from the DEF sight, so LOWER costs here. | |
14909 | 535 lrgs(r)._cost += n->rematerialize() ? 0 : block->_freq; |
0 | 536 |
14909 | 537 // If it is not live, then this instruction is dead. Probably caused |
538 // by spilling and rematerialization. Who cares why, yank this baby. | |
539 if( !liveout.member(r) && n->Opcode() != Op_SafePoint ) { | |
540 Node *def = n->in(0); | |
541 if( !n->is_Proj() || | |
542 // Could also be a flags-projection of a dead ADD or such. | |
543 (_lrg_map.live_range_id(def) && !liveout.member(_lrg_map.live_range_id(def)))) { | |
544 block->remove_node(j - 1); | |
545 if (lrgs(r)._def == n) { | |
546 lrgs(r)._def = 0; | |
547 } | |
548 n->disconnect_inputs(NULL, C); | |
549 _cfg.unmap_node_from_block(n); | |
550 n->replace_by(C->top()); | |
551 // Since yanking a Node from block, high pressure moves up one | |
552 hrp_index[0]--; | |
553 hrp_index[1]--; | |
0 | 554 continue; |
555 } | |
14909 | 556 |
557 // Fat-projections kill many registers which cannot be used to | |
558 // hold live ranges. | |
559 if (lrgs(r)._fat_proj) { | |
560 // Count the int-only registers | |
561 RegMask itmp = lrgs(r).mask(); | |
562 itmp.AND(*Matcher::idealreg2regmask[Op_RegI]); | |
563 int iregs = itmp.Size(); | |
564 if (pressure[0]+iregs > block->_reg_pressure) { | |
565 block->_reg_pressure = pressure[0] + iregs; | |
566 } | |
567 if (pressure[0] <= (uint)INTPRESSURE && pressure[0] + iregs > (uint)INTPRESSURE) { | |
568 hrp_index[0] = j - 1; | |
569 } | |
570 // Count the float-only registers | |
571 RegMask ftmp = lrgs(r).mask(); | |
572 ftmp.AND(*Matcher::idealreg2regmask[Op_RegD]); | |
573 int fregs = ftmp.Size(); | |
574 if (pressure[1] + fregs > block->_freg_pressure) { | |
575 block->_freg_pressure = pressure[1] + fregs; | |
576 } | |
577 if(pressure[1] <= (uint)FLOATPRESSURE && pressure[1]+fregs > (uint)FLOATPRESSURE) { | |
578 hrp_index[1] = j - 1; | |
579 } | |
0 | 580 } |
14909 | 581 |
582 } else { // Else it is live | |
583 // A DEF also ends 'area' partway through the block. | |
584 lrgs(r)._area -= cost; | |
585 assert(!(lrgs(r)._area < 0.0), "negative spill area" ); | |
586 | |
587 // Insure high score for immediate-use spill copies so they get a color | |
588 if( n->is_SpillCopy() | |
589 && lrgs(r).is_singledef() // MultiDef live range can still split | |
590 && n->outcnt() == 1 // and use must be in this block | |
591 && _cfg.get_block_for_node(n->unique_out()) == block) { | |
592 // All single-use MachSpillCopy(s) that immediately precede their | |
593 // use must color early. If a longer live range steals their | |
594 // color, the spill copy will split and may push another spill copy | |
595 // further away resulting in an infinite spill-split-retry cycle. | |
596 // Assigning a zero area results in a high score() and a good | |
597 // location in the simplify list. | |
598 // | |
599 | |
600 Node *single_use = n->unique_out(); | |
601 assert(block->find_node(single_use) >= j, "Use must be later in block"); | |
602 // Use can be earlier in block if it is a Phi, but then I should be a MultiDef | |
603 | |
604 // Find first non SpillCopy 'm' that follows the current instruction | |
605 // (j - 1) is index for current instruction 'n' | |
606 Node *m = n; | |
607 for (uint i = j; i <= last_inst && m->is_SpillCopy(); ++i) { | |
608 m = block->get_node(i); | |
609 } | |
610 if (m == single_use) { | |
611 lrgs(r)._area = 0.0; | |
612 } | |
14499
1077c8270209
8033260: assert(lrg._area >= 0.0) failed: negative spill area
adlertz
parents:
14496
diff
changeset
|
613 } |
0 | 614 |
14909 | 615 // Remove from live-out set |
616 if( liveout.remove(r) ) { | |
617 // Adjust register pressure. | |
618 // Capture last hi-to-lo pressure transition | |
619 lower_pressure(&lrgs(r), j - 1, block, pressure, hrp_index); | |
620 assert( pressure[0] == count_int_pressure (&liveout), "" ); | |
621 assert( pressure[1] == count_float_pressure(&liveout), "" ); | |
622 } | |
0 | 623 |
14909 | 624 // Copies do not define a new value and so do not interfere. |
625 // Remove the copies source from the liveout set before interfering. | |
626 uint idx = n->is_Copy(); | |
627 if (idx) { | |
628 uint x = _lrg_map.live_range_id(n->in(idx)); | |
629 if (liveout.remove(x)) { | |
630 lrgs(x)._area -= cost; | |
631 // Adjust register pressure. | |
632 lower_pressure(&lrgs(x), j - 1, block, pressure, hrp_index); | |
633 assert( pressure[0] == count_int_pressure (&liveout), "" ); | |
634 assert( pressure[1] == count_float_pressure(&liveout), "" ); | |
635 } | |
14388
c84312468f5c
8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical
adlertz
parents:
14223
diff
changeset
|
636 } |
14909 | 637 } // End of if live or not |
638 | |
639 // Interfere with everything live. If the defined value must | |
640 // go in a particular register, just remove that register from | |
641 // all conflicting parties and avoid the interference. | |
0 | 642 |
14909 | 643 // Make exclusions for rematerializable defs. Since rematerializable |
644 // DEFs are not bound but the live range is, some uses must be bound. | |
645 // If we spill live range 'r', it can rematerialize at each use site | |
646 // according to its bindings. | |
647 const RegMask &rmask = lrgs(r).mask(); | |
648 if( lrgs(r).is_bound() && !(n->rematerialize()) && rmask.is_NotEmpty() ) { | |
649 // Check for common case | |
650 int r_size = lrgs(r).num_regs(); | |
651 OptoReg::Name r_reg = (r_size == 1) ? rmask.find_first_elem() : OptoReg::Physical; | |
652 // Smear odd bits | |
653 IndexSetIterator elements(&liveout); | |
654 uint l; | |
655 while ((l = elements.next()) != 0) { | |
656 LRG &lrg = lrgs(l); | |
657 // If 'l' must spill already, do not further hack his bits. | |
658 // He'll get some interferences and be forced to spill later. | |
659 if( lrg._must_spill ) continue; | |
660 // Remove bound register(s) from 'l's choices | |
661 RegMask old = lrg.mask(); | |
662 uint old_size = lrg.mask_size(); | |
663 // Remove the bits from LRG 'r' from LRG 'l' so 'l' no | |
664 // longer interferes with 'r'. If 'l' requires aligned | |
665 // adjacent pairs, subtract out bit pairs. | |
666 assert(!lrg._is_vector || !lrg._fat_proj, "sanity"); | |
667 if (lrg.num_regs() > 1 && !lrg._fat_proj) { | |
668 RegMask r2mask = rmask; | |
669 // Leave only aligned set of bits. | |
670 r2mask.smear_to_sets(lrg.num_regs()); | |
671 // It includes vector case. | |
672 lrg.SUBTRACT( r2mask ); | |
673 lrg.compute_set_mask_size(); | |
674 } else if( r_size != 1 ) { // fat proj | |
675 lrg.SUBTRACT( rmask ); | |
676 lrg.compute_set_mask_size(); | |
677 } else { // Common case: size 1 bound removal | |
678 if( lrg.mask().Member(r_reg) ) { | |
679 lrg.Remove(r_reg); | |
680 lrg.set_mask_size(lrg.mask().is_AllStack() ? LRG::AllStack_size : old_size - 1); | |
681 } | |
682 } | |
683 // If 'l' goes completely dry, it must spill. | |
684 if( lrg.not_free() ) { | |
685 // Give 'l' some kind of reasonable mask, so he picks up | |
686 // interferences (and will spill later). | |
687 lrg.set_mask( old ); | |
688 lrg.set_mask_size(old_size); | |
689 must_spill++; | |
690 lrg._must_spill = 1; | |
691 lrg.set_reg(OptoReg::Name(LRG::SPILL_REG)); | |
692 } | |
693 } | |
694 } // End of if bound | |
695 | |
696 // Now interference with everything that is live and has | |
697 // compatible register sets. | |
698 interfere_with_live(r,&liveout); | |
699 | |
700 } // End of if normal register-allocated value | |
0 | 701 |
369
5f85534046c2
6750588: assert(lrg._area >= 0,"negative spill area") running NSK stmp0101 test
rasbold
parents:
295
diff
changeset
|
702 // Area remaining in the block |
5f85534046c2
6750588: assert(lrg._area >= 0,"negative spill area") running NSK stmp0101 test
rasbold
parents:
295
diff
changeset
|
703 inst_count--; |
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
704 cost = (inst_count <= 0) ? 0.0 : block->_freq * double(inst_count); |
0 | 705 |
14909 | 706 // Make all inputs live |
707 if( !n->is_Phi() ) { // Phi function uses come from prior block | |
708 JVMState* jvms = n->jvms(); | |
709 uint debug_start = jvms ? jvms->debug_start() : 999999; | |
710 // Start loop at 1 (skip control edge) for most Nodes. | |
711 // SCMemProj's might be the sole use of a StoreLConditional. | |
712 // While StoreLConditionals set memory (the SCMemProj use) | |
713 // they also def flags; if that flag def is unused the | |
714 // allocator sees a flag-setting instruction with no use of | |
715 // the flags and assumes it's dead. This keeps the (useless) | |
716 // flag-setting behavior alive while also keeping the (useful) | |
717 // memory update effect. | |
718 for (uint k = ((n->Opcode() == Op_SCMemProj) ? 0:1); k < n->req(); k++) { | |
719 Node *def = n->in(k); | |
720 uint x = _lrg_map.live_range_id(def); | |
721 if (!x) { | |
722 continue; | |
723 } | |
724 LRG &lrg = lrgs(x); | |
725 // No use-side cost for spilling debug info | |
726 if (k < debug_start) { | |
727 // A USE costs twice block frequency (once for the Load, once | |
728 // for a Load-delay). Rematerialized uses only cost once. | |
729 lrg._cost += (def->rematerialize() ? block->_freq : (block->_freq + block->_freq)); | |
730 } | |
731 // It is live now | |
732 if (liveout.insert(x)) { | |
733 // Newly live things assumed live from here to top of block | |
734 lrg._area += cost; | |
735 // Adjust register pressure | |
736 if (lrg.mask().is_UP() && lrg.mask_size()) { | |
737 if (lrg._is_float || lrg._is_vector) { | |
738 pressure[1] += lrg.reg_pressure(); | |
739 if (pressure[1] > block->_freg_pressure) { | |
740 block->_freg_pressure = pressure[1]; | |
741 } | |
742 } else if( lrg.mask().overlap(*Matcher::idealreg2regmask[Op_RegI]) ) { | |
743 pressure[0] += lrg.reg_pressure(); | |
744 if (pressure[0] > block->_reg_pressure) { | |
745 block->_reg_pressure = pressure[0]; | |
746 } | |
747 } | |
748 } | |
749 assert( pressure[0] == count_int_pressure (&liveout), "" ); | |
750 assert( pressure[1] == count_float_pressure(&liveout), "" ); | |
751 } | |
752 assert(!(lrg._area < 0.0), "negative spill area" ); | |
753 } | |
754 } | |
755 } // End of reverse pass over all instructions in block | |
756 | |
757 // If we run off the top of the block with high pressure and | |
758 // never see a hi-to-low pressure transition, just record that | |
759 // the whole block is high pressure. | |
760 if (pressure[0] > (uint)INTPRESSURE) { | |
761 hrp_index[0] = 0; | |
762 if (pressure[0] > block->_reg_pressure) { | |
763 block->_reg_pressure = pressure[0]; | |
764 } | |
765 } | |
766 if (pressure[1] > (uint)FLOATPRESSURE) { | |
767 hrp_index[1] = 0; | |
768 if (pressure[1] > block->_freg_pressure) { | |
769 block->_freg_pressure = pressure[1]; | |
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
770 } |
0 | 771 } |
772 | |
14909 | 773 // Compute high pressure indice; avoid landing in the middle of projnodes |
774 j = hrp_index[0]; | |
775 if (j < block->number_of_nodes() && j < block->end_idx() + 1) { | |
776 Node* cur = block->get_node(j); | |
777 while (cur->is_Proj() || (cur->is_MachNullCheck()) || cur->is_Catch()) { | |
778 j--; | |
779 cur = block->get_node(j); | |
780 } | |
781 } | |
782 block->_ihrp_index = j; | |
783 j = hrp_index[1]; | |
784 if (j < block->number_of_nodes() && j < block->end_idx() + 1) { | |
785 Node* cur = block->get_node(j); | |
786 while (cur->is_Proj() || (cur->is_MachNullCheck()) || cur->is_Catch()) { | |
787 j--; | |
788 cur = block->get_node(j); | |
789 } | |
790 } | |
791 block->_fhrp_index = j; | |
0 | 792 |
793 #ifndef PRODUCT | |
794 // Gather Register Pressure Statistics | |
14909 | 795 if( PrintOptoStatistics ) { |
796 if (block->_reg_pressure > (uint)INTPRESSURE || block->_freg_pressure > (uint)FLOATPRESSURE) { | |
0 | 797 _high_pressure++; |
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
798 } else { |
0 | 799 _low_pressure++; |
12071
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
adlertz
parents:
12023
diff
changeset
|
800 } |
0 | 801 } |
802 #endif | |
14909 | 803 } // End of for all blocks |
0 | 804 |
805 return must_spill; | |
806 } |