Mercurial > hg > truffle
annotate src/cpu/x86/vm/globals_x86.hpp @ 20304:a22acf6d7598
8048112: G1 Full GC needs to support the case when the very first region is not available
Summary: Refactor preparation for compaction during Full GC so that it lazily initializes the first compaction point. This also avoids problems later when the first region may not be committed. Also reviewed by K. Barrett.
Reviewed-by: brutisso
author | tschatzl |
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date | Mon, 21 Jul 2014 10:00:31 +0200 |
parents | dac61d838654 |
children | 166d744df0de |
rev | line source |
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0 | 1 /* |
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2 * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #ifndef CPU_X86_VM_GLOBALS_X86_HPP |
26 #define CPU_X86_VM_GLOBALS_X86_HPP | |
27 | |
28 #include "utilities/globalDefinitions.hpp" | |
29 #include "utilities/macros.hpp" | |
30 | |
0 | 31 // Sets the default values for platform dependent flags used by the runtime system. |
32 // (see globals.hpp) | |
33 | |
1064 | 34 define_pd_global(bool, ConvertSleepToYield, true); |
35 define_pd_global(bool, ShareVtableStubs, true); | |
36 define_pd_global(bool, CountInterpCalls, true); | |
37 define_pd_global(bool, NeedsDeoptSuspend, false); // only register window machines need this | |
0 | 38 |
1064 | 39 define_pd_global(bool, ImplicitNullChecks, true); // Generate code for implicit null checks |
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40 define_pd_global(bool, TrapBasedNullChecks, false); // Not needed on x86. |
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41 define_pd_global(bool, UncommonNullCast, true); // Uncommon-trap NULLs passed to check cast |
0 | 42 |
43 // See 4827828 for this change. There is no globals_core_i486.hpp. I can't | |
44 // assign a different value for C2 without touching a number of files. Use | |
45 // #ifdef to minimize the change as it's late in Mantis. -- FIXME. | |
46 // c1 doesn't have this problem because the fix to 4858033 assures us | |
47 // the the vep is aligned at CodeEntryAlignment whereas c2 only aligns | |
48 // the uep and the vep doesn't get real alignment but just slops on by | |
49 // only assured that the entry instruction meets the 5 byte size requirement. | |
50 #ifdef COMPILER2 | |
1064 | 51 define_pd_global(intx, CodeEntryAlignment, 32); |
0 | 52 #else |
1064 | 53 define_pd_global(intx, CodeEntryAlignment, 16); |
0 | 54 #endif // COMPILER2 |
1365 | 55 define_pd_global(intx, OptoLoopAlignment, 16); |
1064 | 56 define_pd_global(intx, InlineFrequencyCount, 100); |
57 define_pd_global(intx, InlineSmallCode, 1000); | |
0 | 58 |
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59 define_pd_global(intx, StackYellowPages, NOT_WINDOWS(2) WINDOWS_ONLY(3)); |
1064 | 60 define_pd_global(intx, StackRedPages, 1); |
0 | 61 #ifdef AMD64 |
62 // Very large C++ stack frames using solaris-amd64 optimized builds | |
63 // due to lack of optimization caused by C++ compiler bugs | |
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64 define_pd_global(intx, StackShadowPages, NOT_WIN64(20) WIN64_ONLY(6) DEBUG_ONLY(+2)); |
0 | 65 #else |
4942 | 66 define_pd_global(intx, StackShadowPages, 4 DEBUG_ONLY(+5)); |
0 | 67 #endif // AMD64 |
68 | |
1064 | 69 define_pd_global(intx, PreInflateSpin, 10); |
0 | 70 |
71 define_pd_global(bool, RewriteBytecodes, true); | |
72 define_pd_global(bool, RewriteFrequentPairs, true); | |
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73 |
3960 | 74 #ifdef _ALLBSD_SOURCE |
75 define_pd_global(bool, UseMembar, true); | |
76 #else | |
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77 define_pd_global(bool, UseMembar, false); |
3960 | 78 #endif |
1972 | 79 |
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80 // GC Ergo Flags |
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81 define_pd_global(uintx, CMSYoungGenPerWorker, 64*M); // default max size of CMS young gen, per GC worker thread |
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82 |
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83 define_pd_global(uintx, TypeProfileLevel, 111); |
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84 |
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85 #define ARCH_FLAGS(develop, product, diagnostic, experimental, notproduct) \ |
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86 \ |
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87 develop(bool, IEEEPrecision, true, \ |
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88 "Enables IEEE precision (for INTEL only)") \ |
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89 \ |
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90 product(intx, FenceInstruction, 0, \ |
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91 "(Unsafe,Unstable) Experimental") \ |
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92 \ |
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93 product(intx, ReadPrefetchInstr, 0, \ |
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94 "Prefetch instruction to prefetch ahead") \ |
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95 \ |
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96 product(bool, UseStoreImmI16, true, \ |
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97 "Use store immediate 16-bits value instruction on x86") \ |
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98 \ |
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99 product(intx, UseAVX, 99, \ |
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100 "Highest supported AVX instructions set on x86/x64") \ |
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101 \ |
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102 product(bool, UseCLMUL, false, \ |
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103 "Control whether CLMUL instructions can be used on x86/x64") \ |
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104 \ |
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105 diagnostic(bool, UseIncDec, true, \ |
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106 "Use INC, DEC instructions on x86") \ |
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107 \ |
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108 product(bool, UseNewLongLShift, false, \ |
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109 "Use optimized bitwise shift left") \ |
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110 \ |
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111 product(bool, UseAddressNop, false, \ |
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112 "Use '0F 1F [addr]' NOP instructions on x86 cpus") \ |
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113 \ |
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114 product(bool, UseXmmLoadAndClearUpper, true, \ |
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115 "Load low part of XMM register and clear upper part") \ |
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116 \ |
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117 product(bool, UseXmmRegToRegMoveAll, false, \ |
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118 "Copy all XMM register bits when moving value between registers") \ |
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119 \ |
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120 product(bool, UseXmmI2D, false, \ |
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121 "Use SSE2 CVTDQ2PD instruction to convert Integer to Double") \ |
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122 \ |
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123 product(bool, UseXmmI2F, false, \ |
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124 "Use SSE2 CVTDQ2PS instruction to convert Integer to Float") \ |
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125 \ |
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126 product(bool, UseUnalignedLoadStores, false, \ |
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127 "Use SSE2 MOVDQU instruction for Arraycopy") \ |
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128 \ |
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129 product(bool, UseFastStosb, false, \ |
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130 "Use fast-string operation for zeroing: rep stosb") \ |
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131 \ |
17780 | 132 /* Use Restricted Transactional Memory for lock eliding */ \ |
20284 | 133 product(bool, UseRTMLocking, false, \ |
17780 | 134 "Enable RTM lock eliding for inflated locks in compiled code") \ |
135 \ | |
136 experimental(bool, UseRTMForStackLocks, false, \ | |
137 "Enable RTM lock eliding for stack locks in compiled code") \ | |
138 \ | |
20284 | 139 product(bool, UseRTMDeopt, false, \ |
17780 | 140 "Perform deopt and recompilation based on RTM abort ratio") \ |
141 \ | |
20284 | 142 product(uintx, RTMRetryCount, 5, \ |
17780 | 143 "Number of RTM retries on lock abort or busy") \ |
144 \ | |
145 experimental(intx, RTMSpinLoopCount, 100, \ | |
146 "Spin count for lock to become free before RTM retry") \ | |
147 \ | |
148 experimental(intx, RTMAbortThreshold, 1000, \ | |
149 "Calculate abort ratio after this number of aborts") \ | |
150 \ | |
151 experimental(intx, RTMLockingThreshold, 10000, \ | |
152 "Lock count at which to do RTM lock eliding without " \ | |
153 "abort ratio calculation") \ | |
154 \ | |
155 experimental(intx, RTMAbortRatio, 50, \ | |
156 "Lock abort ratio at which to stop use RTM lock eliding") \ | |
157 \ | |
158 experimental(intx, RTMTotalCountIncrRate, 64, \ | |
159 "Increment total RTM attempted lock count once every n times") \ | |
160 \ | |
161 experimental(intx, RTMLockingCalculationDelay, 0, \ | |
162 "Number of milliseconds to wait before start calculating aborts " \ | |
163 "for RTM locking") \ | |
164 \ | |
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165 experimental(bool, UseRTMXendForLockBusy, true, \ |
17780 | 166 "Use RTM Xend instead of Xabort when lock busy") \ |
167 \ | |
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168 /* assembler */ \ |
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169 product(bool, Use486InstrsOnly, false, \ |
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170 "Use 80486 Compliant instruction subset") \ |
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171 \ |
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172 product(bool, UseCountLeadingZerosInstruction, false, \ |
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173 "Use count leading zeros instruction") \ |
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174 \ |
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175 product(bool, UseCountTrailingZerosInstruction, false, \ |
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176 "Use count trailing zeros instruction") \ |
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177 \ |
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178 product(bool, UseBMI1Instructions, false, \ |
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179 "Use BMI instructions") |
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180 |
1972 | 181 #endif // CPU_X86_VM_GLOBALS_X86_HPP |