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1 //
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2 // Copyright 1998-2007 Sun Microsystems, Inc. All Rights Reserved.
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3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 //
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5 // This code is free software; you can redistribute it and/or modify it
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6 // under the terms of the GNU General Public License version 2 only, as
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7 // published by the Free Software Foundation.
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8 //
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9 // This code is distributed in the hope that it will be useful, but WITHOUT
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10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 // version 2 for more details (a copy is included in the LICENSE file that
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13 // accompanied this code).
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14 //
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15 // You should have received a copy of the GNU General Public License version
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16 // 2 along with this work; if not, write to the Free Software Foundation,
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17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 //
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19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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20 // CA 95054 USA or visit www.sun.com if you need additional information or
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21 // have any questions.
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22 //
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23 //
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24
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25 // SPARC Architecture Description File
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26
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27 //----------REGISTER DEFINITION BLOCK------------------------------------------
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28 // This information is used by the matcher and the register allocator to
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29 // describe individual registers and classes of registers within the target
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30 // archtecture.
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31 register %{
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32 //----------Architecture Description Register Definitions----------------------
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33 // General Registers
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34 // "reg_def" name ( register save type, C convention save type,
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35 // ideal register type, encoding, vm name );
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36 // Register Save Types:
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37 //
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38 // NS = No-Save: The register allocator assumes that these registers
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39 // can be used without saving upon entry to the method, &
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40 // that they do not need to be saved at call sites.
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41 //
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42 // SOC = Save-On-Call: The register allocator assumes that these registers
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43 // can be used without saving upon entry to the method,
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44 // but that they must be saved at call sites.
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45 //
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46 // SOE = Save-On-Entry: The register allocator assumes that these registers
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47 // must be saved before using them upon entry to the
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48 // method, but they do not need to be saved at call
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49 // sites.
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50 //
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51 // AS = Always-Save: The register allocator assumes that these registers
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52 // must be saved before using them upon entry to the
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53 // method, & that they must be saved at call sites.
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54 //
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55 // Ideal Register Type is used to determine how to save & restore a
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56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
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57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
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58 //
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59 // The encoding number is the actual bit-pattern placed into the opcodes.
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60
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61
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62 // ----------------------------
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63 // Integer/Long Registers
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64 // ----------------------------
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65
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66 // Need to expose the hi/lo aspect of 64-bit registers
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67 // This register set is used for both the 64-bit build and
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68 // the 32-bit build with 1-register longs.
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69
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70 // Global Registers 0-7
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71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
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72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
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73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
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74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
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75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
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76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
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77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
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78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
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79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
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80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
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81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
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82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
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83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
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84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
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85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
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86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
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87
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88 // Output Registers 0-7
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89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
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90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
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91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
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92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
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93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
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94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
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95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
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96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
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97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
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98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
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99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
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100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
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101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
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102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
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103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
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104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
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105
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106 // Local Registers 0-7
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107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
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108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
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109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
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110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
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111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
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112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
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113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
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114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
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115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
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116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
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117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
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118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
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119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
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120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
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121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
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122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
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123
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124 // Input Registers 0-7
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125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
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126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
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127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
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128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
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129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
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130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
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131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
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132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
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133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
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134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
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135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
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136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
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137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
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138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
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139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
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140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
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141
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142 // ----------------------------
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143 // Float/Double Registers
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144 // ----------------------------
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145
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146 // Float Registers
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147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
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148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
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149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
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150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
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151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
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152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
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153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
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154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
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155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
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156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
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157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
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158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
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159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
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160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
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161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
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162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
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163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
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164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
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165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
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166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
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167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
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168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
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169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
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170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
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171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
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172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
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173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
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174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
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175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
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176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
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177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
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178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
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179
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180 // Double Registers
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181 // The rules of ADL require that double registers be defined in pairs.
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182 // Each pair must be two 32-bit values, but not necessarily a pair of
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183 // single float registers. In each pair, ADLC-assigned register numbers
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184 // must be adjacent, with the lower number even. Finally, when the
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185 // CPU stores such a register pair to memory, the word associated with
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186 // the lower ADLC-assigned number must be stored to the lower address.
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187
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188 // These definitions specify the actual bit encodings of the sparc
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189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
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190 // wants 0-63, so we have to convert every time we want to use fp regs
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191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
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192 // 255 is a flag meaning 'dont go here'.
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193 // I believe we can't handle callee-save doubles D32 and up until
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194 // the place in the sparc stack crawler that asserts on the 255 is
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195 // fixed up.
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196 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg());
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197 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()->next());
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198 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg());
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199 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()->next());
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200 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg());
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201 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()->next());
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202 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg());
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203 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()->next());
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204 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg());
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205 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()->next());
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206 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg());
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207 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()->next());
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208 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg());
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209 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()->next());
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210 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg());
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211 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()->next());
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212 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg());
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213 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()->next());
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214 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg());
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215 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()->next());
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216 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg());
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217 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()->next());
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218 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg());
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219 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()->next());
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220 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg());
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221 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()->next());
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222 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg());
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223 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()->next());
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224 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg());
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225 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()->next());
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226 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg());
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227 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()->next());
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228
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229
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230 // ----------------------------
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231 // Special Registers
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232 // Condition Codes Flag Registers
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233 // I tried to break out ICC and XCC but it's not very pretty.
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234 // Every Sparc instruction which defs/kills one also kills the other.
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235 // Hence every compare instruction which defs one kind of flags ends
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236 // up needing a kill of the other.
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237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
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238
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239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
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240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
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241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
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242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
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243
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244 // ----------------------------
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245 // Specify the enum values for the registers. These enums are only used by the
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246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
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247 // for visibility to the rest of the vm. The order of this enum influences the
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248 // register allocator so having the freedom to set this order and not be stuck
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249 // with the order that is natural for the rest of the vm is worth it.
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250 alloc_class chunk0(
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251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
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252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
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253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
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254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
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255
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256 // Note that a register is not allocatable unless it is also mentioned
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257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
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258
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259 alloc_class chunk1(
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260 // The first registers listed here are those most likely to be used
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261 // as temporaries. We move F0..F7 away from the front of the list,
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262 // to reduce the likelihood of interferences with parameters and
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263 // return values. Likewise, we avoid using F0/F1 for parameters,
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264 // since they are used for return values.
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265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
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266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
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267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
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268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
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269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
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270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
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271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
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272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
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273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
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274
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275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
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276
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277 //----------Architecture Description Register Classes--------------------------
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278 // Several register classes are automatically defined based upon information in
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279 // this architecture description.
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280 // 1) reg_class inline_cache_reg ( as defined in frame section )
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281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
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282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
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283 //
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284
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285 // G0 is not included in integer class since it has special meaning.
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286 reg_class g0_reg(R_G0);
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287
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288 // ----------------------------
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289 // Integer Register Classes
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290 // ----------------------------
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291 // Exclusions from i_reg:
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292 // R_G0: hardwired zero
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293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
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294 // R_G6: reserved by Solaris ABI to tools
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295 // R_G7: reserved by Solaris ABI to libthread
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296 // R_O7: Used as a temp in many encodings
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297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
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298
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299 // Class for all integer registers, except the G registers. This is used for
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300 // encodings which use G registers as temps. The regular inputs to such
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301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
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302 // will not put an input into a temp register.
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303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
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304
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305 reg_class g1_regI(R_G1);
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306 reg_class g3_regI(R_G3);
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307 reg_class g4_regI(R_G4);
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308 reg_class o0_regI(R_O0);
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309 reg_class o7_regI(R_O7);
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310
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311 // ----------------------------
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312 // Pointer Register Classes
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313 // ----------------------------
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314 #ifdef _LP64
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315 // 64-bit build means 64-bit pointers means hi/lo pairs
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316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
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317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
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318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
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319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
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320 // Lock encodings use G3 and G4 internally
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321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
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322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
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323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
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324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
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325 // Special class for storeP instructions, which can store SP or RPC to TLS.
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326 // It is also used for memory addressing, allowing direct TLS addressing.
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327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
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328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
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329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
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330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
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331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
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332 // We use it to save R_G2 across calls out of Java.
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333 reg_class l7_regP(R_L7H,R_L7);
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334
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335 // Other special pointer regs
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336 reg_class g1_regP(R_G1H,R_G1);
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337 reg_class g2_regP(R_G2H,R_G2);
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338 reg_class g3_regP(R_G3H,R_G3);
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339 reg_class g4_regP(R_G4H,R_G4);
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340 reg_class g5_regP(R_G5H,R_G5);
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341 reg_class i0_regP(R_I0H,R_I0);
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342 reg_class o0_regP(R_O0H,R_O0);
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343 reg_class o1_regP(R_O1H,R_O1);
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344 reg_class o2_regP(R_O2H,R_O2);
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345 reg_class o7_regP(R_O7H,R_O7);
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346
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347 #else // _LP64
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348 // 32-bit build means 32-bit pointers means 1 register.
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349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
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350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
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351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
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352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
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353 // Lock encodings use G3 and G4 internally
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354 reg_class lock_ptr_reg(R_G1, R_G5,
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355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
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356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
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357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
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358 // Special class for storeP instructions, which can store SP or RPC to TLS.
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359 // It is also used for memory addressing, allowing direct TLS addressing.
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360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
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361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
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362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
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363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
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364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
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365 // We use it to save R_G2 across calls out of Java.
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366 reg_class l7_regP(R_L7);
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367
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368 // Other special pointer regs
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369 reg_class g1_regP(R_G1);
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|
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370 reg_class g2_regP(R_G2);
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371 reg_class g3_regP(R_G3);
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|
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372 reg_class g4_regP(R_G4);
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373 reg_class g5_regP(R_G5);
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374 reg_class i0_regP(R_I0);
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375 reg_class o0_regP(R_O0);
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376 reg_class o1_regP(R_O1);
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377 reg_class o2_regP(R_O2);
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|
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378 reg_class o7_regP(R_O7);
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|
|
379 #endif // _LP64
|
|
|
380
|
|
|
381
|
|
|
382 // ----------------------------
|
|
|
383 // Long Register Classes
|
|
|
384 // ----------------------------
|
|
|
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
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|
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
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|
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387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
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388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
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|
|
389 #ifdef _LP64
|
|
|
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
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|
|
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
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392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
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393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
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|
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394 #endif // _LP64
|
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|
395 );
|
|
|
396
|
|
|
397 reg_class g1_regL(R_G1H,R_G1);
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|
|
398 reg_class o2_regL(R_O2H,R_O2);
|
|
|
399 reg_class o7_regL(R_O7H,R_O7);
|
|
|
400
|
|
|
401 // ----------------------------
|
|
|
402 // Special Class for Condition Code Flags Register
|
|
|
403 reg_class int_flags(CCR);
|
|
|
404 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
|
|
|
405 reg_class float_flag0(FCC0);
|
|
|
406
|
|
|
407
|
|
|
408 // ----------------------------
|
|
|
409 // Float Point Register Classes
|
|
|
410 // ----------------------------
|
|
|
411 // Skip F30/F31, they are reserved for mem-mem copies
|
|
|
412 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
|
|
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413
|
|
|
414 // Paired floating point registers--they show up in the same order as the floats,
|
|
|
415 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
|
|
|
416 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
|
|
|
417 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
|
|
|
418 /* Use extra V9 double registers; this AD file does not support V8 */
|
|
|
419 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
|
|
|
420 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
|
|
|
421 );
|
|
|
422
|
|
|
423 // Paired floating point registers--they show up in the same order as the floats,
|
|
|
424 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
|
|
|
425 // This class is usable for mis-aligned loads as happen in I2C adapters.
|
|
|
426 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
|
|
|
427 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 );
|
|
|
428 %}
|
|
|
429
|
|
|
430 //----------DEFINITION BLOCK---------------------------------------------------
|
|
|
431 // Define name --> value mappings to inform the ADLC of an integer valued name
|
|
|
432 // Current support includes integer values in the range [0, 0x7FFFFFFF]
|
|
|
433 // Format:
|
|
|
434 // int_def <name> ( <int_value>, <expression>);
|
|
|
435 // Generated Code in ad_<arch>.hpp
|
|
|
436 // #define <name> (<expression>)
|
|
|
437 // // value == <int_value>
|
|
|
438 // Generated code in ad_<arch>.cpp adlc_verification()
|
|
|
439 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
|
|
|
440 //
|
|
|
441 definitions %{
|
|
|
442 // The default cost (of an ALU instruction).
|
|
|
443 int_def DEFAULT_COST ( 100, 100);
|
|
|
444 int_def HUGE_COST (1000000, 1000000);
|
|
|
445
|
|
|
446 // Memory refs are twice as expensive as run-of-the-mill.
|
|
|
447 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
|
|
|
448
|
|
|
449 // Branches are even more expensive.
|
|
|
450 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
|
|
|
451 int_def CALL_COST ( 300, DEFAULT_COST * 3);
|
|
|
452 %}
|
|
|
453
|
|
|
454
|
|
|
455 //----------SOURCE BLOCK-------------------------------------------------------
|
|
|
456 // This is a block of C++ code which provides values, functions, and
|
|
|
457 // definitions necessary in the rest of the architecture description
|
|
|
458 source_hpp %{
|
|
|
459 // Must be visible to the DFA in dfa_sparc.cpp
|
|
|
460 extern bool can_branch_register( Node *bol, Node *cmp );
|
|
|
461
|
|
|
462 // Macros to extract hi & lo halves from a long pair.
|
|
|
463 // G0 is not part of any long pair, so assert on that.
|
|
|
464 // Prevents accidently using G1 instead of G0.
|
|
|
465 #define LONG_HI_REG(x) (x)
|
|
|
466 #define LONG_LO_REG(x) (x)
|
|
|
467
|
|
|
468 %}
|
|
|
469
|
|
|
470 source %{
|
|
|
471 #define __ _masm.
|
|
|
472
|
|
|
473 // tertiary op of a LoadP or StoreP encoding
|
|
|
474 #define REGP_OP true
|
|
|
475
|
|
|
476 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
|
|
|
477 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
|
|
|
478 static Register reg_to_register_object(int register_encoding);
|
|
|
479
|
|
|
480 // Used by the DFA in dfa_sparc.cpp.
|
|
|
481 // Check for being able to use a V9 branch-on-register. Requires a
|
|
|
482 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
|
|
|
483 // extended. Doesn't work following an integer ADD, for example, because of
|
|
|
484 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
|
|
|
485 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
|
|
|
486 // replace them with zero, which could become sign-extension in a different OS
|
|
|
487 // release. There's no obvious reason why an interrupt will ever fill these
|
|
|
488 // bits with non-zero junk (the registers are reloaded with standard LD
|
|
|
489 // instructions which either zero-fill or sign-fill).
|
|
|
490 bool can_branch_register( Node *bol, Node *cmp ) {
|
|
|
491 if( !BranchOnRegister ) return false;
|
|
|
492 #ifdef _LP64
|
|
|
493 if( cmp->Opcode() == Op_CmpP )
|
|
|
494 return true; // No problems with pointer compares
|
|
|
495 #endif
|
|
|
496 if( cmp->Opcode() == Op_CmpL )
|
|
|
497 return true; // No problems with long compares
|
|
|
498
|
|
|
499 if( !SparcV9RegsHiBitsZero ) return false;
|
|
|
500 if( bol->as_Bool()->_test._test != BoolTest::ne &&
|
|
|
501 bol->as_Bool()->_test._test != BoolTest::eq )
|
|
|
502 return false;
|
|
|
503
|
|
|
504 // Check for comparing against a 'safe' value. Any operation which
|
|
|
505 // clears out the high word is safe. Thus, loads and certain shifts
|
|
|
506 // are safe, as are non-negative constants. Any operation which
|
|
|
507 // preserves zero bits in the high word is safe as long as each of its
|
|
|
508 // inputs are safe. Thus, phis and bitwise booleans are safe if their
|
|
|
509 // inputs are safe. At present, the only important case to recognize
|
|
|
510 // seems to be loads. Constants should fold away, and shifts &
|
|
|
511 // logicals can use the 'cc' forms.
|
|
|
512 Node *x = cmp->in(1);
|
|
|
513 if( x->is_Load() ) return true;
|
|
|
514 if( x->is_Phi() ) {
|
|
|
515 for( uint i = 1; i < x->req(); i++ )
|
|
|
516 if( !x->in(i)->is_Load() )
|
|
|
517 return false;
|
|
|
518 return true;
|
|
|
519 }
|
|
|
520 return false;
|
|
|
521 }
|
|
|
522
|
|
|
523 // ****************************************************************************
|
|
|
524
|
|
|
525 // REQUIRED FUNCTIONALITY
|
|
|
526
|
|
|
527 // !!!!! Special hack to get all type of calls to specify the byte offset
|
|
|
528 // from the start of the call to the point where the return address
|
|
|
529 // will point.
|
|
|
530 // The "return address" is the address of the call instruction, plus 8.
|
|
|
531
|
|
|
532 int MachCallStaticJavaNode::ret_addr_offset() {
|
|
|
533 return NativeCall::instruction_size; // call; delay slot
|
|
|
534 }
|
|
|
535
|
|
|
536 int MachCallDynamicJavaNode::ret_addr_offset() {
|
|
|
537 int vtable_index = this->_vtable_index;
|
|
|
538 if (vtable_index < 0) {
|
|
|
539 // must be invalid_vtable_index, not nonvirtual_vtable_index
|
|
|
540 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
|
|
|
541 return (NativeMovConstReg::instruction_size +
|
|
|
542 NativeCall::instruction_size); // sethi; setlo; call; delay slot
|
|
|
543 } else {
|
|
|
544 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
|
|
|
545 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
|
|
|
546 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
|
|
|
547 if( Assembler::is_simm13(v_off) ) {
|
|
|
548 return (3*BytesPerInstWord + // ld_ptr, ld_ptr, ld_ptr
|
|
|
549 NativeCall::instruction_size); // call; delay slot
|
|
|
550 } else {
|
|
|
551 return (5*BytesPerInstWord + // ld_ptr, set_hi, set, ld_ptr, ld_ptr
|
|
|
552 NativeCall::instruction_size); // call; delay slot
|
|
|
553 }
|
|
|
554 }
|
|
|
555 }
|
|
|
556
|
|
|
557 int MachCallRuntimeNode::ret_addr_offset() {
|
|
|
558 #ifdef _LP64
|
|
|
559 return NativeFarCall::instruction_size; // farcall; delay slot
|
|
|
560 #else
|
|
|
561 return NativeCall::instruction_size; // call; delay slot
|
|
|
562 #endif
|
|
|
563 }
|
|
|
564
|
|
|
565 // Indicate if the safepoint node needs the polling page as an input.
|
|
|
566 // Since Sparc does not have absolute addressing, it does.
|
|
|
567 bool SafePointNode::needs_polling_address_input() {
|
|
|
568 return true;
|
|
|
569 }
|
|
|
570
|
|
|
571 // emit an interrupt that is caught by the debugger (for debugging compiler)
|
|
|
572 void emit_break(CodeBuffer &cbuf) {
|
|
|
573 MacroAssembler _masm(&cbuf);
|
|
|
574 __ breakpoint_trap();
|
|
|
575 }
|
|
|
576
|
|
|
577 #ifndef PRODUCT
|
|
|
578 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
|
|
|
579 st->print("TA");
|
|
|
580 }
|
|
|
581 #endif
|
|
|
582
|
|
|
583 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
|
|
|
584 emit_break(cbuf);
|
|
|
585 }
|
|
|
586
|
|
|
587 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
|
|
|
588 return MachNode::size(ra_);
|
|
|
589 }
|
|
|
590
|
|
|
591 // Traceable jump
|
|
|
592 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
|
|
|
593 MacroAssembler _masm(&cbuf);
|
|
|
594 Register rdest = reg_to_register_object(jump_target);
|
|
|
595 __ JMP(rdest, 0);
|
|
|
596 __ delayed()->nop();
|
|
|
597 }
|
|
|
598
|
|
|
599 // Traceable jump and set exception pc
|
|
|
600 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
|
|
|
601 MacroAssembler _masm(&cbuf);
|
|
|
602 Register rdest = reg_to_register_object(jump_target);
|
|
|
603 __ JMP(rdest, 0);
|
|
|
604 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
|
|
|
605 }
|
|
|
606
|
|
|
607 void emit_nop(CodeBuffer &cbuf) {
|
|
|
608 MacroAssembler _masm(&cbuf);
|
|
|
609 __ nop();
|
|
|
610 }
|
|
|
611
|
|
|
612 void emit_illtrap(CodeBuffer &cbuf) {
|
|
|
613 MacroAssembler _masm(&cbuf);
|
|
|
614 __ illtrap(0);
|
|
|
615 }
|
|
|
616
|
|
|
617
|
|
|
618 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
|
|
|
619 assert(n->rule() != loadUB_rule, "");
|
|
|
620
|
|
|
621 intptr_t offset = 0;
|
|
|
622 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
|
|
|
623 const Node* addr = n->get_base_and_disp(offset, adr_type);
|
|
|
624 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
|
|
|
625 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
|
|
|
626 assert(addr->bottom_type()->isa_oopptr() == atype, "");
|
|
|
627 atype = atype->add_offset(offset);
|
|
|
628 assert(disp32 == offset, "wrong disp32");
|
|
|
629 return atype->_offset;
|
|
|
630 }
|
|
|
631
|
|
|
632
|
|
|
633 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
|
|
|
634 assert(n->rule() != loadUB_rule, "");
|
|
|
635
|
|
|
636 intptr_t offset = 0;
|
|
|
637 Node* addr = n->in(2);
|
|
|
638 assert(addr->bottom_type()->isa_oopptr() == atype, "");
|
|
|
639 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
|
|
|
640 Node* a = addr->in(2/*AddPNode::Address*/);
|
|
|
641 Node* o = addr->in(3/*AddPNode::Offset*/);
|
|
|
642 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
|
|
|
643 atype = a->bottom_type()->is_ptr()->add_offset(offset);
|
|
|
644 assert(atype->isa_oop_ptr(), "still an oop");
|
|
|
645 }
|
|
|
646 offset = atype->is_ptr()->_offset;
|
|
|
647 if (offset != Type::OffsetBot) offset += disp32;
|
|
|
648 return offset;
|
|
|
649 }
|
|
|
650
|
|
|
651 // Standard Sparc opcode form2 field breakdown
|
|
|
652 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
|
|
|
653 f0 &= (1<<19)-1; // Mask displacement to 19 bits
|
|
|
654 int op = (f30 << 30) |
|
|
|
655 (f29 << 29) |
|
|
|
656 (f25 << 25) |
|
|
|
657 (f22 << 22) |
|
|
|
658 (f20 << 20) |
|
|
|
659 (f19 << 19) |
|
|
|
660 (f0 << 0);
|
|
|
661 *((int*)(cbuf.code_end())) = op;
|
|
|
662 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
|
|
|
663 }
|
|
|
664
|
|
|
665 // Standard Sparc opcode form2 field breakdown
|
|
|
666 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
|
|
|
667 f0 >>= 10; // Drop 10 bits
|
|
|
668 f0 &= (1<<22)-1; // Mask displacement to 22 bits
|
|
|
669 int op = (f30 << 30) |
|
|
|
670 (f25 << 25) |
|
|
|
671 (f22 << 22) |
|
|
|
672 (f0 << 0);
|
|
|
673 *((int*)(cbuf.code_end())) = op;
|
|
|
674 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
|
|
|
675 }
|
|
|
676
|
|
|
677 // Standard Sparc opcode form3 field breakdown
|
|
|
678 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
|
|
|
679 int op = (f30 << 30) |
|
|
|
680 (f25 << 25) |
|
|
|
681 (f19 << 19) |
|
|
|
682 (f14 << 14) |
|
|
|
683 (f5 << 5) |
|
|
|
684 (f0 << 0);
|
|
|
685 *((int*)(cbuf.code_end())) = op;
|
|
|
686 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
|
|
|
687 }
|
|
|
688
|
|
|
689 // Standard Sparc opcode form3 field breakdown
|
|
|
690 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
|
|
|
691 simm13 &= (1<<13)-1; // Mask to 13 bits
|
|
|
692 int op = (f30 << 30) |
|
|
|
693 (f25 << 25) |
|
|
|
694 (f19 << 19) |
|
|
|
695 (f14 << 14) |
|
|
|
696 (1 << 13) | // bit to indicate immediate-mode
|
|
|
697 (simm13<<0);
|
|
|
698 *((int*)(cbuf.code_end())) = op;
|
|
|
699 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
|
|
|
700 }
|
|
|
701
|
|
|
702 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
|
|
|
703 simm10 &= (1<<10)-1; // Mask to 10 bits
|
|
|
704 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
|
|
|
705 }
|
|
|
706
|
|
|
707 #ifdef ASSERT
|
|
|
708 // Helper function for VerifyOops in emit_form3_mem_reg
|
|
|
709 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
|
|
|
710 warning("VerifyOops encountered unexpected instruction:");
|
|
|
711 n->dump(2);
|
|
|
712 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
|
|
|
713 }
|
|
|
714 #endif
|
|
|
715
|
|
|
716
|
|
|
717 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
|
|
|
718 int src1_enc, int disp32, int src2_enc, int dst_enc) {
|
|
|
719
|
|
|
720 #ifdef ASSERT
|
|
|
721 // The following code implements the +VerifyOops feature.
|
|
|
722 // It verifies oop values which are loaded into or stored out of
|
|
|
723 // the current method activation. +VerifyOops complements techniques
|
|
|
724 // like ScavengeALot, because it eagerly inspects oops in transit,
|
|
|
725 // as they enter or leave the stack, as opposed to ScavengeALot,
|
|
|
726 // which inspects oops "at rest", in the stack or heap, at safepoints.
|
|
|
727 // For this reason, +VerifyOops can sometimes detect bugs very close
|
|
|
728 // to their point of creation. It can also serve as a cross-check
|
|
|
729 // on the validity of oop maps, when used toegether with ScavengeALot.
|
|
|
730
|
|
|
731 // It would be good to verify oops at other points, especially
|
|
|
732 // when an oop is used as a base pointer for a load or store.
|
|
|
733 // This is presently difficult, because it is hard to know when
|
|
|
734 // a base address is biased or not. (If we had such information,
|
|
|
735 // it would be easy and useful to make a two-argument version of
|
|
|
736 // verify_oop which unbiases the base, and performs verification.)
|
|
|
737
|
|
|
738 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
|
|
|
739 bool is_verified_oop_base = false;
|
|
|
740 bool is_verified_oop_load = false;
|
|
|
741 bool is_verified_oop_store = false;
|
|
|
742 int tmp_enc = -1;
|
|
|
743 if (VerifyOops && src1_enc != R_SP_enc) {
|
|
|
744 // classify the op, mainly for an assert check
|
|
|
745 int st_op = 0, ld_op = 0;
|
|
|
746 switch (primary) {
|
|
|
747 case Assembler::stb_op3: st_op = Op_StoreB; break;
|
|
|
748 case Assembler::sth_op3: st_op = Op_StoreC; break;
|
|
|
749 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
|
|
|
750 case Assembler::stw_op3: st_op = Op_StoreI; break;
|
|
|
751 case Assembler::std_op3: st_op = Op_StoreL; break;
|
|
|
752 case Assembler::stf_op3: st_op = Op_StoreF; break;
|
|
|
753 case Assembler::stdf_op3: st_op = Op_StoreD; break;
|
|
|
754
|
|
|
755 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
|
|
|
756 case Assembler::lduh_op3: ld_op = Op_LoadC; break;
|
|
|
757 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
|
|
|
758 case Assembler::ldx_op3: // may become LoadP or stay LoadI
|
|
|
759 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
|
|
|
760 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
|
|
|
761 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
|
|
|
762 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
|
|
|
763 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
|
|
|
764 case Assembler::ldub_op3: ld_op = Op_LoadB; break;
|
|
|
765 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
|
|
|
766
|
|
|
767 default: ShouldNotReachHere();
|
|
|
768 }
|
|
|
769 if (tertiary == REGP_OP) {
|
|
|
770 if (st_op == Op_StoreI) st_op = Op_StoreP;
|
|
|
771 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
|
|
|
772 else ShouldNotReachHere();
|
|
|
773 if (st_op) {
|
|
|
774 // a store
|
|
|
775 // inputs are (0:control, 1:memory, 2:address, 3:value)
|
|
|
776 Node* n2 = n->in(3);
|
|
|
777 if (n2 != NULL) {
|
|
|
778 const Type* t = n2->bottom_type();
|
|
|
779 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
|
|
|
780 }
|
|
|
781 } else {
|
|
|
782 // a load
|
|
|
783 const Type* t = n->bottom_type();
|
|
|
784 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
|
|
|
785 }
|
|
|
786 }
|
|
|
787
|
|
|
788 if (ld_op) {
|
|
|
789 // a Load
|
|
|
790 // inputs are (0:control, 1:memory, 2:address)
|
|
|
791 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
|
|
|
792 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) &&
|
|
|
793 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
|
|
|
794 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
|
|
|
795 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
|
|
|
796 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
|
|
|
797 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
|
|
|
798 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
|
|
|
799 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
|
|
|
800 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
|
|
|
801 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
|
|
|
802 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
|
|
|
803 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
|
|
|
804 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
|
|
|
805 !(n->rule() == loadUB_rule)) {
|
|
|
806 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
|
|
|
807 }
|
|
|
808 } else if (st_op) {
|
|
|
809 // a Store
|
|
|
810 // inputs are (0:control, 1:memory, 2:address, 3:value)
|
|
|
811 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
|
|
|
812 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
|
|
|
813 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
|
|
|
814 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
|
|
|
815 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
|
|
|
816 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
|
|
|
817 verify_oops_warning(n, n->ideal_Opcode(), st_op);
|
|
|
818 }
|
|
|
819 }
|
|
|
820
|
|
|
821 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
|
|
|
822 Node* addr = n->in(2);
|
|
|
823 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
|
|
|
824 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
|
|
|
825 if (atype != NULL) {
|
|
|
826 intptr_t offset = get_offset_from_base(n, atype, disp32);
|
|
|
827 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
|
|
|
828 if (offset != offset_2) {
|
|
|
829 get_offset_from_base(n, atype, disp32);
|
|
|
830 get_offset_from_base_2(n, atype, disp32);
|
|
|
831 }
|
|
|
832 assert(offset == offset_2, "different offsets");
|
|
|
833 if (offset == disp32) {
|
|
|
834 // we now know that src1 is a true oop pointer
|
|
|
835 is_verified_oop_base = true;
|
|
|
836 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
|
|
|
837 if( primary == Assembler::ldd_op3 ) {
|
|
|
838 is_verified_oop_base = false; // Cannot 'ldd' into O7
|
|
|
839 } else {
|
|
|
840 tmp_enc = dst_enc;
|
|
|
841 dst_enc = R_O7_enc; // Load into O7; preserve source oop
|
|
|
842 assert(src1_enc != dst_enc, "");
|
|
|
843 }
|
|
|
844 }
|
|
|
845 }
|
|
|
846 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
|
|
|
847 || offset == oopDesc::mark_offset_in_bytes())) {
|
|
|
848 // loading the mark should not be allowed either, but
|
|
|
849 // we don't check this since it conflicts with InlineObjectHash
|
|
|
850 // usage of LoadINode to get the mark. We could keep the
|
|
|
851 // check if we create a new LoadMarkNode
|
|
|
852 // but do not verify the object before its header is initialized
|
|
|
853 ShouldNotReachHere();
|
|
|
854 }
|
|
|
855 }
|
|
|
856 }
|
|
|
857 }
|
|
|
858 }
|
|
|
859 #endif
|
|
|
860
|
|
|
861 uint instr;
|
|
|
862 instr = (Assembler::ldst_op << 30)
|
|
|
863 | (dst_enc << 25)
|
|
|
864 | (primary << 19)
|
|
|
865 | (src1_enc << 14);
|
|
|
866
|
|
|
867 uint index = src2_enc;
|
|
|
868 int disp = disp32;
|
|
|
869
|
|
|
870 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
|
|
|
871 disp += STACK_BIAS;
|
|
|
872
|
|
|
873 // We should have a compiler bailout here rather than a guarantee.
|
|
|
874 // Better yet would be some mechanism to handle variable-size matches correctly.
|
|
|
875 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
|
|
|
876
|
|
|
877 if( disp == 0 ) {
|
|
|
878 // use reg-reg form
|
|
|
879 // bit 13 is already zero
|
|
|
880 instr |= index;
|
|
|
881 } else {
|
|
|
882 // use reg-imm form
|
|
|
883 instr |= 0x00002000; // set bit 13 to one
|
|
|
884 instr |= disp & 0x1FFF;
|
|
|
885 }
|
|
|
886
|
|
|
887 uint *code = (uint*)cbuf.code_end();
|
|
|
888 *code = instr;
|
|
|
889 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
|
|
|
890
|
|
|
891 #ifdef ASSERT
|
|
|
892 {
|
|
|
893 MacroAssembler _masm(&cbuf);
|
|
|
894 if (is_verified_oop_base) {
|
|
|
895 __ verify_oop(reg_to_register_object(src1_enc));
|
|
|
896 }
|
|
|
897 if (is_verified_oop_store) {
|
|
|
898 __ verify_oop(reg_to_register_object(dst_enc));
|
|
|
899 }
|
|
|
900 if (tmp_enc != -1) {
|
|
|
901 __ mov(O7, reg_to_register_object(tmp_enc));
|
|
|
902 }
|
|
|
903 if (is_verified_oop_load) {
|
|
|
904 __ verify_oop(reg_to_register_object(dst_enc));
|
|
|
905 }
|
|
|
906 }
|
|
|
907 #endif
|
|
|
908 }
|
|
|
909
|
|
|
910 void emit_form3_mem_reg_asi(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
|
|
|
911 int src1_enc, int disp32, int src2_enc, int dst_enc, int asi) {
|
|
|
912
|
|
|
913 uint instr;
|
|
|
914 instr = (Assembler::ldst_op << 30)
|
|
|
915 | (dst_enc << 25)
|
|
|
916 | (primary << 19)
|
|
|
917 | (src1_enc << 14);
|
|
|
918
|
|
|
919 int disp = disp32;
|
|
|
920 int index = src2_enc;
|
|
|
921
|
|
|
922 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
|
|
|
923 disp += STACK_BIAS;
|
|
|
924
|
|
|
925 // We should have a compiler bailout here rather than a guarantee.
|
|
|
926 // Better yet would be some mechanism to handle variable-size matches correctly.
|
|
|
927 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
|
|
|
928
|
|
|
929 if( disp != 0 ) {
|
|
|
930 // use reg-reg form
|
|
|
931 // set src2=R_O7 contains offset
|
|
|
932 index = R_O7_enc;
|
|
|
933 emit3_simm13( cbuf, Assembler::arith_op, index, Assembler::or_op3, 0, disp);
|
|
|
934 }
|
|
|
935 instr |= (asi << 5);
|
|
|
936 instr |= index;
|
|
|
937 uint *code = (uint*)cbuf.code_end();
|
|
|
938 *code = instr;
|
|
|
939 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
|
|
|
940 }
|
|
|
941
|
|
|
942 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) {
|
|
|
943 // The method which records debug information at every safepoint
|
|
|
944 // expects the call to be the first instruction in the snippet as
|
|
|
945 // it creates a PcDesc structure which tracks the offset of a call
|
|
|
946 // from the start of the codeBlob. This offset is computed as
|
|
|
947 // code_end() - code_begin() of the code which has been emitted
|
|
|
948 // so far.
|
|
|
949 // In this particular case we have skirted around the problem by
|
|
|
950 // putting the "mov" instruction in the delay slot but the problem
|
|
|
951 // may bite us again at some other point and a cleaner/generic
|
|
|
952 // solution using relocations would be needed.
|
|
|
953 MacroAssembler _masm(&cbuf);
|
|
|
954 __ set_inst_mark();
|
|
|
955
|
|
|
956 // We flush the current window just so that there is a valid stack copy
|
|
|
957 // the fact that the current window becomes active again instantly is
|
|
|
958 // not a problem there is nothing live in it.
|
|
|
959
|
|
|
960 #ifdef ASSERT
|
|
|
961 int startpos = __ offset();
|
|
|
962 #endif /* ASSERT */
|
|
|
963
|
|
|
964 #ifdef _LP64
|
|
|
965 // Calls to the runtime or native may not be reachable from compiled code,
|
|
|
966 // so we generate the far call sequence on 64 bit sparc.
|
|
|
967 // This code sequence is relocatable to any address, even on LP64.
|
|
|
968 if ( force_far_call ) {
|
|
|
969 __ relocate(rtype);
|
|
|
970 Address dest(O7, (address)entry_point);
|
|
|
971 __ jumpl_to(dest, O7);
|
|
|
972 }
|
|
|
973 else
|
|
|
974 #endif
|
|
|
975 {
|
|
|
976 __ call((address)entry_point, rtype);
|
|
|
977 }
|
|
|
978
|
|
|
979 if (preserve_g2) __ delayed()->mov(G2, L7);
|
|
|
980 else __ delayed()->nop();
|
|
|
981
|
|
|
982 if (preserve_g2) __ mov(L7, G2);
|
|
|
983
|
|
|
984 #ifdef ASSERT
|
|
|
985 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
|
|
|
986 #ifdef _LP64
|
|
|
987 // Trash argument dump slots.
|
|
|
988 __ set(0xb0b8ac0db0b8ac0d, G1);
|
|
|
989 __ mov(G1, G5);
|
|
|
990 __ stx(G1, SP, STACK_BIAS + 0x80);
|
|
|
991 __ stx(G1, SP, STACK_BIAS + 0x88);
|
|
|
992 __ stx(G1, SP, STACK_BIAS + 0x90);
|
|
|
993 __ stx(G1, SP, STACK_BIAS + 0x98);
|
|
|
994 __ stx(G1, SP, STACK_BIAS + 0xA0);
|
|
|
995 __ stx(G1, SP, STACK_BIAS + 0xA8);
|
|
|
996 #else // _LP64
|
|
|
997 // this is also a native call, so smash the first 7 stack locations,
|
|
|
998 // and the various registers
|
|
|
999
|
|
|
1000 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
|
|
|
1001 // while [SP+0x44..0x58] are the argument dump slots.
|
|
|
1002 __ set((intptr_t)0xbaadf00d, G1);
|
|
|
1003 __ mov(G1, G5);
|
|
|
1004 __ sllx(G1, 32, G1);
|
|
|
1005 __ or3(G1, G5, G1);
|
|
|
1006 __ mov(G1, G5);
|
|
|
1007 __ stx(G1, SP, 0x40);
|
|
|
1008 __ stx(G1, SP, 0x48);
|
|
|
1009 __ stx(G1, SP, 0x50);
|
|
|
1010 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
|
|
|
1011 #endif // _LP64
|
|
|
1012 }
|
|
|
1013 #endif /*ASSERT*/
|
|
|
1014 }
|
|
|
1015
|
|
|
1016 //=============================================================================
|
|
|
1017 // REQUIRED FUNCTIONALITY for encoding
|
|
|
1018 void emit_lo(CodeBuffer &cbuf, int val) { }
|
|
|
1019 void emit_hi(CodeBuffer &cbuf, int val) { }
|
|
|
1020
|
|
|
1021 void emit_ptr(CodeBuffer &cbuf, intptr_t val, Register reg, bool ForceRelocatable) {
|
|
|
1022 MacroAssembler _masm(&cbuf);
|
|
|
1023 if (ForceRelocatable) {
|
|
|
1024 Address addr(reg, (address)val);
|
|
|
1025 __ sethi(addr, ForceRelocatable);
|
|
|
1026 __ add(addr, reg);
|
|
|
1027 } else {
|
|
|
1028 __ set(val, reg);
|
|
|
1029 }
|
|
|
1030 }
|
|
|
1031
|
|
|
1032
|
|
|
1033 //=============================================================================
|
|
|
1034
|
|
|
1035 #ifndef PRODUCT
|
|
|
1036 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
|
|
|
1037 Compile* C = ra_->C;
|
|
|
1038
|
|
|
1039 for (int i = 0; i < OptoPrologueNops; i++) {
|
|
|
1040 st->print_cr("NOP"); st->print("\t");
|
|
|
1041 }
|
|
|
1042
|
|
|
1043 if( VerifyThread ) {
|
|
|
1044 st->print_cr("Verify_Thread"); st->print("\t");
|
|
|
1045 }
|
|
|
1046
|
|
|
1047 size_t framesize = C->frame_slots() << LogBytesPerInt;
|
|
|
1048
|
|
|
1049 // Calls to C2R adapters often do not accept exceptional returns.
|
|
|
1050 // We require that their callers must bang for them. But be careful, because
|
|
|
1051 // some VM calls (such as call site linkage) can use several kilobytes of
|
|
|
1052 // stack. But the stack safety zone should account for that.
|
|
|
1053 // See bugs 4446381, 4468289, 4497237.
|
|
|
1054 if (C->need_stack_bang(framesize)) {
|
|
|
1055 st->print_cr("! stack bang"); st->print("\t");
|
|
|
1056 }
|
|
|
1057
|
|
|
1058 if (Assembler::is_simm13(-framesize)) {
|
|
|
1059 st->print ("SAVE R_SP,-%d,R_SP",framesize);
|
|
|
1060 } else {
|
|
|
1061 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
|
|
|
1062 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
|
|
|
1063 st->print ("SAVE R_SP,R_G3,R_SP");
|
|
|
1064 }
|
|
|
1065
|
|
|
1066 }
|
|
|
1067 #endif
|
|
|
1068
|
|
|
1069 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
|
|
|
1070 Compile* C = ra_->C;
|
|
|
1071 MacroAssembler _masm(&cbuf);
|
|
|
1072
|
|
|
1073 for (int i = 0; i < OptoPrologueNops; i++) {
|
|
|
1074 __ nop();
|
|
|
1075 }
|
|
|
1076
|
|
|
1077 __ verify_thread();
|
|
|
1078
|
|
|
1079 size_t framesize = C->frame_slots() << LogBytesPerInt;
|
|
|
1080 assert(framesize >= 16*wordSize, "must have room for reg. save area");
|
|
|
1081 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
|
|
|
1082
|
|
|
1083 // Calls to C2R adapters often do not accept exceptional returns.
|
|
|
1084 // We require that their callers must bang for them. But be careful, because
|
|
|
1085 // some VM calls (such as call site linkage) can use several kilobytes of
|
|
|
1086 // stack. But the stack safety zone should account for that.
|
|
|
1087 // See bugs 4446381, 4468289, 4497237.
|
|
|
1088 if (C->need_stack_bang(framesize)) {
|
|
|
1089 __ generate_stack_overflow_check(framesize);
|
|
|
1090 }
|
|
|
1091
|
|
|
1092 if (Assembler::is_simm13(-framesize)) {
|
|
|
1093 __ save(SP, -framesize, SP);
|
|
|
1094 } else {
|
|
|
1095 __ sethi(-framesize & ~0x3ff, G3);
|
|
|
1096 __ add(G3, -framesize & 0x3ff, G3);
|
|
|
1097 __ save(SP, G3, SP);
|
|
|
1098 }
|
|
|
1099 C->set_frame_complete( __ offset() );
|
|
|
1100 }
|
|
|
1101
|
|
|
1102 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
|
|
|
1103 return MachNode::size(ra_);
|
|
|
1104 }
|
|
|
1105
|
|
|
1106 int MachPrologNode::reloc() const {
|
|
|
1107 return 10; // a large enough number
|
|
|
1108 }
|
|
|
1109
|
|
|
1110 //=============================================================================
|
|
|
1111 #ifndef PRODUCT
|
|
|
1112 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
|
|
|
1113 Compile* C = ra_->C;
|
|
|
1114
|
|
|
1115 if( do_polling() && ra_->C->is_method_compilation() ) {
|
|
|
1116 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
|
|
|
1117 #ifdef _LP64
|
|
|
1118 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
|
|
|
1119 #else
|
|
|
1120 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
|
|
|
1121 #endif
|
|
|
1122 }
|
|
|
1123
|
|
|
1124 if( do_polling() )
|
|
|
1125 st->print("RET\n\t");
|
|
|
1126
|
|
|
1127 st->print("RESTORE");
|
|
|
1128 }
|
|
|
1129 #endif
|
|
|
1130
|
|
|
1131 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
|
|
|
1132 MacroAssembler _masm(&cbuf);
|
|
|
1133 Compile* C = ra_->C;
|
|
|
1134
|
|
|
1135 __ verify_thread();
|
|
|
1136
|
|
|
1137 // If this does safepoint polling, then do it here
|
|
|
1138 if( do_polling() && ra_->C->is_method_compilation() ) {
|
|
|
1139 Address polling_page(L0, (address)os::get_polling_page());
|
|
|
1140 __ sethi(polling_page, false);
|
|
|
1141 __ relocate(relocInfo::poll_return_type);
|
|
|
1142 __ ld_ptr( L0, 0, G0 );
|
|
|
1143 }
|
|
|
1144
|
|
|
1145 // If this is a return, then stuff the restore in the delay slot
|
|
|
1146 if( do_polling() ) {
|
|
|
1147 __ ret();
|
|
|
1148 __ delayed()->restore();
|
|
|
1149 } else {
|
|
|
1150 __ restore();
|
|
|
1151 }
|
|
|
1152 }
|
|
|
1153
|
|
|
1154 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
|
|
|
1155 return MachNode::size(ra_);
|
|
|
1156 }
|
|
|
1157
|
|
|
1158 int MachEpilogNode::reloc() const {
|
|
|
1159 return 16; // a large enough number
|
|
|
1160 }
|
|
|
1161
|
|
|
1162 const Pipeline * MachEpilogNode::pipeline() const {
|
|
|
1163 return MachNode::pipeline_class();
|
|
|
1164 }
|
|
|
1165
|
|
|
1166 int MachEpilogNode::safepoint_offset() const {
|
|
|
1167 assert( do_polling(), "no return for this epilog node");
|
|
|
1168 return MacroAssembler::size_of_sethi(os::get_polling_page());
|
|
|
1169 }
|
|
|
1170
|
|
|
1171 //=============================================================================
|
|
|
1172
|
|
|
1173 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
|
|
|
1174 enum RC { rc_bad, rc_int, rc_float, rc_stack };
|
|
|
1175 static enum RC rc_class( OptoReg::Name reg ) {
|
|
|
1176 if( !OptoReg::is_valid(reg) ) return rc_bad;
|
|
|
1177 if (OptoReg::is_stack(reg)) return rc_stack;
|
|
|
1178 VMReg r = OptoReg::as_VMReg(reg);
|
|
|
1179 if (r->is_Register()) return rc_int;
|
|
|
1180 assert(r->is_FloatRegister(), "must be");
|
|
|
1181 return rc_float;
|
|
|
1182 }
|
|
|
1183
|
|
|
1184 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
|
|
|
1185 if( cbuf ) {
|
|
|
1186 // Better yet would be some mechanism to handle variable-size matches correctly
|
|
|
1187 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
|
|
|
1188 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
|
|
|
1189 } else {
|
|
|
1190 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
|
|
|
1191 }
|
|
|
1192 }
|
|
|
1193 #ifndef PRODUCT
|
|
|
1194 else if( !do_size ) {
|
|
|
1195 if( size != 0 ) st->print("\n\t");
|
|
|
1196 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
|
|
|
1197 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
|
|
|
1198 }
|
|
|
1199 #endif
|
|
|
1200 return size+4;
|
|
|
1201 }
|
|
|
1202
|
|
|
1203 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
|
|
|
1204 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
|
|
|
1205 #ifndef PRODUCT
|
|
|
1206 else if( !do_size ) {
|
|
|
1207 if( size != 0 ) st->print("\n\t");
|
|
|
1208 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
|
|
|
1209 }
|
|
|
1210 #endif
|
|
|
1211 return size+4;
|
|
|
1212 }
|
|
|
1213
|
|
|
1214 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
|
|
|
1215 PhaseRegAlloc *ra_,
|
|
|
1216 bool do_size,
|
|
|
1217 outputStream* st ) const {
|
|
|
1218 // Get registers to move
|
|
|
1219 OptoReg::Name src_second = ra_->get_reg_second(in(1));
|
|
|
1220 OptoReg::Name src_first = ra_->get_reg_first(in(1));
|
|
|
1221 OptoReg::Name dst_second = ra_->get_reg_second(this );
|
|
|
1222 OptoReg::Name dst_first = ra_->get_reg_first(this );
|
|
|
1223
|
|
|
1224 enum RC src_second_rc = rc_class(src_second);
|
|
|
1225 enum RC src_first_rc = rc_class(src_first);
|
|
|
1226 enum RC dst_second_rc = rc_class(dst_second);
|
|
|
1227 enum RC dst_first_rc = rc_class(dst_first);
|
|
|
1228
|
|
|
1229 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
|
|
|
1230
|
|
|
1231 // Generate spill code!
|
|
|
1232 int size = 0;
|
|
|
1233
|
|
|
1234 if( src_first == dst_first && src_second == dst_second )
|
|
|
1235 return size; // Self copy, no move
|
|
|
1236
|
|
|
1237 // --------------------------------------
|
|
|
1238 // Check for mem-mem move. Load into unused float registers and fall into
|
|
|
1239 // the float-store case.
|
|
|
1240 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
|
|
|
1241 int offset = ra_->reg2offset(src_first);
|
|
|
1242 // Further check for aligned-adjacent pair, so we can use a double load
|
|
|
1243 if( (src_first&1)==0 && src_first+1 == src_second ) {
|
|
|
1244 src_second = OptoReg::Name(R_F31_num);
|
|
|
1245 src_second_rc = rc_float;
|
|
|
1246 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
|
|
|
1247 } else {
|
|
|
1248 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
|
|
|
1249 }
|
|
|
1250 src_first = OptoReg::Name(R_F30_num);
|
|
|
1251 src_first_rc = rc_float;
|
|
|
1252 }
|
|
|
1253
|
|
|
1254 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
|
|
|
1255 int offset = ra_->reg2offset(src_second);
|
|
|
1256 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
|
|
|
1257 src_second = OptoReg::Name(R_F31_num);
|
|
|
1258 src_second_rc = rc_float;
|
|
|
1259 }
|
|
|
1260
|
|
|
1261 // --------------------------------------
|
|
|
1262 // Check for float->int copy; requires a trip through memory
|
|
|
1263 if( src_first_rc == rc_float && dst_first_rc == rc_int ) {
|
|
|
1264 int offset = frame::register_save_words*wordSize;
|
|
|
1265 if( cbuf ) {
|
|
|
1266 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
|
|
|
1267 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
|
|
|
1268 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
|
|
|
1269 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
|
|
|
1270 }
|
|
|
1271 #ifndef PRODUCT
|
|
|
1272 else if( !do_size ) {
|
|
|
1273 if( size != 0 ) st->print("\n\t");
|
|
|
1274 st->print( "SUB R_SP,16,R_SP\n");
|
|
|
1275 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
|
|
|
1276 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
|
|
|
1277 st->print("\tADD R_SP,16,R_SP\n");
|
|
|
1278 }
|
|
|
1279 #endif
|
|
|
1280 size += 16;
|
|
|
1281 }
|
|
|
1282
|
|
|
1283 // --------------------------------------
|
|
|
1284 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
|
|
|
1285 // In such cases, I have to do the big-endian swap. For aligned targets, the
|
|
|
1286 // hardware does the flop for me. Doubles are always aligned, so no problem
|
|
|
1287 // there. Misaligned sources only come from native-long-returns (handled
|
|
|
1288 // special below).
|
|
|
1289 #ifndef _LP64
|
|
|
1290 if( src_first_rc == rc_int && // source is already big-endian
|
|
|
1291 src_second_rc != rc_bad && // 64-bit move
|
|
|
1292 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
|
|
|
1293 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
|
|
|
1294 // Do the big-endian flop.
|
|
|
1295 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
|
|
|
1296 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
|
|
|
1297 }
|
|
|
1298 #endif
|
|
|
1299
|
|
|
1300 // --------------------------------------
|
|
|
1301 // Check for integer reg-reg copy
|
|
|
1302 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
|
|
|
1303 #ifndef _LP64
|
|
|
1304 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
|
|
|
1305 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
|
|
|
1306 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
|
|
|
1307 // operand contains the least significant word of the 64-bit value and vice versa.
|
|
|
1308 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
|
|
|
1309 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
|
|
|
1310 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
|
|
|
1311 if( cbuf ) {
|
|
|
1312 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
|
|
|
1313 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
|
|
|
1314 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
|
|
|
1315 #ifndef PRODUCT
|
|
|
1316 } else if( !do_size ) {
|
|
|
1317 if( size != 0 ) st->print("\n\t");
|
|
|
1318 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
|
|
|
1319 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
|
|
|
1320 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
|
|
|
1321 #endif
|
|
|
1322 }
|
|
|
1323 return size+12;
|
|
|
1324 }
|
|
|
1325 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
|
|
|
1326 // returning a long value in I0/I1
|
|
|
1327 // a SpillCopy must be able to target a return instruction's reg_class
|
|
|
1328 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
|
|
|
1329 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
|
|
|
1330 // operand contains the least significant word of the 64-bit value and vice versa.
|
|
|
1331 OptoReg::Name tdest = dst_first;
|
|
|
1332
|
|
|
1333 if (src_first == dst_first) {
|
|
|
1334 tdest = OptoReg::Name(R_O7_num);
|
|
|
1335 size += 4;
|
|
|
1336 }
|
|
|
1337
|
|
|
1338 if( cbuf ) {
|
|
|
1339 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
|
|
|
1340 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
|
|
|
1341 // ShrL_reg_imm6
|
|
|
1342 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
|
|
|
1343 // ShrR_reg_imm6 src, 0, dst
|
|
|
1344 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
|
|
|
1345 if (tdest != dst_first) {
|
|
|
1346 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
|
|
|
1347 }
|
|
|
1348 }
|
|
|
1349 #ifndef PRODUCT
|
|
|
1350 else if( !do_size ) {
|
|
|
1351 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
|
|
|
1352 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
|
|
|
1353 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
|
|
|
1354 if (tdest != dst_first) {
|
|
|
1355 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
|
|
|
1356 }
|
|
|
1357 }
|
|
|
1358 #endif // PRODUCT
|
|
|
1359 return size+8;
|
|
|
1360 }
|
|
|
1361 #endif // !_LP64
|
|
|
1362 // Else normal reg-reg copy
|
|
|
1363 assert( src_second != dst_first, "smashed second before evacuating it" );
|
|
|
1364 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
|
|
|
1365 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
|
|
|
1366 // This moves an aligned adjacent pair.
|
|
|
1367 // See if we are done.
|
|
|
1368 if( src_first+1 == src_second && dst_first+1 == dst_second )
|
|
|
1369 return size;
|
|
|
1370 }
|
|
|
1371
|
|
|
1372 // Check for integer store
|
|
|
1373 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
|
|
|
1374 int offset = ra_->reg2offset(dst_first);
|
|
|
1375 // Further check for aligned-adjacent pair, so we can use a double store
|
|
|
1376 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
|
|
|
1377 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
|
|
|
1378 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
|
|
|
1379 }
|
|
|
1380
|
|
|
1381 // Check for integer load
|
|
|
1382 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
|
|
|
1383 int offset = ra_->reg2offset(src_first);
|
|
|
1384 // Further check for aligned-adjacent pair, so we can use a double load
|
|
|
1385 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
|
|
|
1386 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
|
|
|
1387 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
|
|
|
1388 }
|
|
|
1389
|
|
|
1390 // Check for float reg-reg copy
|
|
|
1391 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
|
|
|
1392 // Further check for aligned-adjacent pair, so we can use a double move
|
|
|
1393 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
|
|
|
1394 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
|
|
|
1395 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
|
|
|
1396 }
|
|
|
1397
|
|
|
1398 // Check for float store
|
|
|
1399 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
|
|
|
1400 int offset = ra_->reg2offset(dst_first);
|
|
|
1401 // Further check for aligned-adjacent pair, so we can use a double store
|
|
|
1402 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
|
|
|
1403 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
|
|
|
1404 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
|
|
|
1405 }
|
|
|
1406
|
|
|
1407 // Check for float load
|
|
|
1408 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
|
|
|
1409 int offset = ra_->reg2offset(src_first);
|
|
|
1410 // Further check for aligned-adjacent pair, so we can use a double load
|
|
|
1411 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
|
|
|
1412 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
|
|
|
1413 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
|
|
|
1414 }
|
|
|
1415
|
|
|
1416 // --------------------------------------------------------------------
|
|
|
1417 // Check for hi bits still needing moving. Only happens for misaligned
|
|
|
1418 // arguments to native calls.
|
|
|
1419 if( src_second == dst_second )
|
|
|
1420 return size; // Self copy; no move
|
|
|
1421 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
|
|
|
1422
|
|
|
1423 #ifndef _LP64
|
|
|
1424 // In the LP64 build, all registers can be moved as aligned/adjacent
|
|
|
1425 // pairs, so there's never any need to move the high bits seperately.
|
|
|
1426 // The 32-bit builds have to deal with the 32-bit ABI which can force
|
|
|
1427 // all sorts of silly alignment problems.
|
|
|
1428
|
|
|
1429 // Check for integer reg-reg copy. Hi bits are stuck up in the top
|
|
|
1430 // 32-bits of a 64-bit register, but are needed in low bits of another
|
|
|
1431 // register (else it's a hi-bits-to-hi-bits copy which should have
|
|
|
1432 // happened already as part of a 64-bit move)
|
|
|
1433 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
|
|
|
1434 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
|
|
|
1435 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
|
|
|
1436 // Shift src_second down to dst_second's low bits.
|
|
|
1437 if( cbuf ) {
|
|
|
1438 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
|
|
|
1439 #ifndef PRODUCT
|
|
|
1440 } else if( !do_size ) {
|
|
|
1441 if( size != 0 ) st->print("\n\t");
|
|
|
1442 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
|
|
|
1443 #endif
|
|
|
1444 }
|
|
|
1445 return size+4;
|
|
|
1446 }
|
|
|
1447
|
|
|
1448 // Check for high word integer store. Must down-shift the hi bits
|
|
|
1449 // into a temp register, then fall into the case of storing int bits.
|
|
|
1450 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
|
|
|
1451 // Shift src_second down to dst_second's low bits.
|
|
|
1452 if( cbuf ) {
|
|
|
1453 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
|
|
|
1454 #ifndef PRODUCT
|
|
|
1455 } else if( !do_size ) {
|
|
|
1456 if( size != 0 ) st->print("\n\t");
|
|
|
1457 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
|
|
|
1458 #endif
|
|
|
1459 }
|
|
|
1460 size+=4;
|
|
|
1461 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
|
|
|
1462 }
|
|
|
1463
|
|
|
1464 // Check for high word integer load
|
|
|
1465 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
|
|
|
1466 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
|
|
|
1467
|
|
|
1468 // Check for high word integer store
|
|
|
1469 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
|
|
|
1470 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
|
|
|
1471
|
|
|
1472 // Check for high word float store
|
|
|
1473 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
|
|
|
1474 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
|
|
|
1475
|
|
|
1476 #endif // !_LP64
|
|
|
1477
|
|
|
1478 Unimplemented();
|
|
|
1479 }
|
|
|
1480
|
|
|
1481 #ifndef PRODUCT
|
|
|
1482 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
|
|
|
1483 implementation( NULL, ra_, false, st );
|
|
|
1484 }
|
|
|
1485 #endif
|
|
|
1486
|
|
|
1487 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
|
|
|
1488 implementation( &cbuf, ra_, false, NULL );
|
|
|
1489 }
|
|
|
1490
|
|
|
1491 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
|
|
|
1492 return implementation( NULL, ra_, true, NULL );
|
|
|
1493 }
|
|
|
1494
|
|
|
1495 //=============================================================================
|
|
|
1496 #ifndef PRODUCT
|
|
|
1497 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
|
|
|
1498 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
|
|
|
1499 }
|
|
|
1500 #endif
|
|
|
1501
|
|
|
1502 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
|
|
|
1503 MacroAssembler _masm(&cbuf);
|
|
|
1504 for(int i = 0; i < _count; i += 1) {
|
|
|
1505 __ nop();
|
|
|
1506 }
|
|
|
1507 }
|
|
|
1508
|
|
|
1509 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
|
|
|
1510 return 4 * _count;
|
|
|
1511 }
|
|
|
1512
|
|
|
1513
|
|
|
1514 //=============================================================================
|
|
|
1515 #ifndef PRODUCT
|
|
|
1516 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
|
|
|
1517 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
|
|
|
1518 int reg = ra_->get_reg_first(this);
|
|
|
1519 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
|
|
|
1520 }
|
|
|
1521 #endif
|
|
|
1522
|
|
|
1523 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
|
|
|
1524 MacroAssembler _masm(&cbuf);
|
|
|
1525 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
|
|
|
1526 int reg = ra_->get_encode(this);
|
|
|
1527
|
|
|
1528 if (Assembler::is_simm13(offset)) {
|
|
|
1529 __ add(SP, offset, reg_to_register_object(reg));
|
|
|
1530 } else {
|
|
|
1531 __ set(offset, O7);
|
|
|
1532 __ add(SP, O7, reg_to_register_object(reg));
|
|
|
1533 }
|
|
|
1534 }
|
|
|
1535
|
|
|
1536 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
|
|
|
1537 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
|
|
|
1538 assert(ra_ == ra_->C->regalloc(), "sanity");
|
|
|
1539 return ra_->C->scratch_emit_size(this);
|
|
|
1540 }
|
|
|
1541
|
|
|
1542 //=============================================================================
|
|
|
1543
|
|
|
1544 // emit call stub, compiled java to interpretor
|
|
|
1545 void emit_java_to_interp(CodeBuffer &cbuf ) {
|
|
|
1546
|
|
|
1547 // Stub is fixed up when the corresponding call is converted from calling
|
|
|
1548 // compiled code to calling interpreted code.
|
|
|
1549 // set (empty), G5
|
|
|
1550 // jmp -1
|
|
|
1551
|
|
|
1552 address mark = cbuf.inst_mark(); // get mark within main instrs section
|
|
|
1553
|
|
|
1554 MacroAssembler _masm(&cbuf);
|
|
|
1555
|
|
|
1556 address base =
|
|
|
1557 __ start_a_stub(Compile::MAX_stubs_size);
|
|
|
1558 if (base == NULL) return; // CodeBuffer::expand failed
|
|
|
1559
|
|
|
1560 // static stub relocation stores the instruction address of the call
|
|
|
1561 __ relocate(static_stub_Relocation::spec(mark));
|
|
|
1562
|
|
|
1563 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
|
|
|
1564
|
|
|
1565 __ set_inst_mark();
|
|
|
1566 Address a(G3, (address)-1);
|
|
|
1567 __ JUMP(a, 0);
|
|
|
1568
|
|
|
1569 __ delayed()->nop();
|
|
|
1570
|
|
|
1571 // Update current stubs pointer and restore code_end.
|
|
|
1572 __ end_a_stub();
|
|
|
1573 }
|
|
|
1574
|
|
|
1575 // size of call stub, compiled java to interpretor
|
|
|
1576 uint size_java_to_interp() {
|
|
|
1577 // This doesn't need to be accurate but it must be larger or equal to
|
|
|
1578 // the real size of the stub.
|
|
|
1579 return (NativeMovConstReg::instruction_size + // sethi/setlo;
|
|
|
1580 NativeJump::instruction_size + // sethi; jmp; nop
|
|
|
1581 (TraceJumps ? 20 * BytesPerInstWord : 0) );
|
|
|
1582 }
|
|
|
1583 // relocation entries for call stub, compiled java to interpretor
|
|
|
1584 uint reloc_java_to_interp() {
|
|
|
1585 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call
|
|
|
1586 }
|
|
|
1587
|
|
|
1588
|
|
|
1589 //=============================================================================
|
|
|
1590 #ifndef PRODUCT
|
|
|
1591 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
|
|
|
1592 st->print_cr("\nUEP:");
|
|
|
1593 #ifdef _LP64
|
|
|
1594 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
|
|
|
1595 st->print_cr("\tCMP R_G5,R_G3" );
|
|
|
1596 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
|
|
|
1597 #else // _LP64
|
|
|
1598 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
|
|
|
1599 st->print_cr("\tCMP R_G5,R_G3" );
|
|
|
1600 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
|
|
|
1601 #endif // _LP64
|
|
|
1602 }
|
|
|
1603 #endif
|
|
|
1604
|
|
|
1605 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
|
|
|
1606 MacroAssembler _masm(&cbuf);
|
|
|
1607 Label L;
|
|
|
1608 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
|
|
|
1609 Register temp_reg = G3;
|
|
|
1610 assert( G5_ic_reg != temp_reg, "conflicting registers" );
|
|
|
1611
|
|
|
1612 // Load klass from reciever
|
|
|
1613 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), temp_reg);
|
|
|
1614 // Compare against expected klass
|
|
|
1615 __ cmp(temp_reg, G5_ic_reg);
|
|
|
1616 // Branch to miss code, checks xcc or icc depending
|
|
|
1617 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
|
|
|
1618 }
|
|
|
1619
|
|
|
1620 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
|
|
|
1621 return MachNode::size(ra_);
|
|
|
1622 }
|
|
|
1623
|
|
|
1624
|
|
|
1625 //=============================================================================
|
|
|
1626
|
|
|
1627 uint size_exception_handler() {
|
|
|
1628 if (TraceJumps) {
|
|
|
1629 return (400); // just a guess
|
|
|
1630 }
|
|
|
1631 return ( NativeJump::instruction_size ); // sethi;jmp;nop
|
|
|
1632 }
|
|
|
1633
|
|
|
1634 uint size_deopt_handler() {
|
|
|
1635 if (TraceJumps) {
|
|
|
1636 return (400); // just a guess
|
|
|
1637 }
|
|
|
1638 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
|
|
|
1639 }
|
|
|
1640
|
|
|
1641 // Emit exception handler code.
|
|
|
1642 int emit_exception_handler(CodeBuffer& cbuf) {
|
|
|
1643 Register temp_reg = G3;
|
|
|
1644 Address exception_blob(temp_reg, OptoRuntime::exception_blob()->instructions_begin());
|
|
|
1645 MacroAssembler _masm(&cbuf);
|
|
|
1646
|
|
|
1647 address base =
|
|
|
1648 __ start_a_stub(size_exception_handler());
|
|
|
1649 if (base == NULL) return 0; // CodeBuffer::expand failed
|
|
|
1650
|
|
|
1651 int offset = __ offset();
|
|
|
1652
|
|
|
1653 __ JUMP(exception_blob, 0); // sethi;jmp
|
|
|
1654 __ delayed()->nop();
|
|
|
1655
|
|
|
1656 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
|
|
|
1657
|
|
|
1658 __ end_a_stub();
|
|
|
1659
|
|
|
1660 return offset;
|
|
|
1661 }
|
|
|
1662
|
|
|
1663 int emit_deopt_handler(CodeBuffer& cbuf) {
|
|
|
1664 // Can't use any of the current frame's registers as we may have deopted
|
|
|
1665 // at a poll and everything (including G3) can be live.
|
|
|
1666 Register temp_reg = L0;
|
|
|
1667 Address deopt_blob(temp_reg, SharedRuntime::deopt_blob()->unpack());
|
|
|
1668 MacroAssembler _masm(&cbuf);
|
|
|
1669
|
|
|
1670 address base =
|
|
|
1671 __ start_a_stub(size_deopt_handler());
|
|
|
1672 if (base == NULL) return 0; // CodeBuffer::expand failed
|
|
|
1673
|
|
|
1674 int offset = __ offset();
|
|
|
1675 __ save_frame(0);
|
|
|
1676 __ JUMP(deopt_blob, 0); // sethi;jmp
|
|
|
1677 __ delayed()->restore();
|
|
|
1678
|
|
|
1679 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
|
|
|
1680
|
|
|
1681 __ end_a_stub();
|
|
|
1682 return offset;
|
|
|
1683
|
|
|
1684 }
|
|
|
1685
|
|
|
1686 // Given a register encoding, produce a Integer Register object
|
|
|
1687 static Register reg_to_register_object(int register_encoding) {
|
|
|
1688 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
|
|
|
1689 return as_Register(register_encoding);
|
|
|
1690 }
|
|
|
1691
|
|
|
1692 // Given a register encoding, produce a single-precision Float Register object
|
|
|
1693 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
|
|
|
1694 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
|
|
|
1695 return as_SingleFloatRegister(register_encoding);
|
|
|
1696 }
|
|
|
1697
|
|
|
1698 // Given a register encoding, produce a double-precision Float Register object
|
|
|
1699 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
|
|
|
1700 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
|
|
|
1701 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
|
|
|
1702 return as_DoubleFloatRegister(register_encoding);
|
|
|
1703 }
|
|
|
1704
|
|
|
1705 int Matcher::regnum_to_fpu_offset(int regnum) {
|
|
|
1706 return regnum - 32; // The FP registers are in the second chunk
|
|
|
1707 }
|
|
|
1708
|
|
|
1709 #ifdef ASSERT
|
|
|
1710 address last_rethrow = NULL; // debugging aid for Rethrow encoding
|
|
|
1711 #endif
|
|
|
1712
|
|
|
1713 // Vector width in bytes
|
|
|
1714 const uint Matcher::vector_width_in_bytes(void) {
|
|
|
1715 return 8;
|
|
|
1716 }
|
|
|
1717
|
|
|
1718 // Vector ideal reg
|
|
|
1719 const uint Matcher::vector_ideal_reg(void) {
|
|
|
1720 return Op_RegD;
|
|
|
1721 }
|
|
|
1722
|
|
|
1723 // USII supports fxtof through the whole range of number, USIII doesn't
|
|
|
1724 const bool Matcher::convL2FSupported(void) {
|
|
|
1725 return VM_Version::has_fast_fxtof();
|
|
|
1726 }
|
|
|
1727
|
|
|
1728 // Is this branch offset short enough that a short branch can be used?
|
|
|
1729 //
|
|
|
1730 // NOTE: If the platform does not provide any short branch variants, then
|
|
|
1731 // this method should return false for offset 0.
|
|
|
1732 bool Matcher::is_short_branch_offset(int offset) {
|
|
|
1733 return false;
|
|
|
1734 }
|
|
|
1735
|
|
|
1736 const bool Matcher::isSimpleConstant64(jlong value) {
|
|
|
1737 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
|
|
|
1738 // Depends on optimizations in MacroAssembler::setx.
|
|
|
1739 int hi = (int)(value >> 32);
|
|
|
1740 int lo = (int)(value & ~0);
|
|
|
1741 return (hi == 0) || (hi == -1) || (lo == 0);
|
|
|
1742 }
|
|
|
1743
|
|
|
1744 // No scaling for the parameter the ClearArray node.
|
|
|
1745 const bool Matcher::init_array_count_is_in_bytes = true;
|
|
|
1746
|
|
|
1747 // Threshold size for cleararray.
|
|
|
1748 const int Matcher::init_array_short_size = 8 * BytesPerLong;
|
|
|
1749
|
|
|
1750 // Should the Matcher clone shifts on addressing modes, expecting them to
|
|
|
1751 // be subsumed into complex addressing expressions or compute them into
|
|
|
1752 // registers? True for Intel but false for most RISCs
|
|
|
1753 const bool Matcher::clone_shift_expressions = false;
|
|
|
1754
|
|
|
1755 // Is it better to copy float constants, or load them directly from memory?
|
|
|
1756 // Intel can load a float constant from a direct address, requiring no
|
|
|
1757 // extra registers. Most RISCs will have to materialize an address into a
|
|
|
1758 // register first, so they would do better to copy the constant from stack.
|
|
|
1759 const bool Matcher::rematerialize_float_constants = false;
|
|
|
1760
|
|
|
1761 // If CPU can load and store mis-aligned doubles directly then no fixup is
|
|
|
1762 // needed. Else we split the double into 2 integer pieces and move it
|
|
|
1763 // piece-by-piece. Only happens when passing doubles into C code as the
|
|
|
1764 // Java calling convention forces doubles to be aligned.
|
|
|
1765 #ifdef _LP64
|
|
|
1766 const bool Matcher::misaligned_doubles_ok = true;
|
|
|
1767 #else
|
|
|
1768 const bool Matcher::misaligned_doubles_ok = false;
|
|
|
1769 #endif
|
|
|
1770
|
|
|
1771 // No-op on SPARC.
|
|
|
1772 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
|
|
|
1773 }
|
|
|
1774
|
|
|
1775 // Advertise here if the CPU requires explicit rounding operations
|
|
|
1776 // to implement the UseStrictFP mode.
|
|
|
1777 const bool Matcher::strict_fp_requires_explicit_rounding = false;
|
|
|
1778
|
|
|
1779 // Do floats take an entire double register or just half?
|
|
|
1780 const bool Matcher::float_in_double = false;
|
|
|
1781
|
|
|
1782 // Do ints take an entire long register or just half?
|
|
|
1783 // Note that we if-def off of _LP64.
|
|
|
1784 // The relevant question is how the int is callee-saved. In _LP64
|
|
|
1785 // the whole long is written but de-opt'ing will have to extract
|
|
|
1786 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
|
|
|
1787 #ifdef _LP64
|
|
|
1788 const bool Matcher::int_in_long = true;
|
|
|
1789 #else
|
|
|
1790 const bool Matcher::int_in_long = false;
|
|
|
1791 #endif
|
|
|
1792
|
|
|
1793 // Return whether or not this register is ever used as an argument. This
|
|
|
1794 // function is used on startup to build the trampoline stubs in generateOptoStub.
|
|
|
1795 // Registers not mentioned will be killed by the VM call in the trampoline, and
|
|
|
1796 // arguments in those registers not be available to the callee.
|
|
|
1797 bool Matcher::can_be_java_arg( int reg ) {
|
|
|
1798 // Standard sparc 6 args in registers
|
|
|
1799 if( reg == R_I0_num ||
|
|
|
1800 reg == R_I1_num ||
|
|
|
1801 reg == R_I2_num ||
|
|
|
1802 reg == R_I3_num ||
|
|
|
1803 reg == R_I4_num ||
|
|
|
1804 reg == R_I5_num ) return true;
|
|
|
1805 #ifdef _LP64
|
|
|
1806 // 64-bit builds can pass 64-bit pointers and longs in
|
|
|
1807 // the high I registers
|
|
|
1808 if( reg == R_I0H_num ||
|
|
|
1809 reg == R_I1H_num ||
|
|
|
1810 reg == R_I2H_num ||
|
|
|
1811 reg == R_I3H_num ||
|
|
|
1812 reg == R_I4H_num ||
|
|
|
1813 reg == R_I5H_num ) return true;
|
|
|
1814 #else
|
|
|
1815 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
|
|
|
1816 // Longs cannot be passed in O regs, because O regs become I regs
|
|
|
1817 // after a 'save' and I regs get their high bits chopped off on
|
|
|
1818 // interrupt.
|
|
|
1819 if( reg == R_G1H_num || reg == R_G1_num ) return true;
|
|
|
1820 if( reg == R_G4H_num || reg == R_G4_num ) return true;
|
|
|
1821 #endif
|
|
|
1822 // A few float args in registers
|
|
|
1823 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
|
|
|
1824
|
|
|
1825 return false;
|
|
|
1826 }
|
|
|
1827
|
|
|
1828 bool Matcher::is_spillable_arg( int reg ) {
|
|
|
1829 return can_be_java_arg(reg);
|
|
|
1830 }
|
|
|
1831
|
|
|
1832 // Register for DIVI projection of divmodI
|
|
|
1833 RegMask Matcher::divI_proj_mask() {
|
|
|
1834 ShouldNotReachHere();
|
|
|
1835 return RegMask();
|
|
|
1836 }
|
|
|
1837
|
|
|
1838 // Register for MODI projection of divmodI
|
|
|
1839 RegMask Matcher::modI_proj_mask() {
|
|
|
1840 ShouldNotReachHere();
|
|
|
1841 return RegMask();
|
|
|
1842 }
|
|
|
1843
|
|
|
1844 // Register for DIVL projection of divmodL
|
|
|
1845 RegMask Matcher::divL_proj_mask() {
|
|
|
1846 ShouldNotReachHere();
|
|
|
1847 return RegMask();
|
|
|
1848 }
|
|
|
1849
|
|
|
1850 // Register for MODL projection of divmodL
|
|
|
1851 RegMask Matcher::modL_proj_mask() {
|
|
|
1852 ShouldNotReachHere();
|
|
|
1853 return RegMask();
|
|
|
1854 }
|
|
|
1855
|
|
|
1856 %}
|
|
|
1857
|
|
|
1858
|
|
|
1859 // The intptr_t operand types, defined by textual substitution.
|
|
|
1860 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
|
|
|
1861 #ifdef _LP64
|
|
|
1862 #define immX immL
|
|
|
1863 #define immX13 immL13
|
|
|
1864 #define iRegX iRegL
|
|
|
1865 #define g1RegX g1RegL
|
|
|
1866 #else
|
|
|
1867 #define immX immI
|
|
|
1868 #define immX13 immI13
|
|
|
1869 #define iRegX iRegI
|
|
|
1870 #define g1RegX g1RegI
|
|
|
1871 #endif
|
|
|
1872
|
|
|
1873 //----------ENCODING BLOCK-----------------------------------------------------
|
|
|
1874 // This block specifies the encoding classes used by the compiler to output
|
|
|
1875 // byte streams. Encoding classes are parameterized macros used by
|
|
|
1876 // Machine Instruction Nodes in order to generate the bit encoding of the
|
|
|
1877 // instruction. Operands specify their base encoding interface with the
|
|
|
1878 // interface keyword. There are currently supported four interfaces,
|
|
|
1879 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
|
|
|
1880 // operand to generate a function which returns its register number when
|
|
|
1881 // queried. CONST_INTER causes an operand to generate a function which
|
|
|
1882 // returns the value of the constant when queried. MEMORY_INTER causes an
|
|
|
1883 // operand to generate four functions which return the Base Register, the
|
|
|
1884 // Index Register, the Scale Value, and the Offset Value of the operand when
|
|
|
1885 // queried. COND_INTER causes an operand to generate six functions which
|
|
|
1886 // return the encoding code (ie - encoding bits for the instruction)
|
|
|
1887 // associated with each basic boolean condition for a conditional instruction.
|
|
|
1888 //
|
|
|
1889 // Instructions specify two basic values for encoding. Again, a function
|
|
|
1890 // is available to check if the constant displacement is an oop. They use the
|
|
|
1891 // ins_encode keyword to specify their encoding classes (which must be
|
|
|
1892 // a sequence of enc_class names, and their parameters, specified in
|
|
|
1893 // the encoding block), and they use the
|
|
|
1894 // opcode keyword to specify, in order, their primary, secondary, and
|
|
|
1895 // tertiary opcode. Only the opcode sections which a particular instruction
|
|
|
1896 // needs for encoding need to be specified.
|
|
|
1897 encode %{
|
|
|
1898 enc_class enc_untested %{
|
|
|
1899 #ifdef ASSERT
|
|
|
1900 MacroAssembler _masm(&cbuf);
|
|
|
1901 __ untested("encoding");
|
|
|
1902 #endif
|
|
|
1903 %}
|
|
|
1904
|
|
|
1905 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
|
|
|
1906 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
|
|
|
1907 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
|
|
|
1908 %}
|
|
|
1909
|
|
|
1910 enc_class form3_mem_reg_little( memory mem, iRegI dst) %{
|
|
|
1911 emit_form3_mem_reg_asi(cbuf, this, $primary, $tertiary,
|
|
|
1912 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg, Assembler::ASI_PRIMARY_LITTLE);
|
|
|
1913 %}
|
|
|
1914
|
|
|
1915 enc_class form3_mem_prefetch_read( memory mem ) %{
|
|
|
1916 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
|
|
|
1917 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
|
|
|
1918 %}
|
|
|
1919
|
|
|
1920 enc_class form3_mem_prefetch_write( memory mem ) %{
|
|
|
1921 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
|
|
|
1922 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
|
|
|
1923 %}
|
|
|
1924
|
|
|
1925 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
|
|
|
1926 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
|
|
|
1927 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
|
|
|
1928 guarantee($mem$$index == R_G0_enc, "double index?");
|
|
|
1929 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
|
|
|
1930 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
|
|
|
1931 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
|
|
|
1932 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
|
|
|
1933 %}
|
|
|
1934
|
|
|
1935 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
|
|
|
1936 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
|
|
|
1937 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
|
|
|
1938 guarantee($mem$$index == R_G0_enc, "double index?");
|
|
|
1939 // Load long with 2 instructions
|
|
|
1940 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
|
|
|
1941 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
|
|
|
1942 %}
|
|
|
1943
|
|
|
1944 //%%% form3_mem_plus_4_reg is a hack--get rid of it
|
|
|
1945 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
|
|
|
1946 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
|
|
|
1947 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
|
|
|
1948 %}
|
|
|
1949
|
|
|
1950 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
|
|
|
1951 // Encode a reg-reg copy. If it is useless, then empty encoding.
|
|
|
1952 if( $rs2$$reg != $rd$$reg )
|
|
|
1953 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
|
|
|
1954 %}
|
|
|
1955
|
|
|
1956 // Target lo half of long
|
|
|
1957 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
|
|
|
1958 // Encode a reg-reg copy. If it is useless, then empty encoding.
|
|
|
1959 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
|
|
|
1960 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
|
|
|
1961 %}
|
|
|
1962
|
|
|
1963 // Source lo half of long
|
|
|
1964 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
|
|
|
1965 // Encode a reg-reg copy. If it is useless, then empty encoding.
|
|
|
1966 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
|
|
|
1967 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
|
|
|
1968 %}
|
|
|
1969
|
|
|
1970 // Target hi half of long
|
|
|
1971 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
|
|
|
1972 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
|
|
|
1973 %}
|
|
|
1974
|
|
|
1975 // Source lo half of long, and leave it sign extended.
|
|
|
1976 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
|
|
|
1977 // Sign extend low half
|
|
|
1978 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
|
|
|
1979 %}
|
|
|
1980
|
|
|
1981 // Source hi half of long, and leave it sign extended.
|
|
|
1982 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
|
|
|
1983 // Shift high half to low half
|
|
|
1984 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
|
|
|
1985 %}
|
|
|
1986
|
|
|
1987 // Source hi half of long
|
|
|
1988 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
|
|
|
1989 // Encode a reg-reg copy. If it is useless, then empty encoding.
|
|
|
1990 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
|
|
|
1991 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
|
|
|
1992 %}
|
|
|
1993
|
|
|
1994 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
|
|
|
1995 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
|
|
|
1996 %}
|
|
|
1997
|
|
|
1998 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
|
|
|
1999 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
|
|
|
2000 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
|
|
|
2001 %}
|
|
|
2002
|
|
|
2003 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
|
|
|
2004 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
|
|
|
2005 // clear if nothing else is happening
|
|
|
2006 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
|
|
|
2007 // blt,a,pn done
|
|
|
2008 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
|
|
|
2009 // mov dst,-1 in delay slot
|
|
|
2010 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
|
|
|
2011 %}
|
|
|
2012
|
|
|
2013 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
|
|
|
2014 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
|
|
|
2015 %}
|
|
|
2016
|
|
|
2017 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
|
|
|
2018 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
|
|
|
2019 %}
|
|
|
2020
|
|
|
2021 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
|
|
|
2022 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
|
|
|
2023 %}
|
|
|
2024
|
|
|
2025 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
|
|
|
2026 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
|
|
|
2027 %}
|
|
|
2028
|
|
|
2029 enc_class move_return_pc_to_o1() %{
|
|
|
2030 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
|
|
|
2031 %}
|
|
|
2032
|
|
|
2033 #ifdef _LP64
|
|
|
2034 /* %%% merge with enc_to_bool */
|
|
|
2035 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
|
|
|
2036 MacroAssembler _masm(&cbuf);
|
|
|
2037
|
|
|
2038 Register src_reg = reg_to_register_object($src$$reg);
|
|
|
2039 Register dst_reg = reg_to_register_object($dst$$reg);
|
|
|
2040 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
|
|
|
2041 %}
|
|
|
2042 #endif
|
|
|
2043
|
|
|
2044 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
|
|
|
2045 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
|
|
|
2046 MacroAssembler _masm(&cbuf);
|
|
|
2047
|
|
|
2048 Register p_reg = reg_to_register_object($p$$reg);
|
|
|
2049 Register q_reg = reg_to_register_object($q$$reg);
|
|
|
2050 Register y_reg = reg_to_register_object($y$$reg);
|
|
|
2051 Register tmp_reg = reg_to_register_object($tmp$$reg);
|
|
|
2052
|
|
|
2053 __ subcc( p_reg, q_reg, p_reg );
|
|
|
2054 __ add ( p_reg, y_reg, tmp_reg );
|
|
|
2055 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
|
|
|
2056 %}
|
|
|
2057
|
|
|
2058 enc_class form_d2i_helper(regD src, regF dst) %{
|
|
|
2059 // fcmp %fcc0,$src,$src
|
|
|
2060 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
|
|
|
2061 // branch %fcc0 not-nan, predict taken
|
|
|
2062 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
|
|
|
2063 // fdtoi $src,$dst
|
|
|
2064 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
|
|
|
2065 // fitos $dst,$dst (if nan)
|
|
|
2066 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
|
|
|
2067 // clear $dst (if nan)
|
|
|
2068 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
|
|
|
2069 // carry on here...
|
|
|
2070 %}
|
|
|
2071
|
|
|
2072 enc_class form_d2l_helper(regD src, regD dst) %{
|
|
|
2073 // fcmp %fcc0,$src,$src check for NAN
|
|
|
2074 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
|
|
|
2075 // branch %fcc0 not-nan, predict taken
|
|
|
2076 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
|
|
|
2077 // fdtox $src,$dst convert in delay slot
|
|
|
2078 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
|
|
|
2079 // fxtod $dst,$dst (if nan)
|
|
|
2080 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
|
|
|
2081 // clear $dst (if nan)
|
|
|
2082 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
|
|
|
2083 // carry on here...
|
|
|
2084 %}
|
|
|
2085
|
|
|
2086 enc_class form_f2i_helper(regF src, regF dst) %{
|
|
|
2087 // fcmps %fcc0,$src,$src
|
|
|
2088 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
|
|
|
2089 // branch %fcc0 not-nan, predict taken
|
|
|
2090 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
|
|
|
2091 // fstoi $src,$dst
|
|
|
2092 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
|
|
|
2093 // fitos $dst,$dst (if nan)
|
|
|
2094 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
|
|
|
2095 // clear $dst (if nan)
|
|
|
2096 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
|
|
|
2097 // carry on here...
|
|
|
2098 %}
|
|
|
2099
|
|
|
2100 enc_class form_f2l_helper(regF src, regD dst) %{
|
|
|
2101 // fcmps %fcc0,$src,$src
|
|
|
2102 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
|
|
|
2103 // branch %fcc0 not-nan, predict taken
|
|
|
2104 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
|
|
|
2105 // fstox $src,$dst
|
|
|
2106 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
|
|
|
2107 // fxtod $dst,$dst (if nan)
|
|
|
2108 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
|
|
|
2109 // clear $dst (if nan)
|
|
|
2110 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
|
|
|
2111 // carry on here...
|
|
|
2112 %}
|
|
|
2113
|
|
|
2114 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
|
|
|
2115 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
|
|
|
2116 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
|
|
|
2117 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
|
|
|
2118
|
|
|
2119 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
|
|
|
2120
|
|
|
2121 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
|
|
|
2122 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
|
|
|
2123
|
|
|
2124 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
|
|
|
2125 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
|
|
|
2126 %}
|
|
|
2127
|
|
|
2128 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
|
|
|
2129 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
|
|
|
2130 %}
|
|
|
2131
|
|
|
2132 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
|
|
|
2133 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
|
|
|
2134 %}
|
|
|
2135
|
|
|
2136 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
|
|
|
2137 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
|
|
|
2138 %}
|
|
|
2139
|
|
|
2140 enc_class form3_convI2F(regF rs2, regF rd) %{
|
|
|
2141 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
|
|
|
2142 %}
|
|
|
2143
|
|
|
2144 // Encloding class for traceable jumps
|
|
|
2145 enc_class form_jmpl(g3RegP dest) %{
|
|
|
2146 emit_jmpl(cbuf, $dest$$reg);
|
|
|
2147 %}
|
|
|
2148
|
|
|
2149 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
|
|
|
2150 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
|
|
|
2151 %}
|
|
|
2152
|
|
|
2153 enc_class form2_nop() %{
|
|
|
2154 emit_nop(cbuf);
|
|
|
2155 %}
|
|
|
2156
|
|
|
2157 enc_class form2_illtrap() %{
|
|
|
2158 emit_illtrap(cbuf);
|
|
|
2159 %}
|
|
|
2160
|
|
|
2161
|
|
|
2162 // Compare longs and convert into -1, 0, 1.
|
|
|
2163 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
|
|
|
2164 // CMP $src1,$src2
|
|
|
2165 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
|
|
|
2166 // blt,a,pn done
|
|
|
2167 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
|
|
|
2168 // mov dst,-1 in delay slot
|
|
|
2169 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
|
|
|
2170 // bgt,a,pn done
|
|
|
2171 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
|
|
|
2172 // mov dst,1 in delay slot
|
|
|
2173 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
|
|
|
2174 // CLR $dst
|
|
|
2175 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
|
|
|
2176 %}
|
|
|
2177
|
|
|
2178 enc_class enc_PartialSubtypeCheck() %{
|
|
|
2179 MacroAssembler _masm(&cbuf);
|
|
|
2180 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
|
|
|
2181 __ delayed()->nop();
|
|
|
2182 %}
|
|
|
2183
|
|
|
2184 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{
|
|
|
2185 MacroAssembler _masm(&cbuf);
|
|
|
2186 Label &L = *($labl$$label);
|
|
|
2187 Assembler::Predict predict_taken =
|
|
|
2188 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
|
|
|
2189
|
|
|
2190 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L);
|
|
|
2191 __ delayed()->nop();
|
|
|
2192 %}
|
|
|
2193
|
|
|
2194 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{
|
|
|
2195 MacroAssembler _masm(&cbuf);
|
|
|
2196 Label &L = *($labl$$label);
|
|
|
2197 Assembler::Predict predict_taken =
|
|
|
2198 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
|
|
|
2199
|
|
|
2200 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L);
|
|
|
2201 __ delayed()->nop();
|
|
|
2202 %}
|
|
|
2203
|
|
|
2204 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{
|
|
|
2205 MacroAssembler _masm(&cbuf);
|
|
|
2206 Label &L = *($labl$$label);
|
|
|
2207 Assembler::Predict predict_taken =
|
|
|
2208 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
|
|
|
2209
|
|
|
2210 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L);
|
|
|
2211 __ delayed()->nop();
|
|
|
2212 %}
|
|
|
2213
|
|
|
2214 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{
|
|
|
2215 MacroAssembler _masm(&cbuf);
|
|
|
2216 Label &L = *($labl$$label);
|
|
|
2217 Assembler::Predict predict_taken =
|
|
|
2218 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
|
|
|
2219
|
|
|
2220 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L);
|
|
|
2221 __ delayed()->nop();
|
|
|
2222 %}
|
|
|
2223
|
|
|
2224 enc_class jump_enc( iRegX switch_val, o7RegI table) %{
|
|
|
2225 MacroAssembler _masm(&cbuf);
|
|
|
2226
|
|
|
2227 Register switch_reg = as_Register($switch_val$$reg);
|
|
|
2228 Register table_reg = O7;
|
|
|
2229
|
|
|
2230 address table_base = __ address_table_constant(_index2label);
|
|
|
2231 RelocationHolder rspec = internal_word_Relocation::spec(table_base);
|
|
|
2232
|
|
|
2233 // Load table address
|
|
|
2234 Address the_pc(table_reg, table_base, rspec);
|
|
|
2235 __ load_address(the_pc);
|
|
|
2236
|
|
|
2237 // Jump to base address + switch value
|
|
|
2238 __ ld_ptr(table_reg, switch_reg, table_reg);
|
|
|
2239 __ jmp(table_reg, G0);
|
|
|
2240 __ delayed()->nop();
|
|
|
2241
|
|
|
2242 %}
|
|
|
2243
|
|
|
2244 enc_class enc_ba( Label labl ) %{
|
|
|
2245 MacroAssembler _masm(&cbuf);
|
|
|
2246 Label &L = *($labl$$label);
|
|
|
2247 __ ba(false, L);
|
|
|
2248 __ delayed()->nop();
|
|
|
2249 %}
|
|
|
2250
|
|
|
2251 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{
|
|
|
2252 MacroAssembler _masm(&cbuf);
|
|
|
2253 Label &L = *$labl$$label;
|
|
|
2254 Assembler::Predict predict_taken =
|
|
|
2255 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
|
|
|
2256
|
|
|
2257 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L);
|
|
|
2258 __ delayed()->nop();
|
|
|
2259 %}
|
|
|
2260
|
|
|
2261 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
|
|
|
2262 int op = (Assembler::arith_op << 30) |
|
|
|
2263 ($dst$$reg << 25) |
|
|
|
2264 (Assembler::movcc_op3 << 19) |
|
|
|
2265 (1 << 18) | // cc2 bit for 'icc'
|
|
|
2266 ($cmp$$cmpcode << 14) |
|
|
|
2267 (0 << 13) | // select register move
|
|
|
2268 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
|
|
|
2269 ($src$$reg << 0);
|
|
|
2270 *((int*)(cbuf.code_end())) = op;
|
|
|
2271 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
|
|
|
2272 %}
|
|
|
2273
|
|
|
2274 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
|
|
|
2275 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
|
|
|
2276 int op = (Assembler::arith_op << 30) |
|
|
|
2277 ($dst$$reg << 25) |
|
|
|
2278 (Assembler::movcc_op3 << 19) |
|
|
|
2279 (1 << 18) | // cc2 bit for 'icc'
|
|
|
2280 ($cmp$$cmpcode << 14) |
|
|
|
2281 (1 << 13) | // select immediate move
|
|
|
2282 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
|
|
|
2283 (simm11 << 0);
|
|
|
2284 *((int*)(cbuf.code_end())) = op;
|
|
|
2285 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
|
|
|
2286 %}
|
|
|
2287
|
|
|
2288 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
|
|
|
2289 int op = (Assembler::arith_op << 30) |
|
|
|
2290 ($dst$$reg << 25) |
|
|
|
2291 (Assembler::movcc_op3 << 19) |
|
|
|
2292 (0 << 18) | // cc2 bit for 'fccX'
|
|
|
2293 ($cmp$$cmpcode << 14) |
|
|
|
2294 (0 << 13) | // select register move
|
|
|
2295 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
|
|
|
2296 ($src$$reg << 0);
|
|
|
2297 *((int*)(cbuf.code_end())) = op;
|
|
|
2298 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
|
|
|
2299 %}
|
|
|
2300
|
|
|
2301 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
|
|
|
2302 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
|
|
|
2303 int op = (Assembler::arith_op << 30) |
|
|
|
2304 ($dst$$reg << 25) |
|
|
|
2305 (Assembler::movcc_op3 << 19) |
|
|
|
2306 (0 << 18) | // cc2 bit for 'fccX'
|
|
|
2307 ($cmp$$cmpcode << 14) |
|
|
|
2308 (1 << 13) | // select immediate move
|
|
|
2309 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
|
|
|
2310 (simm11 << 0);
|
|
|
2311 *((int*)(cbuf.code_end())) = op;
|
|
|
2312 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
|
|
|
2313 %}
|
|
|
2314
|
|
|
2315 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
|
|
|
2316 int op = (Assembler::arith_op << 30) |
|
|
|
2317 ($dst$$reg << 25) |
|
|
|
2318 (Assembler::fpop2_op3 << 19) |
|
|
|
2319 (0 << 18) |
|
|
|
2320 ($cmp$$cmpcode << 14) |
|
|
|
2321 (1 << 13) | // select register move
|
|
|
2322 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
|
|
|
2323 ($primary << 5) | // select single, double or quad
|
|
|
2324 ($src$$reg << 0);
|
|
|
2325 *((int*)(cbuf.code_end())) = op;
|
|
|
2326 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
|
|
|
2327 %}
|
|
|
2328
|
|
|
2329 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
|
|
|
2330 int op = (Assembler::arith_op << 30) |
|
|
|
2331 ($dst$$reg << 25) |
|
|
|
2332 (Assembler::fpop2_op3 << 19) |
|
|
|
2333 (0 << 18) |
|
|
|
2334 ($cmp$$cmpcode << 14) |
|
|
|
2335 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
|
|
|
2336 ($primary << 5) | // select single, double or quad
|
|
|
2337 ($src$$reg << 0);
|
|
|
2338 *((int*)(cbuf.code_end())) = op;
|
|
|
2339 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
|
|
|
2340 %}
|
|
|
2341
|
|
|
2342 // Used by the MIN/MAX encodings. Same as a CMOV, but
|
|
|
2343 // the condition comes from opcode-field instead of an argument.
|
|
|
2344 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
|
|
|
2345 int op = (Assembler::arith_op << 30) |
|
|
|
2346 ($dst$$reg << 25) |
|
|
|
2347 (Assembler::movcc_op3 << 19) |
|
|
|
2348 (1 << 18) | // cc2 bit for 'icc'
|
|
|
2349 ($primary << 14) |
|
|
|
2350 (0 << 13) | // select register move
|
|
|
2351 (0 << 11) | // cc1, cc0 bits for 'icc'
|
|
|
2352 ($src$$reg << 0);
|
|
|
2353 *((int*)(cbuf.code_end())) = op;
|
|
|
2354 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
|
|
|
2355 %}
|
|
|
2356
|
|
|
2357 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
|
|
|
2358 int op = (Assembler::arith_op << 30) |
|
|
|
2359 ($dst$$reg << 25) |
|
|
|
2360 (Assembler::movcc_op3 << 19) |
|
|
|
2361 (6 << 16) | // cc2 bit for 'xcc'
|
|
|
2362 ($primary << 14) |
|
|
|
2363 (0 << 13) | // select register move
|
|
|
2364 (0 << 11) | // cc1, cc0 bits for 'icc'
|
|
|
2365 ($src$$reg << 0);
|
|
|
2366 *((int*)(cbuf.code_end())) = op;
|
|
|
2367 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
|
|
|
2368 %}
|
|
|
2369
|
|
|
2370 // Utility encoding for loading a 64 bit Pointer into a register
|
|
|
2371 // The 64 bit pointer is stored in the generated code stream
|
|
|
2372 enc_class SetPtr( immP src, iRegP rd ) %{
|
|
|
2373 Register dest = reg_to_register_object($rd$$reg);
|
|
|
2374 // [RGV] This next line should be generated from ADLC
|
|
|
2375 if ( _opnds[1]->constant_is_oop() ) {
|
|
|
2376 intptr_t val = $src$$constant;
|
|
|
2377 MacroAssembler _masm(&cbuf);
|
|
|
2378 __ set_oop_constant((jobject)val, dest);
|
|
|
2379 } else { // non-oop pointers, e.g. card mark base, heap top
|
|
|
2380 emit_ptr(cbuf, $src$$constant, dest, /*ForceRelocatable=*/ false);
|
|
|
2381 }
|
|
|
2382 %}
|
|
|
2383
|
|
|
2384 enc_class Set13( immI13 src, iRegI rd ) %{
|
|
|
2385 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
|
|
|
2386 %}
|
|
|
2387
|
|
|
2388 enc_class SetHi22( immI src, iRegI rd ) %{
|
|
|
2389 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
|
|
|
2390 %}
|
|
|
2391
|
|
|
2392 enc_class Set32( immI src, iRegI rd ) %{
|
|
|
2393 MacroAssembler _masm(&cbuf);
|
|
|
2394 __ set($src$$constant, reg_to_register_object($rd$$reg));
|
|
|
2395 %}
|
|
|
2396
|
|
|
2397 enc_class SetNull( iRegI rd ) %{
|
|
|
2398 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 );
|
|
|
2399 %}
|
|
|
2400
|
|
|
2401 enc_class call_epilog %{
|
|
|
2402 if( VerifyStackAtCalls ) {
|
|
|
2403 MacroAssembler _masm(&cbuf);
|
|
|
2404 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
|
|
|
2405 Register temp_reg = G3;
|
|
|
2406 __ add(SP, framesize, temp_reg);
|
|
|
2407 __ cmp(temp_reg, FP);
|
|
|
2408 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
|
|
|
2409 }
|
|
|
2410 %}
|
|
|
2411
|
|
|
2412 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
|
|
|
2413 // to G1 so the register allocator will not have to deal with the misaligned register
|
|
|
2414 // pair.
|
|
|
2415 enc_class adjust_long_from_native_call %{
|
|
|
2416 #ifndef _LP64
|
|
|
2417 if (returns_long()) {
|
|
|
2418 // sllx O0,32,O0
|
|
|
2419 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
|
|
|
2420 // srl O1,0,O1
|
|
|
2421 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
|
|
|
2422 // or O0,O1,G1
|
|
|
2423 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
|
|
|
2424 }
|
|
|
2425 #endif
|
|
|
2426 %}
|
|
|
2427
|
|
|
2428 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
|
|
|
2429 // CALL directly to the runtime
|
|
|
2430 // The user of this is responsible for ensuring that R_L7 is empty (killed).
|
|
|
2431 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
|
|
|
2432 /*preserve_g2=*/true, /*force far call*/true);
|
|
|
2433 %}
|
|
|
2434
|
|
|
2435 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
|
|
|
2436 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
|
|
|
2437 // who we intended to call.
|
|
|
2438 if ( !_method ) {
|
|
|
2439 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
|
|
|
2440 } else if (_optimized_virtual) {
|
|
|
2441 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
|
|
|
2442 } else {
|
|
|
2443 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
|
|
|
2444 }
|
|
|
2445 if( _method ) { // Emit stub for static call
|
|
|
2446 emit_java_to_interp(cbuf);
|
|
|
2447 }
|
|
|
2448 %}
|
|
|
2449
|
|
|
2450 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
|
|
|
2451 MacroAssembler _masm(&cbuf);
|
|
|
2452 __ set_inst_mark();
|
|
|
2453 int vtable_index = this->_vtable_index;
|
|
|
2454 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
|
|
|
2455 if (vtable_index < 0) {
|
|
|
2456 // must be invalid_vtable_index, not nonvirtual_vtable_index
|
|
|
2457 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
|
|
|
2458 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
|
|
|
2459 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
|
|
|
2460 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
|
|
|
2461 // !!!!!
|
|
|
2462 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info
|
|
|
2463 // emit_call_dynamic_prologue( cbuf );
|
|
|
2464 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg);
|
|
|
2465
|
|
|
2466 address virtual_call_oop_addr = __ inst_mark();
|
|
|
2467 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
|
|
|
2468 // who we intended to call.
|
|
|
2469 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
|
|
|
2470 emit_call_reloc(cbuf, $meth$$method, relocInfo::none);
|
|
|
2471 } else {
|
|
|
2472 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
|
|
|
2473 // Just go thru the vtable
|
|
|
2474 // get receiver klass (receiver already checked for non-null)
|
|
|
2475 // If we end up going thru a c2i adapter interpreter expects method in G5
|
|
|
2476 int off = __ offset();
|
|
|
2477 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), G3_scratch);
|
|
|
2478 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
|
|
|
2479 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
|
|
|
2480 if( __ is_simm13(v_off) ) {
|
|
|
2481 __ ld_ptr(G3, v_off, G5_method);
|
|
|
2482 } else {
|
|
|
2483 // Generate 2 instructions
|
|
|
2484 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
|
|
|
2485 __ or3(G5_method, v_off & 0x3ff, G5_method);
|
|
|
2486 // ld_ptr, set_hi, set
|
|
|
2487 assert(__ offset() - off == 3*BytesPerInstWord, "Unexpected instruction size(s)");
|
|
|
2488 __ ld_ptr(G3, G5_method, G5_method);
|
|
|
2489 }
|
|
|
2490 // NOTE: for vtable dispatches, the vtable entry will never be null.
|
|
|
2491 // However it may very well end up in handle_wrong_method if the
|
|
|
2492 // method is abstract for the particular class.
|
|
|
2493 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch);
|
|
|
2494 // jump to target (either compiled code or c2iadapter)
|
|
|
2495 __ jmpl(G3_scratch, G0, O7);
|
|
|
2496 __ delayed()->nop();
|
|
|
2497 }
|
|
|
2498 %}
|
|
|
2499
|
|
|
2500 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
|
|
|
2501 MacroAssembler _masm(&cbuf);
|
|
|
2502
|
|
|
2503 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
|
|
|
2504 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
|
|
|
2505 // we might be calling a C2I adapter which needs it.
|
|
|
2506
|
|
|
2507 assert(temp_reg != G5_ic_reg, "conflicting registers");
|
|
|
2508 // Load nmethod
|
|
|
2509 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg);
|
|
|
2510
|
|
|
2511 // CALL to compiled java, indirect the contents of G3
|
|
|
2512 __ set_inst_mark();
|
|
|
2513 __ callr(temp_reg, G0);
|
|
|
2514 __ delayed()->nop();
|
|
|
2515 %}
|
|
|
2516
|
|
|
2517 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
|
|
|
2518 MacroAssembler _masm(&cbuf);
|
|
|
2519 Register Rdividend = reg_to_register_object($src1$$reg);
|
|
|
2520 Register Rdivisor = reg_to_register_object($src2$$reg);
|
|
|
2521 Register Rresult = reg_to_register_object($dst$$reg);
|
|
|
2522
|
|
|
2523 __ sra(Rdivisor, 0, Rdivisor);
|
|
|
2524 __ sra(Rdividend, 0, Rdividend);
|
|
|
2525 __ sdivx(Rdividend, Rdivisor, Rresult);
|
|
|
2526 %}
|
|
|
2527
|
|
|
2528 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
|
|
|
2529 MacroAssembler _masm(&cbuf);
|
|
|
2530
|
|
|
2531 Register Rdividend = reg_to_register_object($src1$$reg);
|
|
|
2532 int divisor = $imm$$constant;
|
|
|
2533 Register Rresult = reg_to_register_object($dst$$reg);
|
|
|
2534
|
|
|
2535 __ sra(Rdividend, 0, Rdividend);
|
|
|
2536 __ sdivx(Rdividend, divisor, Rresult);
|
|
|
2537 %}
|
|
|
2538
|
|
|
2539 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
|
|
|
2540 MacroAssembler _masm(&cbuf);
|
|
|
2541 Register Rsrc1 = reg_to_register_object($src1$$reg);
|
|
|
2542 Register Rsrc2 = reg_to_register_object($src2$$reg);
|
|
|
2543 Register Rdst = reg_to_register_object($dst$$reg);
|
|
|
2544
|
|
|
2545 __ sra( Rsrc1, 0, Rsrc1 );
|
|
|
2546 __ sra( Rsrc2, 0, Rsrc2 );
|
|
|
2547 __ mulx( Rsrc1, Rsrc2, Rdst );
|
|
|
2548 __ srlx( Rdst, 32, Rdst );
|
|
|
2549 %}
|
|
|
2550
|
|
|
2551 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
|
|
|
2552 MacroAssembler _masm(&cbuf);
|
|
|
2553 Register Rdividend = reg_to_register_object($src1$$reg);
|
|
|
2554 Register Rdivisor = reg_to_register_object($src2$$reg);
|
|
|
2555 Register Rresult = reg_to_register_object($dst$$reg);
|
|
|
2556 Register Rscratch = reg_to_register_object($scratch$$reg);
|
|
|
2557
|
|
|
2558 assert(Rdividend != Rscratch, "");
|
|
|
2559 assert(Rdivisor != Rscratch, "");
|
|
|
2560
|
|
|
2561 __ sra(Rdividend, 0, Rdividend);
|
|
|
2562 __ sra(Rdivisor, 0, Rdivisor);
|
|
|
2563 __ sdivx(Rdividend, Rdivisor, Rscratch);
|
|
|
2564 __ mulx(Rscratch, Rdivisor, Rscratch);
|
|
|
2565 __ sub(Rdividend, Rscratch, Rresult);
|
|
|
2566 %}
|
|
|
2567
|
|
|
2568 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
|
|
|
2569 MacroAssembler _masm(&cbuf);
|
|
|
2570
|
|
|
2571 Register Rdividend = reg_to_register_object($src1$$reg);
|
|
|
2572 int divisor = $imm$$constant;
|
|
|
2573 Register Rresult = reg_to_register_object($dst$$reg);
|
|
|
2574 Register Rscratch = reg_to_register_object($scratch$$reg);
|
|
|
2575
|
|
|
2576 assert(Rdividend != Rscratch, "");
|
|
|
2577
|
|
|
2578 __ sra(Rdividend, 0, Rdividend);
|
|
|
2579 __ sdivx(Rdividend, divisor, Rscratch);
|
|
|
2580 __ mulx(Rscratch, divisor, Rscratch);
|
|
|
2581 __ sub(Rdividend, Rscratch, Rresult);
|
|
|
2582 %}
|
|
|
2583
|
|
|
2584 enc_class fabss (sflt_reg dst, sflt_reg src) %{
|
|
|
2585 MacroAssembler _masm(&cbuf);
|
|
|
2586
|
|
|
2587 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
|
|
|
2588 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
|
|
|
2589
|
|
|
2590 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
|
|
|
2591 %}
|
|
|
2592
|
|
|
2593 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
|
|
|
2594 MacroAssembler _masm(&cbuf);
|
|
|
2595
|
|
|
2596 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
|
|
|
2597 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
|
|
|
2598
|
|
|
2599 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
|
|
|
2600 %}
|
|
|
2601
|
|
|
2602 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
|
|
|
2603 MacroAssembler _masm(&cbuf);
|
|
|
2604
|
|
|
2605 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
|
|
|
2606 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
|
|
|
2607
|
|
|
2608 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
|
|
|
2609 %}
|
|
|
2610
|
|
|
2611 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
|
|
|
2612 MacroAssembler _masm(&cbuf);
|
|
|
2613
|
|
|
2614 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
|
|
|
2615 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
|
|
|
2616
|
|
|
2617 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
|
|
|
2618 %}
|
|
|
2619
|
|
|
2620 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
|
|
|
2621 MacroAssembler _masm(&cbuf);
|
|
|
2622
|
|
|
2623 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
|
|
|
2624 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
|
|
|
2625
|
|
|
2626 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
|
|
|
2627 %}
|
|
|
2628
|
|
|
2629 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
|
|
|
2630 MacroAssembler _masm(&cbuf);
|
|
|
2631
|
|
|
2632 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
|
|
|
2633 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
|
|
|
2634
|
|
|
2635 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
|
|
|
2636 %}
|
|
|
2637
|
|
|
2638 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
|
|
|
2639 MacroAssembler _masm(&cbuf);
|
|
|
2640
|
|
|
2641 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
|
|
|
2642 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
|
|
|
2643
|
|
|
2644 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
|
|
|
2645 %}
|
|
|
2646
|
|
|
2647 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
|
|
|
2648 MacroAssembler _masm(&cbuf);
|
|
|
2649
|
|
|
2650 Register Roop = reg_to_register_object($oop$$reg);
|
|
|
2651 Register Rbox = reg_to_register_object($box$$reg);
|
|
|
2652 Register Rscratch = reg_to_register_object($scratch$$reg);
|
|
|
2653 Register Rmark = reg_to_register_object($scratch2$$reg);
|
|
|
2654
|
|
|
2655 assert(Roop != Rscratch, "");
|
|
|
2656 assert(Roop != Rmark, "");
|
|
|
2657 assert(Rbox != Rscratch, "");
|
|
|
2658 assert(Rbox != Rmark, "");
|
|
|
2659
|
|
|
2660 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters);
|
|
|
2661 %}
|
|
|
2662
|
|
|
2663 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
|
|
|
2664 MacroAssembler _masm(&cbuf);
|
|
|
2665
|
|
|
2666 Register Roop = reg_to_register_object($oop$$reg);
|
|
|
2667 Register Rbox = reg_to_register_object($box$$reg);
|
|
|
2668 Register Rscratch = reg_to_register_object($scratch$$reg);
|
|
|
2669 Register Rmark = reg_to_register_object($scratch2$$reg);
|
|
|
2670
|
|
|
2671 assert(Roop != Rscratch, "");
|
|
|
2672 assert(Roop != Rmark, "");
|
|
|
2673 assert(Rbox != Rscratch, "");
|
|
|
2674 assert(Rbox != Rmark, "");
|
|
|
2675
|
|
|
2676 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch);
|
|
|
2677 %}
|
|
|
2678
|
|
|
2679 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
|
|
|
2680 MacroAssembler _masm(&cbuf);
|
|
|
2681 Register Rmem = reg_to_register_object($mem$$reg);
|
|
|
2682 Register Rold = reg_to_register_object($old$$reg);
|
|
|
2683 Register Rnew = reg_to_register_object($new$$reg);
|
|
|
2684
|
|
|
2685 // casx_under_lock picks 1 of 3 encodings:
|
|
|
2686 // For 32-bit pointers you get a 32-bit CAS
|
|
|
2687 // For 64-bit pointers you get a 64-bit CASX
|
|
|
2688 __ casx_under_lock(Rmem, Rold, Rnew, // Swap(*Rmem,Rnew) if *Rmem == Rold
|
|
|
2689 (address) StubRoutines::Sparc::atomic_memory_operation_lock_addr());
|
|
|
2690 __ cmp( Rold, Rnew );
|
|
|
2691 %}
|
|
|
2692
|
|
|
2693 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
|
|
|
2694 Register Rmem = reg_to_register_object($mem$$reg);
|
|
|
2695 Register Rold = reg_to_register_object($old$$reg);
|
|
|
2696 Register Rnew = reg_to_register_object($new$$reg);
|
|
|
2697
|
|
|
2698 MacroAssembler _masm(&cbuf);
|
|
|
2699 __ mov(Rnew, O7);
|
|
|
2700 __ casx(Rmem, Rold, O7);
|
|
|
2701 __ cmp( Rold, O7 );
|
|
|
2702 %}
|
|
|
2703
|
|
|
2704 // raw int cas, used for compareAndSwap
|
|
|
2705 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
|
|
|
2706 Register Rmem = reg_to_register_object($mem$$reg);
|
|
|
2707 Register Rold = reg_to_register_object($old$$reg);
|
|
|
2708 Register Rnew = reg_to_register_object($new$$reg);
|
|
|
2709
|
|
|
2710 MacroAssembler _masm(&cbuf);
|
|
|
2711 __ mov(Rnew, O7);
|
|
|
2712 __ cas(Rmem, Rold, O7);
|
|
|
2713 __ cmp( Rold, O7 );
|
|
|
2714 %}
|
|
|
2715
|
|
|
2716 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
|
|
|
2717 Register Rres = reg_to_register_object($res$$reg);
|
|
|
2718
|
|
|
2719 MacroAssembler _masm(&cbuf);
|
|
|
2720 __ mov(1, Rres);
|
|
|
2721 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
|
|
|
2722 %}
|
|
|
2723
|
|
|
2724 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
|
|
|
2725 Register Rres = reg_to_register_object($res$$reg);
|
|
|
2726
|
|
|
2727 MacroAssembler _masm(&cbuf);
|
|
|
2728 __ mov(1, Rres);
|
|
|
2729 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
|
|
|
2730 %}
|
|
|
2731
|
|
|
2732 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
|
|
|
2733 MacroAssembler _masm(&cbuf);
|
|
|
2734 Register Rdst = reg_to_register_object($dst$$reg);
|
|
|
2735 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
|
|
|
2736 : reg_to_DoubleFloatRegister_object($src1$$reg);
|
|
|
2737 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
|
|
|
2738 : reg_to_DoubleFloatRegister_object($src2$$reg);
|
|
|
2739
|
|
|
2740 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
|
|
|
2741 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
|
|
|
2742 %}
|
|
|
2743
|
|
|
2744 enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{ // Load Immediate
|
|
|
2745 MacroAssembler _masm(&cbuf);
|
|
|
2746 Register dest = reg_to_register_object($dst$$reg);
|
|
|
2747 Register temp = reg_to_register_object($tmp$$reg);
|
|
|
2748 __ set64( $src$$constant, dest, temp );
|
|
|
2749 %}
|
|
|
2750
|
|
|
2751 enc_class LdImmF(immF src, regF dst, o7RegP tmp) %{ // Load Immediate
|
|
|
2752 address float_address = MacroAssembler(&cbuf).float_constant($src$$constant);
|
|
|
2753 RelocationHolder rspec = internal_word_Relocation::spec(float_address);
|
|
|
2754 #ifdef _LP64
|
|
|
2755 Register tmp_reg = reg_to_register_object($tmp$$reg);
|
|
|
2756 cbuf.relocate(cbuf.code_end(), rspec, 0);
|
|
|
2757 emit_ptr(cbuf, (intptr_t)float_address, tmp_reg, /*ForceRelocatable=*/ true);
|
|
|
2758 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::ldf_op3, $tmp$$reg, 0 );
|
|
|
2759 #else // _LP64
|
|
|
2760 uint *code;
|
|
|
2761 int tmp_reg = $tmp$$reg;
|
|
|
2762
|
|
|
2763 cbuf.relocate(cbuf.code_end(), rspec, 0);
|
|
|
2764 emit2_22( cbuf, Assembler::branch_op, tmp_reg, Assembler::sethi_op2, (intptr_t) float_address );
|
|
|
2765
|
|
|
2766 cbuf.relocate(cbuf.code_end(), rspec, 0);
|
|
|
2767 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::ldf_op3, tmp_reg, (intptr_t) float_address );
|
|
|
2768 #endif // _LP64
|
|
|
2769 %}
|
|
|
2770
|
|
|
2771 enc_class LdImmD(immD src, regD dst, o7RegP tmp) %{ // Load Immediate
|
|
|
2772 address double_address = MacroAssembler(&cbuf).double_constant($src$$constant);
|
|
|
2773 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
|
|
|
2774 #ifdef _LP64
|
|
|
2775 Register tmp_reg = reg_to_register_object($tmp$$reg);
|
|
|
2776 cbuf.relocate(cbuf.code_end(), rspec, 0);
|
|
|
2777 emit_ptr(cbuf, (intptr_t)double_address, tmp_reg, /*ForceRelocatable=*/ true);
|
|
|
2778 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, $tmp$$reg, 0 );
|
|
|
2779 #else // _LP64
|
|
|
2780 uint *code;
|
|
|
2781 int tmp_reg = $tmp$$reg;
|
|
|
2782
|
|
|
2783 cbuf.relocate(cbuf.code_end(), rspec, 0);
|
|
|
2784 emit2_22( cbuf, Assembler::branch_op, tmp_reg, Assembler::sethi_op2, (intptr_t) double_address );
|
|
|
2785
|
|
|
2786 cbuf.relocate(cbuf.code_end(), rspec, 0);
|
|
|
2787 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, tmp_reg, (intptr_t) double_address );
|
|
|
2788 #endif // _LP64
|
|
|
2789 %}
|
|
|
2790
|
|
|
2791 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{
|
|
|
2792 // Load a constant replicated "count" times with width "width"
|
|
|
2793 int bit_width = $width$$constant * 8;
|
|
|
2794 jlong elt_val = $src$$constant;
|
|
|
2795 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits
|
|
|
2796 jlong val = elt_val;
|
|
|
2797 for (int i = 0; i < $count$$constant - 1; i++) {
|
|
|
2798 val <<= bit_width;
|
|
|
2799 val |= elt_val;
|
|
|
2800 }
|
|
|
2801 jdouble dval = *(jdouble*)&val; // coerce to double type
|
|
|
2802 address double_address = MacroAssembler(&cbuf).double_constant(dval);
|
|
|
2803 RelocationHolder rspec = internal_word_Relocation::spec(double_address);
|
|
|
2804 #ifdef _LP64
|
|
|
2805 Register tmp_reg = reg_to_register_object($tmp$$reg);
|
|
|
2806 cbuf.relocate(cbuf.code_end(), rspec, 0);
|
|
|
2807 emit_ptr(cbuf, (intptr_t)double_address, tmp_reg, /*ForceRelocatable=*/ true);
|
|
|
2808 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, $tmp$$reg, 0 );
|
|
|
2809 #else // _LP64
|
|
|
2810 uint *code;
|
|
|
2811 int tmp_reg = $tmp$$reg;
|
|
|
2812
|
|
|
2813 cbuf.relocate(cbuf.code_end(), rspec, 0);
|
|
|
2814 emit2_22( cbuf, Assembler::branch_op, tmp_reg, Assembler::sethi_op2, (intptr_t) double_address );
|
|
|
2815
|
|
|
2816 cbuf.relocate(cbuf.code_end(), rspec, 0);
|
|
|
2817 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, tmp_reg, (intptr_t) double_address );
|
|
|
2818 #endif // _LP64
|
|
|
2819 %}
|
|
|
2820
|
|
|
2821
|
|
|
2822 enc_class ShouldNotEncodeThis ( ) %{
|
|
|
2823 ShouldNotCallThis();
|
|
|
2824 %}
|
|
|
2825
|
|
|
2826 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
|
|
|
2827 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{
|
|
|
2828 MacroAssembler _masm(&cbuf);
|
|
|
2829 Register nof_bytes_arg = reg_to_register_object($cnt$$reg);
|
|
|
2830 Register nof_bytes_tmp = reg_to_register_object($temp$$reg);
|
|
|
2831 Register base_pointer_arg = reg_to_register_object($base$$reg);
|
|
|
2832
|
|
|
2833 Label loop;
|
|
|
2834 __ mov(nof_bytes_arg, nof_bytes_tmp);
|
|
|
2835
|
|
|
2836 // Loop and clear, walking backwards through the array.
|
|
|
2837 // nof_bytes_tmp (if >0) is always the number of bytes to zero
|
|
|
2838 __ bind(loop);
|
|
|
2839 __ deccc(nof_bytes_tmp, 8);
|
|
|
2840 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
|
|
|
2841 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
|
|
|
2842 // %%%% this mini-loop must not cross a cache boundary!
|
|
|
2843 %}
|
|
|
2844
|
|
|
2845
|
|
|
2846 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{
|
|
|
2847 Label Ldone, Lloop;
|
|
|
2848 MacroAssembler _masm(&cbuf);
|
|
|
2849
|
|
|
2850 Register str1_reg = reg_to_register_object($str1$$reg);
|
|
|
2851 Register str2_reg = reg_to_register_object($str2$$reg);
|
|
|
2852 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
|
|
|
2853 Register tmp2_reg = reg_to_register_object($tmp2$$reg);
|
|
|
2854 Register result_reg = reg_to_register_object($result$$reg);
|
|
|
2855
|
|
|
2856 // Get the first character position in both strings
|
|
|
2857 // [8] char array, [12] offset, [16] count
|
|
|
2858 int value_offset = java_lang_String:: value_offset_in_bytes();
|
|
|
2859 int offset_offset = java_lang_String::offset_offset_in_bytes();
|
|
|
2860 int count_offset = java_lang_String:: count_offset_in_bytes();
|
|
|
2861
|
|
|
2862 // load str1 (jchar*) base address into tmp1_reg
|
|
|
2863 __ ld_ptr(Address(str1_reg, 0, value_offset), tmp1_reg);
|
|
|
2864 __ ld(Address(str1_reg, 0, offset_offset), result_reg);
|
|
|
2865 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg);
|
|
|
2866 __ ld(Address(str1_reg, 0, count_offset), str1_reg); // hoisted
|
|
|
2867 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
|
|
|
2868 __ ld_ptr(Address(str2_reg, 0, value_offset), tmp2_reg); // hoisted
|
|
|
2869 __ add(result_reg, tmp1_reg, tmp1_reg);
|
|
|
2870
|
|
|
2871 // load str2 (jchar*) base address into tmp2_reg
|
|
|
2872 // __ ld_ptr(Address(str2_reg, 0, value_offset), tmp2_reg); // hoisted
|
|
|
2873 __ ld(Address(str2_reg, 0, offset_offset), result_reg);
|
|
|
2874 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg);
|
|
|
2875 __ ld(Address(str2_reg, 0, count_offset), str2_reg); // hoisted
|
|
|
2876 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
|
|
|
2877 __ subcc(str1_reg, str2_reg, O7); // hoisted
|
|
|
2878 __ add(result_reg, tmp2_reg, tmp2_reg);
|
|
|
2879
|
|
|
2880 // Compute the minimum of the string lengths(str1_reg) and the
|
|
|
2881 // difference of the string lengths (stack)
|
|
|
2882
|
|
|
2883 // discard string base pointers, after loading up the lengths
|
|
|
2884 // __ ld(Address(str1_reg, 0, count_offset), str1_reg); // hoisted
|
|
|
2885 // __ ld(Address(str2_reg, 0, count_offset), str2_reg); // hoisted
|
|
|
2886
|
|
|
2887 // See if the lengths are different, and calculate min in str1_reg.
|
|
|
2888 // Stash diff in O7 in case we need it for a tie-breaker.
|
|
|
2889 Label Lskip;
|
|
|
2890 // __ subcc(str1_reg, str2_reg, O7); // hoisted
|
|
|
2891 __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit
|
|
|
2892 __ br(Assembler::greater, true, Assembler::pt, Lskip);
|
|
|
2893 // str2 is shorter, so use its count:
|
|
|
2894 __ delayed()->sll(str2_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit
|
|
|
2895 __ bind(Lskip);
|
|
|
2896
|
|
|
2897 // reallocate str1_reg, str2_reg, result_reg
|
|
|
2898 // Note: limit_reg holds the string length pre-scaled by 2
|
|
|
2899 Register limit_reg = str1_reg;
|
|
|
2900 Register chr2_reg = str2_reg;
|
|
|
2901 Register chr1_reg = result_reg;
|
|
|
2902 // tmp{12} are the base pointers
|
|
|
2903
|
|
|
2904 // Is the minimum length zero?
|
|
|
2905 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
|
|
|
2906 __ br(Assembler::equal, true, Assembler::pn, Ldone);
|
|
|
2907 __ delayed()->mov(O7, result_reg); // result is difference in lengths
|
|
|
2908
|
|
|
2909 // Load first characters
|
|
|
2910 __ lduh(tmp1_reg, 0, chr1_reg);
|
|
|
2911 __ lduh(tmp2_reg, 0, chr2_reg);
|
|
|
2912
|
|
|
2913 // Compare first characters
|
|
|
2914 __ subcc(chr1_reg, chr2_reg, chr1_reg);
|
|
|
2915 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
|
|
|
2916 assert(chr1_reg == result_reg, "result must be pre-placed");
|
|
|
2917 __ delayed()->nop();
|
|
|
2918
|
|
|
2919 {
|
|
|
2920 // Check after comparing first character to see if strings are equivalent
|
|
|
2921 Label LSkip2;
|
|
|
2922 // Check if the strings start at same location
|
|
|
2923 __ cmp(tmp1_reg, tmp2_reg);
|
|
|
2924 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
|
|
|
2925 __ delayed()->nop();
|
|
|
2926
|
|
|
2927 // Check if the length difference is zero (in O7)
|
|
|
2928 __ cmp(G0, O7);
|
|
|
2929 __ br(Assembler::equal, true, Assembler::pn, Ldone);
|
|
|
2930 __ delayed()->mov(G0, result_reg); // result is zero
|
|
|
2931
|
|
|
2932 // Strings might not be equal
|
|
|
2933 __ bind(LSkip2);
|
|
|
2934 }
|
|
|
2935
|
|
|
2936 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
|
|
|
2937 __ br(Assembler::equal, true, Assembler::pn, Ldone);
|
|
|
2938 __ delayed()->mov(O7, result_reg); // result is difference in lengths
|
|
|
2939
|
|
|
2940 // Shift tmp1_reg and tmp2_reg to the end of the arrays, negate limit
|
|
|
2941 __ add(tmp1_reg, limit_reg, tmp1_reg);
|
|
|
2942 __ add(tmp2_reg, limit_reg, tmp2_reg);
|
|
|
2943 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
|
|
|
2944
|
|
|
2945 // Compare the rest of the characters
|
|
|
2946 __ lduh(tmp1_reg, limit_reg, chr1_reg);
|
|
|
2947 __ bind(Lloop);
|
|
|
2948 // __ lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted
|
|
|
2949 __ lduh(tmp2_reg, limit_reg, chr2_reg);
|
|
|
2950 __ subcc(chr1_reg, chr2_reg, chr1_reg);
|
|
|
2951 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
|
|
|
2952 assert(chr1_reg == result_reg, "result must be pre-placed");
|
|
|
2953 __ delayed()->inccc(limit_reg, sizeof(jchar));
|
|
|
2954 // annul LDUH if branch is not taken to prevent access past end of string
|
|
|
2955 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
|
|
|
2956 __ delayed()->lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted
|
|
|
2957
|
|
|
2958 // If strings are equal up to min length, return the length difference.
|
|
|
2959 __ mov(O7, result_reg);
|
|
|
2960
|
|
|
2961 // Otherwise, return the difference between the first mismatched chars.
|
|
|
2962 __ bind(Ldone);
|
|
|
2963 %}
|
|
|
2964
|
|
|
2965 enc_class enc_rethrow() %{
|
|
|
2966 cbuf.set_inst_mark();
|
|
|
2967 Register temp_reg = G3;
|
|
|
2968 Address rethrow_stub(temp_reg, OptoRuntime::rethrow_stub());
|
|
|
2969 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
|
|
|
2970 MacroAssembler _masm(&cbuf);
|
|
|
2971 #ifdef ASSERT
|
|
|
2972 __ save_frame(0);
|
|
|
2973 Address last_rethrow_addr(L1, (address)&last_rethrow);
|
|
|
2974 __ sethi(last_rethrow_addr);
|
|
|
2975 __ get_pc(L2);
|
|
|
2976 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
|
|
|
2977 __ st_ptr(L2, last_rethrow_addr);
|
|
|
2978 __ restore();
|
|
|
2979 #endif
|
|
|
2980 __ JUMP(rethrow_stub, 0); // sethi;jmp
|
|
|
2981 __ delayed()->nop();
|
|
|
2982 %}
|
|
|
2983
|
|
|
2984 enc_class emit_mem_nop() %{
|
|
|
2985 // Generates the instruction LDUXA [o6,g0],#0x82,g0
|
|
|
2986 unsigned int *code = (unsigned int*)cbuf.code_end();
|
|
|
2987 *code = (unsigned int)0xc0839040;
|
|
|
2988 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
|
|
|
2989 %}
|
|
|
2990
|
|
|
2991 enc_class emit_fadd_nop() %{
|
|
|
2992 // Generates the instruction FMOVS f31,f31
|
|
|
2993 unsigned int *code = (unsigned int*)cbuf.code_end();
|
|
|
2994 *code = (unsigned int)0xbfa0003f;
|
|
|
2995 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
|
|
|
2996 %}
|
|
|
2997
|
|
|
2998 enc_class emit_br_nop() %{
|
|
|
2999 // Generates the instruction BPN,PN .
|
|
|
3000 unsigned int *code = (unsigned int*)cbuf.code_end();
|
|
|
3001 *code = (unsigned int)0x00400000;
|
|
|
3002 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
|
|
|
3003 %}
|
|
|
3004
|
|
|
3005 enc_class enc_membar_acquire %{
|
|
|
3006 MacroAssembler _masm(&cbuf);
|
|
|
3007 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
|
|
|
3008 %}
|
|
|
3009
|
|
|
3010 enc_class enc_membar_release %{
|
|
|
3011 MacroAssembler _masm(&cbuf);
|
|
|
3012 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
|
|
|
3013 %}
|
|
|
3014
|
|
|
3015 enc_class enc_membar_volatile %{
|
|
|
3016 MacroAssembler _masm(&cbuf);
|
|
|
3017 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
|
|
|
3018 %}
|
|
|
3019 enc_class enc_repl8b( iRegI src, iRegL dst ) %{
|
|
|
3020 MacroAssembler _masm(&cbuf);
|
|
|
3021 Register src_reg = reg_to_register_object($src$$reg);
|
|
|
3022 Register dst_reg = reg_to_register_object($dst$$reg);
|
|
|
3023 __ sllx(src_reg, 56, dst_reg);
|
|
|
3024 __ srlx(dst_reg, 8, O7);
|
|
|
3025 __ or3 (dst_reg, O7, dst_reg);
|
|
|
3026 __ srlx(dst_reg, 16, O7);
|
|
|
3027 __ or3 (dst_reg, O7, dst_reg);
|
|
|
3028 __ srlx(dst_reg, 32, O7);
|
|
|
3029 __ or3 (dst_reg, O7, dst_reg);
|
|
|
3030 %}
|
|
|
3031
|
|
|
3032 enc_class enc_repl4b( iRegI src, iRegL dst ) %{
|
|
|
3033 MacroAssembler _masm(&cbuf);
|
|
|
3034 Register src_reg = reg_to_register_object($src$$reg);
|
|
|
3035 Register dst_reg = reg_to_register_object($dst$$reg);
|
|
|
3036 __ sll(src_reg, 24, dst_reg);
|
|
|
3037 __ srl(dst_reg, 8, O7);
|
|
|
3038 __ or3(dst_reg, O7, dst_reg);
|
|
|
3039 __ srl(dst_reg, 16, O7);
|
|
|
3040 __ or3(dst_reg, O7, dst_reg);
|
|
|
3041 %}
|
|
|
3042
|
|
|
3043 enc_class enc_repl4s( iRegI src, iRegL dst ) %{
|
|
|
3044 MacroAssembler _masm(&cbuf);
|
|
|
3045 Register src_reg = reg_to_register_object($src$$reg);
|
|
|
3046 Register dst_reg = reg_to_register_object($dst$$reg);
|
|
|
3047 __ sllx(src_reg, 48, dst_reg);
|
|
|
3048 __ srlx(dst_reg, 16, O7);
|
|
|
3049 __ or3 (dst_reg, O7, dst_reg);
|
|
|
3050 __ srlx(dst_reg, 32, O7);
|
|
|
3051 __ or3 (dst_reg, O7, dst_reg);
|
|
|
3052 %}
|
|
|
3053
|
|
|
3054 enc_class enc_repl2i( iRegI src, iRegL dst ) %{
|
|
|
3055 MacroAssembler _masm(&cbuf);
|
|
|
3056 Register src_reg = reg_to_register_object($src$$reg);
|
|
|
3057 Register dst_reg = reg_to_register_object($dst$$reg);
|
|
|
3058 __ sllx(src_reg, 32, dst_reg);
|
|
|
3059 __ srlx(dst_reg, 32, O7);
|
|
|
3060 __ or3 (dst_reg, O7, dst_reg);
|
|
|
3061 %}
|
|
|
3062
|
|
|
3063 %}
|
|
|
3064
|
|
|
3065 //----------FRAME--------------------------------------------------------------
|
|
|
3066 // Definition of frame structure and management information.
|
|
|
3067 //
|
|
|
3068 // S T A C K L A Y O U T Allocators stack-slot number
|
|
|
3069 // | (to get allocators register number
|
|
|
3070 // G Owned by | | v add VMRegImpl::stack0)
|
|
|
3071 // r CALLER | |
|
|
|
3072 // o | +--------+ pad to even-align allocators stack-slot
|
|
|
3073 // w V | pad0 | numbers; owned by CALLER
|
|
|
3074 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
|
|
|
3075 // h ^ | in | 5
|
|
|
3076 // | | args | 4 Holes in incoming args owned by SELF
|
|
|
3077 // | | | | 3
|
|
|
3078 // | | +--------+
|
|
|
3079 // V | | old out| Empty on Intel, window on Sparc
|
|
|
3080 // | old |preserve| Must be even aligned.
|
|
|
3081 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
|
|
|
3082 // | | in | 3 area for Intel ret address
|
|
|
3083 // Owned by |preserve| Empty on Sparc.
|
|
|
3084 // SELF +--------+
|
|
|
3085 // | | pad2 | 2 pad to align old SP
|
|
|
3086 // | +--------+ 1
|
|
|
3087 // | | locks | 0
|
|
|
3088 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
|
|
|
3089 // | | pad1 | 11 pad to align new SP
|
|
|
3090 // | +--------+
|
|
|
3091 // | | | 10
|
|
|
3092 // | | spills | 9 spills
|
|
|
3093 // V | | 8 (pad0 slot for callee)
|
|
|
3094 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
|
|
|
3095 // ^ | out | 7
|
|
|
3096 // | | args | 6 Holes in outgoing args owned by CALLEE
|
|
|
3097 // Owned by +--------+
|
|
|
3098 // CALLEE | new out| 6 Empty on Intel, window on Sparc
|
|
|
3099 // | new |preserve| Must be even-aligned.
|
|
|
3100 // | SP-+--------+----> Matcher::_new_SP, even aligned
|
|
|
3101 // | | |
|
|
|
3102 //
|
|
|
3103 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
|
|
|
3104 // known from SELF's arguments and the Java calling convention.
|
|
|
3105 // Region 6-7 is determined per call site.
|
|
|
3106 // Note 2: If the calling convention leaves holes in the incoming argument
|
|
|
3107 // area, those holes are owned by SELF. Holes in the outgoing area
|
|
|
3108 // are owned by the CALLEE. Holes should not be nessecary in the
|
|
|
3109 // incoming area, as the Java calling convention is completely under
|
|
|
3110 // the control of the AD file. Doubles can be sorted and packed to
|
|
|
3111 // avoid holes. Holes in the outgoing arguments may be nessecary for
|
|
|
3112 // varargs C calling conventions.
|
|
|
3113 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
|
|
|
3114 // even aligned with pad0 as needed.
|
|
|
3115 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
|
|
|
3116 // region 6-11 is even aligned; it may be padded out more so that
|
|
|
3117 // the region from SP to FP meets the minimum stack alignment.
|
|
|
3118
|
|
|
3119 frame %{
|
|
|
3120 // What direction does stack grow in (assumed to be same for native & Java)
|
|
|
3121 stack_direction(TOWARDS_LOW);
|
|
|
3122
|
|
|
3123 // These two registers define part of the calling convention
|
|
|
3124 // between compiled code and the interpreter.
|
|
|
3125 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C
|
|
|
3126 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
|
|
|
3127
|
|
|
3128 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
|
|
|
3129 cisc_spilling_operand_name(indOffset);
|
|
|
3130
|
|
|
3131 // Number of stack slots consumed by a Monitor enter
|
|
|
3132 #ifdef _LP64
|
|
|
3133 sync_stack_slots(2);
|
|
|
3134 #else
|
|
|
3135 sync_stack_slots(1);
|
|
|
3136 #endif
|
|
|
3137
|
|
|
3138 // Compiled code's Frame Pointer
|
|
|
3139 frame_pointer(R_SP);
|
|
|
3140
|
|
|
3141 // Stack alignment requirement
|
|
|
3142 stack_alignment(StackAlignmentInBytes);
|
|
|
3143 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
|
|
|
3144 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
|
|
|
3145
|
|
|
3146 // Number of stack slots between incoming argument block and the start of
|
|
|
3147 // a new frame. The PROLOG must add this many slots to the stack. The
|
|
|
3148 // EPILOG must remove this many slots.
|
|
|
3149 in_preserve_stack_slots(0);
|
|
|
3150
|
|
|
3151 // Number of outgoing stack slots killed above the out_preserve_stack_slots
|
|
|
3152 // for calls to C. Supports the var-args backing area for register parms.
|
|
|
3153 // ADLC doesn't support parsing expressions, so I folded the math by hand.
|
|
|
3154 #ifdef _LP64
|
|
|
3155 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
|
|
|
3156 varargs_C_out_slots_killed(12);
|
|
|
3157 #else
|
|
|
3158 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
|
|
|
3159 varargs_C_out_slots_killed( 7);
|
|
|
3160 #endif
|
|
|
3161
|
|
|
3162 // The after-PROLOG location of the return address. Location of
|
|
|
3163 // return address specifies a type (REG or STACK) and a number
|
|
|
3164 // representing the register number (i.e. - use a register name) or
|
|
|
3165 // stack slot.
|
|
|
3166 return_addr(REG R_I7); // Ret Addr is in register I7
|
|
|
3167
|
|
|
3168 // Body of function which returns an OptoRegs array locating
|
|
|
3169 // arguments either in registers or in stack slots for calling
|
|
|
3170 // java
|
|
|
3171 calling_convention %{
|
|
|
3172 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
|
|
|
3173
|
|
|
3174 %}
|
|
|
3175
|
|
|
3176 // Body of function which returns an OptoRegs array locating
|
|
|
3177 // arguments either in registers or in stack slots for callin
|
|
|
3178 // C.
|
|
|
3179 c_calling_convention %{
|
|
|
3180 // This is obviously always outgoing
|
|
|
3181 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
|
|
|
3182 %}
|
|
|
3183
|
|
|
3184 // Location of native (C/C++) and interpreter return values. This is specified to
|
|
|
3185 // be the same as Java. In the 32-bit VM, long values are actually returned from
|
|
|
3186 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
|
|
|
3187 // to and from the register pairs is done by the appropriate call and epilog
|
|
|
3188 // opcodes. This simplifies the register allocator.
|
|
|
3189 c_return_value %{
|
|
|
3190 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
|
|
|
3191 #ifdef _LP64
|
|
|
3192 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
|
|
|
3193 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
|
|
|
3194 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
|
|
|
3195 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
|
|
|
3196 #else // !_LP64
|
|
|
3197 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
|
|
|
3198 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
|
|
|
3199 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
|
|
|
3200 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
|
|
|
3201 #endif
|
|
|
3202 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
|
|
|
3203 (is_outgoing?lo_out:lo_in)[ideal_reg] );
|
|
|
3204 %}
|
|
|
3205
|
|
|
3206 // Location of compiled Java return values. Same as C
|
|
|
3207 return_value %{
|
|
|
3208 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
|
|
|
3209 #ifdef _LP64
|
|
|
3210 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
|
|
|
3211 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
|
|
|
3212 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
|
|
|
3213 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
|
|
|
3214 #else // !_LP64
|
|
|
3215 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
|
|
|
3216 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
|
|
|
3217 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
|
|
|
3218 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
|
|
|
3219 #endif
|
|
|
3220 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
|
|
|
3221 (is_outgoing?lo_out:lo_in)[ideal_reg] );
|
|
|
3222 %}
|
|
|
3223
|
|
|
3224 %}
|
|
|
3225
|
|
|
3226
|
|
|
3227 //----------ATTRIBUTES---------------------------------------------------------
|
|
|
3228 //----------Operand Attributes-------------------------------------------------
|
|
|
3229 op_attrib op_cost(1); // Required cost attribute
|
|
|
3230
|
|
|
3231 //----------Instruction Attributes---------------------------------------------
|
|
|
3232 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
|
|
|
3233 ins_attrib ins_size(32); // Required size attribute (in bits)
|
|
|
3234 ins_attrib ins_pc_relative(0); // Required PC Relative flag
|
|
|
3235 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
|
|
|
3236 // non-matching short branch variant of some
|
|
|
3237 // long branch?
|
|
|
3238
|
|
|
3239 //----------OPERANDS-----------------------------------------------------------
|
|
|
3240 // Operand definitions must precede instruction definitions for correct parsing
|
|
|
3241 // in the ADLC because operands constitute user defined types which are used in
|
|
|
3242 // instruction definitions.
|
|
|
3243
|
|
|
3244 //----------Simple Operands----------------------------------------------------
|
|
|
3245 // Immediate Operands
|
|
|
3246 // Integer Immediate: 32-bit
|
|
|
3247 operand immI() %{
|
|
|
3248 match(ConI);
|
|
|
3249
|
|
|
3250 op_cost(0);
|
|
|
3251 // formats are generated automatically for constants and base registers
|
|
|
3252 format %{ %}
|
|
|
3253 interface(CONST_INTER);
|
|
|
3254 %}
|
|
|
3255
|
|
|
3256 // Integer Immediate: 13-bit
|
|
|
3257 operand immI13() %{
|
|
|
3258 predicate(Assembler::is_simm13(n->get_int()));
|
|
|
3259 match(ConI);
|
|
|
3260 op_cost(0);
|
|
|
3261
|
|
|
3262 format %{ %}
|
|
|
3263 interface(CONST_INTER);
|
|
|
3264 %}
|
|
|
3265
|
|
|
3266 // Unsigned (positive) Integer Immediate: 13-bit
|
|
|
3267 operand immU13() %{
|
|
|
3268 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
|
|
|
3269 match(ConI);
|
|
|
3270 op_cost(0);
|
|
|
3271
|
|
|
3272 format %{ %}
|
|
|
3273 interface(CONST_INTER);
|
|
|
3274 %}
|
|
|
3275
|
|
|
3276 // Integer Immediate: 6-bit
|
|
|
3277 operand immU6() %{
|
|
|
3278 predicate(n->get_int() >= 0 && n->get_int() <= 63);
|
|
|
3279 match(ConI);
|
|
|
3280 op_cost(0);
|
|
|
3281 format %{ %}
|
|
|
3282 interface(CONST_INTER);
|
|
|
3283 %}
|
|
|
3284
|
|
|
3285 // Integer Immediate: 11-bit
|
|
|
3286 operand immI11() %{
|
|
|
3287 predicate(Assembler::is_simm(n->get_int(),11));
|
|
|
3288 match(ConI);
|
|
|
3289 op_cost(0);
|
|
|
3290 format %{ %}
|
|
|
3291 interface(CONST_INTER);
|
|
|
3292 %}
|
|
|
3293
|
|
|
3294 // Integer Immediate: 0-bit
|
|
|
3295 operand immI0() %{
|
|
|
3296 predicate(n->get_int() == 0);
|
|
|
3297 match(ConI);
|
|
|
3298 op_cost(0);
|
|
|
3299
|
|
|
3300 format %{ %}
|
|
|
3301 interface(CONST_INTER);
|
|
|
3302 %}
|
|
|
3303
|
|
|
3304 // Integer Immediate: the value 10
|
|
|
3305 operand immI10() %{
|
|
|
3306 predicate(n->get_int() == 10);
|
|
|
3307 match(ConI);
|
|
|
3308 op_cost(0);
|
|
|
3309
|
|
|
3310 format %{ %}
|
|
|
3311 interface(CONST_INTER);
|
|
|
3312 %}
|
|
|
3313
|
|
|
3314 // Integer Immediate: the values 0-31
|
|
|
3315 operand immU5() %{
|
|
|
3316 predicate(n->get_int() >= 0 && n->get_int() <= 31);
|
|
|
3317 match(ConI);
|
|
|
3318 op_cost(0);
|
|
|
3319
|
|
|
3320 format %{ %}
|
|
|
3321 interface(CONST_INTER);
|
|
|
3322 %}
|
|
|
3323
|
|
|
3324 // Integer Immediate: the values 1-31
|
|
|
3325 operand immI_1_31() %{
|
|
|
3326 predicate(n->get_int() >= 1 && n->get_int() <= 31);
|
|
|
3327 match(ConI);
|
|
|
3328 op_cost(0);
|
|
|
3329
|
|
|
3330 format %{ %}
|
|
|
3331 interface(CONST_INTER);
|
|
|
3332 %}
|
|
|
3333
|
|
|
3334 // Integer Immediate: the values 32-63
|
|
|
3335 operand immI_32_63() %{
|
|
|
3336 predicate(n->get_int() >= 32 && n->get_int() <= 63);
|
|
|
3337 match(ConI);
|
|
|
3338 op_cost(0);
|
|
|
3339
|
|
|
3340 format %{ %}
|
|
|
3341 interface(CONST_INTER);
|
|
|
3342 %}
|
|
|
3343
|
|
|
3344 // Integer Immediate: the value 255
|
|
|
3345 operand immI_255() %{
|
|
|
3346 predicate( n->get_int() == 255 );
|
|
|
3347 match(ConI);
|
|
|
3348 op_cost(0);
|
|
|
3349
|
|
|
3350 format %{ %}
|
|
|
3351 interface(CONST_INTER);
|
|
|
3352 %}
|
|
|
3353
|
|
|
3354 // Long Immediate: the value FF
|
|
|
3355 operand immL_FF() %{
|
|
|
3356 predicate( n->get_long() == 0xFFL );
|
|
|
3357 match(ConL);
|
|
|
3358 op_cost(0);
|
|
|
3359
|
|
|
3360 format %{ %}
|
|
|
3361 interface(CONST_INTER);
|
|
|
3362 %}
|
|
|
3363
|
|
|
3364 // Long Immediate: the value FFFF
|
|
|
3365 operand immL_FFFF() %{
|
|
|
3366 predicate( n->get_long() == 0xFFFFL );
|
|
|
3367 match(ConL);
|
|
|
3368 op_cost(0);
|
|
|
3369
|
|
|
3370 format %{ %}
|
|
|
3371 interface(CONST_INTER);
|
|
|
3372 %}
|
|
|
3373
|
|
|
3374 // Pointer Immediate: 32 or 64-bit
|
|
|
3375 operand immP() %{
|
|
|
3376 match(ConP);
|
|
|
3377
|
|
|
3378 op_cost(5);
|
|
|
3379 // formats are generated automatically for constants and base registers
|
|
|
3380 format %{ %}
|
|
|
3381 interface(CONST_INTER);
|
|
|
3382 %}
|
|
|
3383
|
|
|
3384 operand immP13() %{
|
|
|
3385 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
|
|
|
3386 match(ConP);
|
|
|
3387 op_cost(0);
|
|
|
3388
|
|
|
3389 format %{ %}
|
|
|
3390 interface(CONST_INTER);
|
|
|
3391 %}
|
|
|
3392
|
|
|
3393 operand immP0() %{
|
|
|
3394 predicate(n->get_ptr() == 0);
|
|
|
3395 match(ConP);
|
|
|
3396 op_cost(0);
|
|
|
3397
|
|
|
3398 format %{ %}
|
|
|
3399 interface(CONST_INTER);
|
|
|
3400 %}
|
|
|
3401
|
|
|
3402 operand immP_poll() %{
|
|
|
3403 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
|
|
|
3404 match(ConP);
|
|
|
3405
|
|
|
3406 // formats are generated automatically for constants and base registers
|
|
|
3407 format %{ %}
|
|
|
3408 interface(CONST_INTER);
|
|
|
3409 %}
|
|
|
3410
|
|
|
3411 operand immL() %{
|
|
|
3412 match(ConL);
|
|
|
3413 op_cost(40);
|
|
|
3414 // formats are generated automatically for constants and base registers
|
|
|
3415 format %{ %}
|
|
|
3416 interface(CONST_INTER);
|
|
|
3417 %}
|
|
|
3418
|
|
|
3419 operand immL0() %{
|
|
|
3420 predicate(n->get_long() == 0L);
|
|
|
3421 match(ConL);
|
|
|
3422 op_cost(0);
|
|
|
3423 // formats are generated automatically for constants and base registers
|
|
|
3424 format %{ %}
|
|
|
3425 interface(CONST_INTER);
|
|
|
3426 %}
|
|
|
3427
|
|
|
3428 // Long Immediate: 13-bit
|
|
|
3429 operand immL13() %{
|
|
|
3430 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
|
|
|
3431 match(ConL);
|
|
|
3432 op_cost(0);
|
|
|
3433
|
|
|
3434 format %{ %}
|
|
|
3435 interface(CONST_INTER);
|
|
|
3436 %}
|
|
|
3437
|
|
|
3438 // Long Immediate: low 32-bit mask
|
|
|
3439 operand immL_32bits() %{
|
|
|
3440 predicate(n->get_long() == 0xFFFFFFFFL);
|
|
|
3441 match(ConL);
|
|
|
3442 op_cost(0);
|
|
|
3443
|
|
|
3444 format %{ %}
|
|
|
3445 interface(CONST_INTER);
|
|
|
3446 %}
|
|
|
3447
|
|
|
3448 // Double Immediate
|
|
|
3449 operand immD() %{
|
|
|
3450 match(ConD);
|
|
|
3451
|
|
|
3452 op_cost(40);
|
|
|
3453 format %{ %}
|
|
|
3454 interface(CONST_INTER);
|
|
|
3455 %}
|
|
|
3456
|
|
|
3457 operand immD0() %{
|
|
|
3458 #ifdef _LP64
|
|
|
3459 // on 64-bit architectures this comparision is faster
|
|
|
3460 predicate(jlong_cast(n->getd()) == 0);
|
|
|
3461 #else
|
|
|
3462 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
|
|
|
3463 #endif
|
|
|
3464 match(ConD);
|
|
|
3465
|
|
|
3466 op_cost(0);
|
|
|
3467 format %{ %}
|
|
|
3468 interface(CONST_INTER);
|
|
|
3469 %}
|
|
|
3470
|
|
|
3471 // Float Immediate
|
|
|
3472 operand immF() %{
|
|
|
3473 match(ConF);
|
|
|
3474
|
|
|
3475 op_cost(20);
|
|
|
3476 format %{ %}
|
|
|
3477 interface(CONST_INTER);
|
|
|
3478 %}
|
|
|
3479
|
|
|
3480 // Float Immediate: 0
|
|
|
3481 operand immF0() %{
|
|
|
3482 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
|
|
|
3483 match(ConF);
|
|
|
3484
|
|
|
3485 op_cost(0);
|
|
|
3486 format %{ %}
|
|
|
3487 interface(CONST_INTER);
|
|
|
3488 %}
|
|
|
3489
|
|
|
3490 // Integer Register Operands
|
|
|
3491 // Integer Register
|
|
|
3492 operand iRegI() %{
|
|
|
3493 constraint(ALLOC_IN_RC(int_reg));
|
|
|
3494 match(RegI);
|
|
|
3495
|
|
|
3496 match(notemp_iRegI);
|
|
|
3497 match(g1RegI);
|
|
|
3498 match(o0RegI);
|
|
|
3499 match(iRegIsafe);
|
|
|
3500
|
|
|
3501 format %{ %}
|
|
|
3502 interface(REG_INTER);
|
|
|
3503 %}
|
|
|
3504
|
|
|
3505 operand notemp_iRegI() %{
|
|
|
3506 constraint(ALLOC_IN_RC(notemp_int_reg));
|
|
|
3507 match(RegI);
|
|
|
3508
|
|
|
3509 match(o0RegI);
|
|
|
3510
|
|
|
3511 format %{ %}
|
|
|
3512 interface(REG_INTER);
|
|
|
3513 %}
|
|
|
3514
|
|
|
3515 operand o0RegI() %{
|
|
|
3516 constraint(ALLOC_IN_RC(o0_regI));
|
|
|
3517 match(iRegI);
|
|
|
3518
|
|
|
3519 format %{ %}
|
|
|
3520 interface(REG_INTER);
|
|
|
3521 %}
|
|
|
3522
|
|
|
3523 // Pointer Register
|
|
|
3524 operand iRegP() %{
|
|
|
3525 constraint(ALLOC_IN_RC(ptr_reg));
|
|
|
3526 match(RegP);
|
|
|
3527
|
|
|
3528 match(lock_ptr_RegP);
|
|
|
3529 match(g1RegP);
|
|
|
3530 match(g2RegP);
|
|
|
3531 match(g3RegP);
|
|
|
3532 match(g4RegP);
|
|
|
3533 match(i0RegP);
|
|
|
3534 match(o0RegP);
|
|
|
3535 match(o1RegP);
|
|
|
3536 match(l7RegP);
|
|
|
3537
|
|
|
3538 format %{ %}
|
|
|
3539 interface(REG_INTER);
|
|
|
3540 %}
|
|
|
3541
|
|
|
3542 operand sp_ptr_RegP() %{
|
|
|
3543 constraint(ALLOC_IN_RC(sp_ptr_reg));
|
|
|
3544 match(RegP);
|
|
|
3545 match(iRegP);
|
|
|
3546
|
|
|
3547 format %{ %}
|
|
|
3548 interface(REG_INTER);
|
|
|
3549 %}
|
|
|
3550
|
|
|
3551 operand lock_ptr_RegP() %{
|
|
|
3552 constraint(ALLOC_IN_RC(lock_ptr_reg));
|
|
|
3553 match(RegP);
|
|
|
3554 match(i0RegP);
|
|
|
3555 match(o0RegP);
|
|
|
3556 match(o1RegP);
|
|
|
3557 match(l7RegP);
|
|
|
3558
|
|
|
3559 format %{ %}
|
|
|
3560 interface(REG_INTER);
|
|
|
3561 %}
|
|
|
3562
|
|
|
3563 operand g1RegP() %{
|
|
|
3564 constraint(ALLOC_IN_RC(g1_regP));
|
|
|
3565 match(iRegP);
|
|
|
3566
|
|
|
3567 format %{ %}
|
|
|
3568 interface(REG_INTER);
|
|
|
3569 %}
|
|
|
3570
|
|
|
3571 operand g2RegP() %{
|
|
|
3572 constraint(ALLOC_IN_RC(g2_regP));
|
|
|
3573 match(iRegP);
|
|
|
3574
|
|
|
3575 format %{ %}
|
|
|
3576 interface(REG_INTER);
|
|
|
3577 %}
|
|
|
3578
|
|
|
3579 operand g3RegP() %{
|
|
|
3580 constraint(ALLOC_IN_RC(g3_regP));
|
|
|
3581 match(iRegP);
|
|
|
3582
|
|
|
3583 format %{ %}
|
|
|
3584 interface(REG_INTER);
|
|
|
3585 %}
|
|
|
3586
|
|
|
3587 operand g1RegI() %{
|
|
|
3588 constraint(ALLOC_IN_RC(g1_regI));
|
|
|
3589 match(iRegI);
|
|
|
3590
|
|
|
3591 format %{ %}
|
|
|
3592 interface(REG_INTER);
|
|
|
3593 %}
|
|
|
3594
|
|
|
3595 operand g3RegI() %{
|
|
|
3596 constraint(ALLOC_IN_RC(g3_regI));
|
|
|
3597 match(iRegI);
|
|
|
3598
|
|
|
3599 format %{ %}
|
|
|
3600 interface(REG_INTER);
|
|
|
3601 %}
|
|
|
3602
|
|
|
3603 operand g4RegI() %{
|
|
|
3604 constraint(ALLOC_IN_RC(g4_regI));
|
|
|
3605 match(iRegI);
|
|
|
3606
|
|
|
3607 format %{ %}
|
|
|
3608 interface(REG_INTER);
|
|
|
3609 %}
|
|
|
3610
|
|
|
3611 operand g4RegP() %{
|
|
|
3612 constraint(ALLOC_IN_RC(g4_regP));
|
|
|
3613 match(iRegP);
|
|
|
3614
|
|
|
3615 format %{ %}
|
|
|
3616 interface(REG_INTER);
|
|
|
3617 %}
|
|
|
3618
|
|
|
3619 operand i0RegP() %{
|
|
|
3620 constraint(ALLOC_IN_RC(i0_regP));
|
|
|
3621 match(iRegP);
|
|
|
3622
|
|
|
3623 format %{ %}
|
|
|
3624 interface(REG_INTER);
|
|
|
3625 %}
|
|
|
3626
|
|
|
3627 operand o0RegP() %{
|
|
|
3628 constraint(ALLOC_IN_RC(o0_regP));
|
|
|
3629 match(iRegP);
|
|
|
3630
|
|
|
3631 format %{ %}
|
|
|
3632 interface(REG_INTER);
|
|
|
3633 %}
|
|
|
3634
|
|
|
3635 operand o1RegP() %{
|
|
|
3636 constraint(ALLOC_IN_RC(o1_regP));
|
|
|
3637 match(iRegP);
|
|
|
3638
|
|
|
3639 format %{ %}
|
|
|
3640 interface(REG_INTER);
|
|
|
3641 %}
|
|
|
3642
|
|
|
3643 operand o2RegP() %{
|
|
|
3644 constraint(ALLOC_IN_RC(o2_regP));
|
|
|
3645 match(iRegP);
|
|
|
3646
|
|
|
3647 format %{ %}
|
|
|
3648 interface(REG_INTER);
|
|
|
3649 %}
|
|
|
3650
|
|
|
3651 operand o7RegP() %{
|
|
|
3652 constraint(ALLOC_IN_RC(o7_regP));
|
|
|
3653 match(iRegP);
|
|
|
3654
|
|
|
3655 format %{ %}
|
|
|
3656 interface(REG_INTER);
|
|
|
3657 %}
|
|
|
3658
|
|
|
3659 operand l7RegP() %{
|
|
|
3660 constraint(ALLOC_IN_RC(l7_regP));
|
|
|
3661 match(iRegP);
|
|
|
3662
|
|
|
3663 format %{ %}
|
|
|
3664 interface(REG_INTER);
|
|
|
3665 %}
|
|
|
3666
|
|
|
3667 operand o7RegI() %{
|
|
|
3668 constraint(ALLOC_IN_RC(o7_regI));
|
|
|
3669 match(iRegI);
|
|
|
3670
|
|
|
3671 format %{ %}
|
|
|
3672 interface(REG_INTER);
|
|
|
3673 %}
|
|
|
3674
|
|
|
3675 // Long Register
|
|
|
3676 operand iRegL() %{
|
|
|
3677 constraint(ALLOC_IN_RC(long_reg));
|
|
|
3678 match(RegL);
|
|
|
3679
|
|
|
3680 format %{ %}
|
|
|
3681 interface(REG_INTER);
|
|
|
3682 %}
|
|
|
3683
|
|
|
3684 operand o2RegL() %{
|
|
|
3685 constraint(ALLOC_IN_RC(o2_regL));
|
|
|
3686 match(iRegL);
|
|
|
3687
|
|
|
3688 format %{ %}
|
|
|
3689 interface(REG_INTER);
|
|
|
3690 %}
|
|
|
3691
|
|
|
3692 operand o7RegL() %{
|
|
|
3693 constraint(ALLOC_IN_RC(o7_regL));
|
|
|
3694 match(iRegL);
|
|
|
3695
|
|
|
3696 format %{ %}
|
|
|
3697 interface(REG_INTER);
|
|
|
3698 %}
|
|
|
3699
|
|
|
3700 operand g1RegL() %{
|
|
|
3701 constraint(ALLOC_IN_RC(g1_regL));
|
|
|
3702 match(iRegL);
|
|
|
3703
|
|
|
3704 format %{ %}
|
|
|
3705 interface(REG_INTER);
|
|
|
3706 %}
|
|
|
3707
|
|
|
3708 // Int Register safe
|
|
|
3709 // This is 64bit safe
|
|
|
3710 operand iRegIsafe() %{
|
|
|
3711 constraint(ALLOC_IN_RC(long_reg));
|
|
|
3712
|
|
|
3713 match(iRegI);
|
|
|
3714
|
|
|
3715 format %{ %}
|
|
|
3716 interface(REG_INTER);
|
|
|
3717 %}
|
|
|
3718
|
|
|
3719 // Condition Code Flag Register
|
|
|
3720 operand flagsReg() %{
|
|
|
3721 constraint(ALLOC_IN_RC(int_flags));
|
|
|
3722 match(RegFlags);
|
|
|
3723
|
|
|
3724 format %{ "ccr" %} // both ICC and XCC
|
|
|
3725 interface(REG_INTER);
|
|
|
3726 %}
|
|
|
3727
|
|
|
3728 // Condition Code Register, unsigned comparisons.
|
|
|
3729 operand flagsRegU() %{
|
|
|
3730 constraint(ALLOC_IN_RC(int_flags));
|
|
|
3731 match(RegFlags);
|
|
|
3732
|
|
|
3733 format %{ "icc_U" %}
|
|
|
3734 interface(REG_INTER);
|
|
|
3735 %}
|
|
|
3736
|
|
|
3737 // Condition Code Register, pointer comparisons.
|
|
|
3738 operand flagsRegP() %{
|
|
|
3739 constraint(ALLOC_IN_RC(int_flags));
|
|
|
3740 match(RegFlags);
|
|
|
3741
|
|
|
3742 #ifdef _LP64
|
|
|
3743 format %{ "xcc_P" %}
|
|
|
3744 #else
|
|
|
3745 format %{ "icc_P" %}
|
|
|
3746 #endif
|
|
|
3747 interface(REG_INTER);
|
|
|
3748 %}
|
|
|
3749
|
|
|
3750 // Condition Code Register, long comparisons.
|
|
|
3751 operand flagsRegL() %{
|
|
|
3752 constraint(ALLOC_IN_RC(int_flags));
|
|
|
3753 match(RegFlags);
|
|
|
3754
|
|
|
3755 format %{ "xcc_L" %}
|
|
|
3756 interface(REG_INTER);
|
|
|
3757 %}
|
|
|
3758
|
|
|
3759 // Condition Code Register, floating comparisons, unordered same as "less".
|
|
|
3760 operand flagsRegF() %{
|
|
|
3761 constraint(ALLOC_IN_RC(float_flags));
|
|
|
3762 match(RegFlags);
|
|
|
3763 match(flagsRegF0);
|
|
|
3764
|
|
|
3765 format %{ %}
|
|
|
3766 interface(REG_INTER);
|
|
|
3767 %}
|
|
|
3768
|
|
|
3769 operand flagsRegF0() %{
|
|
|
3770 constraint(ALLOC_IN_RC(float_flag0));
|
|
|
3771 match(RegFlags);
|
|
|
3772
|
|
|
3773 format %{ %}
|
|
|
3774 interface(REG_INTER);
|
|
|
3775 %}
|
|
|
3776
|
|
|
3777
|
|
|
3778 // Condition Code Flag Register used by long compare
|
|
|
3779 operand flagsReg_long_LTGE() %{
|
|
|
3780 constraint(ALLOC_IN_RC(int_flags));
|
|
|
3781 match(RegFlags);
|
|
|
3782 format %{ "icc_LTGE" %}
|
|
|
3783 interface(REG_INTER);
|
|
|
3784 %}
|
|
|
3785 operand flagsReg_long_EQNE() %{
|
|
|
3786 constraint(ALLOC_IN_RC(int_flags));
|
|
|
3787 match(RegFlags);
|
|
|
3788 format %{ "icc_EQNE" %}
|
|
|
3789 interface(REG_INTER);
|
|
|
3790 %}
|
|
|
3791 operand flagsReg_long_LEGT() %{
|
|
|
3792 constraint(ALLOC_IN_RC(int_flags));
|
|
|
3793 match(RegFlags);
|
|
|
3794 format %{ "icc_LEGT" %}
|
|
|
3795 interface(REG_INTER);
|
|
|
3796 %}
|
|
|
3797
|
|
|
3798
|
|
|
3799 operand regD() %{
|
|
|
3800 constraint(ALLOC_IN_RC(dflt_reg));
|
|
|
3801 match(RegD);
|
|
|
3802
|
|
|
3803 format %{ %}
|
|
|
3804 interface(REG_INTER);
|
|
|
3805 %}
|
|
|
3806
|
|
|
3807 operand regF() %{
|
|
|
3808 constraint(ALLOC_IN_RC(sflt_reg));
|
|
|
3809 match(RegF);
|
|
|
3810
|
|
|
3811 format %{ %}
|
|
|
3812 interface(REG_INTER);
|
|
|
3813 %}
|
|
|
3814
|
|
|
3815 operand regD_low() %{
|
|
|
3816 constraint(ALLOC_IN_RC(dflt_low_reg));
|
|
|
3817 match(RegD);
|
|
|
3818
|
|
|
3819 format %{ %}
|
|
|
3820 interface(REG_INTER);
|
|
|
3821 %}
|
|
|
3822
|
|
|
3823 // Special Registers
|
|
|
3824
|
|
|
3825 // Method Register
|
|
|
3826 operand inline_cache_regP(iRegP reg) %{
|
|
|
3827 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
|
|
|
3828 match(reg);
|
|
|
3829 format %{ %}
|
|
|
3830 interface(REG_INTER);
|
|
|
3831 %}
|
|
|
3832
|
|
|
3833 operand interpreter_method_oop_regP(iRegP reg) %{
|
|
|
3834 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
|
|
|
3835 match(reg);
|
|
|
3836 format %{ %}
|
|
|
3837 interface(REG_INTER);
|
|
|
3838 %}
|
|
|
3839
|
|
|
3840
|
|
|
3841 //----------Complex Operands---------------------------------------------------
|
|
|
3842 // Indirect Memory Reference
|
|
|
3843 operand indirect(sp_ptr_RegP reg) %{
|
|
|
3844 constraint(ALLOC_IN_RC(sp_ptr_reg));
|
|
|
3845 match(reg);
|
|
|
3846
|
|
|
3847 op_cost(100);
|
|
|
3848 format %{ "[$reg]" %}
|
|
|
3849 interface(MEMORY_INTER) %{
|
|
|
3850 base($reg);
|
|
|
3851 index(0x0);
|
|
|
3852 scale(0x0);
|
|
|
3853 disp(0x0);
|
|
|
3854 %}
|
|
|
3855 %}
|
|
|
3856
|
|
|
3857 // Indirect with Offset
|
|
|
3858 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
|
|
|
3859 constraint(ALLOC_IN_RC(sp_ptr_reg));
|
|
|
3860 match(AddP reg offset);
|
|
|
3861
|
|
|
3862 op_cost(100);
|
|
|
3863 format %{ "[$reg + $offset]" %}
|
|
|
3864 interface(MEMORY_INTER) %{
|
|
|
3865 base($reg);
|
|
|
3866 index(0x0);
|
|
|
3867 scale(0x0);
|
|
|
3868 disp($offset);
|
|
|
3869 %}
|
|
|
3870 %}
|
|
|
3871
|
|
|
3872 // Note: Intel has a swapped version also, like this:
|
|
|
3873 //operand indOffsetX(iRegI reg, immP offset) %{
|
|
|
3874 // constraint(ALLOC_IN_RC(int_reg));
|
|
|
3875 // match(AddP offset reg);
|
|
|
3876 //
|
|
|
3877 // op_cost(100);
|
|
|
3878 // format %{ "[$reg + $offset]" %}
|
|
|
3879 // interface(MEMORY_INTER) %{
|
|
|
3880 // base($reg);
|
|
|
3881 // index(0x0);
|
|
|
3882 // scale(0x0);
|
|
|
3883 // disp($offset);
|
|
|
3884 // %}
|
|
|
3885 //%}
|
|
|
3886 //// However, it doesn't make sense for SPARC, since
|
|
|
3887 // we have no particularly good way to embed oops in
|
|
|
3888 // single instructions.
|
|
|
3889
|
|
|
3890 // Indirect with Register Index
|
|
|
3891 operand indIndex(iRegP addr, iRegX index) %{
|
|
|
3892 constraint(ALLOC_IN_RC(ptr_reg));
|
|
|
3893 match(AddP addr index);
|
|
|
3894
|
|
|
3895 op_cost(100);
|
|
|
3896 format %{ "[$addr + $index]" %}
|
|
|
3897 interface(MEMORY_INTER) %{
|
|
|
3898 base($addr);
|
|
|
3899 index($index);
|
|
|
3900 scale(0x0);
|
|
|
3901 disp(0x0);
|
|
|
3902 %}
|
|
|
3903 %}
|
|
|
3904
|
|
|
3905 //----------Special Memory Operands--------------------------------------------
|
|
|
3906 // Stack Slot Operand - This operand is used for loading and storing temporary
|
|
|
3907 // values on the stack where a match requires a value to
|
|
|
3908 // flow through memory.
|
|
|
3909 operand stackSlotI(sRegI reg) %{
|
|
|
3910 constraint(ALLOC_IN_RC(stack_slots));
|
|
|
3911 op_cost(100);
|
|
|
3912 //match(RegI);
|
|
|
3913 format %{ "[$reg]" %}
|
|
|
3914 interface(MEMORY_INTER) %{
|
|
|
3915 base(0xE); // R_SP
|
|
|
3916 index(0x0);
|
|
|
3917 scale(0x0);
|
|
|
3918 disp($reg); // Stack Offset
|
|
|
3919 %}
|
|
|
3920 %}
|
|
|
3921
|
|
|
3922 operand stackSlotP(sRegP reg) %{
|
|
|
3923 constraint(ALLOC_IN_RC(stack_slots));
|
|
|
3924 op_cost(100);
|
|
|
3925 //match(RegP);
|
|
|
3926 format %{ "[$reg]" %}
|
|
|
3927 interface(MEMORY_INTER) %{
|
|
|
3928 base(0xE); // R_SP
|
|
|
3929 index(0x0);
|
|
|
3930 scale(0x0);
|
|
|
3931 disp($reg); // Stack Offset
|
|
|
3932 %}
|
|
|
3933 %}
|
|
|
3934
|
|
|
3935 operand stackSlotF(sRegF reg) %{
|
|
|
3936 constraint(ALLOC_IN_RC(stack_slots));
|
|
|
3937 op_cost(100);
|
|
|
3938 //match(RegF);
|
|
|
3939 format %{ "[$reg]" %}
|
|
|
3940 interface(MEMORY_INTER) %{
|
|
|
3941 base(0xE); // R_SP
|
|
|
3942 index(0x0);
|
|
|
3943 scale(0x0);
|
|
|
3944 disp($reg); // Stack Offset
|
|
|
3945 %}
|
|
|
3946 %}
|
|
|
3947 operand stackSlotD(sRegD reg) %{
|
|
|
3948 constraint(ALLOC_IN_RC(stack_slots));
|
|
|
3949 op_cost(100);
|
|
|
3950 //match(RegD);
|
|
|
3951 format %{ "[$reg]" %}
|
|
|
3952 interface(MEMORY_INTER) %{
|
|
|
3953 base(0xE); // R_SP
|
|
|
3954 index(0x0);
|
|
|
3955 scale(0x0);
|
|
|
3956 disp($reg); // Stack Offset
|
|
|
3957 %}
|
|
|
3958 %}
|
|
|
3959 operand stackSlotL(sRegL reg) %{
|
|
|
3960 constraint(ALLOC_IN_RC(stack_slots));
|
|
|
3961 op_cost(100);
|
|
|
3962 //match(RegL);
|
|
|
3963 format %{ "[$reg]" %}
|
|
|
3964 interface(MEMORY_INTER) %{
|
|
|
3965 base(0xE); // R_SP
|
|
|
3966 index(0x0);
|
|
|
3967 scale(0x0);
|
|
|
3968 disp($reg); // Stack Offset
|
|
|
3969 %}
|
|
|
3970 %}
|
|
|
3971
|
|
|
3972 // Operands for expressing Control Flow
|
|
|
3973 // NOTE: Label is a predefined operand which should not be redefined in
|
|
|
3974 // the AD file. It is generically handled within the ADLC.
|
|
|
3975
|
|
|
3976 //----------Conditional Branch Operands----------------------------------------
|
|
|
3977 // Comparison Op - This is the operation of the comparison, and is limited to
|
|
|
3978 // the following set of codes:
|
|
|
3979 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
|
|
|
3980 //
|
|
|
3981 // Other attributes of the comparison, such as unsignedness, are specified
|
|
|
3982 // by the comparison instruction that sets a condition code flags register.
|
|
|
3983 // That result is represented by a flags operand whose subtype is appropriate
|
|
|
3984 // to the unsignedness (etc.) of the comparison.
|
|
|
3985 //
|
|
|
3986 // Later, the instruction which matches both the Comparison Op (a Bool) and
|
|
|
3987 // the flags (produced by the Cmp) specifies the coding of the comparison op
|
|
|
3988 // by matching a specific subtype of Bool operand below, such as cmpOpU.
|
|
|
3989
|
|
|
3990 operand cmpOp() %{
|
|
|
3991 match(Bool);
|
|
|
3992
|
|
|
3993 format %{ "" %}
|
|
|
3994 interface(COND_INTER) %{
|
|
|
3995 equal(0x1);
|
|
|
3996 not_equal(0x9);
|
|
|
3997 less(0x3);
|
|
|
3998 greater_equal(0xB);
|
|
|
3999 less_equal(0x2);
|
|
|
4000 greater(0xA);
|
|
|
4001 %}
|
|
|
4002 %}
|
|
|
4003
|
|
|
4004 // Comparison Op, unsigned
|
|
|
4005 operand cmpOpU() %{
|
|
|
4006 match(Bool);
|
|
|
4007
|
|
|
4008 format %{ "u" %}
|
|
|
4009 interface(COND_INTER) %{
|
|
|
4010 equal(0x1);
|
|
|
4011 not_equal(0x9);
|
|
|
4012 less(0x5);
|
|
|
4013 greater_equal(0xD);
|
|
|
4014 less_equal(0x4);
|
|
|
4015 greater(0xC);
|
|
|
4016 %}
|
|
|
4017 %}
|
|
|
4018
|
|
|
4019 // Comparison Op, pointer (same as unsigned)
|
|
|
4020 operand cmpOpP() %{
|
|
|
4021 match(Bool);
|
|
|
4022
|
|
|
4023 format %{ "p" %}
|
|
|
4024 interface(COND_INTER) %{
|
|
|
4025 equal(0x1);
|
|
|
4026 not_equal(0x9);
|
|
|
4027 less(0x5);
|
|
|
4028 greater_equal(0xD);
|
|
|
4029 less_equal(0x4);
|
|
|
4030 greater(0xC);
|
|
|
4031 %}
|
|
|
4032 %}
|
|
|
4033
|
|
|
4034 // Comparison Op, branch-register encoding
|
|
|
4035 operand cmpOp_reg() %{
|
|
|
4036 match(Bool);
|
|
|
4037
|
|
|
4038 format %{ "" %}
|
|
|
4039 interface(COND_INTER) %{
|
|
|
4040 equal (0x1);
|
|
|
4041 not_equal (0x5);
|
|
|
4042 less (0x3);
|
|
|
4043 greater_equal(0x7);
|
|
|
4044 less_equal (0x2);
|
|
|
4045 greater (0x6);
|
|
|
4046 %}
|
|
|
4047 %}
|
|
|
4048
|
|
|
4049 // Comparison Code, floating, unordered same as less
|
|
|
4050 operand cmpOpF() %{
|
|
|
4051 match(Bool);
|
|
|
4052
|
|
|
4053 format %{ "fl" %}
|
|
|
4054 interface(COND_INTER) %{
|
|
|
4055 equal(0x9);
|
|
|
4056 not_equal(0x1);
|
|
|
4057 less(0x3);
|
|
|
4058 greater_equal(0xB);
|
|
|
4059 less_equal(0xE);
|
|
|
4060 greater(0x6);
|
|
|
4061 %}
|
|
|
4062 %}
|
|
|
4063
|
|
|
4064 // Used by long compare
|
|
|
4065 operand cmpOp_commute() %{
|
|
|
4066 match(Bool);
|
|
|
4067
|
|
|
4068 format %{ "" %}
|
|
|
4069 interface(COND_INTER) %{
|
|
|
4070 equal(0x1);
|
|
|
4071 not_equal(0x9);
|
|
|
4072 less(0xA);
|
|
|
4073 greater_equal(0x2);
|
|
|
4074 less_equal(0xB);
|
|
|
4075 greater(0x3);
|
|
|
4076 %}
|
|
|
4077 %}
|
|
|
4078
|
|
|
4079 //----------OPERAND CLASSES----------------------------------------------------
|
|
|
4080 // Operand Classes are groups of operands that are used to simplify
|
|
|
4081 // instruction definitions by not requiring the AD writer to specify seperate
|
|
|
4082 // instructions for every form of operand when the instruction accepts
|
|
|
4083 // multiple operand types with the same basic encoding and format. The classic
|
|
|
4084 // case of this is memory operands.
|
|
|
4085 // Indirect is not included since its use is limited to Compare & Swap
|
|
|
4086 opclass memory( indirect, indOffset13, indIndex );
|
|
|
4087
|
|
|
4088 //----------PIPELINE-----------------------------------------------------------
|
|
|
4089 pipeline %{
|
|
|
4090
|
|
|
4091 //----------ATTRIBUTES---------------------------------------------------------
|
|
|
4092 attributes %{
|
|
|
4093 fixed_size_instructions; // Fixed size instructions
|
|
|
4094 branch_has_delay_slot; // Branch has delay slot following
|
|
|
4095 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
|
|
|
4096 instruction_unit_size = 4; // An instruction is 4 bytes long
|
|
|
4097 instruction_fetch_unit_size = 16; // The processor fetches one line
|
|
|
4098 instruction_fetch_units = 1; // of 16 bytes
|
|
|
4099
|
|
|
4100 // List of nop instructions
|
|
|
4101 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
|
|
|
4102 %}
|
|
|
4103
|
|
|
4104 //----------RESOURCES----------------------------------------------------------
|
|
|
4105 // Resources are the functional units available to the machine
|
|
|
4106 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
|
|
|
4107
|
|
|
4108 //----------PIPELINE DESCRIPTION-----------------------------------------------
|
|
|
4109 // Pipeline Description specifies the stages in the machine's pipeline
|
|
|
4110
|
|
|
4111 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
|
|
|
4112
|
|
|
4113 //----------PIPELINE CLASSES---------------------------------------------------
|
|
|
4114 // Pipeline Classes describe the stages in which input and output are
|
|
|
4115 // referenced by the hardware pipeline.
|
|
|
4116
|
|
|
4117 // Integer ALU reg-reg operation
|
|
|
4118 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
|
|
|
4119 single_instruction;
|
|
|
4120 dst : E(write);
|
|
|
4121 src1 : R(read);
|
|
|
4122 src2 : R(read);
|
|
|
4123 IALU : R;
|
|
|
4124 %}
|
|
|
4125
|
|
|
4126 // Integer ALU reg-reg long operation
|
|
|
4127 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
|
|
|
4128 instruction_count(2);
|
|
|
4129 dst : E(write);
|
|
|
4130 src1 : R(read);
|
|
|
4131 src2 : R(read);
|
|
|
4132 IALU : R;
|
|
|
4133 IALU : R;
|
|
|
4134 %}
|
|
|
4135
|
|
|
4136 // Integer ALU reg-reg long dependent operation
|
|
|
4137 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
|
|
|
4138 instruction_count(1); multiple_bundles;
|
|
|
4139 dst : E(write);
|
|
|
4140 src1 : R(read);
|
|
|
4141 src2 : R(read);
|
|
|
4142 cr : E(write);
|
|
|
4143 IALU : R(2);
|
|
|
4144 %}
|
|
|
4145
|
|
|
4146 // Integer ALU reg-imm operaion
|
|
|
4147 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
|
|
|
4148 single_instruction;
|
|
|
4149 dst : E(write);
|
|
|
4150 src1 : R(read);
|
|
|
4151 IALU : R;
|
|
|
4152 %}
|
|
|
4153
|
|
|
4154 // Integer ALU reg-reg operation with condition code
|
|
|
4155 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
|
|
|
4156 single_instruction;
|
|
|
4157 dst : E(write);
|
|
|
4158 cr : E(write);
|
|
|
4159 src1 : R(read);
|
|
|
4160 src2 : R(read);
|
|
|
4161 IALU : R;
|
|
|
4162 %}
|
|
|
4163
|
|
|
4164 // Integer ALU reg-imm operation with condition code
|
|
|
4165 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
|
|
|
4166 single_instruction;
|
|
|
4167 dst : E(write);
|
|
|
4168 cr : E(write);
|
|
|
4169 src1 : R(read);
|
|
|
4170 IALU : R;
|
|
|
4171 %}
|
|
|
4172
|
|
|
4173 // Integer ALU zero-reg operation
|
|
|
4174 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
|
|
|
4175 single_instruction;
|
|
|
4176 dst : E(write);
|
|
|
4177 src2 : R(read);
|
|
|
4178 IALU : R;
|
|
|
4179 %}
|
|
|
4180
|
|
|
4181 // Integer ALU zero-reg operation with condition code only
|
|
|
4182 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
|
|
|
4183 single_instruction;
|
|
|
4184 cr : E(write);
|
|
|
4185 src : R(read);
|
|
|
4186 IALU : R;
|
|
|
4187 %}
|
|
|
4188
|
|
|
4189 // Integer ALU reg-reg operation with condition code only
|
|
|
4190 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
|
|
|
4191 single_instruction;
|
|
|
4192 cr : E(write);
|
|
|
4193 src1 : R(read);
|
|
|
4194 src2 : R(read);
|
|
|
4195 IALU : R;
|
|
|
4196 %}
|
|
|
4197
|
|
|
4198 // Integer ALU reg-imm operation with condition code only
|
|
|
4199 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
|
|
|
4200 single_instruction;
|
|
|
4201 cr : E(write);
|
|
|
4202 src1 : R(read);
|
|
|
4203 IALU : R;
|
|
|
4204 %}
|
|
|
4205
|
|
|
4206 // Integer ALU reg-reg-zero operation with condition code only
|
|
|
4207 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
|
|
|
4208 single_instruction;
|
|
|
4209 cr : E(write);
|
|
|
4210 src1 : R(read);
|
|
|
4211 src2 : R(read);
|
|
|
4212 IALU : R;
|
|
|
4213 %}
|
|
|
4214
|
|
|
4215 // Integer ALU reg-imm-zero operation with condition code only
|
|
|
4216 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
|
|
|
4217 single_instruction;
|
|
|
4218 cr : E(write);
|
|
|
4219 src1 : R(read);
|
|
|
4220 IALU : R;
|
|
|
4221 %}
|
|
|
4222
|
|
|
4223 // Integer ALU reg-reg operation with condition code, src1 modified
|
|
|
4224 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
|
|
|
4225 single_instruction;
|
|
|
4226 cr : E(write);
|
|
|
4227 src1 : E(write);
|
|
|
4228 src1 : R(read);
|
|
|
4229 src2 : R(read);
|
|
|
4230 IALU : R;
|
|
|
4231 %}
|
|
|
4232
|
|
|
4233 // Integer ALU reg-imm operation with condition code, src1 modified
|
|
|
4234 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
|
|
|
4235 single_instruction;
|
|
|
4236 cr : E(write);
|
|
|
4237 src1 : E(write);
|
|
|
4238 src1 : R(read);
|
|
|
4239 IALU : R;
|
|
|
4240 %}
|
|
|
4241
|
|
|
4242 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
|
|
|
4243 multiple_bundles;
|
|
|
4244 dst : E(write)+4;
|
|
|
4245 cr : E(write);
|
|
|
4246 src1 : R(read);
|
|
|
4247 src2 : R(read);
|
|
|
4248 IALU : R(3);
|
|
|
4249 BR : R(2);
|
|
|
4250 %}
|
|
|
4251
|
|
|
4252 // Integer ALU operation
|
|
|
4253 pipe_class ialu_none(iRegI dst) %{
|
|
|
4254 single_instruction;
|
|
|
4255 dst : E(write);
|
|
|
4256 IALU : R;
|
|
|
4257 %}
|
|
|
4258
|
|
|
4259 // Integer ALU reg operation
|
|
|
4260 pipe_class ialu_reg(iRegI dst, iRegI src) %{
|
|
|
4261 single_instruction; may_have_no_code;
|
|
|
4262 dst : E(write);
|
|
|
4263 src : R(read);
|
|
|
4264 IALU : R;
|
|
|
4265 %}
|
|
|
4266
|
|
|
4267 // Integer ALU reg conditional operation
|
|
|
4268 // This instruction has a 1 cycle stall, and cannot execute
|
|
|
4269 // in the same cycle as the instruction setting the condition
|
|
|
4270 // code. We kludge this by pretending to read the condition code
|
|
|
4271 // 1 cycle earlier, and by marking the functional units as busy
|
|
|
4272 // for 2 cycles with the result available 1 cycle later than
|
|
|
4273 // is really the case.
|
|
|
4274 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
|
|
|
4275 single_instruction;
|
|
|
4276 op2_out : C(write);
|
|
|
4277 op1 : R(read);
|
|
|
4278 cr : R(read); // This is really E, with a 1 cycle stall
|
|
|
4279 BR : R(2);
|
|
|
4280 MS : R(2);
|
|
|
4281 %}
|
|
|
4282
|
|
|
4283 #ifdef _LP64
|
|
|
4284 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
|
|
|
4285 instruction_count(1); multiple_bundles;
|
|
|
4286 dst : C(write)+1;
|
|
|
4287 src : R(read)+1;
|
|
|
4288 IALU : R(1);
|
|
|
4289 BR : E(2);
|
|
|
4290 MS : E(2);
|
|
|
4291 %}
|
|
|
4292 #endif
|
|
|
4293
|
|
|
4294 // Integer ALU reg operation
|
|
|
4295 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
|
|
|
4296 single_instruction; may_have_no_code;
|
|
|
4297 dst : E(write);
|
|
|
4298 src : R(read);
|
|
|
4299 IALU : R;
|
|
|
4300 %}
|
|
|
4301 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
|
|
|
4302 single_instruction; may_have_no_code;
|
|
|
4303 dst : E(write);
|
|
|
4304 src : R(read);
|
|
|
4305 IALU : R;
|
|
|
4306 %}
|
|
|
4307
|
|
|
4308 // Two integer ALU reg operations
|
|
|
4309 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
|
|
|
4310 instruction_count(2);
|
|
|
4311 dst : E(write);
|
|
|
4312 src : R(read);
|
|
|
4313 A0 : R;
|
|
|
4314 A1 : R;
|
|
|
4315 %}
|
|
|
4316
|
|
|
4317 // Two integer ALU reg operations
|
|
|
4318 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
|
|
|
4319 instruction_count(2); may_have_no_code;
|
|
|
4320 dst : E(write);
|
|
|
4321 src : R(read);
|
|
|
4322 A0 : R;
|
|
|
4323 A1 : R;
|
|
|
4324 %}
|
|
|
4325
|
|
|
4326 // Integer ALU imm operation
|
|
|
4327 pipe_class ialu_imm(iRegI dst, immI13 src) %{
|
|
|
4328 single_instruction;
|
|
|
4329 dst : E(write);
|
|
|
4330 IALU : R;
|
|
|
4331 %}
|
|
|
4332
|
|
|
4333 // Integer ALU reg-reg with carry operation
|
|
|
4334 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
|
|
|
4335 single_instruction;
|
|
|
4336 dst : E(write);
|
|
|
4337 src1 : R(read);
|
|
|
4338 src2 : R(read);
|
|
|
4339 IALU : R;
|
|
|
4340 %}
|
|
|
4341
|
|
|
4342 // Integer ALU cc operation
|
|
|
4343 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
|
|
|
4344 single_instruction;
|
|
|
4345 dst : E(write);
|
|
|
4346 cc : R(read);
|
|
|
4347 IALU : R;
|
|
|
4348 %}
|
|
|
4349
|
|
|
4350 // Integer ALU cc / second IALU operation
|
|
|
4351 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
|
|
|
4352 instruction_count(1); multiple_bundles;
|
|
|
4353 dst : E(write)+1;
|
|
|
4354 src : R(read);
|
|
|
4355 IALU : R;
|
|
|
4356 %}
|
|
|
4357
|
|
|
4358 // Integer ALU cc / second IALU operation
|
|
|
4359 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
|
|
|
4360 instruction_count(1); multiple_bundles;
|
|
|
4361 dst : E(write)+1;
|
|
|
4362 p : R(read);
|
|
|
4363 q : R(read);
|
|
|
4364 IALU : R;
|
|
|
4365 %}
|
|
|
4366
|
|
|
4367 // Integer ALU hi-lo-reg operation
|
|
|
4368 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
|
|
|
4369 instruction_count(1); multiple_bundles;
|
|
|
4370 dst : E(write)+1;
|
|
|
4371 IALU : R(2);
|
|
|
4372 %}
|
|
|
4373
|
|
|
4374 // Float ALU hi-lo-reg operation (with temp)
|
|
|
4375 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
|
|
|
4376 instruction_count(1); multiple_bundles;
|
|
|
4377 dst : E(write)+1;
|
|
|
4378 IALU : R(2);
|
|
|
4379 %}
|
|
|
4380
|
|
|
4381 // Long Constant
|
|
|
4382 pipe_class loadConL( iRegL dst, immL src ) %{
|
|
|
4383 instruction_count(2); multiple_bundles;
|
|
|
4384 dst : E(write)+1;
|
|
|
4385 IALU : R(2);
|
|
|
4386 IALU : R(2);
|
|
|
4387 %}
|
|
|
4388
|
|
|
4389 // Pointer Constant
|
|
|
4390 pipe_class loadConP( iRegP dst, immP src ) %{
|
|
|
4391 instruction_count(0); multiple_bundles;
|
|
|
4392 fixed_latency(6);
|
|
|
4393 %}
|
|
|
4394
|
|
|
4395 // Polling Address
|
|
|
4396 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
|
|
|
4397 #ifdef _LP64
|
|
|
4398 instruction_count(0); multiple_bundles;
|
|
|
4399 fixed_latency(6);
|
|
|
4400 #else
|
|
|
4401 dst : E(write);
|
|
|
4402 IALU : R;
|
|
|
4403 #endif
|
|
|
4404 %}
|
|
|
4405
|
|
|
4406 // Long Constant small
|
|
|
4407 pipe_class loadConLlo( iRegL dst, immL src ) %{
|
|
|
4408 instruction_count(2);
|
|
|
4409 dst : E(write);
|
|
|
4410 IALU : R;
|
|
|
4411 IALU : R;
|
|
|
4412 %}
|
|
|
4413
|
|
|
4414 // [PHH] This is wrong for 64-bit. See LdImmF/D.
|
|
|
4415 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
|
|
|
4416 instruction_count(1); multiple_bundles;
|
|
|
4417 src : R(read);
|
|
|
4418 dst : M(write)+1;
|
|
|
4419 IALU : R;
|
|
|
4420 MS : E;
|
|
|
4421 %}
|
|
|
4422
|
|
|
4423 // Integer ALU nop operation
|
|
|
4424 pipe_class ialu_nop() %{
|
|
|
4425 single_instruction;
|
|
|
4426 IALU : R;
|
|
|
4427 %}
|
|
|
4428
|
|
|
4429 // Integer ALU nop operation
|
|
|
4430 pipe_class ialu_nop_A0() %{
|
|
|
4431 single_instruction;
|
|
|
4432 A0 : R;
|
|
|
4433 %}
|
|
|
4434
|
|
|
4435 // Integer ALU nop operation
|
|
|
4436 pipe_class ialu_nop_A1() %{
|
|
|
4437 single_instruction;
|
|
|
4438 A1 : R;
|
|
|
4439 %}
|
|
|
4440
|
|
|
4441 // Integer Multiply reg-reg operation
|
|
|
4442 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
|
|
|
4443 single_instruction;
|
|
|
4444 dst : E(write);
|
|
|
4445 src1 : R(read);
|
|
|
4446 src2 : R(read);
|
|
|
4447 MS : R(5);
|
|
|
4448 %}
|
|
|
4449
|
|
|
4450 // Integer Multiply reg-imm operation
|
|
|
4451 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
|
|
|
4452 single_instruction;
|
|
|
4453 dst : E(write);
|
|
|
4454 src1 : R(read);
|
|
|
4455 MS : R(5);
|
|
|
4456 %}
|
|
|
4457
|
|
|
4458 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
|
|
|
4459 single_instruction;
|
|
|
4460 dst : E(write)+4;
|
|
|
4461 src1 : R(read);
|
|
|
4462 src2 : R(read);
|
|
|
4463 MS : R(6);
|
|
|
4464 %}
|
|
|
4465
|
|
|
4466 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
|
|
|
4467 single_instruction;
|
|
|
4468 dst : E(write)+4;
|
|
|
4469 src1 : R(read);
|
|
|
4470 MS : R(6);
|
|
|
4471 %}
|
|
|
4472
|
|
|
4473 // Integer Divide reg-reg
|
|
|
4474 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
|
|
|
4475 instruction_count(1); multiple_bundles;
|
|
|
4476 dst : E(write);
|
|
|
4477 temp : E(write);
|
|
|
4478 src1 : R(read);
|
|
|
4479 src2 : R(read);
|
|
|
4480 temp : R(read);
|
|
|
4481 MS : R(38);
|
|
|
4482 %}
|
|
|
4483
|
|
|
4484 // Integer Divide reg-imm
|
|
|
4485 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
|
|
|
4486 instruction_count(1); multiple_bundles;
|
|
|
4487 dst : E(write);
|
|
|
4488 temp : E(write);
|
|
|
4489 src1 : R(read);
|
|
|
4490 temp : R(read);
|
|
|
4491 MS : R(38);
|
|
|
4492 %}
|
|
|
4493
|
|
|
4494 // Long Divide
|
|
|
4495 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
|
|
|
4496 dst : E(write)+71;
|
|
|
4497 src1 : R(read);
|
|
|
4498 src2 : R(read)+1;
|
|
|
4499 MS : R(70);
|
|
|
4500 %}
|
|
|
4501
|
|
|
4502 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
|
|
|
4503 dst : E(write)+71;
|
|
|
4504 src1 : R(read);
|
|
|
4505 MS : R(70);
|
|
|
4506 %}
|
|
|
4507
|
|
|
4508 // Floating Point Add Float
|
|
|
4509 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
|
|
|
4510 single_instruction;
|
|
|
4511 dst : X(write);
|
|
|
4512 src1 : E(read);
|
|
|
4513 src2 : E(read);
|
|
|
4514 FA : R;
|
|
|
4515 %}
|
|
|
4516
|
|
|
4517 // Floating Point Add Double
|
|
|
4518 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
|
|
|
4519 single_instruction;
|
|
|
4520 dst : X(write);
|
|
|
4521 src1 : E(read);
|
|
|
4522 src2 : E(read);
|
|
|
4523 FA : R;
|
|
|
4524 %}
|
|
|
4525
|
|
|
4526 // Floating Point Conditional Move based on integer flags
|
|
|
4527 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
|
|
|
4528 single_instruction;
|
|
|
4529 dst : X(write);
|
|
|
4530 src : E(read);
|
|
|
4531 cr : R(read);
|
|
|
4532 FA : R(2);
|
|
|
4533 BR : R(2);
|
|
|
4534 %}
|
|
|
4535
|
|
|
4536 // Floating Point Conditional Move based on integer flags
|
|
|
4537 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
|
|
|
4538 single_instruction;
|
|
|
4539 dst : X(write);
|
|
|
4540 src : E(read);
|
|
|
4541 cr : R(read);
|
|
|
4542 FA : R(2);
|
|
|
4543 BR : R(2);
|
|
|
4544 %}
|
|
|
4545
|
|
|
4546 // Floating Point Multiply Float
|
|
|
4547 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
|
|
|
4548 single_instruction;
|
|
|
4549 dst : X(write);
|
|
|
4550 src1 : E(read);
|
|
|
4551 src2 : E(read);
|
|
|
4552 FM : R;
|
|
|
4553 %}
|
|
|
4554
|
|
|
4555 // Floating Point Multiply Double
|
|
|
4556 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
|
|
|
4557 single_instruction;
|
|
|
4558 dst : X(write);
|
|
|
4559 src1 : E(read);
|
|
|
4560 src2 : E(read);
|
|
|
4561 FM : R;
|
|
|
4562 %}
|
|
|
4563
|
|
|
4564 // Floating Point Divide Float
|
|
|
4565 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
|
|
|
4566 single_instruction;
|
|
|
4567 dst : X(write);
|
|
|
4568 src1 : E(read);
|
|
|
4569 src2 : E(read);
|
|
|
4570 FM : R;
|
|
|
4571 FDIV : C(14);
|
|
|
4572 %}
|
|
|
4573
|
|
|
4574 // Floating Point Divide Double
|
|
|
4575 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
|
|
|
4576 single_instruction;
|
|
|
4577 dst : X(write);
|
|
|
4578 src1 : E(read);
|
|
|
4579 src2 : E(read);
|
|
|
4580 FM : R;
|
|
|
4581 FDIV : C(17);
|
|
|
4582 %}
|
|
|
4583
|
|
|
4584 // Floating Point Move/Negate/Abs Float
|
|
|
4585 pipe_class faddF_reg(regF dst, regF src) %{
|
|
|
4586 single_instruction;
|
|
|
4587 dst : W(write);
|
|
|
4588 src : E(read);
|
|
|
4589 FA : R(1);
|
|
|
4590 %}
|
|
|
4591
|
|
|
4592 // Floating Point Move/Negate/Abs Double
|
|
|
4593 pipe_class faddD_reg(regD dst, regD src) %{
|
|
|
4594 single_instruction;
|
|
|
4595 dst : W(write);
|
|
|
4596 src : E(read);
|
|
|
4597 FA : R;
|
|
|
4598 %}
|
|
|
4599
|
|
|
4600 // Floating Point Convert F->D
|
|
|
4601 pipe_class fcvtF2D(regD dst, regF src) %{
|
|
|
4602 single_instruction;
|
|
|
4603 dst : X(write);
|
|
|
4604 src : E(read);
|
|
|
4605 FA : R;
|
|
|
4606 %}
|
|
|
4607
|
|
|
4608 // Floating Point Convert I->D
|
|
|
4609 pipe_class fcvtI2D(regD dst, regF src) %{
|
|
|
4610 single_instruction;
|
|
|
4611 dst : X(write);
|
|
|
4612 src : E(read);
|
|
|
4613 FA : R;
|
|
|
4614 %}
|
|
|
4615
|
|
|
4616 // Floating Point Convert LHi->D
|
|
|
4617 pipe_class fcvtLHi2D(regD dst, regD src) %{
|
|
|
4618 single_instruction;
|
|
|
4619 dst : X(write);
|
|
|
4620 src : E(read);
|
|
|
4621 FA : R;
|
|
|
4622 %}
|
|
|
4623
|
|
|
4624 // Floating Point Convert L->D
|
|
|
4625 pipe_class fcvtL2D(regD dst, regF src) %{
|
|
|
4626 single_instruction;
|
|
|
4627 dst : X(write);
|
|
|
4628 src : E(read);
|
|
|
4629 FA : R;
|
|
|
4630 %}
|
|
|
4631
|
|
|
4632 // Floating Point Convert L->F
|
|
|
4633 pipe_class fcvtL2F(regD dst, regF src) %{
|
|
|
4634 single_instruction;
|
|
|
4635 dst : X(write);
|
|
|
4636 src : E(read);
|
|
|
4637 FA : R;
|
|
|
4638 %}
|
|
|
4639
|
|
|
4640 // Floating Point Convert D->F
|
|
|
4641 pipe_class fcvtD2F(regD dst, regF src) %{
|
|
|
4642 single_instruction;
|
|
|
4643 dst : X(write);
|
|
|
4644 src : E(read);
|
|
|
4645 FA : R;
|
|
|
4646 %}
|
|
|
4647
|
|
|
4648 // Floating Point Convert I->L
|
|
|
4649 pipe_class fcvtI2L(regD dst, regF src) %{
|
|
|
4650 single_instruction;
|
|
|
4651 dst : X(write);
|
|
|
4652 src : E(read);
|
|
|
4653 FA : R;
|
|
|
4654 %}
|
|
|
4655
|
|
|
4656 // Floating Point Convert D->F
|
|
|
4657 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
|
|
|
4658 instruction_count(1); multiple_bundles;
|
|
|
4659 dst : X(write)+6;
|
|
|
4660 src : E(read);
|
|
|
4661 FA : R;
|
|
|
4662 %}
|
|
|
4663
|
|
|
4664 // Floating Point Convert D->L
|
|
|
4665 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
|
|
|
4666 instruction_count(1); multiple_bundles;
|
|
|
4667 dst : X(write)+6;
|
|
|
4668 src : E(read);
|
|
|
4669 FA : R;
|
|
|
4670 %}
|
|
|
4671
|
|
|
4672 // Floating Point Convert F->I
|
|
|
4673 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
|
|
|
4674 instruction_count(1); multiple_bundles;
|
|
|
4675 dst : X(write)+6;
|
|
|
4676 src : E(read);
|
|
|
4677 FA : R;
|
|
|
4678 %}
|
|
|
4679
|
|
|
4680 // Floating Point Convert F->L
|
|
|
4681 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
|
|
|
4682 instruction_count(1); multiple_bundles;
|
|
|
4683 dst : X(write)+6;
|
|
|
4684 src : E(read);
|
|
|
4685 FA : R;
|
|
|
4686 %}
|
|
|
4687
|
|
|
4688 // Floating Point Convert I->F
|
|
|
4689 pipe_class fcvtI2F(regF dst, regF src) %{
|
|
|
4690 single_instruction;
|
|
|
4691 dst : X(write);
|
|
|
4692 src : E(read);
|
|
|
4693 FA : R;
|
|
|
4694 %}
|
|
|
4695
|
|
|
4696 // Floating Point Compare
|
|
|
4697 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
|
|
|
4698 single_instruction;
|
|
|
4699 cr : X(write);
|
|
|
4700 src1 : E(read);
|
|
|
4701 src2 : E(read);
|
|
|
4702 FA : R;
|
|
|
4703 %}
|
|
|
4704
|
|
|
4705 // Floating Point Compare
|
|
|
4706 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
|
|
|
4707 single_instruction;
|
|
|
4708 cr : X(write);
|
|
|
4709 src1 : E(read);
|
|
|
4710 src2 : E(read);
|
|
|
4711 FA : R;
|
|
|
4712 %}
|
|
|
4713
|
|
|
4714 // Floating Add Nop
|
|
|
4715 pipe_class fadd_nop() %{
|
|
|
4716 single_instruction;
|
|
|
4717 FA : R;
|
|
|
4718 %}
|
|
|
4719
|
|
|
4720 // Integer Store to Memory
|
|
|
4721 pipe_class istore_mem_reg(memory mem, iRegI src) %{
|
|
|
4722 single_instruction;
|
|
|
4723 mem : R(read);
|
|
|
4724 src : C(read);
|
|
|
4725 MS : R;
|
|
|
4726 %}
|
|
|
4727
|
|
|
4728 // Integer Store to Memory
|
|
|
4729 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
|
|
|
4730 single_instruction;
|
|
|
4731 mem : R(read);
|
|
|
4732 src : C(read);
|
|
|
4733 MS : R;
|
|
|
4734 %}
|
|
|
4735
|
|
|
4736 // Integer Store Zero to Memory
|
|
|
4737 pipe_class istore_mem_zero(memory mem, immI0 src) %{
|
|
|
4738 single_instruction;
|
|
|
4739 mem : R(read);
|
|
|
4740 MS : R;
|
|
|
4741 %}
|
|
|
4742
|
|
|
4743 // Special Stack Slot Store
|
|
|
4744 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
|
|
|
4745 single_instruction;
|
|
|
4746 stkSlot : R(read);
|
|
|
4747 src : C(read);
|
|
|
4748 MS : R;
|
|
|
4749 %}
|
|
|
4750
|
|
|
4751 // Special Stack Slot Store
|
|
|
4752 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
|
|
|
4753 instruction_count(2); multiple_bundles;
|
|
|
4754 stkSlot : R(read);
|
|
|
4755 src : C(read);
|
|
|
4756 MS : R(2);
|
|
|
4757 %}
|
|
|
4758
|
|
|
4759 // Float Store
|
|
|
4760 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
|
|
|
4761 single_instruction;
|
|
|
4762 mem : R(read);
|
|
|
4763 src : C(read);
|
|
|
4764 MS : R;
|
|
|
4765 %}
|
|
|
4766
|
|
|
4767 // Float Store
|
|
|
4768 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
|
|
|
4769 single_instruction;
|
|
|
4770 mem : R(read);
|
|
|
4771 MS : R;
|
|
|
4772 %}
|
|
|
4773
|
|
|
4774 // Double Store
|
|
|
4775 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
|
|
|
4776 instruction_count(1);
|
|
|
4777 mem : R(read);
|
|
|
4778 src : C(read);
|
|
|
4779 MS : R;
|
|
|
4780 %}
|
|
|
4781
|
|
|
4782 // Double Store
|
|
|
4783 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
|
|
|
4784 single_instruction;
|
|
|
4785 mem : R(read);
|
|
|
4786 MS : R;
|
|
|
4787 %}
|
|
|
4788
|
|
|
4789 // Special Stack Slot Float Store
|
|
|
4790 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
|
|
|
4791 single_instruction;
|
|
|
4792 stkSlot : R(read);
|
|
|
4793 src : C(read);
|
|
|
4794 MS : R;
|
|
|
4795 %}
|
|
|
4796
|
|
|
4797 // Special Stack Slot Double Store
|
|
|
4798 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
|
|
|
4799 single_instruction;
|
|
|
4800 stkSlot : R(read);
|
|
|
4801 src : C(read);
|
|
|
4802 MS : R;
|
|
|
4803 %}
|
|
|
4804
|
|
|
4805 // Integer Load (when sign bit propagation not needed)
|
|
|
4806 pipe_class iload_mem(iRegI dst, memory mem) %{
|
|
|
4807 single_instruction;
|
|
|
4808 mem : R(read);
|
|
|
4809 dst : C(write);
|
|
|
4810 MS : R;
|
|
|
4811 %}
|
|
|
4812
|
|
|
4813 // Integer Load from stack operand
|
|
|
4814 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
|
|
|
4815 single_instruction;
|
|
|
4816 mem : R(read);
|
|
|
4817 dst : C(write);
|
|
|
4818 MS : R;
|
|
|
4819 %}
|
|
|
4820
|
|
|
4821 // Integer Load (when sign bit propagation or masking is needed)
|
|
|
4822 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
|
|
|
4823 single_instruction;
|
|
|
4824 mem : R(read);
|
|
|
4825 dst : M(write);
|
|
|
4826 MS : R;
|
|
|
4827 %}
|
|
|
4828
|
|
|
4829 // Float Load
|
|
|
4830 pipe_class floadF_mem(regF dst, memory mem) %{
|
|
|
4831 single_instruction;
|
|
|
4832 mem : R(read);
|
|
|
4833 dst : M(write);
|
|
|
4834 MS : R;
|
|
|
4835 %}
|
|
|
4836
|
|
|
4837 // Float Load
|
|
|
4838 pipe_class floadD_mem(regD dst, memory mem) %{
|
|
|
4839 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
|
|
|
4840 mem : R(read);
|
|
|
4841 dst : M(write);
|
|
|
4842 MS : R;
|
|
|
4843 %}
|
|
|
4844
|
|
|
4845 // Float Load
|
|
|
4846 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
|
|
|
4847 single_instruction;
|
|
|
4848 stkSlot : R(read);
|
|
|
4849 dst : M(write);
|
|
|
4850 MS : R;
|
|
|
4851 %}
|
|
|
4852
|
|
|
4853 // Float Load
|
|
|
4854 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
|
|
|
4855 single_instruction;
|
|
|
4856 stkSlot : R(read);
|
|
|
4857 dst : M(write);
|
|
|
4858 MS : R;
|
|
|
4859 %}
|
|
|
4860
|
|
|
4861 // Memory Nop
|
|
|
4862 pipe_class mem_nop() %{
|
|
|
4863 single_instruction;
|
|
|
4864 MS : R;
|
|
|
4865 %}
|
|
|
4866
|
|
|
4867 pipe_class sethi(iRegP dst, immI src) %{
|
|
|
4868 single_instruction;
|
|
|
4869 dst : E(write);
|
|
|
4870 IALU : R;
|
|
|
4871 %}
|
|
|
4872
|
|
|
4873 pipe_class loadPollP(iRegP poll) %{
|
|
|
4874 single_instruction;
|
|
|
4875 poll : R(read);
|
|
|
4876 MS : R;
|
|
|
4877 %}
|
|
|
4878
|
|
|
4879 pipe_class br(Universe br, label labl) %{
|
|
|
4880 single_instruction_with_delay_slot;
|
|
|
4881 BR : R;
|
|
|
4882 %}
|
|
|
4883
|
|
|
4884 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
|
|
|
4885 single_instruction_with_delay_slot;
|
|
|
4886 cr : E(read);
|
|
|
4887 BR : R;
|
|
|
4888 %}
|
|
|
4889
|
|
|
4890 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
|
|
|
4891 single_instruction_with_delay_slot;
|
|
|
4892 op1 : E(read);
|
|
|
4893 BR : R;
|
|
|
4894 MS : R;
|
|
|
4895 %}
|
|
|
4896
|
|
|
4897 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
|
|
|
4898 single_instruction_with_delay_slot;
|
|
|
4899 cr : E(read);
|
|
|
4900 BR : R;
|
|
|
4901 %}
|
|
|
4902
|
|
|
4903 pipe_class br_nop() %{
|
|
|
4904 single_instruction;
|
|
|
4905 BR : R;
|
|
|
4906 %}
|
|
|
4907
|
|
|
4908 pipe_class simple_call(method meth) %{
|
|
|
4909 instruction_count(2); multiple_bundles; force_serialization;
|
|
|
4910 fixed_latency(100);
|
|
|
4911 BR : R(1);
|
|
|
4912 MS : R(1);
|
|
|
4913 A0 : R(1);
|
|
|
4914 %}
|
|
|
4915
|
|
|
4916 pipe_class compiled_call(method meth) %{
|
|
|
4917 instruction_count(1); multiple_bundles; force_serialization;
|
|
|
4918 fixed_latency(100);
|
|
|
4919 MS : R(1);
|
|
|
4920 %}
|
|
|
4921
|
|
|
4922 pipe_class call(method meth) %{
|
|
|
4923 instruction_count(0); multiple_bundles; force_serialization;
|
|
|
4924 fixed_latency(100);
|
|
|
4925 %}
|
|
|
4926
|
|
|
4927 pipe_class tail_call(Universe ignore, label labl) %{
|
|
|
4928 single_instruction; has_delay_slot;
|
|
|
4929 fixed_latency(100);
|
|
|
4930 BR : R(1);
|
|
|
4931 MS : R(1);
|
|
|
4932 %}
|
|
|
4933
|
|
|
4934 pipe_class ret(Universe ignore) %{
|
|
|
4935 single_instruction; has_delay_slot;
|
|
|
4936 BR : R(1);
|
|
|
4937 MS : R(1);
|
|
|
4938 %}
|
|
|
4939
|
|
|
4940 pipe_class ret_poll(g3RegP poll) %{
|
|
|
4941 instruction_count(3); has_delay_slot;
|
|
|
4942 poll : E(read);
|
|
|
4943 MS : R;
|
|
|
4944 %}
|
|
|
4945
|
|
|
4946 // The real do-nothing guy
|
|
|
4947 pipe_class empty( ) %{
|
|
|
4948 instruction_count(0);
|
|
|
4949 %}
|
|
|
4950
|
|
|
4951 pipe_class long_memory_op() %{
|
|
|
4952 instruction_count(0); multiple_bundles; force_serialization;
|
|
|
4953 fixed_latency(25);
|
|
|
4954 MS : R(1);
|
|
|
4955 %}
|
|
|
4956
|
|
|
4957 // Check-cast
|
|
|
4958 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
|
|
|
4959 array : R(read);
|
|
|
4960 match : R(read);
|
|
|
4961 IALU : R(2);
|
|
|
4962 BR : R(2);
|
|
|
4963 MS : R;
|
|
|
4964 %}
|
|
|
4965
|
|
|
4966 // Convert FPU flags into +1,0,-1
|
|
|
4967 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
|
|
|
4968 src1 : E(read);
|
|
|
4969 src2 : E(read);
|
|
|
4970 dst : E(write);
|
|
|
4971 FA : R;
|
|
|
4972 MS : R(2);
|
|
|
4973 BR : R(2);
|
|
|
4974 %}
|
|
|
4975
|
|
|
4976 // Compare for p < q, and conditionally add y
|
|
|
4977 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
|
|
|
4978 p : E(read);
|
|
|
4979 q : E(read);
|
|
|
4980 y : E(read);
|
|
|
4981 IALU : R(3)
|
|
|
4982 %}
|
|
|
4983
|
|
|
4984 // Perform a compare, then move conditionally in a branch delay slot.
|
|
|
4985 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
|
|
|
4986 src2 : E(read);
|
|
|
4987 srcdst : E(read);
|
|
|
4988 IALU : R;
|
|
|
4989 BR : R;
|
|
|
4990 %}
|
|
|
4991
|
|
|
4992 // Define the class for the Nop node
|
|
|
4993 define %{
|
|
|
4994 MachNop = ialu_nop;
|
|
|
4995 %}
|
|
|
4996
|
|
|
4997 %}
|
|
|
4998
|
|
|
4999 //----------INSTRUCTIONS-------------------------------------------------------
|
|
|
5000
|
|
|
5001 //------------Special Stack Slot instructions - no match rules-----------------
|
|
|
5002 instruct stkI_to_regF(regF dst, stackSlotI src) %{
|
|
|
5003 // No match rule to avoid chain rule match.
|
|
|
5004 effect(DEF dst, USE src);
|
|
|
5005 ins_cost(MEMORY_REF_COST);
|
|
|
5006 size(4);
|
|
|
5007 format %{ "LDF $src,$dst\t! stkI to regF" %}
|
|
|
5008 opcode(Assembler::ldf_op3);
|
|
|
5009 ins_encode(form3_mem_reg(src, dst));
|
|
|
5010 ins_pipe(floadF_stk);
|
|
|
5011 %}
|
|
|
5012
|
|
|
5013 instruct stkL_to_regD(regD dst, stackSlotL src) %{
|
|
|
5014 // No match rule to avoid chain rule match.
|
|
|
5015 effect(DEF dst, USE src);
|
|
|
5016 ins_cost(MEMORY_REF_COST);
|
|
|
5017 size(4);
|
|
|
5018 format %{ "LDDF $src,$dst\t! stkL to regD" %}
|
|
|
5019 opcode(Assembler::lddf_op3);
|
|
|
5020 ins_encode(form3_mem_reg(src, dst));
|
|
|
5021 ins_pipe(floadD_stk);
|
|
|
5022 %}
|
|
|
5023
|
|
|
5024 instruct regF_to_stkI(stackSlotI dst, regF src) %{
|
|
|
5025 // No match rule to avoid chain rule match.
|
|
|
5026 effect(DEF dst, USE src);
|
|
|
5027 ins_cost(MEMORY_REF_COST);
|
|
|
5028 size(4);
|
|
|
5029 format %{ "STF $src,$dst\t! regF to stkI" %}
|
|
|
5030 opcode(Assembler::stf_op3);
|
|
|
5031 ins_encode(form3_mem_reg(dst, src));
|
|
|
5032 ins_pipe(fstoreF_stk_reg);
|
|
|
5033 %}
|
|
|
5034
|
|
|
5035 instruct regD_to_stkL(stackSlotL dst, regD src) %{
|
|
|
5036 // No match rule to avoid chain rule match.
|
|
|
5037 effect(DEF dst, USE src);
|
|
|
5038 ins_cost(MEMORY_REF_COST);
|
|
|
5039 size(4);
|
|
|
5040 format %{ "STDF $src,$dst\t! regD to stkL" %}
|
|
|
5041 opcode(Assembler::stdf_op3);
|
|
|
5042 ins_encode(form3_mem_reg(dst, src));
|
|
|
5043 ins_pipe(fstoreD_stk_reg);
|
|
|
5044 %}
|
|
|
5045
|
|
|
5046 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
|
|
|
5047 effect(DEF dst, USE src);
|
|
|
5048 ins_cost(MEMORY_REF_COST*2);
|
|
|
5049 size(8);
|
|
|
5050 format %{ "STW $src,$dst.hi\t! long\n\t"
|
|
|
5051 "STW R_G0,$dst.lo" %}
|
|
|
5052 opcode(Assembler::stw_op3);
|
|
|
5053 ins_encode(form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
|
|
|
5054 ins_pipe(lstoreI_stk_reg);
|
|
|
5055 %}
|
|
|
5056
|
|
|
5057 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
|
|
|
5058 // No match rule to avoid chain rule match.
|
|
|
5059 effect(DEF dst, USE src);
|
|
|
5060 ins_cost(MEMORY_REF_COST);
|
|
|
5061 size(4);
|
|
|
5062 format %{ "STX $src,$dst\t! regL to stkD" %}
|
|
|
5063 opcode(Assembler::stx_op3);
|
|
|
5064 ins_encode( form3_mem_reg( dst, src ) );
|
|
|
5065 ins_pipe(istore_stk_reg);
|
|
|
5066 %}
|
|
|
5067
|
|
|
5068 //---------- Chain stack slots between similar types --------
|
|
|
5069
|
|
|
5070 // Load integer from stack slot
|
|
|
5071 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
|
|
|
5072 match(Set dst src);
|
|
|
5073 ins_cost(MEMORY_REF_COST);
|
|
|
5074
|
|
|
5075 size(4);
|
|
|
5076 format %{ "LDUW $src,$dst\t!stk" %}
|
|
|
5077 opcode(Assembler::lduw_op3);
|
|
|
5078 ins_encode( form3_mem_reg( src, dst ) );
|
|
|
5079 ins_pipe(iload_mem);
|
|
|
5080 %}
|
|
|
5081
|
|
|
5082 // Store integer to stack slot
|
|
|
5083 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
|
|
|
5084 match(Set dst src);
|
|
|
5085 ins_cost(MEMORY_REF_COST);
|
|
|
5086
|
|
|
5087 size(4);
|
|
|
5088 format %{ "STW $src,$dst\t!stk" %}
|
|
|
5089 opcode(Assembler::stw_op3);
|
|
|
5090 ins_encode( form3_mem_reg( dst, src ) );
|
|
|
5091 ins_pipe(istore_mem_reg);
|
|
|
5092 %}
|
|
|
5093
|
|
|
5094 // Load long from stack slot
|
|
|
5095 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
|
|
|
5096 match(Set dst src);
|
|
|
5097
|
|
|
5098 ins_cost(MEMORY_REF_COST);
|
|
|
5099 size(4);
|
|
|
5100 format %{ "LDX $src,$dst\t! long" %}
|
|
|
5101 opcode(Assembler::ldx_op3);
|
|
|
5102 ins_encode( form3_mem_reg( src, dst ) );
|
|
|
5103 ins_pipe(iload_mem);
|
|
|
5104 %}
|
|
|
5105
|
|
|
5106 // Store long to stack slot
|
|
|
5107 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
|
|
|
5108 match(Set dst src);
|
|
|
5109
|
|
|
5110 ins_cost(MEMORY_REF_COST);
|
|
|
5111 size(4);
|
|
|
5112 format %{ "STX $src,$dst\t! long" %}
|
|
|
5113 opcode(Assembler::stx_op3);
|
|
|
5114 ins_encode( form3_mem_reg( dst, src ) );
|
|
|
5115 ins_pipe(istore_mem_reg);
|
|
|
5116 %}
|
|
|
5117
|
|
|
5118 #ifdef _LP64
|
|
|
5119 // Load pointer from stack slot, 64-bit encoding
|
|
|
5120 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
|
|
|
5121 match(Set dst src);
|
|
|
5122 ins_cost(MEMORY_REF_COST);
|
|
|
5123 size(4);
|
|
|
5124 format %{ "LDX $src,$dst\t!ptr" %}
|
|
|
5125 opcode(Assembler::ldx_op3);
|
|
|
5126 ins_encode( form3_mem_reg( src, dst ) );
|
|
|
5127 ins_pipe(iload_mem);
|
|
|
5128 %}
|
|
|
5129
|
|
|
5130 // Store pointer to stack slot
|
|
|
5131 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
|
|
|
5132 match(Set dst src);
|
|
|
5133 ins_cost(MEMORY_REF_COST);
|
|
|
5134 size(4);
|
|
|
5135 format %{ "STX $src,$dst\t!ptr" %}
|
|
|
5136 opcode(Assembler::stx_op3);
|
|
|
5137 ins_encode( form3_mem_reg( dst, src ) );
|
|
|
5138 ins_pipe(istore_mem_reg);
|
|
|
5139 %}
|
|
|
5140 #else // _LP64
|
|
|
5141 // Load pointer from stack slot, 32-bit encoding
|
|
|
5142 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
|
|
|
5143 match(Set dst src);
|
|
|
5144 ins_cost(MEMORY_REF_COST);
|
|
|
5145 format %{ "LDUW $src,$dst\t!ptr" %}
|
|
|
5146 opcode(Assembler::lduw_op3, Assembler::ldst_op);
|
|
|
5147 ins_encode( form3_mem_reg( src, dst ) );
|
|
|
5148 ins_pipe(iload_mem);
|
|
|
5149 %}
|
|
|
5150
|
|
|
5151 // Store pointer to stack slot
|
|
|
5152 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
|
|
|
5153 match(Set dst src);
|
|
|
5154 ins_cost(MEMORY_REF_COST);
|
|
|
5155 format %{ "STW $src,$dst\t!ptr" %}
|
|
|
5156 opcode(Assembler::stw_op3, Assembler::ldst_op);
|
|
|
5157 ins_encode( form3_mem_reg( dst, src ) );
|
|
|
5158 ins_pipe(istore_mem_reg);
|
|
|
5159 %}
|
|
|
5160 #endif // _LP64
|
|
|
5161
|
|
|
5162 //------------Special Nop instructions for bundling - no match rules-----------
|
|
|
5163 // Nop using the A0 functional unit
|
|
|
5164 instruct Nop_A0() %{
|
|
|
5165 ins_cost(0);
|
|
|
5166
|
|
|
5167 format %{ "NOP ! Alu Pipeline" %}
|
|
|
5168 opcode(Assembler::or_op3, Assembler::arith_op);
|
|
|
5169 ins_encode( form2_nop() );
|
|
|
5170 ins_pipe(ialu_nop_A0);
|
|
|
5171 %}
|
|
|
5172
|
|
|
5173 // Nop using the A1 functional unit
|
|
|
5174 instruct Nop_A1( ) %{
|
|
|
5175 ins_cost(0);
|
|
|
5176
|
|
|
5177 format %{ "NOP ! Alu Pipeline" %}
|
|
|
5178 opcode(Assembler::or_op3, Assembler::arith_op);
|
|
|
5179 ins_encode( form2_nop() );
|
|
|
5180 ins_pipe(ialu_nop_A1);
|
|
|
5181 %}
|
|
|
5182
|
|
|
5183 // Nop using the memory functional unit
|
|
|
5184 instruct Nop_MS( ) %{
|
|
|
5185 ins_cost(0);
|
|
|
5186
|
|
|
5187 format %{ "NOP ! Memory Pipeline" %}
|
|
|
5188 ins_encode( emit_mem_nop );
|
|
|
5189 ins_pipe(mem_nop);
|
|
|
5190 %}
|
|
|
5191
|
|
|
5192 // Nop using the floating add functional unit
|
|
|
5193 instruct Nop_FA( ) %{
|
|
|
5194 ins_cost(0);
|
|
|
5195
|
|
|
5196 format %{ "NOP ! Floating Add Pipeline" %}
|
|
|
5197 ins_encode( emit_fadd_nop );
|
|
|
5198 ins_pipe(fadd_nop);
|
|
|
5199 %}
|
|
|
5200
|
|
|
5201 // Nop using the branch functional unit
|
|
|
5202 instruct Nop_BR( ) %{
|
|
|
5203 ins_cost(0);
|
|
|
5204
|
|
|
5205 format %{ "NOP ! Branch Pipeline" %}
|
|
|
5206 ins_encode( emit_br_nop );
|
|
|
5207 ins_pipe(br_nop);
|
|
|
5208 %}
|
|
|
5209
|
|
|
5210 //----------Load/Store/Move Instructions---------------------------------------
|
|
|
5211 //----------Load Instructions--------------------------------------------------
|
|
|
5212 // Load Byte (8bit signed)
|
|
|
5213 instruct loadB(iRegI dst, memory mem) %{
|
|
|
5214 match(Set dst (LoadB mem));
|
|
|
5215 ins_cost(MEMORY_REF_COST);
|
|
|
5216
|
|
|
5217 size(4);
|
|
|
5218 format %{ "LDSB $mem,$dst" %}
|
|
|
5219 opcode(Assembler::ldsb_op3);
|
|
|
5220 ins_encode( form3_mem_reg( mem, dst ) );
|
|
|
5221 ins_pipe(iload_mask_mem);
|
|
|
5222 %}
|
|
|
5223
|
|
|
5224 // Load Byte (8bit UNsigned) into an int reg
|
|
|
5225 instruct loadUB(iRegI dst, memory mem, immI_255 bytemask) %{
|
|
|
5226 match(Set dst (AndI (LoadB mem) bytemask));
|
|
|
5227 ins_cost(MEMORY_REF_COST);
|
|
|
5228
|
|
|
5229 size(4);
|
|
|
5230 format %{ "LDUB $mem,$dst" %}
|
|
|
5231 opcode(Assembler::ldub_op3);
|
|
|
5232 ins_encode( form3_mem_reg( mem, dst ) );
|
|
|
5233 ins_pipe(iload_mask_mem);
|
|
|
5234 %}
|
|
|
5235
|
|
|
5236 // Load Byte (8bit UNsigned) into a Long Register
|
|
|
5237 instruct loadUBL(iRegL dst, memory mem, immL_FF bytemask) %{
|
|
|
5238 match(Set dst (AndL (ConvI2L (LoadB mem)) bytemask));
|
|
|
5239 ins_cost(MEMORY_REF_COST);
|
|
|
5240
|
|
|
5241 size(4);
|
|
|
5242 format %{ "LDUB $mem,$dst" %}
|
|
|
5243 opcode(Assembler::ldub_op3);
|
|
|
5244 ins_encode( form3_mem_reg( mem, dst ) );
|
|
|
5245 ins_pipe(iload_mask_mem);
|
|
|
5246 %}
|
|
|
5247
|
|
|
5248 // Load Char (16bit UNsigned) into a Long Register
|
|
|
5249 instruct loadUCL(iRegL dst, memory mem, immL_FFFF bytemask) %{
|
|
|
5250 match(Set dst (AndL (ConvI2L (LoadC mem)) bytemask));
|
|
|
5251 ins_cost(MEMORY_REF_COST);
|
|
|
5252
|
|
|
5253 size(4);
|
|
|
5254 format %{ "LDUH $mem,$dst" %}
|
|
|
5255 opcode(Assembler::lduh_op3);
|
|
|
5256 ins_encode( form3_mem_reg( mem, dst ) );
|
|
|
5257 ins_pipe(iload_mask_mem);
|
|
|
5258 %}
|
|
|
5259
|
|
|
5260 // Load Char (16bit unsigned)
|
|
|
5261 instruct loadC(iRegI dst, memory mem) %{
|
|
|
5262 match(Set dst (LoadC mem));
|
|
|
5263 ins_cost(MEMORY_REF_COST);
|
|
|
5264
|
|
|
5265 size(4);
|
|
|
5266 format %{ "LDUH $mem,$dst" %}
|
|
|
5267 opcode(Assembler::lduh_op3);
|
|
|
5268 ins_encode( form3_mem_reg( mem, dst ) );
|
|
|
5269 ins_pipe(iload_mask_mem);
|
|
|
5270 %}
|
|
|
5271
|
|
|
5272 // Load Integer
|
|
|
5273 instruct loadI(iRegI dst, memory mem) %{
|
|
|
5274 match(Set dst (LoadI mem));
|
|
|
5275 ins_cost(MEMORY_REF_COST);
|
|
|
5276 size(4);
|
|
|
5277
|
|
|
5278 format %{ "LDUW $mem,$dst" %}
|
|
|
5279 opcode(Assembler::lduw_op3);
|
|
|
5280 ins_encode( form3_mem_reg( mem, dst ) );
|
|
|
5281 ins_pipe(iload_mem);
|
|
|
5282 %}
|
|
|
5283
|
|
|
5284 // Load Long - aligned
|
|
|
5285 instruct loadL(iRegL dst, memory mem ) %{
|
|
|
5286 match(Set dst (LoadL mem));
|
|
|
5287 ins_cost(MEMORY_REF_COST);
|
|
|
5288 size(4);
|
|
|
5289 format %{ "LDX $mem,$dst\t! long" %}
|
|
|
5290 opcode(Assembler::ldx_op3);
|
|
|
5291 ins_encode( form3_mem_reg( mem, dst ) );
|
|
|
5292 ins_pipe(iload_mem);
|
|
|
5293 %}
|
|
|
5294
|
|
|
5295 // Load Long - UNaligned
|
|
|
5296 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
|
|
|
5297 match(Set dst (LoadL_unaligned mem));
|
|
|
5298 effect(KILL tmp);
|
|
|
5299 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
|
|
|
5300 size(16);
|
|
|
5301 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
|
|
|
5302 "\tLDUW $mem ,$dst\n"
|
|
|
5303 "\tSLLX #32, $dst, $dst\n"
|
|
|
5304 "\tOR $dst, R_O7, $dst" %}
|
|
|
5305 opcode(Assembler::lduw_op3);
|
|
|
5306 ins_encode( form3_mem_reg_long_unaligned_marshal( mem, dst ));
|
|
|
5307 ins_pipe(iload_mem);
|
|
|
5308 %}
|
|
|
5309
|
|
|
5310 // Load Aligned Packed Byte into a Double Register
|
|
|
5311 instruct loadA8B(regD dst, memory mem) %{
|
|
|
5312 match(Set dst (Load8B mem));
|
|
|
5313 ins_cost(MEMORY_REF_COST);
|
|
|
5314 size(4);
|
|
|
5315 format %{ "LDDF $mem,$dst\t! packed8B" %}
|
|
|
5316 opcode(Assembler::lddf_op3);
|
|
|
5317 ins_encode( form3_mem_reg( mem, dst ) );
|
|
|
5318 ins_pipe(floadD_mem);
|
|
|
5319 %}
|
|
|
5320
|
|
|
5321 // Load Aligned Packed Char into a Double Register
|
|
|
5322 instruct loadA4C(regD dst, memory mem) %{
|
|
|
5323 match(Set dst (Load4C mem));
|
|
|
5324 ins_cost(MEMORY_REF_COST);
|
|
|
5325 size(4);
|
|
|
5326 format %{ "LDDF $mem,$dst\t! packed4C" %}
|
|
|
5327 opcode(Assembler::lddf_op3);
|
|
|
5328 ins_encode( form3_mem_reg( mem, dst ) );
|
|
|
5329 ins_pipe(floadD_mem);
|
|
|
5330 %}
|
|
|
5331
|
|
|
5332 // Load Aligned Packed Short into a Double Register
|
|
|
5333 instruct loadA4S(regD dst, memory mem) %{
|
|
|
5334 match(Set dst (Load4S mem));
|
|
|
5335 ins_cost(MEMORY_REF_COST);
|
|
|
5336 size(4);
|
|
|
5337 format %{ "LDDF $mem,$dst\t! packed4S" %}
|
|
|
5338 opcode(Assembler::lddf_op3);
|
|
|
5339 ins_encode( form3_mem_reg( mem, dst ) );
|
|
|
5340 ins_pipe(floadD_mem);
|
|
|
5341 %}
|
|
|
5342
|
|
|
5343 // Load Aligned Packed Int into a Double Register
|
|
|
5344 instruct loadA2I(regD dst, memory mem) %{
|
|
|
5345 match(Set dst (Load2I mem));
|
|
|
5346 ins_cost(MEMORY_REF_COST);
|
|
|
5347 size(4);
|
|
|
5348 format %{ "LDDF $mem,$dst\t! packed2I" %}
|
|
|
5349 opcode(Assembler::lddf_op3);
|
|
|
5350 ins_encode( form3_mem_reg( mem, dst ) );
|
|
|
5351 ins_pipe(floadD_mem);
|
|
|
5352 %}
|
|
|
5353
|
|
|
5354 // Load Range
|
|
|
5355 instruct loadRange(iRegI dst, memory mem) %{
|
|
|
5356 match(Set dst (LoadRange mem));
|
|
|
5357 ins_cost(MEMORY_REF_COST);
|
|
|
5358
|
|
|
5359 size(4);
|
|
|
5360 format %{ "LDUW $mem,$dst\t! range" %}
|
|
|
5361 opcode(Assembler::lduw_op3);
|
|
|
5362 ins_encode( form3_mem_reg( mem, dst ) );
|
|
|
5363 ins_pipe(iload_mem);
|
|
|
5364 %}
|
|
|
5365
|
|
|
5366 // Load Integer into %f register (for fitos/fitod)
|
|
|
5367 instruct loadI_freg(regF dst, memory mem) %{
|
|
|
5368 match(Set dst (LoadI mem));
|
|
|
5369 ins_cost(MEMORY_REF_COST);
|
|
|
5370 size(4);
|
|
|
5371
|
|
|
5372 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
|
|
|
5373 opcode(Assembler::ldf_op3);
|
|
|
5374 ins_encode( form3_mem_reg( mem, dst ) );
|
|
|
5375 ins_pipe(floadF_mem);
|
|
|
5376 %}
|
|
|
5377
|
|
|
5378 // Load Pointer
|
|
|
5379 instruct loadP(iRegP dst, memory mem) %{
|
|
|
5380 match(Set dst (LoadP mem));
|
|
|
5381 ins_cost(MEMORY_REF_COST);
|
|
|
5382 size(4);
|
|
|
5383
|
|
|
5384 #ifndef _LP64
|
|
|
5385 format %{ "LDUW $mem,$dst\t! ptr" %}
|
|
|
5386 opcode(Assembler::lduw_op3, 0, REGP_OP);
|
|
|
5387 #else
|
|
|
5388 format %{ "LDX $mem,$dst\t! ptr" %}
|
|
|
5389 opcode(Assembler::ldx_op3, 0, REGP_OP);
|
|
|
5390 #endif
|
|
|
5391 ins_encode( form3_mem_reg( mem, dst ) );
|
|
|
5392 ins_pipe(iload_mem);
|
|
|
5393 %}
|
|
|
5394
|
|
|
5395 // Load Klass Pointer
|
|
|
5396 instruct loadKlass(iRegP dst, memory mem) %{
|
|
|
5397 match(Set dst (LoadKlass mem));
|
|
|
5398 ins_cost(MEMORY_REF_COST);
|
|
|
5399 size(4);
|
|
|
5400
|
|
|
5401 #ifndef _LP64
|
|
|
5402 format %{ "LDUW $mem,$dst\t! klass ptr" %}
|
|
|
5403 opcode(Assembler::lduw_op3, 0, REGP_OP);
|
|
|
5404 #else
|
|
|
5405 format %{ "LDX $mem,$dst\t! klass ptr" %}
|
|
|
5406 opcode(Assembler::ldx_op3, 0, REGP_OP);
|
|
|
5407 #endif
|
|
|
5408 ins_encode( form3_mem_reg( mem, dst ) );
|
|
|
5409 ins_pipe(iload_mem);
|
|
|
5410 %}
|
|
|
5411
|
|
|
5412 // Load Short (16bit signed)
|
|
|
5413 instruct loadS(iRegI dst, memory mem) %{
|
|
|
5414 match(Set dst (LoadS mem));
|
|
|
5415 ins_cost(MEMORY_REF_COST);
|
|
|
5416
|
|
|
5417 size(4);
|
|
|
5418 format %{ "LDSH $mem,$dst" %}
|
|
|
5419 opcode(Assembler::ldsh_op3);
|
|
|
5420 ins_encode( form3_mem_reg( mem, dst ) );
|
|
|
5421 ins_pipe(iload_mask_mem);
|
|
|
5422 %}
|
|
|
5423
|
|
|
5424 // Load Double
|
|
|
5425 instruct loadD(regD dst, memory mem) %{
|
|
|
5426 match(Set dst (LoadD mem));
|
|
|
5427 ins_cost(MEMORY_REF_COST);
|
|
|
5428
|
|
|
5429 size(4);
|
|
|
5430 format %{ "LDDF $mem,$dst" %}
|
|
|
5431 opcode(Assembler::lddf_op3);
|
|
|
5432 ins_encode( form3_mem_reg( mem, dst ) );
|
|
|
5433 ins_pipe(floadD_mem);
|
|
|
5434 %}
|
|
|
5435
|
|
|
5436 // Load Double - UNaligned
|
|
|
5437 instruct loadD_unaligned(regD_low dst, memory mem ) %{
|
|
|
5438 match(Set dst (LoadD_unaligned mem));
|
|
|
5439 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
|
|
|
5440 size(8);
|
|
|
5441 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
|
|
|
5442 "\tLDF $mem+4,$dst.lo\t!" %}
|
|
|
5443 opcode(Assembler::ldf_op3);
|
|
|
5444 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
|
|
|
5445 ins_pipe(iload_mem);
|
|
|
5446 %}
|
|
|
5447
|
|
|
5448 // Load Float
|
|
|
5449 instruct loadF(regF dst, memory mem) %{
|
|
|
5450 match(Set dst (LoadF mem));
|
|
|
5451 ins_cost(MEMORY_REF_COST);
|
|
|
5452
|
|
|
5453 size(4);
|
|
|
5454 format %{ "LDF $mem,$dst" %}
|
|
|
5455 opcode(Assembler::ldf_op3);
|
|
|
5456 ins_encode( form3_mem_reg( mem, dst ) );
|
|
|
5457 ins_pipe(floadF_mem);
|
|
|
5458 %}
|
|
|
5459
|
|
|
5460 // Load Constant
|
|
|
5461 instruct loadConI( iRegI dst, immI src ) %{
|
|
|
5462 match(Set dst src);
|
|
|
5463 ins_cost(DEFAULT_COST * 3/2);
|
|
|
5464 format %{ "SET $src,$dst" %}
|
|
|
5465 ins_encode( Set32(src, dst) );
|
|
|
5466 ins_pipe(ialu_hi_lo_reg);
|
|
|
5467 %}
|
|
|
5468
|
|
|
5469 instruct loadConI13( iRegI dst, immI13 src ) %{
|
|
|
5470 match(Set dst src);
|
|
|
5471
|
|
|
5472 size(4);
|
|
|
5473 format %{ "MOV $src,$dst" %}
|
|
|
5474 ins_encode( Set13( src, dst ) );
|
|
|
5475 ins_pipe(ialu_imm);
|
|
|
5476 %}
|
|
|
5477
|
|
|
5478 instruct loadConP(iRegP dst, immP src) %{
|
|
|
5479 match(Set dst src);
|
|
|
5480 ins_cost(DEFAULT_COST * 3/2);
|
|
|
5481 format %{ "SET $src,$dst\t!ptr" %}
|
|
|
5482 // This rule does not use "expand" unlike loadConI because then
|
|
|
5483 // the result type is not known to be an Oop. An ADLC
|
|
|
5484 // enhancement will be needed to make that work - not worth it!
|
|
|
5485
|
|
|
5486 ins_encode( SetPtr( src, dst ) );
|
|
|
5487 ins_pipe(loadConP);
|
|
|
5488
|
|
|
5489 %}
|
|
|
5490
|
|
|
5491 instruct loadConP0(iRegP dst, immP0 src) %{
|
|
|
5492 match(Set dst src);
|
|
|
5493
|
|
|
5494 size(4);
|
|
|
5495 format %{ "CLR $dst\t!ptr" %}
|
|
|
5496 ins_encode( SetNull( dst ) );
|
|
|
5497 ins_pipe(ialu_imm);
|
|
|
5498 %}
|
|
|
5499
|
|
|
5500 instruct loadConP_poll(iRegP dst, immP_poll src) %{
|
|
|
5501 match(Set dst src);
|
|
|
5502 ins_cost(DEFAULT_COST);
|
|
|
5503 format %{ "SET $src,$dst\t!ptr" %}
|
|
|
5504 ins_encode %{
|
|
|
5505 Address polling_page(reg_to_register_object($dst$$reg), (address)os::get_polling_page());
|
|
|
5506 __ sethi(polling_page, false );
|
|
|
5507 %}
|
|
|
5508 ins_pipe(loadConP_poll);
|
|
|
5509 %}
|
|
|
5510
|
|
|
5511 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{
|
|
|
5512 // %%% maybe this should work like loadConD
|
|
|
5513 match(Set dst src);
|
|
|
5514 effect(KILL tmp);
|
|
|
5515 ins_cost(DEFAULT_COST * 4);
|
|
|
5516 format %{ "SET64 $src,$dst KILL $tmp\t! long" %}
|
|
|
5517 ins_encode( LdImmL(src, dst, tmp) );
|
|
|
5518 ins_pipe(loadConL);
|
|
|
5519 %}
|
|
|
5520
|
|
|
5521 instruct loadConL0( iRegL dst, immL0 src ) %{
|
|
|
5522 match(Set dst src);
|
|
|
5523 ins_cost(DEFAULT_COST);
|
|
|
5524 size(4);
|
|
|
5525 format %{ "CLR $dst\t! long" %}
|
|
|
5526 ins_encode( Set13( src, dst ) );
|
|
|
5527 ins_pipe(ialu_imm);
|
|
|
5528 %}
|
|
|
5529
|
|
|
5530 instruct loadConL13( iRegL dst, immL13 src ) %{
|
|
|
5531 match(Set dst src);
|
|
|
5532 ins_cost(DEFAULT_COST * 2);
|
|
|
5533
|
|
|
5534 size(4);
|
|
|
5535 format %{ "MOV $src,$dst\t! long" %}
|
|
|
5536 ins_encode( Set13( src, dst ) );
|
|
|
5537 ins_pipe(ialu_imm);
|
|
|
5538 %}
|
|
|
5539
|
|
|
5540 instruct loadConF(regF dst, immF src, o7RegP tmp) %{
|
|
|
5541 match(Set dst src);
|
|
|
5542 effect(KILL tmp);
|
|
|
5543
|
|
|
5544 #ifdef _LP64
|
|
|
5545 size(36);
|
|
|
5546 #else
|
|
|
5547 size(8);
|
|
|
5548 #endif
|
|
|
5549
|
|
|
5550 format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t"
|
|
|
5551 "LDF [$tmp+lo(&$src)],$dst" %}
|
|
|
5552 ins_encode( LdImmF(src, dst, tmp) );
|
|
|
5553 ins_pipe(loadConFD);
|
|
|
5554 %}
|
|
|
5555
|
|
|
5556 instruct loadConD(regD dst, immD src, o7RegP tmp) %{
|
|
|
5557 match(Set dst src);
|
|
|
5558 effect(KILL tmp);
|
|
|
5559
|
|
|
5560 #ifdef _LP64
|
|
|
5561 size(36);
|
|
|
5562 #else
|
|
|
5563 size(8);
|
|
|
5564 #endif
|
|
|
5565
|
|
|
5566 format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t"
|
|
|
5567 "LDDF [$tmp+lo(&$src)],$dst" %}
|
|
|
5568 ins_encode( LdImmD(src, dst, tmp) );
|
|
|
5569 ins_pipe(loadConFD);
|
|
|
5570 %}
|
|
|
5571
|
|
|
5572 // Prefetch instructions.
|
|
|
5573 // Must be safe to execute with invalid address (cannot fault).
|
|
|
5574
|
|
|
5575 instruct prefetchr( memory mem ) %{
|
|
|
5576 match( PrefetchRead mem );
|
|
|
5577 ins_cost(MEMORY_REF_COST);
|
|
|
5578
|
|
|
5579 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
|
|
|
5580 opcode(Assembler::prefetch_op3);
|
|
|
5581 ins_encode( form3_mem_prefetch_read( mem ) );
|
|
|
5582 ins_pipe(iload_mem);
|
|
|
5583 %}
|
|
|
5584
|
|
|
5585 instruct prefetchw( memory mem ) %{
|
|
|
5586 match( PrefetchWrite mem );
|
|
|
5587 ins_cost(MEMORY_REF_COST);
|
|
|
5588
|
|
|
5589 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
|
|
|
5590 opcode(Assembler::prefetch_op3);
|
|
|
5591 ins_encode( form3_mem_prefetch_write( mem ) );
|
|
|
5592 ins_pipe(iload_mem);
|
|
|
5593 %}
|
|
|
5594
|
|
|
5595
|
|
|
5596 //----------Store Instructions-------------------------------------------------
|
|
|
5597 // Store Byte
|
|
|
5598 instruct storeB(memory mem, iRegI src) %{
|
|
|
5599 match(Set mem (StoreB mem src));
|
|
|
5600 ins_cost(MEMORY_REF_COST);
|
|
|
5601
|
|
|
5602 size(4);
|
|
|
5603 format %{ "STB $src,$mem\t! byte" %}
|
|
|
5604 opcode(Assembler::stb_op3);
|
|
|
5605 ins_encode( form3_mem_reg( mem, src ) );
|
|
|
5606 ins_pipe(istore_mem_reg);
|
|
|
5607 %}
|
|
|
5608
|
|
|
5609 instruct storeB0(memory mem, immI0 src) %{
|
|
|
5610 match(Set mem (StoreB mem src));
|
|
|
5611 ins_cost(MEMORY_REF_COST);
|
|
|
5612
|
|
|
5613 size(4);
|
|
|
5614 format %{ "STB $src,$mem\t! byte" %}
|
|
|
5615 opcode(Assembler::stb_op3);
|
|
|
5616 ins_encode( form3_mem_reg( mem, R_G0 ) );
|
|
|
5617 ins_pipe(istore_mem_zero);
|
|
|
5618 %}
|
|
|
5619
|
|
|
5620 instruct storeCM0(memory mem, immI0 src) %{
|
|
|
5621 match(Set mem (StoreCM mem src));
|
|
|
5622 ins_cost(MEMORY_REF_COST);
|
|
|
5623
|
|
|
5624 size(4);
|
|
|
5625 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
|
|
|
5626 opcode(Assembler::stb_op3);
|
|
|
5627 ins_encode( form3_mem_reg( mem, R_G0 ) );
|
|
|
5628 ins_pipe(istore_mem_zero);
|
|
|
5629 %}
|
|
|
5630
|
|
|
5631 // Store Char/Short
|
|
|
5632 instruct storeC(memory mem, iRegI src) %{
|
|
|
5633 match(Set mem (StoreC mem src));
|
|
|
5634 ins_cost(MEMORY_REF_COST);
|
|
|
5635
|
|
|
5636 size(4);
|
|
|
5637 format %{ "STH $src,$mem\t! short" %}
|
|
|
5638 opcode(Assembler::sth_op3);
|
|
|
5639 ins_encode( form3_mem_reg( mem, src ) );
|
|
|
5640 ins_pipe(istore_mem_reg);
|
|
|
5641 %}
|
|
|
5642
|
|
|
5643 instruct storeC0(memory mem, immI0 src) %{
|
|
|
5644 match(Set mem (StoreC mem src));
|
|
|
5645 ins_cost(MEMORY_REF_COST);
|
|
|
5646
|
|
|
5647 size(4);
|
|
|
5648 format %{ "STH $src,$mem\t! short" %}
|
|
|
5649 opcode(Assembler::sth_op3);
|
|
|
5650 ins_encode( form3_mem_reg( mem, R_G0 ) );
|
|
|
5651 ins_pipe(istore_mem_zero);
|
|
|
5652 %}
|
|
|
5653
|
|
|
5654 // Store Integer
|
|
|
5655 instruct storeI(memory mem, iRegI src) %{
|
|
|
5656 match(Set mem (StoreI mem src));
|
|
|
5657 ins_cost(MEMORY_REF_COST);
|
|
|
5658
|
|
|
5659 size(4);
|
|
|
5660 format %{ "STW $src,$mem" %}
|
|
|
5661 opcode(Assembler::stw_op3);
|
|
|
5662 ins_encode( form3_mem_reg( mem, src ) );
|
|
|
5663 ins_pipe(istore_mem_reg);
|
|
|
5664 %}
|
|
|
5665
|
|
|
5666 // Store Long
|
|
|
5667 instruct storeL(memory mem, iRegL src) %{
|
|
|
5668 match(Set mem (StoreL mem src));
|
|
|
5669 ins_cost(MEMORY_REF_COST);
|
|
|
5670 size(4);
|
|
|
5671 format %{ "STX $src,$mem\t! long" %}
|
|
|
5672 opcode(Assembler::stx_op3);
|
|
|
5673 ins_encode( form3_mem_reg( mem, src ) );
|
|
|
5674 ins_pipe(istore_mem_reg);
|
|
|
5675 %}
|
|
|
5676
|
|
|
5677 instruct storeI0(memory mem, immI0 src) %{
|
|
|
5678 match(Set mem (StoreI mem src));
|
|
|
5679 ins_cost(MEMORY_REF_COST);
|
|
|
5680
|
|
|
5681 size(4);
|
|
|
5682 format %{ "STW $src,$mem" %}
|
|
|
5683 opcode(Assembler::stw_op3);
|
|
|
5684 ins_encode( form3_mem_reg( mem, R_G0 ) );
|
|
|
5685 ins_pipe(istore_mem_zero);
|
|
|
5686 %}
|
|
|
5687
|
|
|
5688 instruct storeL0(memory mem, immL0 src) %{
|
|
|
5689 match(Set mem (StoreL mem src));
|
|
|
5690 ins_cost(MEMORY_REF_COST);
|
|
|
5691
|
|
|
5692 size(4);
|
|
|
5693 format %{ "STX $src,$mem" %}
|
|
|
5694 opcode(Assembler::stx_op3);
|
|
|
5695 ins_encode( form3_mem_reg( mem, R_G0 ) );
|
|
|
5696 ins_pipe(istore_mem_zero);
|
|
|
5697 %}
|
|
|
5698
|
|
|
5699 // Store Integer from float register (used after fstoi)
|
|
|
5700 instruct storeI_Freg(memory mem, regF src) %{
|
|
|
5701 match(Set mem (StoreI mem src));
|
|
|
5702 ins_cost(MEMORY_REF_COST);
|
|
|
5703
|
|
|
5704 size(4);
|
|
|
5705 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
|
|
|
5706 opcode(Assembler::stf_op3);
|
|
|
5707 ins_encode( form3_mem_reg( mem, src ) );
|
|
|
5708 ins_pipe(fstoreF_mem_reg);
|
|
|
5709 %}
|
|
|
5710
|
|
|
5711 // Store Pointer
|
|
|
5712 instruct storeP(memory dst, sp_ptr_RegP src) %{
|
|
|
5713 match(Set dst (StoreP dst src));
|
|
|
5714 ins_cost(MEMORY_REF_COST);
|
|
|
5715 size(4);
|
|
|
5716
|
|
|
5717 #ifndef _LP64
|
|
|
5718 format %{ "STW $src,$dst\t! ptr" %}
|
|
|
5719 opcode(Assembler::stw_op3, 0, REGP_OP);
|
|
|
5720 #else
|
|
|
5721 format %{ "STX $src,$dst\t! ptr" %}
|
|
|
5722 opcode(Assembler::stx_op3, 0, REGP_OP);
|
|
|
5723 #endif
|
|
|
5724 ins_encode( form3_mem_reg( dst, src ) );
|
|
|
5725 ins_pipe(istore_mem_spORreg);
|
|
|
5726 %}
|
|
|
5727
|
|
|
5728 instruct storeP0(memory dst, immP0 src) %{
|
|
|
5729 match(Set dst (StoreP dst src));
|
|
|
5730 ins_cost(MEMORY_REF_COST);
|
|
|
5731 size(4);
|
|
|
5732
|
|
|
5733 #ifndef _LP64
|
|
|
5734 format %{ "STW $src,$dst\t! ptr" %}
|
|
|
5735 opcode(Assembler::stw_op3, 0, REGP_OP);
|
|
|
5736 #else
|
|
|
5737 format %{ "STX $src,$dst\t! ptr" %}
|
|
|
5738 opcode(Assembler::stx_op3, 0, REGP_OP);
|
|
|
5739 #endif
|
|
|
5740 ins_encode( form3_mem_reg( dst, R_G0 ) );
|
|
|
5741 ins_pipe(istore_mem_zero);
|
|
|
5742 %}
|
|
|
5743
|
|
|
5744 // Store Double
|
|
|
5745 instruct storeD( memory mem, regD src) %{
|
|
|
5746 match(Set mem (StoreD mem src));
|
|
|
5747 ins_cost(MEMORY_REF_COST);
|
|
|
5748
|
|
|
5749 size(4);
|
|
|
5750 format %{ "STDF $src,$mem" %}
|
|
|
5751 opcode(Assembler::stdf_op3);
|
|
|
5752 ins_encode( form3_mem_reg( mem, src ) );
|
|
|
5753 ins_pipe(fstoreD_mem_reg);
|
|
|
5754 %}
|
|
|
5755
|
|
|
5756 instruct storeD0( memory mem, immD0 src) %{
|
|
|
5757 match(Set mem (StoreD mem src));
|
|
|
5758 ins_cost(MEMORY_REF_COST);
|
|
|
5759
|
|
|
5760 size(4);
|
|
|
5761 format %{ "STX $src,$mem" %}
|
|
|
5762 opcode(Assembler::stx_op3);
|
|
|
5763 ins_encode( form3_mem_reg( mem, R_G0 ) );
|
|
|
5764 ins_pipe(fstoreD_mem_zero);
|
|
|
5765 %}
|
|
|
5766
|
|
|
5767 // Store Float
|
|
|
5768 instruct storeF( memory mem, regF src) %{
|
|
|
5769 match(Set mem (StoreF mem src));
|
|
|
5770 ins_cost(MEMORY_REF_COST);
|
|
|
5771
|
|
|
5772 size(4);
|
|
|
5773 format %{ "STF $src,$mem" %}
|
|
|
5774 opcode(Assembler::stf_op3);
|
|
|
5775 ins_encode( form3_mem_reg( mem, src ) );
|
|
|
5776 ins_pipe(fstoreF_mem_reg);
|
|
|
5777 %}
|
|
|
5778
|
|
|
5779 instruct storeF0( memory mem, immF0 src) %{
|
|
|
5780 match(Set mem (StoreF mem src));
|
|
|
5781 ins_cost(MEMORY_REF_COST);
|
|
|
5782
|
|
|
5783 size(4);
|
|
|
5784 format %{ "STW $src,$mem\t! storeF0" %}
|
|
|
5785 opcode(Assembler::stw_op3);
|
|
|
5786 ins_encode( form3_mem_reg( mem, R_G0 ) );
|
|
|
5787 ins_pipe(fstoreF_mem_zero);
|
|
|
5788 %}
|
|
|
5789
|
|
|
5790 // Store Aligned Packed Bytes in Double register to memory
|
|
|
5791 instruct storeA8B(memory mem, regD src) %{
|
|
|
5792 match(Set mem (Store8B mem src));
|
|
|
5793 ins_cost(MEMORY_REF_COST);
|
|
|
5794 size(4);
|
|
|
5795 format %{ "STDF $src,$mem\t! packed8B" %}
|
|
|
5796 opcode(Assembler::stdf_op3);
|
|
|
5797 ins_encode( form3_mem_reg( mem, src ) );
|
|
|
5798 ins_pipe(fstoreD_mem_reg);
|
|
|
5799 %}
|
|
|
5800
|
|
|
5801 // Store Zero into Aligned Packed Bytes
|
|
|
5802 instruct storeA8B0(memory mem, immI0 zero) %{
|
|
|
5803 match(Set mem (Store8B mem zero));
|
|
|
5804 ins_cost(MEMORY_REF_COST);
|
|
|
5805 size(4);
|
|
|
5806 format %{ "STX $zero,$mem\t! packed8B" %}
|
|
|
5807 opcode(Assembler::stx_op3);
|
|
|
5808 ins_encode( form3_mem_reg( mem, R_G0 ) );
|
|
|
5809 ins_pipe(fstoreD_mem_zero);
|
|
|
5810 %}
|
|
|
5811
|
|
|
5812 // Store Aligned Packed Chars/Shorts in Double register to memory
|
|
|
5813 instruct storeA4C(memory mem, regD src) %{
|
|
|
5814 match(Set mem (Store4C mem src));
|
|
|
5815 ins_cost(MEMORY_REF_COST);
|
|
|
5816 size(4);
|
|
|
5817 format %{ "STDF $src,$mem\t! packed4C" %}
|
|
|
5818 opcode(Assembler::stdf_op3);
|
|
|
5819 ins_encode( form3_mem_reg( mem, src ) );
|
|
|
5820 ins_pipe(fstoreD_mem_reg);
|
|
|
5821 %}
|
|
|
5822
|
|
|
5823 // Store Zero into Aligned Packed Chars/Shorts
|
|
|
5824 instruct storeA4C0(memory mem, immI0 zero) %{
|
|
|
5825 match(Set mem (Store4C mem (Replicate4C zero)));
|
|
|
5826 ins_cost(MEMORY_REF_COST);
|
|
|
5827 size(4);
|
|
|
5828 format %{ "STX $zero,$mem\t! packed4C" %}
|
|
|
5829 opcode(Assembler::stx_op3);
|
|
|
5830 ins_encode( form3_mem_reg( mem, R_G0 ) );
|
|
|
5831 ins_pipe(fstoreD_mem_zero);
|
|
|
5832 %}
|
|
|
5833
|
|
|
5834 // Store Aligned Packed Ints in Double register to memory
|
|
|
5835 instruct storeA2I(memory mem, regD src) %{
|
|
|
5836 match(Set mem (Store2I mem src));
|
|
|
5837 ins_cost(MEMORY_REF_COST);
|
|
|
5838 size(4);
|
|
|
5839 format %{ "STDF $src,$mem\t! packed2I" %}
|
|
|
5840 opcode(Assembler::stdf_op3);
|
|
|
5841 ins_encode( form3_mem_reg( mem, src ) );
|
|
|
5842 ins_pipe(fstoreD_mem_reg);
|
|
|
5843 %}
|
|
|
5844
|
|
|
5845 // Store Zero into Aligned Packed Ints
|
|
|
5846 instruct storeA2I0(memory mem, immI0 zero) %{
|
|
|
5847 match(Set mem (Store2I mem zero));
|
|
|
5848 ins_cost(MEMORY_REF_COST);
|
|
|
5849 size(4);
|
|
|
5850 format %{ "STX $zero,$mem\t! packed2I" %}
|
|
|
5851 opcode(Assembler::stx_op3);
|
|
|
5852 ins_encode( form3_mem_reg( mem, R_G0 ) );
|
|
|
5853 ins_pipe(fstoreD_mem_zero);
|
|
|
5854 %}
|
|
|
5855
|
|
|
5856
|
|
|
5857 //----------MemBar Instructions-----------------------------------------------
|
|
|
5858 // Memory barrier flavors
|
|
|
5859
|
|
|
5860 instruct membar_acquire() %{
|
|
|
5861 match(MemBarAcquire);
|
|
|
5862 ins_cost(4*MEMORY_REF_COST);
|
|
|
5863
|
|
|
5864 size(0);
|
|
|
5865 format %{ "MEMBAR-acquire" %}
|
|
|
5866 ins_encode( enc_membar_acquire );
|
|
|
5867 ins_pipe(long_memory_op);
|
|
|
5868 %}
|
|
|
5869
|
|
|
5870 instruct membar_acquire_lock() %{
|
|
|
5871 match(MemBarAcquire);
|
|
|
5872 predicate(Matcher::prior_fast_lock(n));
|
|
|
5873 ins_cost(0);
|
|
|
5874
|
|
|
5875 size(0);
|
|
|
5876 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
|
|
|
5877 ins_encode( );
|
|
|
5878 ins_pipe(empty);
|
|
|
5879 %}
|
|
|
5880
|
|
|
5881 instruct membar_release() %{
|
|
|
5882 match(MemBarRelease);
|
|
|
5883 ins_cost(4*MEMORY_REF_COST);
|
|
|
5884
|
|
|
5885 size(0);
|
|
|
5886 format %{ "MEMBAR-release" %}
|
|
|
5887 ins_encode( enc_membar_release );
|
|
|
5888 ins_pipe(long_memory_op);
|
|
|
5889 %}
|
|
|
5890
|
|
|
5891 instruct membar_release_lock() %{
|
|
|
5892 match(MemBarRelease);
|
|
|
5893 predicate(Matcher::post_fast_unlock(n));
|
|
|
5894 ins_cost(0);
|
|
|
5895
|
|
|
5896 size(0);
|
|
|
5897 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
|
|
|
5898 ins_encode( );
|
|
|
5899 ins_pipe(empty);
|
|
|
5900 %}
|
|
|
5901
|
|
|
5902 instruct membar_volatile() %{
|
|
|
5903 match(MemBarVolatile);
|
|
|
5904 ins_cost(4*MEMORY_REF_COST);
|
|
|
5905
|
|
|
5906 size(4);
|
|
|
5907 format %{ "MEMBAR-volatile" %}
|
|
|
5908 ins_encode( enc_membar_volatile );
|
|
|
5909 ins_pipe(long_memory_op);
|
|
|
5910 %}
|
|
|
5911
|
|
|
5912 instruct unnecessary_membar_volatile() %{
|
|
|
5913 match(MemBarVolatile);
|
|
|
5914 predicate(Matcher::post_store_load_barrier(n));
|
|
|
5915 ins_cost(0);
|
|
|
5916
|
|
|
5917 size(0);
|
|
|
5918 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
|
|
|
5919 ins_encode( );
|
|
|
5920 ins_pipe(empty);
|
|
|
5921 %}
|
|
|
5922
|
|
|
5923 //----------Register Move Instructions-----------------------------------------
|
|
|
5924 instruct roundDouble_nop(regD dst) %{
|
|
|
5925 match(Set dst (RoundDouble dst));
|
|
|
5926 ins_cost(0);
|
|
|
5927 // SPARC results are already "rounded" (i.e., normal-format IEEE)
|
|
|
5928 ins_encode( );
|
|
|
5929 ins_pipe(empty);
|
|
|
5930 %}
|
|
|
5931
|
|
|
5932
|
|
|
5933 instruct roundFloat_nop(regF dst) %{
|
|
|
5934 match(Set dst (RoundFloat dst));
|
|
|
5935 ins_cost(0);
|
|
|
5936 // SPARC results are already "rounded" (i.e., normal-format IEEE)
|
|
|
5937 ins_encode( );
|
|
|
5938 ins_pipe(empty);
|
|
|
5939 %}
|
|
|
5940
|
|
|
5941
|
|
|
5942 // Cast Index to Pointer for unsafe natives
|
|
|
5943 instruct castX2P(iRegX src, iRegP dst) %{
|
|
|
5944 match(Set dst (CastX2P src));
|
|
|
5945
|
|
|
5946 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
|
|
|
5947 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
|
|
|
5948 ins_pipe(ialu_reg);
|
|
|
5949 %}
|
|
|
5950
|
|
|
5951 // Cast Pointer to Index for unsafe natives
|
|
|
5952 instruct castP2X(iRegP src, iRegX dst) %{
|
|
|
5953 match(Set dst (CastP2X src));
|
|
|
5954
|
|
|
5955 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
|
|
|
5956 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
|
|
|
5957 ins_pipe(ialu_reg);
|
|
|
5958 %}
|
|
|
5959
|
|
|
5960 instruct stfSSD(stackSlotD stkSlot, regD src) %{
|
|
|
5961 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
|
|
|
5962 match(Set stkSlot src); // chain rule
|
|
|
5963 ins_cost(MEMORY_REF_COST);
|
|
|
5964 format %{ "STDF $src,$stkSlot\t!stk" %}
|
|
|
5965 opcode(Assembler::stdf_op3);
|
|
|
5966 ins_encode(form3_mem_reg(stkSlot, src));
|
|
|
5967 ins_pipe(fstoreD_stk_reg);
|
|
|
5968 %}
|
|
|
5969
|
|
|
5970 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
|
|
|
5971 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
|
|
|
5972 match(Set dst stkSlot); // chain rule
|
|
|
5973 ins_cost(MEMORY_REF_COST);
|
|
|
5974 format %{ "LDDF $stkSlot,$dst\t!stk" %}
|
|
|
5975 opcode(Assembler::lddf_op3);
|
|
|
5976 ins_encode(form3_mem_reg(stkSlot, dst));
|
|
|
5977 ins_pipe(floadD_stk);
|
|
|
5978 %}
|
|
|
5979
|
|
|
5980 instruct stfSSF(stackSlotF stkSlot, regF src) %{
|
|
|
5981 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
|
|
|
5982 match(Set stkSlot src); // chain rule
|
|
|
5983 ins_cost(MEMORY_REF_COST);
|
|
|
5984 format %{ "STF $src,$stkSlot\t!stk" %}
|
|
|
5985 opcode(Assembler::stf_op3);
|
|
|
5986 ins_encode(form3_mem_reg(stkSlot, src));
|
|
|
5987 ins_pipe(fstoreF_stk_reg);
|
|
|
5988 %}
|
|
|
5989
|
|
|
5990 //----------Conditional Move---------------------------------------------------
|
|
|
5991 // Conditional move
|
|
|
5992 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
|
|
|
5993 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
|
|
|
5994 ins_cost(150);
|
|
|
5995 format %{ "MOV$cmp $pcc,$src,$dst" %}
|
|
|
5996 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
|
|
|
5997 ins_pipe(ialu_reg);
|
|
|
5998 %}
|
|
|
5999
|
|
|
6000 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
|
|
|
6001 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
|
|
|
6002 ins_cost(140);
|
|
|
6003 format %{ "MOV$cmp $pcc,$src,$dst" %}
|
|
|
6004 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
|
|
|
6005 ins_pipe(ialu_imm);
|
|
|
6006 %}
|
|
|
6007
|
|
|
6008 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
|
|
|
6009 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
|
|
|
6010 ins_cost(150);
|
|
|
6011 size(4);
|
|
|
6012 format %{ "MOV$cmp $icc,$src,$dst" %}
|
|
|
6013 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
|
|
|
6014 ins_pipe(ialu_reg);
|
|
|
6015 %}
|
|
|
6016
|
|
|
6017 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
|
|
|
6018 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
|
|
|
6019 ins_cost(140);
|
|
|
6020 size(4);
|
|
|
6021 format %{ "MOV$cmp $icc,$src,$dst" %}
|
|
|
6022 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
|
|
|
6023 ins_pipe(ialu_imm);
|
|
|
6024 %}
|
|
|
6025
|
|
|
6026 instruct cmovII_U_reg(cmpOp cmp, flagsRegU icc, iRegI dst, iRegI src) %{
|
|
|
6027 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
|
|
|
6028 ins_cost(150);
|
|
|
6029 size(4);
|
|
|
6030 format %{ "MOV$cmp $icc,$src,$dst" %}
|
|
|
6031 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
|
|
|
6032 ins_pipe(ialu_reg);
|
|
|
6033 %}
|
|
|
6034
|
|
|
6035 instruct cmovII_U_imm(cmpOp cmp, flagsRegU icc, iRegI dst, immI11 src) %{
|
|
|
6036 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
|
|
|
6037 ins_cost(140);
|
|
|
6038 size(4);
|
|
|
6039 format %{ "MOV$cmp $icc,$src,$dst" %}
|
|
|
6040 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
|
|
|
6041 ins_pipe(ialu_imm);
|
|
|
6042 %}
|
|
|
6043
|
|
|
6044 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
|
|
|
6045 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
|
|
|
6046 ins_cost(150);
|
|
|
6047 size(4);
|
|
|
6048 format %{ "MOV$cmp $fcc,$src,$dst" %}
|
|
|
6049 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
|
|
|
6050 ins_pipe(ialu_reg);
|
|
|
6051 %}
|
|
|
6052
|
|
|
6053 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
|
|
|
6054 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
|
|
|
6055 ins_cost(140);
|
|
|
6056 size(4);
|
|
|
6057 format %{ "MOV$cmp $fcc,$src,$dst" %}
|
|
|
6058 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
|
|
|
6059 ins_pipe(ialu_imm);
|
|
|
6060 %}
|
|
|
6061
|
|
|
6062 // Conditional move
|
|
|
6063 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
|
|
|
6064 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
|
|
|
6065 ins_cost(150);
|
|
|
6066 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
|
|
|
6067 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
|
|
|
6068 ins_pipe(ialu_reg);
|
|
|
6069 %}
|
|
|
6070
|
|
|
6071 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
|
|
|
6072 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
|
|
|
6073 ins_cost(140);
|
|
|
6074 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
|
|
|
6075 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
|
|
|
6076 ins_pipe(ialu_imm);
|
|
|
6077 %}
|
|
|
6078
|
|
|
6079 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
|
|
|
6080 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
|
|
|
6081 ins_cost(150);
|
|
|
6082
|
|
|
6083 size(4);
|
|
|
6084 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
|
|
|
6085 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
|
|
|
6086 ins_pipe(ialu_reg);
|
|
|
6087 %}
|
|
|
6088
|
|
|
6089 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
|
|
|
6090 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
|
|
|
6091 ins_cost(140);
|
|
|
6092
|
|
|
6093 size(4);
|
|
|
6094 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
|
|
|
6095 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
|
|
|
6096 ins_pipe(ialu_imm);
|
|
|
6097 %}
|
|
|
6098
|
|
|
6099 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
|
|
|
6100 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
|
|
|
6101 ins_cost(150);
|
|
|
6102 size(4);
|
|
|
6103 format %{ "MOV$cmp $fcc,$src,$dst" %}
|
|
|
6104 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
|
|
|
6105 ins_pipe(ialu_imm);
|
|
|
6106 %}
|
|
|
6107
|
|
|
6108 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
|
|
|
6109 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
|
|
|
6110 ins_cost(140);
|
|
|
6111 size(4);
|
|
|
6112 format %{ "MOV$cmp $fcc,$src,$dst" %}
|
|
|
6113 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
|
|
|
6114 ins_pipe(ialu_imm);
|
|
|
6115 %}
|
|
|
6116
|
|
|
6117 // Conditional move
|
|
|
6118 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
|
|
|
6119 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
|
|
|
6120 ins_cost(150);
|
|
|
6121 opcode(0x101);
|
|
|
6122 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
|
|
|
6123 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
|
|
|
6124 ins_pipe(int_conditional_float_move);
|
|
|
6125 %}
|
|
|
6126
|
|
|
6127 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
|
|
|
6128 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
|
|
|
6129 ins_cost(150);
|
|
|
6130
|
|
|
6131 size(4);
|
|
|
6132 format %{ "FMOVS$cmp $icc,$src,$dst" %}
|
|
|
6133 opcode(0x101);
|
|
|
6134 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
|
|
|
6135 ins_pipe(int_conditional_float_move);
|
|
|
6136 %}
|
|
|
6137
|
|
|
6138 // Conditional move,
|
|
|
6139 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
|
|
|
6140 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
|
|
|
6141 ins_cost(150);
|
|
|
6142 size(4);
|
|
|
6143 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
|
|
|
6144 opcode(0x1);
|
|
|
6145 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
|
|
|
6146 ins_pipe(int_conditional_double_move);
|
|
|
6147 %}
|
|
|
6148
|
|
|
6149 // Conditional move
|
|
|
6150 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
|
|
|
6151 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
|
|
|
6152 ins_cost(150);
|
|
|
6153 size(4);
|
|
|
6154 opcode(0x102);
|
|
|
6155 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
|
|
|
6156 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
|
|
|
6157 ins_pipe(int_conditional_double_move);
|
|
|
6158 %}
|
|
|
6159
|
|
|
6160 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
|
|
|
6161 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
|
|
|
6162 ins_cost(150);
|
|
|
6163
|
|
|
6164 size(4);
|
|
|
6165 format %{ "FMOVD$cmp $icc,$src,$dst" %}
|
|
|
6166 opcode(0x102);
|
|
|
6167 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
|
|
|
6168 ins_pipe(int_conditional_double_move);
|
|
|
6169 %}
|
|
|
6170
|
|
|
6171 // Conditional move,
|
|
|
6172 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
|
|
|
6173 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
|
|
|
6174 ins_cost(150);
|
|
|
6175 size(4);
|
|
|
6176 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
|
|
|
6177 opcode(0x2);
|
|
|
6178 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
|
|
|
6179 ins_pipe(int_conditional_double_move);
|
|
|
6180 %}
|
|
|
6181
|
|
|
6182 // Conditional move
|
|
|
6183 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
|
|
|
6184 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
|
|
|
6185 ins_cost(150);
|
|
|
6186 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
|
|
|
6187 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
|
|
|
6188 ins_pipe(ialu_reg);
|
|
|
6189 %}
|
|
|
6190
|
|
|
6191 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
|
|
|
6192 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
|
|
|
6193 ins_cost(140);
|
|
|
6194 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
|
|
|
6195 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
|
|
|
6196 ins_pipe(ialu_imm);
|
|
|
6197 %}
|
|
|
6198
|
|
|
6199 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
|
|
|
6200 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
|
|
|
6201 ins_cost(150);
|
|
|
6202
|
|
|
6203 size(4);
|
|
|
6204 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
|
|
|
6205 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
|
|
|
6206 ins_pipe(ialu_reg);
|
|
|
6207 %}
|
|
|
6208
|
|
|
6209
|
|
|
6210 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
|
|
|
6211 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
|
|
|
6212 ins_cost(150);
|
|
|
6213
|
|
|
6214 size(4);
|
|
|
6215 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
|
|
|
6216 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
|
|
|
6217 ins_pipe(ialu_reg);
|
|
|
6218 %}
|
|
|
6219
|
|
|
6220
|
|
|
6221
|
|
|
6222 //----------OS and Locking Instructions----------------------------------------
|
|
|
6223
|
|
|
6224 // This name is KNOWN by the ADLC and cannot be changed.
|
|
|
6225 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
|
|
|
6226 // for this guy.
|
|
|
6227 instruct tlsLoadP(g2RegP dst) %{
|
|
|
6228 match(Set dst (ThreadLocal));
|
|
|
6229
|
|
|
6230 size(0);
|
|
|
6231 ins_cost(0);
|
|
|
6232 format %{ "# TLS is in G2" %}
|
|
|
6233 ins_encode( /*empty encoding*/ );
|
|
|
6234 ins_pipe(ialu_none);
|
|
|
6235 %}
|
|
|
6236
|
|
|
6237 instruct checkCastPP( iRegP dst ) %{
|
|
|
6238 match(Set dst (CheckCastPP dst));
|
|
|
6239
|
|
|
6240 size(0);
|
|
|
6241 format %{ "# checkcastPP of $dst" %}
|
|
|
6242 ins_encode( /*empty encoding*/ );
|
|
|
6243 ins_pipe(empty);
|
|
|
6244 %}
|
|
|
6245
|
|
|
6246
|
|
|
6247 instruct castPP( iRegP dst ) %{
|
|
|
6248 match(Set dst (CastPP dst));
|
|
|
6249 format %{ "# castPP of $dst" %}
|
|
|
6250 ins_encode( /*empty encoding*/ );
|
|
|
6251 ins_pipe(empty);
|
|
|
6252 %}
|
|
|
6253
|
|
|
6254 instruct castII( iRegI dst ) %{
|
|
|
6255 match(Set dst (CastII dst));
|
|
|
6256 format %{ "# castII of $dst" %}
|
|
|
6257 ins_encode( /*empty encoding*/ );
|
|
|
6258 ins_cost(0);
|
|
|
6259 ins_pipe(empty);
|
|
|
6260 %}
|
|
|
6261
|
|
|
6262 //----------Arithmetic Instructions--------------------------------------------
|
|
|
6263 // Addition Instructions
|
|
|
6264 // Register Addition
|
|
|
6265 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
|
|
|
6266 match(Set dst (AddI src1 src2));
|
|
|
6267
|
|
|
6268 size(4);
|
|
|
6269 format %{ "ADD $src1,$src2,$dst" %}
|
|
|
6270 ins_encode %{
|
|
|
6271 __ add($src1$$Register, $src2$$Register, $dst$$Register);
|
|
|
6272 %}
|
|
|
6273 ins_pipe(ialu_reg_reg);
|
|
|
6274 %}
|
|
|
6275
|
|
|
6276 // Immediate Addition
|
|
|
6277 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
|
|
|
6278 match(Set dst (AddI src1 src2));
|
|
|
6279
|
|
|
6280 size(4);
|
|
|
6281 format %{ "ADD $src1,$src2,$dst" %}
|
|
|
6282 opcode(Assembler::add_op3, Assembler::arith_op);
|
|
|
6283 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
|
|
|
6284 ins_pipe(ialu_reg_imm);
|
|
|
6285 %}
|
|
|
6286
|
|
|
6287 // Pointer Register Addition
|
|
|
6288 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
|
|
|
6289 match(Set dst (AddP src1 src2));
|
|
|
6290
|
|
|
6291 size(4);
|
|
|
6292 format %{ "ADD $src1,$src2,$dst" %}
|
|
|
6293 opcode(Assembler::add_op3, Assembler::arith_op);
|
|
|
6294 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
|
|
|
6295 ins_pipe(ialu_reg_reg);
|
|
|
6296 %}
|
|
|
6297
|
|
|
6298 // Pointer Immediate Addition
|
|
|
6299 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
|
|
|
6300 match(Set dst (AddP src1 src2));
|
|
|
6301
|
|
|
6302 size(4);
|
|
|
6303 format %{ "ADD $src1,$src2,$dst" %}
|
|
|
6304 opcode(Assembler::add_op3, Assembler::arith_op);
|
|
|
6305 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
|
|
|
6306 ins_pipe(ialu_reg_imm);
|
|
|
6307 %}
|
|
|
6308
|
|
|
6309 // Long Addition
|
|
|
6310 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
|
|
|
6311 match(Set dst (AddL src1 src2));
|
|
|
6312
|
|
|
6313 size(4);
|
|
|
6314 format %{ "ADD $src1,$src2,$dst\t! long" %}
|
|
|
6315 opcode(Assembler::add_op3, Assembler::arith_op);
|
|
|
6316 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
|
|
|
6317 ins_pipe(ialu_reg_reg);
|
|
|
6318 %}
|
|
|
6319
|
|
|
6320 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
|
|
|
6321 match(Set dst (AddL src1 con));
|
|
|
6322
|
|
|
6323 size(4);
|
|
|
6324 format %{ "ADD $src1,$con,$dst" %}
|
|
|
6325 opcode(Assembler::add_op3, Assembler::arith_op);
|
|
|
6326 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
|
|
|
6327 ins_pipe(ialu_reg_imm);
|
|
|
6328 %}
|
|
|
6329
|
|
|
6330 //----------Conditional_store--------------------------------------------------
|
|
|
6331 // Conditional-store of the updated heap-top.
|
|
|
6332 // Used during allocation of the shared heap.
|
|
|
6333 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
|
|
|
6334
|
|
|
6335 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
|
|
|
6336 instruct loadPLocked(iRegP dst, memory mem) %{
|
|
|
6337 match(Set dst (LoadPLocked mem));
|
|
|
6338 ins_cost(MEMORY_REF_COST);
|
|
|
6339
|
|
|
6340 #ifndef _LP64
|
|
|
6341 size(4);
|
|
|
6342 format %{ "LDUW $mem,$dst\t! ptr" %}
|
|
|
6343 opcode(Assembler::lduw_op3, 0, REGP_OP);
|
|
|
6344 #else
|
|
|
6345 format %{ "LDX $mem,$dst\t! ptr" %}
|
|
|
6346 opcode(Assembler::ldx_op3, 0, REGP_OP);
|
|
|
6347 #endif
|
|
|
6348 ins_encode( form3_mem_reg( mem, dst ) );
|
|
|
6349 ins_pipe(iload_mem);
|
|
|
6350 %}
|
|
|
6351
|
|
|
6352 // LoadL-locked. Same as a regular long load when used with a compare-swap
|
|
|
6353 instruct loadLLocked(iRegL dst, memory mem) %{
|
|
|
6354 match(Set dst (LoadLLocked mem));
|
|
|
6355 ins_cost(MEMORY_REF_COST);
|
|
|
6356 size(4);
|
|
|
6357 format %{ "LDX $mem,$dst\t! long" %}
|
|
|
6358 opcode(Assembler::ldx_op3);
|
|
|
6359 ins_encode( form3_mem_reg( mem, dst ) );
|
|
|
6360 ins_pipe(iload_mem);
|
|
|
6361 %}
|
|
|
6362
|
|
|
6363 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
|
|
|
6364 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
|
|
|
6365 effect( KILL newval );
|
|
|
6366 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
|
|
|
6367 "CMP R_G3,$oldval\t\t! See if we made progress" %}
|
|
|
6368 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
|
|
|
6369 ins_pipe( long_memory_op );
|
|
|
6370 %}
|
|
|
6371
|
|
|
6372 instruct storeLConditional_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
|
|
|
6373 match(Set res (StoreLConditional mem_ptr (Binary oldval newval)));
|
|
|
6374 effect( USE mem_ptr, KILL ccr, KILL tmp1);
|
|
|
6375 // Marshal the register pairs into V9 64-bit registers, then do the compare-and-swap
|
|
|
6376 format %{
|
|
|
6377 "MOV $newval,R_O7\n\t"
|
|
|
6378 "CASXA [$mem_ptr],$oldval,R_O7\t! If $oldval==[$mem_ptr] Then store R_O7 into [$mem_ptr], set R_O7=[$mem_ptr] in any case\n\t"
|
|
|
6379 "CMP $oldval,R_O7\t\t! See if we made progress\n\t"
|
|
|
6380 "MOV 1,$res\n\t"
|
|
|
6381 "MOVne xcc,R_G0,$res"
|
|
|
6382 %}
|
|
|
6383 ins_encode( enc_casx(mem_ptr, oldval, newval),
|
|
|
6384 enc_lflags_ne_to_boolean(res) );
|
|
|
6385 ins_pipe( long_memory_op );
|
|
|
6386 %}
|
|
|
6387
|
|
|
6388 instruct storeLConditional_flags(iRegP mem_ptr, iRegL oldval, iRegL newval, flagsRegL xcc, o7RegI tmp1, immI0 zero) %{
|
|
|
6389 match(Set xcc (CmpI (StoreLConditional mem_ptr (Binary oldval newval)) zero));
|
|
|
6390 effect( USE mem_ptr, KILL tmp1);
|
|
|
6391 // Marshal the register pairs into V9 64-bit registers, then do the compare-and-swap
|
|
|
6392 format %{
|
|
|
6393 "MOV $newval,R_O7\n\t"
|
|
|
6394 "CASXA [$mem_ptr],$oldval,R_O7\t! If $oldval==[$mem_ptr] Then store R_O7 into [$mem_ptr], set R_O7=[$mem_ptr] in any case\n\t"
|
|
|
6395 "CMP $oldval,R_O7\t\t! See if we made progress"
|
|
|
6396 %}
|
|
|
6397 ins_encode( enc_casx(mem_ptr, oldval, newval));
|
|
|
6398 ins_pipe( long_memory_op );
|
|
|
6399 %}
|
|
|
6400
|
|
|
6401 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
|
|
|
6402
|
|
|
6403 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
|
|
|
6404 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
|
|
|
6405 effect( USE mem_ptr, KILL ccr, KILL tmp1);
|
|
|
6406 format %{
|
|
|
6407 "MOV $newval,O7\n\t"
|
|
|
6408 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
|
|
|
6409 "CMP $oldval,O7\t\t! See if we made progress\n\t"
|
|
|
6410 "MOV 1,$res\n\t"
|
|
|
6411 "MOVne xcc,R_G0,$res"
|
|
|
6412 %}
|
|
|
6413 ins_encode( enc_casx(mem_ptr, oldval, newval),
|
|
|
6414 enc_lflags_ne_to_boolean(res) );
|
|
|
6415 ins_pipe( long_memory_op );
|
|
|
6416 %}
|
|
|
6417
|
|
|
6418
|
|
|
6419 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
|
|
|
6420 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
|
|
|
6421 effect( USE mem_ptr, KILL ccr, KILL tmp1);
|
|
|
6422 format %{
|
|
|
6423 "MOV $newval,O7\n\t"
|
|
|
6424 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
|
|
|
6425 "CMP $oldval,O7\t\t! See if we made progress\n\t"
|
|
|
6426 "MOV 1,$res\n\t"
|
|
|
6427 "MOVne icc,R_G0,$res"
|
|
|
6428 %}
|
|
|
6429 ins_encode( enc_casi(mem_ptr, oldval, newval),
|
|
|
6430 enc_iflags_ne_to_boolean(res) );
|
|
|
6431 ins_pipe( long_memory_op );
|
|
|
6432 %}
|
|
|
6433
|
|
|
6434 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
|
|
|
6435 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
|
|
|
6436 effect( USE mem_ptr, KILL ccr, KILL tmp1);
|
|
|
6437 #ifdef _LP64
|
|
|
6438 format %{
|
|
|
6439 "MOV $newval,O7\n\t"
|
|
|
6440 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
|
|
|
6441 "CMP $oldval,O7\t\t! See if we made progress\n\t"
|
|
|
6442 "MOV 1,$res\n\t"
|
|
|
6443 "MOVne xcc,R_G0,$res"
|
|
|
6444 %}
|
|
|
6445 ins_encode( enc_casx(mem_ptr, oldval, newval),
|
|
|
6446 enc_lflags_ne_to_boolean(res) );
|
|
|
6447 #else
|
|
|
6448 format %{
|
|
|
6449 "MOV $newval,O7\n\t"
|
|
|
6450 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
|
|
|
6451 "CMP $oldval,O7\t\t! See if we made progress\n\t"
|
|
|
6452 "MOV 1,$res\n\t"
|
|
|
6453 "MOVne icc,R_G0,$res"
|
|
|
6454 %}
|
|
|
6455 ins_encode( enc_casi(mem_ptr, oldval, newval),
|
|
|
6456 enc_iflags_ne_to_boolean(res) );
|
|
|
6457 #endif
|
|
|
6458 ins_pipe( long_memory_op );
|
|
|
6459 %}
|
|
|
6460
|
|
|
6461 //---------------------
|
|
|
6462 // Subtraction Instructions
|
|
|
6463 // Register Subtraction
|
|
|
6464 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
|
|
|
6465 match(Set dst (SubI src1 src2));
|
|
|
6466
|
|
|
6467 size(4);
|
|
|
6468 format %{ "SUB $src1,$src2,$dst" %}
|
|
|
6469 opcode(Assembler::sub_op3, Assembler::arith_op);
|
|
|
6470 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
|
|
|
6471 ins_pipe(ialu_reg_reg);
|
|
|
6472 %}
|
|
|
6473
|
|
|
6474 // Immediate Subtraction
|
|
|
6475 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
|
|
|
6476 match(Set dst (SubI src1 src2));
|
|
|
6477
|
|
|
6478 size(4);
|
|
|
6479 format %{ "SUB $src1,$src2,$dst" %}
|
|
|
6480 opcode(Assembler::sub_op3, Assembler::arith_op);
|
|
|
6481 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
|
|
|
6482 ins_pipe(ialu_reg_imm);
|
|
|
6483 %}
|
|
|
6484
|
|
|
6485 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
|
|
|
6486 match(Set dst (SubI zero src2));
|
|
|
6487
|
|
|
6488 size(4);
|
|
|
6489 format %{ "NEG $src2,$dst" %}
|
|
|
6490 opcode(Assembler::sub_op3, Assembler::arith_op);
|
|
|
6491 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
|
|
|
6492 ins_pipe(ialu_zero_reg);
|
|
|
6493 %}
|
|
|
6494
|
|
|
6495 // Long subtraction
|
|
|
6496 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
|
|
|
6497 match(Set dst (SubL src1 src2));
|
|
|
6498
|
|
|
6499 size(4);
|
|
|
6500 format %{ "SUB $src1,$src2,$dst\t! long" %}
|
|
|
6501 opcode(Assembler::sub_op3, Assembler::arith_op);
|
|
|
6502 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
|
|
|
6503 ins_pipe(ialu_reg_reg);
|
|
|
6504 %}
|
|
|
6505
|
|
|
6506 // Immediate Subtraction
|
|
|
6507 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
|
|
|
6508 match(Set dst (SubL src1 con));
|
|
|
6509
|
|
|
6510 size(4);
|
|
|
6511 format %{ "SUB $src1,$con,$dst\t! long" %}
|
|
|
6512 opcode(Assembler::sub_op3, Assembler::arith_op);
|
|
|
6513 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
|
|
|
6514 ins_pipe(ialu_reg_imm);
|
|
|
6515 %}
|
|
|
6516
|
|
|
6517 // Long negation
|
|
|
6518 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
|
|
|
6519 match(Set dst (SubL zero src2));
|
|
|
6520
|
|
|
6521 size(4);
|
|
|
6522 format %{ "NEG $src2,$dst\t! long" %}
|
|
|
6523 opcode(Assembler::sub_op3, Assembler::arith_op);
|
|
|
6524 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
|
|
|
6525 ins_pipe(ialu_zero_reg);
|
|
|
6526 %}
|
|
|
6527
|
|
|
6528 // Multiplication Instructions
|
|
|
6529 // Integer Multiplication
|
|
|
6530 // Register Multiplication
|
|
|
6531 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
|
|
|
6532 match(Set dst (MulI src1 src2));
|
|
|
6533
|
|
|
6534 size(4);
|
|
|
6535 format %{ "MULX $src1,$src2,$dst" %}
|
|
|
6536 opcode(Assembler::mulx_op3, Assembler::arith_op);
|
|
|
6537 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
|
|
|
6538 ins_pipe(imul_reg_reg);
|
|
|
6539 %}
|
|
|
6540
|
|
|
6541 // Immediate Multiplication
|
|
|
6542 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
|
|
|
6543 match(Set dst (MulI src1 src2));
|
|
|
6544
|
|
|
6545 size(4);
|
|
|
6546 format %{ "MULX $src1,$src2,$dst" %}
|
|
|
6547 opcode(Assembler::mulx_op3, Assembler::arith_op);
|
|
|
6548 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
|
|
|
6549 ins_pipe(imul_reg_imm);
|
|
|
6550 %}
|
|
|
6551
|
|
|
6552 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
|
|
|
6553 match(Set dst (MulL src1 src2));
|
|
|
6554 ins_cost(DEFAULT_COST * 5);
|
|
|
6555 size(4);
|
|
|
6556 format %{ "MULX $src1,$src2,$dst\t! long" %}
|
|
|
6557 opcode(Assembler::mulx_op3, Assembler::arith_op);
|
|
|
6558 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
|
|
|
6559 ins_pipe(mulL_reg_reg);
|
|
|
6560 %}
|
|
|
6561
|
|
|
6562 // Immediate Multiplication
|
|
|
6563 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
|
|
|
6564 match(Set dst (MulL src1 src2));
|
|
|
6565 ins_cost(DEFAULT_COST * 5);
|
|
|
6566 size(4);
|
|
|
6567 format %{ "MULX $src1,$src2,$dst" %}
|
|
|
6568 opcode(Assembler::mulx_op3, Assembler::arith_op);
|
|
|
6569 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
|
|
|
6570 ins_pipe(mulL_reg_imm);
|
|
|
6571 %}
|
|
|
6572
|
|
|
6573 // Integer Division
|
|
|
6574 // Register Division
|
|
|
6575 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
|
|
|
6576 match(Set dst (DivI src1 src2));
|
|
|
6577 ins_cost((2+71)*DEFAULT_COST);
|
|
|
6578
|
|
|
6579 format %{ "SRA $src2,0,$src2\n\t"
|
|
|
6580 "SRA $src1,0,$src1\n\t"
|
|
|
6581 "SDIVX $src1,$src2,$dst" %}
|
|
|
6582 ins_encode( idiv_reg( src1, src2, dst ) );
|
|
|
6583 ins_pipe(sdiv_reg_reg);
|
|
|
6584 %}
|
|
|
6585
|
|
|
6586 // Immediate Division
|
|
|
6587 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
|
|
|
6588 match(Set dst (DivI src1 src2));
|
|
|
6589 ins_cost((2+71)*DEFAULT_COST);
|
|
|
6590
|
|
|
6591 format %{ "SRA $src1,0,$src1\n\t"
|
|
|
6592 "SDIVX $src1,$src2,$dst" %}
|
|
|
6593 ins_encode( idiv_imm( src1, src2, dst ) );
|
|
|
6594 ins_pipe(sdiv_reg_imm);
|
|
|
6595 %}
|
|
|
6596
|
|
|
6597 //----------Div-By-10-Expansion------------------------------------------------
|
|
|
6598 // Extract hi bits of a 32x32->64 bit multiply.
|
|
|
6599 // Expand rule only, not matched
|
|
|
6600 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
|
|
|
6601 effect( DEF dst, USE src1, USE src2 );
|
|
|
6602 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
|
|
|
6603 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
|
|
|
6604 ins_encode( enc_mul_hi(dst,src1,src2));
|
|
|
6605 ins_pipe(sdiv_reg_reg);
|
|
|
6606 %}
|
|
|
6607
|
|
|
6608 // Magic constant, reciprical of 10
|
|
|
6609 instruct loadConI_x66666667(iRegIsafe dst) %{
|
|
|
6610 effect( DEF dst );
|
|
|
6611
|
|
|
6612 size(8);
|
|
|
6613 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
|
|
|
6614 ins_encode( Set32(0x66666667, dst) );
|
|
|
6615 ins_pipe(ialu_hi_lo_reg);
|
|
|
6616 %}
|
|
|
6617
|
|
|
6618 // Register Shift Right Arithmatic Long by 32-63
|
|
|
6619 instruct sra_31( iRegI dst, iRegI src ) %{
|
|
|
6620 effect( DEF dst, USE src );
|
|
|
6621 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
|
|
|
6622 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
|
|
|
6623 ins_pipe(ialu_reg_reg);
|
|
|
6624 %}
|
|
|
6625
|
|
|
6626 // Arithmetic Shift Right by 8-bit immediate
|
|
|
6627 instruct sra_reg_2( iRegI dst, iRegI src ) %{
|
|
|
6628 effect( DEF dst, USE src );
|
|
|
6629 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
|
|
|
6630 opcode(Assembler::sra_op3, Assembler::arith_op);
|
|
|
6631 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
|
|
|
6632 ins_pipe(ialu_reg_imm);
|
|
|
6633 %}
|
|
|
6634
|
|
|
6635 // Integer DIV with 10
|
|
|
6636 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
|
|
|
6637 match(Set dst (DivI src div));
|
|
|
6638 ins_cost((6+6)*DEFAULT_COST);
|
|
|
6639 expand %{
|
|
|
6640 iRegIsafe tmp1; // Killed temps;
|
|
|
6641 iRegIsafe tmp2; // Killed temps;
|
|
|
6642 iRegI tmp3; // Killed temps;
|
|
|
6643 iRegI tmp4; // Killed temps;
|
|
|
6644 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
|
|
|
6645 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
|
|
|
6646 sra_31( tmp3, src ); // SRA src,31 -> tmp3
|
|
|
6647 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
|
|
|
6648 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
|
|
|
6649 %}
|
|
|
6650 %}
|
|
|
6651
|
|
|
6652 // Register Long Division
|
|
|
6653 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
|
|
|
6654 match(Set dst (DivL src1 src2));
|
|
|
6655 ins_cost(DEFAULT_COST*71);
|
|
|
6656 size(4);
|
|
|
6657 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
|
|
|
6658 opcode(Assembler::sdivx_op3, Assembler::arith_op);
|
|
|
6659 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
|
|
|
6660 ins_pipe(divL_reg_reg);
|
|
|
6661 %}
|
|
|
6662
|
|
|
6663 // Register Long Division
|
|
|
6664 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
|
|
|
6665 match(Set dst (DivL src1 src2));
|
|
|
6666 ins_cost(DEFAULT_COST*71);
|
|
|
6667 size(4);
|
|
|
6668 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
|
|
|
6669 opcode(Assembler::sdivx_op3, Assembler::arith_op);
|
|
|
6670 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
|
|
|
6671 ins_pipe(divL_reg_imm);
|
|
|
6672 %}
|
|
|
6673
|
|
|
6674 // Integer Remainder
|
|
|
6675 // Register Remainder
|
|
|
6676 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
|
|
|
6677 match(Set dst (ModI src1 src2));
|
|
|
6678 effect( KILL ccr, KILL temp);
|
|
|
6679
|
|
|
6680 format %{ "SREM $src1,$src2,$dst" %}
|
|
|
6681 ins_encode( irem_reg(src1, src2, dst, temp) );
|
|
|
6682 ins_pipe(sdiv_reg_reg);
|
|
|
6683 %}
|
|
|
6684
|
|
|
6685 // Immediate Remainder
|
|
|
6686 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
|
|
|
6687 match(Set dst (ModI src1 src2));
|
|
|
6688 effect( KILL ccr, KILL temp);
|
|
|
6689
|
|
|
6690 format %{ "SREM $src1,$src2,$dst" %}
|
|
|
6691 ins_encode( irem_imm(src1, src2, dst, temp) );
|
|
|
6692 ins_pipe(sdiv_reg_imm);
|
|
|
6693 %}
|
|
|
6694
|
|
|
6695 // Register Long Remainder
|
|
|
6696 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
|
|
|
6697 effect(DEF dst, USE src1, USE src2);
|
|
|
6698 size(4);
|
|
|
6699 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
|
|
|
6700 opcode(Assembler::sdivx_op3, Assembler::arith_op);
|
|
|
6701 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
|
|
|
6702 ins_pipe(divL_reg_reg);
|
|
|
6703 %}
|
|
|
6704
|
|
|
6705 // Register Long Division
|
|
|
6706 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
|
|
|
6707 effect(DEF dst, USE src1, USE src2);
|
|
|
6708 size(4);
|
|
|
6709 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
|
|
|
6710 opcode(Assembler::sdivx_op3, Assembler::arith_op);
|
|
|
6711 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
|
|
|
6712 ins_pipe(divL_reg_imm);
|
|
|
6713 %}
|
|
|
6714
|
|
|
6715 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
|
|
|
6716 effect(DEF dst, USE src1, USE src2);
|
|
|
6717 size(4);
|
|
|
6718 format %{ "MULX $src1,$src2,$dst\t! long" %}
|
|
|
6719 opcode(Assembler::mulx_op3, Assembler::arith_op);
|
|
|
6720 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
|
|
|
6721 ins_pipe(mulL_reg_reg);
|
|
|
6722 %}
|
|
|
6723
|
|
|
6724 // Immediate Multiplication
|
|
|
6725 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
|
|
|
6726 effect(DEF dst, USE src1, USE src2);
|
|
|
6727 size(4);
|
|
|
6728 format %{ "MULX $src1,$src2,$dst" %}
|
|
|
6729 opcode(Assembler::mulx_op3, Assembler::arith_op);
|
|
|
6730 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
|
|
|
6731 ins_pipe(mulL_reg_imm);
|
|
|
6732 %}
|
|
|
6733
|
|
|
6734 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
|
|
|
6735 effect(DEF dst, USE src1, USE src2);
|
|
|
6736 size(4);
|
|
|
6737 format %{ "SUB $src1,$src2,$dst\t! long" %}
|
|
|
6738 opcode(Assembler::sub_op3, Assembler::arith_op);
|
|
|
6739 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
|
|
|
6740 ins_pipe(ialu_reg_reg);
|
|
|
6741 %}
|
|
|
6742
|
|
|
6743 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
|
|
|
6744 effect(DEF dst, USE src1, USE src2);
|
|
|
6745 size(4);
|
|
|
6746 format %{ "SUB $src1,$src2,$dst\t! long" %}
|
|
|
6747 opcode(Assembler::sub_op3, Assembler::arith_op);
|
|
|
6748 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
|
|
|
6749 ins_pipe(ialu_reg_reg);
|
|
|
6750 %}
|
|
|
6751
|
|
|
6752 // Register Long Remainder
|
|
|
6753 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
|
|
|
6754 match(Set dst (ModL src1 src2));
|
|
|
6755 ins_cost(DEFAULT_COST*(71 + 6 + 1));
|
|
|
6756 expand %{
|
|
|
6757 iRegL tmp1;
|
|
|
6758 iRegL tmp2;
|
|
|
6759 divL_reg_reg_1(tmp1, src1, src2);
|
|
|
6760 mulL_reg_reg_1(tmp2, tmp1, src2);
|
|
|
6761 subL_reg_reg_1(dst, src1, tmp2);
|
|
|
6762 %}
|
|
|
6763 %}
|
|
|
6764
|
|
|
6765 // Register Long Remainder
|
|
|
6766 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
|
|
|
6767 match(Set dst (ModL src1 src2));
|
|
|
6768 ins_cost(DEFAULT_COST*(71 + 6 + 1));
|
|
|
6769 expand %{
|
|
|
6770 iRegL tmp1;
|
|
|
6771 iRegL tmp2;
|
|
|
6772 divL_reg_imm13_1(tmp1, src1, src2);
|
|
|
6773 mulL_reg_imm13_1(tmp2, tmp1, src2);
|
|
|
6774 subL_reg_reg_2 (dst, src1, tmp2);
|
|
|
6775 %}
|
|
|
6776 %}
|
|
|
6777
|
|
|
6778 // Integer Shift Instructions
|
|
|
6779 // Register Shift Left
|
|
|
6780 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
|
|
|
6781 match(Set dst (LShiftI src1 src2));
|
|
|
6782
|
|
|
6783 size(4);
|
|
|
6784 format %{ "SLL $src1,$src2,$dst" %}
|
|
|
6785 opcode(Assembler::sll_op3, Assembler::arith_op);
|
|
|
6786 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
|
|
|
6787 ins_pipe(ialu_reg_reg);
|
|
|
6788 %}
|
|
|
6789
|
|
|
6790 // Register Shift Left Immediate
|
|
|
6791 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
|
|
|
6792 match(Set dst (LShiftI src1 src2));
|
|
|
6793
|
|
|
6794 size(4);
|
|
|
6795 format %{ "SLL $src1,$src2,$dst" %}
|
|
|
6796 opcode(Assembler::sll_op3, Assembler::arith_op);
|
|
|
6797 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
|
|
|
6798 ins_pipe(ialu_reg_imm);
|
|
|
6799 %}
|
|
|
6800
|
|
|
6801 // Register Shift Left
|
|
|
6802 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
|
|
|
6803 match(Set dst (LShiftL src1 src2));
|
|
|
6804
|
|
|
6805 size(4);
|
|
|
6806 format %{ "SLLX $src1,$src2,$dst" %}
|
|
|
6807 opcode(Assembler::sllx_op3, Assembler::arith_op);
|
|
|
6808 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
|
|
|
6809 ins_pipe(ialu_reg_reg);
|
|
|
6810 %}
|
|
|
6811
|
|
|
6812 // Register Shift Left Immediate
|
|
|
6813 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
|
|
|
6814 match(Set dst (LShiftL src1 src2));
|
|
|
6815
|
|
|
6816 size(4);
|
|
|
6817 format %{ "SLLX $src1,$src2,$dst" %}
|
|
|
6818 opcode(Assembler::sllx_op3, Assembler::arith_op);
|
|
|
6819 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
|
|
|
6820 ins_pipe(ialu_reg_imm);
|
|
|
6821 %}
|
|
|
6822
|
|
|
6823 // Register Arithmetic Shift Right
|
|
|
6824 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
|
|
|
6825 match(Set dst (RShiftI src1 src2));
|
|
|
6826 size(4);
|
|
|
6827 format %{ "SRA $src1,$src2,$dst" %}
|
|
|
6828 opcode(Assembler::sra_op3, Assembler::arith_op);
|
|
|
6829 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
|
|
|
6830 ins_pipe(ialu_reg_reg);
|
|
|
6831 %}
|
|
|
6832
|
|
|
6833 // Register Arithmetic Shift Right Immediate
|
|
|
6834 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
|
|
|
6835 match(Set dst (RShiftI src1 src2));
|
|
|
6836
|
|
|
6837 size(4);
|
|
|
6838 format %{ "SRA $src1,$src2,$dst" %}
|
|
|
6839 opcode(Assembler::sra_op3, Assembler::arith_op);
|
|
|
6840 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
|
|
|
6841 ins_pipe(ialu_reg_imm);
|
|
|
6842 %}
|
|
|
6843
|
|
|
6844 // Register Shift Right Arithmatic Long
|
|
|
6845 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
|
|
|
6846 match(Set dst (RShiftL src1 src2));
|
|
|
6847
|
|
|
6848 size(4);
|
|
|
6849 format %{ "SRAX $src1,$src2,$dst" %}
|
|
|
6850 opcode(Assembler::srax_op3, Assembler::arith_op);
|
|
|
6851 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
|
|
|
6852 ins_pipe(ialu_reg_reg);
|
|
|
6853 %}
|
|
|
6854
|
|
|
6855 // Register Shift Left Immediate
|
|
|
6856 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
|
|
|
6857 match(Set dst (RShiftL src1 src2));
|
|
|
6858
|
|
|
6859 size(4);
|
|
|
6860 format %{ "SRAX $src1,$src2,$dst" %}
|
|
|
6861 opcode(Assembler::srax_op3, Assembler::arith_op);
|
|
|
6862 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
|
|
|
6863 ins_pipe(ialu_reg_imm);
|
|
|
6864 %}
|
|
|
6865
|
|
|
6866 // Register Shift Right
|
|
|
6867 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
|
|
|
6868 match(Set dst (URShiftI src1 src2));
|
|
|
6869
|
|
|
6870 size(4);
|
|
|
6871 format %{ "SRL $src1,$src2,$dst" %}
|
|
|
6872 opcode(Assembler::srl_op3, Assembler::arith_op);
|
|
|
6873 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
|
|
|
6874 ins_pipe(ialu_reg_reg);
|
|
|
6875 %}
|
|
|
6876
|
|
|
6877 // Register Shift Right Immediate
|
|
|
6878 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
|
|
|
6879 match(Set dst (URShiftI src1 src2));
|
|
|
6880
|
|
|
6881 size(4);
|
|
|
6882 format %{ "SRL $src1,$src2,$dst" %}
|
|
|
6883 opcode(Assembler::srl_op3, Assembler::arith_op);
|
|
|
6884 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
|
|
|
6885 ins_pipe(ialu_reg_imm);
|
|
|
6886 %}
|
|
|
6887
|
|
|
6888 // Register Shift Right
|
|
|
6889 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
|
|
|
6890 match(Set dst (URShiftL src1 src2));
|
|
|
6891
|
|
|
6892 size(4);
|
|
|
6893 format %{ "SRLX $src1,$src2,$dst" %}
|
|
|
6894 opcode(Assembler::srlx_op3, Assembler::arith_op);
|
|
|
6895 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
|
|
|
6896 ins_pipe(ialu_reg_reg);
|
|
|
6897 %}
|
|
|
6898
|
|
|
6899 // Register Shift Right Immediate
|
|
|
6900 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
|
|
|
6901 match(Set dst (URShiftL src1 src2));
|
|
|
6902
|
|
|
6903 size(4);
|
|
|
6904 format %{ "SRLX $src1,$src2,$dst" %}
|
|
|
6905 opcode(Assembler::srlx_op3, Assembler::arith_op);
|
|
|
6906 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
|
|
|
6907 ins_pipe(ialu_reg_imm);
|
|
|
6908 %}
|
|
|
6909
|
|
|
6910 // Register Shift Right Immediate with a CastP2X
|
|
|
6911 #ifdef _LP64
|
|
|
6912 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
|
|
|
6913 match(Set dst (URShiftL (CastP2X src1) src2));
|
|
|
6914 size(4);
|
|
|
6915 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
|
|
|
6916 opcode(Assembler::srlx_op3, Assembler::arith_op);
|
|
|
6917 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
|
|
|
6918 ins_pipe(ialu_reg_imm);
|
|
|
6919 %}
|
|
|
6920 #else
|
|
|
6921 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
|
|
|
6922 match(Set dst (URShiftI (CastP2X src1) src2));
|
|
|
6923 size(4);
|
|
|
6924 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
|
|
|
6925 opcode(Assembler::srl_op3, Assembler::arith_op);
|
|
|
6926 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
|
|
|
6927 ins_pipe(ialu_reg_imm);
|
|
|
6928 %}
|
|
|
6929 #endif
|
|
|
6930
|
|
|
6931
|
|
|
6932 //----------Floating Point Arithmetic Instructions-----------------------------
|
|
|
6933
|
|
|
6934 // Add float single precision
|
|
|
6935 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
|
|
|
6936 match(Set dst (AddF src1 src2));
|
|
|
6937
|
|
|
6938 size(4);
|
|
|
6939 format %{ "FADDS $src1,$src2,$dst" %}
|
|
|
6940 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
|
|
|
6941 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
|
|
|
6942 ins_pipe(faddF_reg_reg);
|
|
|
6943 %}
|
|
|
6944
|
|
|
6945 // Add float double precision
|
|
|
6946 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
|
|
|
6947 match(Set dst (AddD src1 src2));
|
|
|
6948
|
|
|
6949 size(4);
|
|
|
6950 format %{ "FADDD $src1,$src2,$dst" %}
|
|
|
6951 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
|
|
|
6952 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
|
|
|
6953 ins_pipe(faddD_reg_reg);
|
|
|
6954 %}
|
|
|
6955
|
|
|
6956 // Sub float single precision
|
|
|
6957 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
|
|
|
6958 match(Set dst (SubF src1 src2));
|
|
|
6959
|
|
|
6960 size(4);
|
|
|
6961 format %{ "FSUBS $src1,$src2,$dst" %}
|
|
|
6962 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
|
|
|
6963 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
|
|
|
6964 ins_pipe(faddF_reg_reg);
|
|
|
6965 %}
|
|
|
6966
|
|
|
6967 // Sub float double precision
|
|
|
6968 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
|
|
|
6969 match(Set dst (SubD src1 src2));
|
|
|
6970
|
|
|
6971 size(4);
|
|
|
6972 format %{ "FSUBD $src1,$src2,$dst" %}
|
|
|
6973 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
|
|
|
6974 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
|
|
|
6975 ins_pipe(faddD_reg_reg);
|
|
|
6976 %}
|
|
|
6977
|
|
|
6978 // Mul float single precision
|
|
|
6979 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
|
|
|
6980 match(Set dst (MulF src1 src2));
|
|
|
6981
|
|
|
6982 size(4);
|
|
|
6983 format %{ "FMULS $src1,$src2,$dst" %}
|
|
|
6984 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
|
|
|
6985 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
|
|
|
6986 ins_pipe(fmulF_reg_reg);
|
|
|
6987 %}
|
|
|
6988
|
|
|
6989 // Mul float double precision
|
|
|
6990 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
|
|
|
6991 match(Set dst (MulD src1 src2));
|
|
|
6992
|
|
|
6993 size(4);
|
|
|
6994 format %{ "FMULD $src1,$src2,$dst" %}
|
|
|
6995 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
|
|
|
6996 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
|
|
|
6997 ins_pipe(fmulD_reg_reg);
|
|
|
6998 %}
|
|
|
6999
|
|
|
7000 // Div float single precision
|
|
|
7001 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
|
|
|
7002 match(Set dst (DivF src1 src2));
|
|
|
7003
|
|
|
7004 size(4);
|
|
|
7005 format %{ "FDIVS $src1,$src2,$dst" %}
|
|
|
7006 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
|
|
|
7007 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
|
|
|
7008 ins_pipe(fdivF_reg_reg);
|
|
|
7009 %}
|
|
|
7010
|
|
|
7011 // Div float double precision
|
|
|
7012 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
|
|
|
7013 match(Set dst (DivD src1 src2));
|
|
|
7014
|
|
|
7015 size(4);
|
|
|
7016 format %{ "FDIVD $src1,$src2,$dst" %}
|
|
|
7017 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
|
|
|
7018 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
|
|
|
7019 ins_pipe(fdivD_reg_reg);
|
|
|
7020 %}
|
|
|
7021
|
|
|
7022 // Absolute float double precision
|
|
|
7023 instruct absD_reg(regD dst, regD src) %{
|
|
|
7024 match(Set dst (AbsD src));
|
|
|
7025
|
|
|
7026 format %{ "FABSd $src,$dst" %}
|
|
|
7027 ins_encode(fabsd(dst, src));
|
|
|
7028 ins_pipe(faddD_reg);
|
|
|
7029 %}
|
|
|
7030
|
|
|
7031 // Absolute float single precision
|
|
|
7032 instruct absF_reg(regF dst, regF src) %{
|
|
|
7033 match(Set dst (AbsF src));
|
|
|
7034
|
|
|
7035 format %{ "FABSs $src,$dst" %}
|
|
|
7036 ins_encode(fabss(dst, src));
|
|
|
7037 ins_pipe(faddF_reg);
|
|
|
7038 %}
|
|
|
7039
|
|
|
7040 instruct negF_reg(regF dst, regF src) %{
|
|
|
7041 match(Set dst (NegF src));
|
|
|
7042
|
|
|
7043 size(4);
|
|
|
7044 format %{ "FNEGs $src,$dst" %}
|
|
|
7045 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
|
|
|
7046 ins_encode(form3_opf_rs2F_rdF(src, dst));
|
|
|
7047 ins_pipe(faddF_reg);
|
|
|
7048 %}
|
|
|
7049
|
|
|
7050 instruct negD_reg(regD dst, regD src) %{
|
|
|
7051 match(Set dst (NegD src));
|
|
|
7052
|
|
|
7053 format %{ "FNEGd $src,$dst" %}
|
|
|
7054 ins_encode(fnegd(dst, src));
|
|
|
7055 ins_pipe(faddD_reg);
|
|
|
7056 %}
|
|
|
7057
|
|
|
7058 // Sqrt float double precision
|
|
|
7059 instruct sqrtF_reg_reg(regF dst, regF src) %{
|
|
|
7060 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
|
|
|
7061
|
|
|
7062 size(4);
|
|
|
7063 format %{ "FSQRTS $src,$dst" %}
|
|
|
7064 ins_encode(fsqrts(dst, src));
|
|
|
7065 ins_pipe(fdivF_reg_reg);
|
|
|
7066 %}
|
|
|
7067
|
|
|
7068 // Sqrt float double precision
|
|
|
7069 instruct sqrtD_reg_reg(regD dst, regD src) %{
|
|
|
7070 match(Set dst (SqrtD src));
|
|
|
7071
|
|
|
7072 size(4);
|
|
|
7073 format %{ "FSQRTD $src,$dst" %}
|
|
|
7074 ins_encode(fsqrtd(dst, src));
|
|
|
7075 ins_pipe(fdivD_reg_reg);
|
|
|
7076 %}
|
|
|
7077
|
|
|
7078 //----------Logical Instructions-----------------------------------------------
|
|
|
7079 // And Instructions
|
|
|
7080 // Register And
|
|
|
7081 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
|
|
|
7082 match(Set dst (AndI src1 src2));
|
|
|
7083
|
|
|
7084 size(4);
|
|
|
7085 format %{ "AND $src1,$src2,$dst" %}
|
|
|
7086 opcode(Assembler::and_op3, Assembler::arith_op);
|
|
|
7087 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
|
|
|
7088 ins_pipe(ialu_reg_reg);
|
|
|
7089 %}
|
|
|
7090
|
|
|
7091 // Immediate And
|
|
|
7092 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
|
|
|
7093 match(Set dst (AndI src1 src2));
|
|
|
7094
|
|
|
7095 size(4);
|
|
|
7096 format %{ "AND $src1,$src2,$dst" %}
|
|
|
7097 opcode(Assembler::and_op3, Assembler::arith_op);
|
|
|
7098 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
|
|
|
7099 ins_pipe(ialu_reg_imm);
|
|
|
7100 %}
|
|
|
7101
|
|
|
7102 // Register And Long
|
|
|
7103 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
|
|
|
7104 match(Set dst (AndL src1 src2));
|
|
|
7105
|
|
|
7106 ins_cost(DEFAULT_COST);
|
|
|
7107 size(4);
|
|
|
7108 format %{ "AND $src1,$src2,$dst\t! long" %}
|
|
|
7109 opcode(Assembler::and_op3, Assembler::arith_op);
|
|
|
7110 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
|
|
|
7111 ins_pipe(ialu_reg_reg);
|
|
|
7112 %}
|
|
|
7113
|
|
|
7114 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
|
|
|
7115 match(Set dst (AndL src1 con));
|
|
|
7116
|
|
|
7117 ins_cost(DEFAULT_COST);
|
|
|
7118 size(4);
|
|
|
7119 format %{ "AND $src1,$con,$dst\t! long" %}
|
|
|
7120 opcode(Assembler::and_op3, Assembler::arith_op);
|
|
|
7121 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
|
|
|
7122 ins_pipe(ialu_reg_imm);
|
|
|
7123 %}
|
|
|
7124
|
|
|
7125 // Or Instructions
|
|
|
7126 // Register Or
|
|
|
7127 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
|
|
|
7128 match(Set dst (OrI src1 src2));
|
|
|
7129
|
|
|
7130 size(4);
|
|
|
7131 format %{ "OR $src1,$src2,$dst" %}
|
|
|
7132 opcode(Assembler::or_op3, Assembler::arith_op);
|
|
|
7133 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
|
|
|
7134 ins_pipe(ialu_reg_reg);
|
|
|
7135 %}
|
|
|
7136
|
|
|
7137 // Immediate Or
|
|
|
7138 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
|
|
|
7139 match(Set dst (OrI src1 src2));
|
|
|
7140
|
|
|
7141 size(4);
|
|
|
7142 format %{ "OR $src1,$src2,$dst" %}
|
|
|
7143 opcode(Assembler::or_op3, Assembler::arith_op);
|
|
|
7144 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
|
|
|
7145 ins_pipe(ialu_reg_imm);
|
|
|
7146 %}
|
|
|
7147
|
|
|
7148 // Register Or Long
|
|
|
7149 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
|
|
|
7150 match(Set dst (OrL src1 src2));
|
|
|
7151
|
|
|
7152 ins_cost(DEFAULT_COST);
|
|
|
7153 size(4);
|
|
|
7154 format %{ "OR $src1,$src2,$dst\t! long" %}
|
|
|
7155 opcode(Assembler::or_op3, Assembler::arith_op);
|
|
|
7156 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
|
|
|
7157 ins_pipe(ialu_reg_reg);
|
|
|
7158 %}
|
|
|
7159
|
|
|
7160 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
|
|
|
7161 match(Set dst (OrL src1 con));
|
|
|
7162 ins_cost(DEFAULT_COST*2);
|
|
|
7163
|
|
|
7164 ins_cost(DEFAULT_COST);
|
|
|
7165 size(4);
|
|
|
7166 format %{ "OR $src1,$con,$dst\t! long" %}
|
|
|
7167 opcode(Assembler::or_op3, Assembler::arith_op);
|
|
|
7168 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
|
|
|
7169 ins_pipe(ialu_reg_imm);
|
|
|
7170 %}
|
|
|
7171
|
|
|
7172 // Xor Instructions
|
|
|
7173 // Register Xor
|
|
|
7174 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
|
|
|
7175 match(Set dst (XorI src1 src2));
|
|
|
7176
|
|
|
7177 size(4);
|
|
|
7178 format %{ "XOR $src1,$src2,$dst" %}
|
|
|
7179 opcode(Assembler::xor_op3, Assembler::arith_op);
|
|
|
7180 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
|
|
|
7181 ins_pipe(ialu_reg_reg);
|
|
|
7182 %}
|
|
|
7183
|
|
|
7184 // Immediate Xor
|
|
|
7185 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
|
|
|
7186 match(Set dst (XorI src1 src2));
|
|
|
7187
|
|
|
7188 size(4);
|
|
|
7189 format %{ "XOR $src1,$src2,$dst" %}
|
|
|
7190 opcode(Assembler::xor_op3, Assembler::arith_op);
|
|
|
7191 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
|
|
|
7192 ins_pipe(ialu_reg_imm);
|
|
|
7193 %}
|
|
|
7194
|
|
|
7195 // Register Xor Long
|
|
|
7196 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
|
|
|
7197 match(Set dst (XorL src1 src2));
|
|
|
7198
|
|
|
7199 ins_cost(DEFAULT_COST);
|
|
|
7200 size(4);
|
|
|
7201 format %{ "XOR $src1,$src2,$dst\t! long" %}
|
|
|
7202 opcode(Assembler::xor_op3, Assembler::arith_op);
|
|
|
7203 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
|
|
|
7204 ins_pipe(ialu_reg_reg);
|
|
|
7205 %}
|
|
|
7206
|
|
|
7207 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
|
|
|
7208 match(Set dst (XorL src1 con));
|
|
|
7209
|
|
|
7210 ins_cost(DEFAULT_COST);
|
|
|
7211 size(4);
|
|
|
7212 format %{ "XOR $src1,$con,$dst\t! long" %}
|
|
|
7213 opcode(Assembler::xor_op3, Assembler::arith_op);
|
|
|
7214 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
|
|
|
7215 ins_pipe(ialu_reg_imm);
|
|
|
7216 %}
|
|
|
7217
|
|
|
7218 //----------Convert to Boolean-------------------------------------------------
|
|
|
7219 // Nice hack for 32-bit tests but doesn't work for
|
|
|
7220 // 64-bit pointers.
|
|
|
7221 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
|
|
|
7222 match(Set dst (Conv2B src));
|
|
|
7223 effect( KILL ccr );
|
|
|
7224 ins_cost(DEFAULT_COST*2);
|
|
|
7225 format %{ "CMP R_G0,$src\n\t"
|
|
|
7226 "ADDX R_G0,0,$dst" %}
|
|
|
7227 ins_encode( enc_to_bool( src, dst ) );
|
|
|
7228 ins_pipe(ialu_reg_ialu);
|
|
|
7229 %}
|
|
|
7230
|
|
|
7231 #ifndef _LP64
|
|
|
7232 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
|
|
|
7233 match(Set dst (Conv2B src));
|
|
|
7234 effect( KILL ccr );
|
|
|
7235 ins_cost(DEFAULT_COST*2);
|
|
|
7236 format %{ "CMP R_G0,$src\n\t"
|
|
|
7237 "ADDX R_G0,0,$dst" %}
|
|
|
7238 ins_encode( enc_to_bool( src, dst ) );
|
|
|
7239 ins_pipe(ialu_reg_ialu);
|
|
|
7240 %}
|
|
|
7241 #else
|
|
|
7242 instruct convP2B( iRegI dst, iRegP src ) %{
|
|
|
7243 match(Set dst (Conv2B src));
|
|
|
7244 ins_cost(DEFAULT_COST*2);
|
|
|
7245 format %{ "MOV $src,$dst\n\t"
|
|
|
7246 "MOVRNZ $src,1,$dst" %}
|
|
|
7247 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
|
|
|
7248 ins_pipe(ialu_clr_and_mover);
|
|
|
7249 %}
|
|
|
7250 #endif
|
|
|
7251
|
|
|
7252 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
|
|
|
7253 match(Set dst (CmpLTMask p q));
|
|
|
7254 effect( KILL ccr );
|
|
|
7255 ins_cost(DEFAULT_COST*4);
|
|
|
7256 format %{ "CMP $p,$q\n\t"
|
|
|
7257 "MOV #0,$dst\n\t"
|
|
|
7258 "BLT,a .+8\n\t"
|
|
|
7259 "MOV #-1,$dst" %}
|
|
|
7260 ins_encode( enc_ltmask(p,q,dst) );
|
|
|
7261 ins_pipe(ialu_reg_reg_ialu);
|
|
|
7262 %}
|
|
|
7263
|
|
|
7264 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
|
|
|
7265 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
|
|
|
7266 effect(KILL ccr, TEMP tmp);
|
|
|
7267 ins_cost(DEFAULT_COST*3);
|
|
|
7268
|
|
|
7269 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
|
|
|
7270 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
|
|
|
7271 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %}
|
|
|
7272 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
|
|
|
7273 ins_pipe( cadd_cmpltmask );
|
|
|
7274 %}
|
|
|
7275
|
|
|
7276 instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
|
|
|
7277 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y)));
|
|
|
7278 effect( KILL ccr, TEMP tmp);
|
|
|
7279 ins_cost(DEFAULT_COST*3);
|
|
|
7280
|
|
|
7281 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
|
|
|
7282 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
|
|
|
7283 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %}
|
|
|
7284 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
|
|
|
7285 ins_pipe( cadd_cmpltmask );
|
|
|
7286 %}
|
|
|
7287
|
|
|
7288 //----------Arithmetic Conversion Instructions---------------------------------
|
|
|
7289 // The conversions operations are all Alpha sorted. Please keep it that way!
|
|
|
7290
|
|
|
7291 instruct convD2F_reg(regF dst, regD src) %{
|
|
|
7292 match(Set dst (ConvD2F src));
|
|
|
7293 size(4);
|
|
|
7294 format %{ "FDTOS $src,$dst" %}
|
|
|
7295 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
|
|
|
7296 ins_encode(form3_opf_rs2D_rdF(src, dst));
|
|
|
7297 ins_pipe(fcvtD2F);
|
|
|
7298 %}
|
|
|
7299
|
|
|
7300
|
|
|
7301 // Convert a double to an int in a float register.
|
|
|
7302 // If the double is a NAN, stuff a zero in instead.
|
|
|
7303 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
|
|
|
7304 effect(DEF dst, USE src, KILL fcc0);
|
|
|
7305 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
|
|
|
7306 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
|
|
|
7307 "FDTOI $src,$dst\t! convert in delay slot\n\t"
|
|
|
7308 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
|
|
|
7309 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
|
|
|
7310 "skip:" %}
|
|
|
7311 ins_encode(form_d2i_helper(src,dst));
|
|
|
7312 ins_pipe(fcvtD2I);
|
|
|
7313 %}
|
|
|
7314
|
|
|
7315 instruct convD2I_reg(stackSlotI dst, regD src) %{
|
|
|
7316 match(Set dst (ConvD2I src));
|
|
|
7317 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
|
|
|
7318 expand %{
|
|
|
7319 regF tmp;
|
|
|
7320 convD2I_helper(tmp, src);
|
|
|
7321 regF_to_stkI(dst, tmp);
|
|
|
7322 %}
|
|
|
7323 %}
|
|
|
7324
|
|
|
7325 // Convert a double to a long in a double register.
|
|
|
7326 // If the double is a NAN, stuff a zero in instead.
|
|
|
7327 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
|
|
|
7328 effect(DEF dst, USE src, KILL fcc0);
|
|
|
7329 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
|
|
|
7330 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
|
|
|
7331 "FDTOX $src,$dst\t! convert in delay slot\n\t"
|
|
|
7332 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
|
|
|
7333 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
|
|
|
7334 "skip:" %}
|
|
|
7335 ins_encode(form_d2l_helper(src,dst));
|
|
|
7336 ins_pipe(fcvtD2L);
|
|
|
7337 %}
|
|
|
7338
|
|
|
7339
|
|
|
7340 // Double to Long conversion
|
|
|
7341 instruct convD2L_reg(stackSlotL dst, regD src) %{
|
|
|
7342 match(Set dst (ConvD2L src));
|
|
|
7343 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
|
|
|
7344 expand %{
|
|
|
7345 regD tmp;
|
|
|
7346 convD2L_helper(tmp, src);
|
|
|
7347 regD_to_stkL(dst, tmp);
|
|
|
7348 %}
|
|
|
7349 %}
|
|
|
7350
|
|
|
7351
|
|
|
7352 instruct convF2D_reg(regD dst, regF src) %{
|
|
|
7353 match(Set dst (ConvF2D src));
|
|
|
7354 format %{ "FSTOD $src,$dst" %}
|
|
|
7355 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
|
|
|
7356 ins_encode(form3_opf_rs2F_rdD(src, dst));
|
|
|
7357 ins_pipe(fcvtF2D);
|
|
|
7358 %}
|
|
|
7359
|
|
|
7360
|
|
|
7361 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
|
|
|
7362 effect(DEF dst, USE src, KILL fcc0);
|
|
|
7363 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
|
|
|
7364 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
|
|
|
7365 "FSTOI $src,$dst\t! convert in delay slot\n\t"
|
|
|
7366 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
|
|
|
7367 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
|
|
|
7368 "skip:" %}
|
|
|
7369 ins_encode(form_f2i_helper(src,dst));
|
|
|
7370 ins_pipe(fcvtF2I);
|
|
|
7371 %}
|
|
|
7372
|
|
|
7373 instruct convF2I_reg(stackSlotI dst, regF src) %{
|
|
|
7374 match(Set dst (ConvF2I src));
|
|
|
7375 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
|
|
|
7376 expand %{
|
|
|
7377 regF tmp;
|
|
|
7378 convF2I_helper(tmp, src);
|
|
|
7379 regF_to_stkI(dst, tmp);
|
|
|
7380 %}
|
|
|
7381 %}
|
|
|
7382
|
|
|
7383
|
|
|
7384 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
|
|
|
7385 effect(DEF dst, USE src, KILL fcc0);
|
|
|
7386 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
|
|
|
7387 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
|
|
|
7388 "FSTOX $src,$dst\t! convert in delay slot\n\t"
|
|
|
7389 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
|
|
|
7390 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
|
|
|
7391 "skip:" %}
|
|
|
7392 ins_encode(form_f2l_helper(src,dst));
|
|
|
7393 ins_pipe(fcvtF2L);
|
|
|
7394 %}
|
|
|
7395
|
|
|
7396 // Float to Long conversion
|
|
|
7397 instruct convF2L_reg(stackSlotL dst, regF src) %{
|
|
|
7398 match(Set dst (ConvF2L src));
|
|
|
7399 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
|
|
|
7400 expand %{
|
|
|
7401 regD tmp;
|
|
|
7402 convF2L_helper(tmp, src);
|
|
|
7403 regD_to_stkL(dst, tmp);
|
|
|
7404 %}
|
|
|
7405 %}
|
|
|
7406
|
|
|
7407
|
|
|
7408 instruct convI2D_helper(regD dst, regF tmp) %{
|
|
|
7409 effect(USE tmp, DEF dst);
|
|
|
7410 format %{ "FITOD $tmp,$dst" %}
|
|
|
7411 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
|
|
|
7412 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
|
|
|
7413 ins_pipe(fcvtI2D);
|
|
|
7414 %}
|
|
|
7415
|
|
|
7416 instruct convI2D_reg(stackSlotI src, regD dst) %{
|
|
|
7417 match(Set dst (ConvI2D src));
|
|
|
7418 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
|
|
|
7419 expand %{
|
|
|
7420 regF tmp;
|
|
|
7421 stkI_to_regF( tmp, src);
|
|
|
7422 convI2D_helper( dst, tmp);
|
|
|
7423 %}
|
|
|
7424 %}
|
|
|
7425
|
|
|
7426 instruct convI2D_mem( regD_low dst, memory mem ) %{
|
|
|
7427 match(Set dst (ConvI2D (LoadI mem)));
|
|
|
7428 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
|
|
|
7429 size(8);
|
|
|
7430 format %{ "LDF $mem,$dst\n\t"
|
|
|
7431 "FITOD $dst,$dst" %}
|
|
|
7432 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
|
|
|
7433 ins_encode( form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
|
|
|
7434 ins_pipe(floadF_mem);
|
|
|
7435 %}
|
|
|
7436
|
|
|
7437
|
|
|
7438 instruct convI2F_helper(regF dst, regF tmp) %{
|
|
|
7439 effect(DEF dst, USE tmp);
|
|
|
7440 format %{ "FITOS $tmp,$dst" %}
|
|
|
7441 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
|
|
|
7442 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
|
|
|
7443 ins_pipe(fcvtI2F);
|
|
|
7444 %}
|
|
|
7445
|
|
|
7446 instruct convI2F_reg( regF dst, stackSlotI src ) %{
|
|
|
7447 match(Set dst (ConvI2F src));
|
|
|
7448 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
|
|
|
7449 expand %{
|
|
|
7450 regF tmp;
|
|
|
7451 stkI_to_regF(tmp,src);
|
|
|
7452 convI2F_helper(dst, tmp);
|
|
|
7453 %}
|
|
|
7454 %}
|
|
|
7455
|
|
|
7456 instruct convI2F_mem( regF dst, memory mem ) %{
|
|
|
7457 match(Set dst (ConvI2F (LoadI mem)));
|
|
|
7458 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
|
|
|
7459 size(8);
|
|
|
7460 format %{ "LDF $mem,$dst\n\t"
|
|
|
7461 "FITOS $dst,$dst" %}
|
|
|
7462 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
|
|
|
7463 ins_encode( form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
|
|
|
7464 ins_pipe(floadF_mem);
|
|
|
7465 %}
|
|
|
7466
|
|
|
7467
|
|
|
7468 instruct convI2L_reg(iRegL dst, iRegI src) %{
|
|
|
7469 match(Set dst (ConvI2L src));
|
|
|
7470 size(4);
|
|
|
7471 format %{ "SRA $src,0,$dst\t! int->long" %}
|
|
|
7472 opcode(Assembler::sra_op3, Assembler::arith_op);
|
|
|
7473 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
|
|
|
7474 ins_pipe(ialu_reg_reg);
|
|
|
7475 %}
|
|
|
7476
|
|
|
7477 // Zero-extend convert int to long
|
|
|
7478 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
|
|
|
7479 match(Set dst (AndL (ConvI2L src) mask) );
|
|
|
7480 size(4);
|
|
|
7481 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
|
|
|
7482 opcode(Assembler::srl_op3, Assembler::arith_op);
|
|
|
7483 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
|
|
|
7484 ins_pipe(ialu_reg_reg);
|
|
|
7485 %}
|
|
|
7486
|
|
|
7487 // Zero-extend long
|
|
|
7488 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
|
|
|
7489 match(Set dst (AndL src mask) );
|
|
|
7490 size(4);
|
|
|
7491 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
|
|
|
7492 opcode(Assembler::srl_op3, Assembler::arith_op);
|
|
|
7493 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
|
|
|
7494 ins_pipe(ialu_reg_reg);
|
|
|
7495 %}
|
|
|
7496
|
|
|
7497 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
|
|
|
7498 match(Set dst (MoveF2I src));
|
|
|
7499 effect(DEF dst, USE src);
|
|
|
7500 ins_cost(MEMORY_REF_COST);
|
|
|
7501
|
|
|
7502 size(4);
|
|
|
7503 format %{ "LDUW $src,$dst\t! MoveF2I" %}
|
|
|
7504 opcode(Assembler::lduw_op3);
|
|
|
7505 ins_encode( form3_mem_reg( src, dst ) );
|
|
|
7506 ins_pipe(iload_mem);
|
|
|
7507 %}
|
|
|
7508
|
|
|
7509 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
|
|
|
7510 match(Set dst (MoveI2F src));
|
|
|
7511 effect(DEF dst, USE src);
|
|
|
7512 ins_cost(MEMORY_REF_COST);
|
|
|
7513
|
|
|
7514 size(4);
|
|
|
7515 format %{ "LDF $src,$dst\t! MoveI2F" %}
|
|
|
7516 opcode(Assembler::ldf_op3);
|
|
|
7517 ins_encode(form3_mem_reg(src, dst));
|
|
|
7518 ins_pipe(floadF_stk);
|
|
|
7519 %}
|
|
|
7520
|
|
|
7521 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
|
|
|
7522 match(Set dst (MoveD2L src));
|
|
|
7523 effect(DEF dst, USE src);
|
|
|
7524 ins_cost(MEMORY_REF_COST);
|
|
|
7525
|
|
|
7526 size(4);
|
|
|
7527 format %{ "LDX $src,$dst\t! MoveD2L" %}
|
|
|
7528 opcode(Assembler::ldx_op3);
|
|
|
7529 ins_encode( form3_mem_reg( src, dst ) );
|
|
|
7530 ins_pipe(iload_mem);
|
|
|
7531 %}
|
|
|
7532
|
|
|
7533 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
|
|
|
7534 match(Set dst (MoveL2D src));
|
|
|
7535 effect(DEF dst, USE src);
|
|
|
7536 ins_cost(MEMORY_REF_COST);
|
|
|
7537
|
|
|
7538 size(4);
|
|
|
7539 format %{ "LDDF $src,$dst\t! MoveL2D" %}
|
|
|
7540 opcode(Assembler::lddf_op3);
|
|
|
7541 ins_encode(form3_mem_reg(src, dst));
|
|
|
7542 ins_pipe(floadD_stk);
|
|
|
7543 %}
|
|
|
7544
|
|
|
7545 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
|
|
|
7546 match(Set dst (MoveF2I src));
|
|
|
7547 effect(DEF dst, USE src);
|
|
|
7548 ins_cost(MEMORY_REF_COST);
|
|
|
7549
|
|
|
7550 size(4);
|
|
|
7551 format %{ "STF $src,$dst\t!MoveF2I" %}
|
|
|
7552 opcode(Assembler::stf_op3);
|
|
|
7553 ins_encode(form3_mem_reg(dst, src));
|
|
|
7554 ins_pipe(fstoreF_stk_reg);
|
|
|
7555 %}
|
|
|
7556
|
|
|
7557 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
|
|
|
7558 match(Set dst (MoveI2F src));
|
|
|
7559 effect(DEF dst, USE src);
|
|
|
7560 ins_cost(MEMORY_REF_COST);
|
|
|
7561
|
|
|
7562 size(4);
|
|
|
7563 format %{ "STW $src,$dst\t!MoveI2F" %}
|
|
|
7564 opcode(Assembler::stw_op3);
|
|
|
7565 ins_encode( form3_mem_reg( dst, src ) );
|
|
|
7566 ins_pipe(istore_mem_reg);
|
|
|
7567 %}
|
|
|
7568
|
|
|
7569 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
|
|
|
7570 match(Set dst (MoveD2L src));
|
|
|
7571 effect(DEF dst, USE src);
|
|
|
7572 ins_cost(MEMORY_REF_COST);
|
|
|
7573
|
|
|
7574 size(4);
|
|
|
7575 format %{ "STDF $src,$dst\t!MoveD2L" %}
|
|
|
7576 opcode(Assembler::stdf_op3);
|
|
|
7577 ins_encode(form3_mem_reg(dst, src));
|
|
|
7578 ins_pipe(fstoreD_stk_reg);
|
|
|
7579 %}
|
|
|
7580
|
|
|
7581 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
|
|
|
7582 match(Set dst (MoveL2D src));
|
|
|
7583 effect(DEF dst, USE src);
|
|
|
7584 ins_cost(MEMORY_REF_COST);
|
|
|
7585
|
|
|
7586 size(4);
|
|
|
7587 format %{ "STX $src,$dst\t!MoveL2D" %}
|
|
|
7588 opcode(Assembler::stx_op3);
|
|
|
7589 ins_encode( form3_mem_reg( dst, src ) );
|
|
|
7590 ins_pipe(istore_mem_reg);
|
|
|
7591 %}
|
|
|
7592
|
|
|
7593
|
|
|
7594 //-----------
|
|
|
7595 // Long to Double conversion using V8 opcodes.
|
|
|
7596 // Still useful because cheetah traps and becomes
|
|
|
7597 // amazingly slow for some common numbers.
|
|
|
7598
|
|
|
7599 // Magic constant, 0x43300000
|
|
|
7600 instruct loadConI_x43300000(iRegI dst) %{
|
|
|
7601 effect(DEF dst);
|
|
|
7602 size(4);
|
|
|
7603 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
|
|
|
7604 ins_encode(SetHi22(0x43300000, dst));
|
|
|
7605 ins_pipe(ialu_none);
|
|
|
7606 %}
|
|
|
7607
|
|
|
7608 // Magic constant, 0x41f00000
|
|
|
7609 instruct loadConI_x41f00000(iRegI dst) %{
|
|
|
7610 effect(DEF dst);
|
|
|
7611 size(4);
|
|
|
7612 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
|
|
|
7613 ins_encode(SetHi22(0x41f00000, dst));
|
|
|
7614 ins_pipe(ialu_none);
|
|
|
7615 %}
|
|
|
7616
|
|
|
7617 // Construct a double from two float halves
|
|
|
7618 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
|
|
|
7619 effect(DEF dst, USE src1, USE src2);
|
|
|
7620 size(8);
|
|
|
7621 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
|
|
|
7622 "FMOVS $src2.lo,$dst.lo" %}
|
|
|
7623 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
|
|
|
7624 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
|
|
|
7625 ins_pipe(faddD_reg_reg);
|
|
|
7626 %}
|
|
|
7627
|
|
|
7628 // Convert integer in high half of a double register (in the lower half of
|
|
|
7629 // the double register file) to double
|
|
|
7630 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
|
|
|
7631 effect(DEF dst, USE src);
|
|
|
7632 size(4);
|
|
|
7633 format %{ "FITOD $src,$dst" %}
|
|
|
7634 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
|
|
|
7635 ins_encode(form3_opf_rs2D_rdD(src, dst));
|
|
|
7636 ins_pipe(fcvtLHi2D);
|
|
|
7637 %}
|
|
|
7638
|
|
|
7639 // Add float double precision
|
|
|
7640 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
|
|
|
7641 effect(DEF dst, USE src1, USE src2);
|
|
|
7642 size(4);
|
|
|
7643 format %{ "FADDD $src1,$src2,$dst" %}
|
|
|
7644 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
|
|
|
7645 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
|
|
|
7646 ins_pipe(faddD_reg_reg);
|
|
|
7647 %}
|
|
|
7648
|
|
|
7649 // Sub float double precision
|
|
|
7650 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
|
|
|
7651 effect(DEF dst, USE src1, USE src2);
|
|
|
7652 size(4);
|
|
|
7653 format %{ "FSUBD $src1,$src2,$dst" %}
|
|
|
7654 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
|
|
|
7655 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
|
|
|
7656 ins_pipe(faddD_reg_reg);
|
|
|
7657 %}
|
|
|
7658
|
|
|
7659 // Mul float double precision
|
|
|
7660 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
|
|
|
7661 effect(DEF dst, USE src1, USE src2);
|
|
|
7662 size(4);
|
|
|
7663 format %{ "FMULD $src1,$src2,$dst" %}
|
|
|
7664 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
|
|
|
7665 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
|
|
|
7666 ins_pipe(fmulD_reg_reg);
|
|
|
7667 %}
|
|
|
7668
|
|
|
7669 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
|
|
|
7670 match(Set dst (ConvL2D src));
|
|
|
7671 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
|
|
|
7672
|
|
|
7673 expand %{
|
|
|
7674 regD_low tmpsrc;
|
|
|
7675 iRegI ix43300000;
|
|
|
7676 iRegI ix41f00000;
|
|
|
7677 stackSlotL lx43300000;
|
|
|
7678 stackSlotL lx41f00000;
|
|
|
7679 regD_low dx43300000;
|
|
|
7680 regD dx41f00000;
|
|
|
7681 regD tmp1;
|
|
|
7682 regD_low tmp2;
|
|
|
7683 regD tmp3;
|
|
|
7684 regD tmp4;
|
|
|
7685
|
|
|
7686 stkL_to_regD(tmpsrc, src);
|
|
|
7687
|
|
|
7688 loadConI_x43300000(ix43300000);
|
|
|
7689 loadConI_x41f00000(ix41f00000);
|
|
|
7690 regI_to_stkLHi(lx43300000, ix43300000);
|
|
|
7691 regI_to_stkLHi(lx41f00000, ix41f00000);
|
|
|
7692 stkL_to_regD(dx43300000, lx43300000);
|
|
|
7693 stkL_to_regD(dx41f00000, lx41f00000);
|
|
|
7694
|
|
|
7695 convI2D_regDHi_regD(tmp1, tmpsrc);
|
|
|
7696 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
|
|
|
7697 subD_regD_regD(tmp3, tmp2, dx43300000);
|
|
|
7698 mulD_regD_regD(tmp4, tmp1, dx41f00000);
|
|
|
7699 addD_regD_regD(dst, tmp3, tmp4);
|
|
|
7700 %}
|
|
|
7701 %}
|
|
|
7702
|
|
|
7703 // Long to Double conversion using fast fxtof
|
|
|
7704 instruct convL2D_helper(regD dst, regD tmp) %{
|
|
|
7705 effect(DEF dst, USE tmp);
|
|
|
7706 size(4);
|
|
|
7707 format %{ "FXTOD $tmp,$dst" %}
|
|
|
7708 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
|
|
|
7709 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
|
|
|
7710 ins_pipe(fcvtL2D);
|
|
|
7711 %}
|
|
|
7712
|
|
|
7713 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{
|
|
|
7714 predicate(VM_Version::has_fast_fxtof());
|
|
|
7715 match(Set dst (ConvL2D src));
|
|
|
7716 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
|
|
|
7717 expand %{
|
|
|
7718 regD tmp;
|
|
|
7719 stkL_to_regD(tmp, src);
|
|
|
7720 convL2D_helper(dst, tmp);
|
|
|
7721 %}
|
|
|
7722 %}
|
|
|
7723
|
|
|
7724 //-----------
|
|
|
7725 // Long to Float conversion using V8 opcodes.
|
|
|
7726 // Still useful because cheetah traps and becomes
|
|
|
7727 // amazingly slow for some common numbers.
|
|
|
7728
|
|
|
7729 // Long to Float conversion using fast fxtof
|
|
|
7730 instruct convL2F_helper(regF dst, regD tmp) %{
|
|
|
7731 effect(DEF dst, USE tmp);
|
|
|
7732 size(4);
|
|
|
7733 format %{ "FXTOS $tmp,$dst" %}
|
|
|
7734 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
|
|
|
7735 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
|
|
|
7736 ins_pipe(fcvtL2F);
|
|
|
7737 %}
|
|
|
7738
|
|
|
7739 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{
|
|
|
7740 match(Set dst (ConvL2F src));
|
|
|
7741 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
|
|
|
7742 expand %{
|
|
|
7743 regD tmp;
|
|
|
7744 stkL_to_regD(tmp, src);
|
|
|
7745 convL2F_helper(dst, tmp);
|
|
|
7746 %}
|
|
|
7747 %}
|
|
|
7748 //-----------
|
|
|
7749
|
|
|
7750 instruct convL2I_reg(iRegI dst, iRegL src) %{
|
|
|
7751 match(Set dst (ConvL2I src));
|
|
|
7752 #ifndef _LP64
|
|
|
7753 format %{ "MOV $src.lo,$dst\t! long->int" %}
|
|
|
7754 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
|
|
|
7755 ins_pipe(ialu_move_reg_I_to_L);
|
|
|
7756 #else
|
|
|
7757 size(4);
|
|
|
7758 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
|
|
|
7759 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
|
|
|
7760 ins_pipe(ialu_reg);
|
|
|
7761 #endif
|
|
|
7762 %}
|
|
|
7763
|
|
|
7764 // Register Shift Right Immediate
|
|
|
7765 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
|
|
|
7766 match(Set dst (ConvL2I (RShiftL src cnt)));
|
|
|
7767
|
|
|
7768 size(4);
|
|
|
7769 format %{ "SRAX $src,$cnt,$dst" %}
|
|
|
7770 opcode(Assembler::srax_op3, Assembler::arith_op);
|
|
|
7771 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
|
|
|
7772 ins_pipe(ialu_reg_imm);
|
|
|
7773 %}
|
|
|
7774
|
|
|
7775 // Replicate scalar to packed byte values in Double register
|
|
|
7776 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{
|
|
|
7777 effect(DEF dst, USE src);
|
|
|
7778 format %{ "SLLX $src,56,$dst\n\t"
|
|
|
7779 "SRLX $dst, 8,O7\n\t"
|
|
|
7780 "OR $dst,O7,$dst\n\t"
|
|
|
7781 "SRLX $dst,16,O7\n\t"
|
|
|
7782 "OR $dst,O7,$dst\n\t"
|
|
|
7783 "SRLX $dst,32,O7\n\t"
|
|
|
7784 "OR $dst,O7,$dst\t! replicate8B" %}
|
|
|
7785 ins_encode( enc_repl8b(src, dst));
|
|
|
7786 ins_pipe(ialu_reg);
|
|
|
7787 %}
|
|
|
7788
|
|
|
7789 // Replicate scalar to packed byte values in Double register
|
|
|
7790 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{
|
|
|
7791 match(Set dst (Replicate8B src));
|
|
|
7792 expand %{
|
|
|
7793 iRegL tmp;
|
|
|
7794 Repl8B_reg_helper(tmp, src);
|
|
|
7795 regL_to_stkD(dst, tmp);
|
|
|
7796 %}
|
|
|
7797 %}
|
|
|
7798
|
|
|
7799 // Replicate scalar constant to packed byte values in Double register
|
|
|
7800 instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{
|
|
|
7801 match(Set dst (Replicate8B src));
|
|
|
7802 #ifdef _LP64
|
|
|
7803 size(36);
|
|
|
7804 #else
|
|
|
7805 size(8);
|
|
|
7806 #endif
|
|
|
7807 format %{ "SETHI hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t"
|
|
|
7808 "LDDF [$tmp+lo(&Repl8($src))],$dst" %}
|
|
|
7809 ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) );
|
|
|
7810 ins_pipe(loadConFD);
|
|
|
7811 %}
|
|
|
7812
|
|
|
7813 // Replicate scalar to packed char values into stack slot
|
|
|
7814 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{
|
|
|
7815 effect(DEF dst, USE src);
|
|
|
7816 format %{ "SLLX $src,48,$dst\n\t"
|
|
|
7817 "SRLX $dst,16,O7\n\t"
|
|
|
7818 "OR $dst,O7,$dst\n\t"
|
|
|
7819 "SRLX $dst,32,O7\n\t"
|
|
|
7820 "OR $dst,O7,$dst\t! replicate4C" %}
|
|
|
7821 ins_encode( enc_repl4s(src, dst) );
|
|
|
7822 ins_pipe(ialu_reg);
|
|
|
7823 %}
|
|
|
7824
|
|
|
7825 // Replicate scalar to packed char values into stack slot
|
|
|
7826 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{
|
|
|
7827 match(Set dst (Replicate4C src));
|
|
|
7828 expand %{
|
|
|
7829 iRegL tmp;
|
|
|
7830 Repl4C_reg_helper(tmp, src);
|
|
|
7831 regL_to_stkD(dst, tmp);
|
|
|
7832 %}
|
|
|
7833 %}
|
|
|
7834
|
|
|
7835 // Replicate scalar constant to packed char values in Double register
|
|
|
7836 instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{
|
|
|
7837 match(Set dst (Replicate4C src));
|
|
|
7838 #ifdef _LP64
|
|
|
7839 size(36);
|
|
|
7840 #else
|
|
|
7841 size(8);
|
|
|
7842 #endif
|
|
|
7843 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t"
|
|
|
7844 "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
|
|
|
7845 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
|
|
|
7846 ins_pipe(loadConFD);
|
|
|
7847 %}
|
|
|
7848
|
|
|
7849 // Replicate scalar to packed short values into stack slot
|
|
|
7850 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{
|
|
|
7851 effect(DEF dst, USE src);
|
|
|
7852 format %{ "SLLX $src,48,$dst\n\t"
|
|
|
7853 "SRLX $dst,16,O7\n\t"
|
|
|
7854 "OR $dst,O7,$dst\n\t"
|
|
|
7855 "SRLX $dst,32,O7\n\t"
|
|
|
7856 "OR $dst,O7,$dst\t! replicate4S" %}
|
|
|
7857 ins_encode( enc_repl4s(src, dst) );
|
|
|
7858 ins_pipe(ialu_reg);
|
|
|
7859 %}
|
|
|
7860
|
|
|
7861 // Replicate scalar to packed short values into stack slot
|
|
|
7862 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{
|
|
|
7863 match(Set dst (Replicate4S src));
|
|
|
7864 expand %{
|
|
|
7865 iRegL tmp;
|
|
|
7866 Repl4S_reg_helper(tmp, src);
|
|
|
7867 regL_to_stkD(dst, tmp);
|
|
|
7868 %}
|
|
|
7869 %}
|
|
|
7870
|
|
|
7871 // Replicate scalar constant to packed short values in Double register
|
|
|
7872 instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{
|
|
|
7873 match(Set dst (Replicate4S src));
|
|
|
7874 #ifdef _LP64
|
|
|
7875 size(36);
|
|
|
7876 #else
|
|
|
7877 size(8);
|
|
|
7878 #endif
|
|
|
7879 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t"
|
|
|
7880 "LDDF [$tmp+lo(&Repl4($src))],$dst" %}
|
|
|
7881 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
|
|
|
7882 ins_pipe(loadConFD);
|
|
|
7883 %}
|
|
|
7884
|
|
|
7885 // Replicate scalar to packed int values in Double register
|
|
|
7886 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{
|
|
|
7887 effect(DEF dst, USE src);
|
|
|
7888 format %{ "SLLX $src,32,$dst\n\t"
|
|
|
7889 "SRLX $dst,32,O7\n\t"
|
|
|
7890 "OR $dst,O7,$dst\t! replicate2I" %}
|
|
|
7891 ins_encode( enc_repl2i(src, dst));
|
|
|
7892 ins_pipe(ialu_reg);
|
|
|
7893 %}
|
|
|
7894
|
|
|
7895 // Replicate scalar to packed int values in Double register
|
|
|
7896 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{
|
|
|
7897 match(Set dst (Replicate2I src));
|
|
|
7898 expand %{
|
|
|
7899 iRegL tmp;
|
|
|
7900 Repl2I_reg_helper(tmp, src);
|
|
|
7901 regL_to_stkD(dst, tmp);
|
|
|
7902 %}
|
|
|
7903 %}
|
|
|
7904
|
|
|
7905 // Replicate scalar zero constant to packed int values in Double register
|
|
|
7906 instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{
|
|
|
7907 match(Set dst (Replicate2I src));
|
|
|
7908 #ifdef _LP64
|
|
|
7909 size(36);
|
|
|
7910 #else
|
|
|
7911 size(8);
|
|
|
7912 #endif
|
|
|
7913 format %{ "SETHI hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t"
|
|
|
7914 "LDDF [$tmp+lo(&Repl2($src))],$dst" %}
|
|
|
7915 ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) );
|
|
|
7916 ins_pipe(loadConFD);
|
|
|
7917 %}
|
|
|
7918
|
|
|
7919 //----------Control Flow Instructions------------------------------------------
|
|
|
7920 // Compare Instructions
|
|
|
7921 // Compare Integers
|
|
|
7922 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
|
|
|
7923 match(Set icc (CmpI op1 op2));
|
|
|
7924 effect( DEF icc, USE op1, USE op2 );
|
|
|
7925
|
|
|
7926 size(4);
|
|
|
7927 format %{ "CMP $op1,$op2" %}
|
|
|
7928 opcode(Assembler::subcc_op3, Assembler::arith_op);
|
|
|
7929 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
|
|
|
7930 ins_pipe(ialu_cconly_reg_reg);
|
|
|
7931 %}
|
|
|
7932
|
|
|
7933 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
|
|
|
7934 match(Set icc (CmpU op1 op2));
|
|
|
7935
|
|
|
7936 size(4);
|
|
|
7937 format %{ "CMP $op1,$op2\t! unsigned" %}
|
|
|
7938 opcode(Assembler::subcc_op3, Assembler::arith_op);
|
|
|
7939 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
|
|
|
7940 ins_pipe(ialu_cconly_reg_reg);
|
|
|
7941 %}
|
|
|
7942
|
|
|
7943 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
|
|
|
7944 match(Set icc (CmpI op1 op2));
|
|
|
7945 effect( DEF icc, USE op1 );
|
|
|
7946
|
|
|
7947 size(4);
|
|
|
7948 format %{ "CMP $op1,$op2" %}
|
|
|
7949 opcode(Assembler::subcc_op3, Assembler::arith_op);
|
|
|
7950 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
|
|
|
7951 ins_pipe(ialu_cconly_reg_imm);
|
|
|
7952 %}
|
|
|
7953
|
|
|
7954 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
|
|
|
7955 match(Set icc (CmpI (AndI op1 op2) zero));
|
|
|
7956
|
|
|
7957 size(4);
|
|
|
7958 format %{ "BTST $op2,$op1" %}
|
|
|
7959 opcode(Assembler::andcc_op3, Assembler::arith_op);
|
|
|
7960 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
|
|
|
7961 ins_pipe(ialu_cconly_reg_reg_zero);
|
|
|
7962 %}
|
|
|
7963
|
|
|
7964 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
|
|
|
7965 match(Set icc (CmpI (AndI op1 op2) zero));
|
|
|
7966
|
|
|
7967 size(4);
|
|
|
7968 format %{ "BTST $op2,$op1" %}
|
|
|
7969 opcode(Assembler::andcc_op3, Assembler::arith_op);
|
|
|
7970 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
|
|
|
7971 ins_pipe(ialu_cconly_reg_imm_zero);
|
|
|
7972 %}
|
|
|
7973
|
|
|
7974 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
|
|
|
7975 match(Set xcc (CmpL op1 op2));
|
|
|
7976 effect( DEF xcc, USE op1, USE op2 );
|
|
|
7977
|
|
|
7978 size(4);
|
|
|
7979 format %{ "CMP $op1,$op2\t\t! long" %}
|
|
|
7980 opcode(Assembler::subcc_op3, Assembler::arith_op);
|
|
|
7981 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
|
|
|
7982 ins_pipe(ialu_cconly_reg_reg);
|
|
|
7983 %}
|
|
|
7984
|
|
|
7985 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
|
|
|
7986 match(Set xcc (CmpL op1 con));
|
|
|
7987 effect( DEF xcc, USE op1, USE con );
|
|
|
7988
|
|
|
7989 size(4);
|
|
|
7990 format %{ "CMP $op1,$con\t\t! long" %}
|
|
|
7991 opcode(Assembler::subcc_op3, Assembler::arith_op);
|
|
|
7992 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
|
|
|
7993 ins_pipe(ialu_cconly_reg_reg);
|
|
|
7994 %}
|
|
|
7995
|
|
|
7996 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
|
|
|
7997 match(Set xcc (CmpL (AndL op1 op2) zero));
|
|
|
7998 effect( DEF xcc, USE op1, USE op2 );
|
|
|
7999
|
|
|
8000 size(4);
|
|
|
8001 format %{ "BTST $op1,$op2\t\t! long" %}
|
|
|
8002 opcode(Assembler::andcc_op3, Assembler::arith_op);
|
|
|
8003 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
|
|
|
8004 ins_pipe(ialu_cconly_reg_reg);
|
|
|
8005 %}
|
|
|
8006
|
|
|
8007 // useful for checking the alignment of a pointer:
|
|
|
8008 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
|
|
|
8009 match(Set xcc (CmpL (AndL op1 con) zero));
|
|
|
8010 effect( DEF xcc, USE op1, USE con );
|
|
|
8011
|
|
|
8012 size(4);
|
|
|
8013 format %{ "BTST $op1,$con\t\t! long" %}
|
|
|
8014 opcode(Assembler::andcc_op3, Assembler::arith_op);
|
|
|
8015 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
|
|
|
8016 ins_pipe(ialu_cconly_reg_reg);
|
|
|
8017 %}
|
|
|
8018
|
|
|
8019 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
|
|
|
8020 match(Set icc (CmpU op1 op2));
|
|
|
8021
|
|
|
8022 size(4);
|
|
|
8023 format %{ "CMP $op1,$op2\t! unsigned" %}
|
|
|
8024 opcode(Assembler::subcc_op3, Assembler::arith_op);
|
|
|
8025 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
|
|
|
8026 ins_pipe(ialu_cconly_reg_imm);
|
|
|
8027 %}
|
|
|
8028
|
|
|
8029 // Compare Pointers
|
|
|
8030 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
|
|
|
8031 match(Set pcc (CmpP op1 op2));
|
|
|
8032
|
|
|
8033 size(4);
|
|
|
8034 format %{ "CMP $op1,$op2\t! ptr" %}
|
|
|
8035 opcode(Assembler::subcc_op3, Assembler::arith_op);
|
|
|
8036 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
|
|
|
8037 ins_pipe(ialu_cconly_reg_reg);
|
|
|
8038 %}
|
|
|
8039
|
|
|
8040 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
|
|
|
8041 match(Set pcc (CmpP op1 op2));
|
|
|
8042
|
|
|
8043 size(4);
|
|
|
8044 format %{ "CMP $op1,$op2\t! ptr" %}
|
|
|
8045 opcode(Assembler::subcc_op3, Assembler::arith_op);
|
|
|
8046 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
|
|
|
8047 ins_pipe(ialu_cconly_reg_imm);
|
|
|
8048 %}
|
|
|
8049
|
|
|
8050 //----------Max and Min--------------------------------------------------------
|
|
|
8051 // Min Instructions
|
|
|
8052 // Conditional move for min
|
|
|
8053 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
|
|
|
8054 effect( USE_DEF op2, USE op1, USE icc );
|
|
|
8055
|
|
|
8056 size(4);
|
|
|
8057 format %{ "MOVlt icc,$op1,$op2\t! min" %}
|
|
|
8058 opcode(Assembler::less);
|
|
|
8059 ins_encode( enc_cmov_reg_minmax(op2,op1) );
|
|
|
8060 ins_pipe(ialu_reg_flags);
|
|
|
8061 %}
|
|
|
8062
|
|
|
8063 // Min Register with Register.
|
|
|
8064 instruct minI_eReg(iRegI op1, iRegI op2) %{
|
|
|
8065 match(Set op2 (MinI op1 op2));
|
|
|
8066 ins_cost(DEFAULT_COST*2);
|
|
|
8067 expand %{
|
|
|
8068 flagsReg icc;
|
|
|
8069 compI_iReg(icc,op1,op2);
|
|
|
8070 cmovI_reg_lt(op2,op1,icc);
|
|
|
8071 %}
|
|
|
8072 %}
|
|
|
8073
|
|
|
8074 // Max Instructions
|
|
|
8075 // Conditional move for max
|
|
|
8076 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
|
|
|
8077 effect( USE_DEF op2, USE op1, USE icc );
|
|
|
8078 format %{ "MOVgt icc,$op1,$op2\t! max" %}
|
|
|
8079 opcode(Assembler::greater);
|
|
|
8080 ins_encode( enc_cmov_reg_minmax(op2,op1) );
|
|
|
8081 ins_pipe(ialu_reg_flags);
|
|
|
8082 %}
|
|
|
8083
|
|
|
8084 // Max Register with Register
|
|
|
8085 instruct maxI_eReg(iRegI op1, iRegI op2) %{
|
|
|
8086 match(Set op2 (MaxI op1 op2));
|
|
|
8087 ins_cost(DEFAULT_COST*2);
|
|
|
8088 expand %{
|
|
|
8089 flagsReg icc;
|
|
|
8090 compI_iReg(icc,op1,op2);
|
|
|
8091 cmovI_reg_gt(op2,op1,icc);
|
|
|
8092 %}
|
|
|
8093 %}
|
|
|
8094
|
|
|
8095
|
|
|
8096 //----------Float Compares----------------------------------------------------
|
|
|
8097 // Compare floating, generate condition code
|
|
|
8098 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
|
|
|
8099 match(Set fcc (CmpF src1 src2));
|
|
|
8100
|
|
|
8101 size(4);
|
|
|
8102 format %{ "FCMPs $fcc,$src1,$src2" %}
|
|
|
8103 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
|
|
|
8104 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
|
|
|
8105 ins_pipe(faddF_fcc_reg_reg_zero);
|
|
|
8106 %}
|
|
|
8107
|
|
|
8108 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
|
|
|
8109 match(Set fcc (CmpD src1 src2));
|
|
|
8110
|
|
|
8111 size(4);
|
|
|
8112 format %{ "FCMPd $fcc,$src1,$src2" %}
|
|
|
8113 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
|
|
|
8114 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
|
|
|
8115 ins_pipe(faddD_fcc_reg_reg_zero);
|
|
|
8116 %}
|
|
|
8117
|
|
|
8118
|
|
|
8119 // Compare floating, generate -1,0,1
|
|
|
8120 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
|
|
|
8121 match(Set dst (CmpF3 src1 src2));
|
|
|
8122 effect(KILL fcc0);
|
|
|
8123 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
|
|
|
8124 format %{ "fcmpl $dst,$src1,$src2" %}
|
|
|
8125 // Primary = float
|
|
|
8126 opcode( true );
|
|
|
8127 ins_encode( floating_cmp( dst, src1, src2 ) );
|
|
|
8128 ins_pipe( floating_cmp );
|
|
|
8129 %}
|
|
|
8130
|
|
|
8131 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
|
|
|
8132 match(Set dst (CmpD3 src1 src2));
|
|
|
8133 effect(KILL fcc0);
|
|
|
8134 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
|
|
|
8135 format %{ "dcmpl $dst,$src1,$src2" %}
|
|
|
8136 // Primary = double (not float)
|
|
|
8137 opcode( false );
|
|
|
8138 ins_encode( floating_cmp( dst, src1, src2 ) );
|
|
|
8139 ins_pipe( floating_cmp );
|
|
|
8140 %}
|
|
|
8141
|
|
|
8142 //----------Branches---------------------------------------------------------
|
|
|
8143 // Jump
|
|
|
8144 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
|
|
|
8145 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
|
|
|
8146 match(Jump switch_val);
|
|
|
8147
|
|
|
8148 ins_cost(350);
|
|
|
8149
|
|
|
8150 format %{ "SETHI [hi(table_base)],O7\n\t"
|
|
|
8151 "ADD O7, lo(table_base), O7\n\t"
|
|
|
8152 "LD [O7+$switch_val], O7\n\t"
|
|
|
8153 "JUMP O7"
|
|
|
8154 %}
|
|
|
8155 ins_encode( jump_enc( switch_val, table) );
|
|
|
8156 ins_pc_relative(1);
|
|
|
8157 ins_pipe(ialu_reg_reg);
|
|
|
8158 %}
|
|
|
8159
|
|
|
8160 // Direct Branch. Use V8 version with longer range.
|
|
|
8161 instruct branch(label labl) %{
|
|
|
8162 match(Goto);
|
|
|
8163 effect(USE labl);
|
|
|
8164
|
|
|
8165 size(8);
|
|
|
8166 ins_cost(BRANCH_COST);
|
|
|
8167 format %{ "BA $labl" %}
|
|
|
8168 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond
|
|
|
8169 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always);
|
|
|
8170 ins_encode( enc_ba( labl ) );
|
|
|
8171 ins_pc_relative(1);
|
|
|
8172 ins_pipe(br);
|
|
|
8173 %}
|
|
|
8174
|
|
|
8175 // Conditional Direct Branch
|
|
|
8176 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
|
|
|
8177 match(If cmp icc);
|
|
|
8178 effect(USE labl);
|
|
|
8179
|
|
|
8180 size(8);
|
|
|
8181 ins_cost(BRANCH_COST);
|
|
|
8182 format %{ "BP$cmp $icc,$labl" %}
|
|
|
8183 // Prim = bits 24-22, Secnd = bits 31-30
|
|
|
8184 ins_encode( enc_bp( labl, cmp, icc ) );
|
|
|
8185 ins_pc_relative(1);
|
|
|
8186 ins_pipe(br_cc);
|
|
|
8187 %}
|
|
|
8188
|
|
|
8189 // Branch-on-register tests all 64 bits. We assume that values
|
|
|
8190 // in 64-bit registers always remains zero or sign extended
|
|
|
8191 // unless our code munges the high bits. Interrupts can chop
|
|
|
8192 // the high order bits to zero or sign at any time.
|
|
|
8193 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
|
|
|
8194 match(If cmp (CmpI op1 zero));
|
|
|
8195 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
|
|
|
8196 effect(USE labl);
|
|
|
8197
|
|
|
8198 size(8);
|
|
|
8199 ins_cost(BRANCH_COST);
|
|
|
8200 format %{ "BR$cmp $op1,$labl" %}
|
|
|
8201 ins_encode( enc_bpr( labl, cmp, op1 ) );
|
|
|
8202 ins_pc_relative(1);
|
|
|
8203 ins_pipe(br_reg);
|
|
|
8204 %}
|
|
|
8205
|
|
|
8206 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
|
|
|
8207 match(If cmp (CmpP op1 null));
|
|
|
8208 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
|
|
|
8209 effect(USE labl);
|
|
|
8210
|
|
|
8211 size(8);
|
|
|
8212 ins_cost(BRANCH_COST);
|
|
|
8213 format %{ "BR$cmp $op1,$labl" %}
|
|
|
8214 ins_encode( enc_bpr( labl, cmp, op1 ) );
|
|
|
8215 ins_pc_relative(1);
|
|
|
8216 ins_pipe(br_reg);
|
|
|
8217 %}
|
|
|
8218
|
|
|
8219 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
|
|
|
8220 match(If cmp (CmpL op1 zero));
|
|
|
8221 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
|
|
|
8222 effect(USE labl);
|
|
|
8223
|
|
|
8224 size(8);
|
|
|
8225 ins_cost(BRANCH_COST);
|
|
|
8226 format %{ "BR$cmp $op1,$labl" %}
|
|
|
8227 ins_encode( enc_bpr( labl, cmp, op1 ) );
|
|
|
8228 ins_pc_relative(1);
|
|
|
8229 ins_pipe(br_reg);
|
|
|
8230 %}
|
|
|
8231
|
|
|
8232 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
|
|
|
8233 match(If cmp icc);
|
|
|
8234 effect(USE labl);
|
|
|
8235
|
|
|
8236 format %{ "BP$cmp $icc,$labl" %}
|
|
|
8237 // Prim = bits 24-22, Secnd = bits 31-30
|
|
|
8238 ins_encode( enc_bp( labl, cmp, icc ) );
|
|
|
8239 ins_pc_relative(1);
|
|
|
8240 ins_pipe(br_cc);
|
|
|
8241 %}
|
|
|
8242
|
|
|
8243 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
|
|
|
8244 match(If cmp pcc);
|
|
|
8245 effect(USE labl);
|
|
|
8246
|
|
|
8247 size(8);
|
|
|
8248 ins_cost(BRANCH_COST);
|
|
|
8249 format %{ "BP$cmp $pcc,$labl" %}
|
|
|
8250 // Prim = bits 24-22, Secnd = bits 31-30
|
|
|
8251 ins_encode( enc_bpx( labl, cmp, pcc ) );
|
|
|
8252 ins_pc_relative(1);
|
|
|
8253 ins_pipe(br_cc);
|
|
|
8254 %}
|
|
|
8255
|
|
|
8256 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
|
|
|
8257 match(If cmp fcc);
|
|
|
8258 effect(USE labl);
|
|
|
8259
|
|
|
8260 size(8);
|
|
|
8261 ins_cost(BRANCH_COST);
|
|
|
8262 format %{ "FBP$cmp $fcc,$labl" %}
|
|
|
8263 // Prim = bits 24-22, Secnd = bits 31-30
|
|
|
8264 ins_encode( enc_fbp( labl, cmp, fcc ) );
|
|
|
8265 ins_pc_relative(1);
|
|
|
8266 ins_pipe(br_fcc);
|
|
|
8267 %}
|
|
|
8268
|
|
|
8269 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
|
|
|
8270 match(CountedLoopEnd cmp icc);
|
|
|
8271 effect(USE labl);
|
|
|
8272
|
|
|
8273 size(8);
|
|
|
8274 ins_cost(BRANCH_COST);
|
|
|
8275 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
|
|
|
8276 // Prim = bits 24-22, Secnd = bits 31-30
|
|
|
8277 ins_encode( enc_bp( labl, cmp, icc ) );
|
|
|
8278 ins_pc_relative(1);
|
|
|
8279 ins_pipe(br_cc);
|
|
|
8280 %}
|
|
|
8281
|
|
|
8282 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
|
|
|
8283 match(CountedLoopEnd cmp icc);
|
|
|
8284 effect(USE labl);
|
|
|
8285
|
|
|
8286 size(8);
|
|
|
8287 ins_cost(BRANCH_COST);
|
|
|
8288 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
|
|
|
8289 // Prim = bits 24-22, Secnd = bits 31-30
|
|
|
8290 ins_encode( enc_bp( labl, cmp, icc ) );
|
|
|
8291 ins_pc_relative(1);
|
|
|
8292 ins_pipe(br_cc);
|
|
|
8293 %}
|
|
|
8294
|
|
|
8295 // ============================================================================
|
|
|
8296 // Long Compare
|
|
|
8297 //
|
|
|
8298 // Currently we hold longs in 2 registers. Comparing such values efficiently
|
|
|
8299 // is tricky. The flavor of compare used depends on whether we are testing
|
|
|
8300 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
|
|
|
8301 // The GE test is the negated LT test. The LE test can be had by commuting
|
|
|
8302 // the operands (yielding a GE test) and then negating; negate again for the
|
|
|
8303 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
|
|
|
8304 // NE test is negated from that.
|
|
|
8305
|
|
|
8306 // Due to a shortcoming in the ADLC, it mixes up expressions like:
|
|
|
8307 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
|
|
|
8308 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
|
|
|
8309 // are collapsed internally in the ADLC's dfa-gen code. The match for
|
|
|
8310 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
|
|
|
8311 // foo match ends up with the wrong leaf. One fix is to not match both
|
|
|
8312 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
|
|
|
8313 // both forms beat the trinary form of long-compare and both are very useful
|
|
|
8314 // on Intel which has so few registers.
|
|
|
8315
|
|
|
8316 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
|
|
|
8317 match(If cmp xcc);
|
|
|
8318 effect(USE labl);
|
|
|
8319
|
|
|
8320 size(8);
|
|
|
8321 ins_cost(BRANCH_COST);
|
|
|
8322 format %{ "BP$cmp $xcc,$labl" %}
|
|
|
8323 // Prim = bits 24-22, Secnd = bits 31-30
|
|
|
8324 ins_encode( enc_bpl( labl, cmp, xcc ) );
|
|
|
8325 ins_pc_relative(1);
|
|
|
8326 ins_pipe(br_cc);
|
|
|
8327 %}
|
|
|
8328
|
|
|
8329 // Manifest a CmpL3 result in an integer register. Very painful.
|
|
|
8330 // This is the test to avoid.
|
|
|
8331 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
|
|
|
8332 match(Set dst (CmpL3 src1 src2) );
|
|
|
8333 effect( KILL ccr );
|
|
|
8334 ins_cost(6*DEFAULT_COST);
|
|
|
8335 size(24);
|
|
|
8336 format %{ "CMP $src1,$src2\t\t! long\n"
|
|
|
8337 "\tBLT,a,pn done\n"
|
|
|
8338 "\tMOV -1,$dst\t! delay slot\n"
|
|
|
8339 "\tBGT,a,pn done\n"
|
|
|
8340 "\tMOV 1,$dst\t! delay slot\n"
|
|
|
8341 "\tCLR $dst\n"
|
|
|
8342 "done:" %}
|
|
|
8343 ins_encode( cmpl_flag(src1,src2,dst) );
|
|
|
8344 ins_pipe(cmpL_reg);
|
|
|
8345 %}
|
|
|
8346
|
|
|
8347 // Conditional move
|
|
|
8348 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
|
|
|
8349 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
|
|
|
8350 ins_cost(150);
|
|
|
8351 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
|
|
|
8352 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
|
|
|
8353 ins_pipe(ialu_reg);
|
|
|
8354 %}
|
|
|
8355
|
|
|
8356 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
|
|
|
8357 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
|
|
|
8358 ins_cost(140);
|
|
|
8359 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
|
|
|
8360 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
|
|
|
8361 ins_pipe(ialu_imm);
|
|
|
8362 %}
|
|
|
8363
|
|
|
8364 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
|
|
|
8365 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
|
|
|
8366 ins_cost(150);
|
|
|
8367 format %{ "MOV$cmp $xcc,$src,$dst" %}
|
|
|
8368 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
|
|
|
8369 ins_pipe(ialu_reg);
|
|
|
8370 %}
|
|
|
8371
|
|
|
8372 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
|
|
|
8373 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
|
|
|
8374 ins_cost(140);
|
|
|
8375 format %{ "MOV$cmp $xcc,$src,$dst" %}
|
|
|
8376 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
|
|
|
8377 ins_pipe(ialu_imm);
|
|
|
8378 %}
|
|
|
8379
|
|
|
8380 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
|
|
|
8381 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
|
|
|
8382 ins_cost(150);
|
|
|
8383 format %{ "MOV$cmp $xcc,$src,$dst" %}
|
|
|
8384 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
|
|
|
8385 ins_pipe(ialu_reg);
|
|
|
8386 %}
|
|
|
8387
|
|
|
8388 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
|
|
|
8389 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
|
|
|
8390 ins_cost(140);
|
|
|
8391 format %{ "MOV$cmp $xcc,$src,$dst" %}
|
|
|
8392 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
|
|
|
8393 ins_pipe(ialu_imm);
|
|
|
8394 %}
|
|
|
8395
|
|
|
8396 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
|
|
|
8397 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
|
|
|
8398 ins_cost(150);
|
|
|
8399 opcode(0x101);
|
|
|
8400 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
|
|
|
8401 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
|
|
|
8402 ins_pipe(int_conditional_float_move);
|
|
|
8403 %}
|
|
|
8404
|
|
|
8405 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
|
|
|
8406 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
|
|
|
8407 ins_cost(150);
|
|
|
8408 opcode(0x102);
|
|
|
8409 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
|
|
|
8410 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
|
|
|
8411 ins_pipe(int_conditional_float_move);
|
|
|
8412 %}
|
|
|
8413
|
|
|
8414 // ============================================================================
|
|
|
8415 // Safepoint Instruction
|
|
|
8416 instruct safePoint_poll(iRegP poll) %{
|
|
|
8417 match(SafePoint poll);
|
|
|
8418 effect(USE poll);
|
|
|
8419
|
|
|
8420 size(4);
|
|
|
8421 #ifdef _LP64
|
|
|
8422 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
|
|
|
8423 #else
|
|
|
8424 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
|
|
|
8425 #endif
|
|
|
8426 ins_encode %{
|
|
|
8427 __ relocate(relocInfo::poll_type);
|
|
|
8428 __ ld_ptr($poll$$Register, 0, G0);
|
|
|
8429 %}
|
|
|
8430 ins_pipe(loadPollP);
|
|
|
8431 %}
|
|
|
8432
|
|
|
8433 // ============================================================================
|
|
|
8434 // Call Instructions
|
|
|
8435 // Call Java Static Instruction
|
|
|
8436 instruct CallStaticJavaDirect( method meth ) %{
|
|
|
8437 match(CallStaticJava);
|
|
|
8438 effect(USE meth);
|
|
|
8439
|
|
|
8440 size(8);
|
|
|
8441 ins_cost(CALL_COST);
|
|
|
8442 format %{ "CALL,static ; NOP ==> " %}
|
|
|
8443 ins_encode( Java_Static_Call( meth ), call_epilog );
|
|
|
8444 ins_pc_relative(1);
|
|
|
8445 ins_pipe(simple_call);
|
|
|
8446 %}
|
|
|
8447
|
|
|
8448 // Call Java Dynamic Instruction
|
|
|
8449 instruct CallDynamicJavaDirect( method meth ) %{
|
|
|
8450 match(CallDynamicJava);
|
|
|
8451 effect(USE meth);
|
|
|
8452
|
|
|
8453 ins_cost(CALL_COST);
|
|
|
8454 format %{ "SET (empty),R_G5\n\t"
|
|
|
8455 "CALL,dynamic ; NOP ==> " %}
|
|
|
8456 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
|
|
|
8457 ins_pc_relative(1);
|
|
|
8458 ins_pipe(call);
|
|
|
8459 %}
|
|
|
8460
|
|
|
8461 // Call Runtime Instruction
|
|
|
8462 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
|
|
|
8463 match(CallRuntime);
|
|
|
8464 effect(USE meth, KILL l7);
|
|
|
8465 ins_cost(CALL_COST);
|
|
|
8466 format %{ "CALL,runtime" %}
|
|
|
8467 ins_encode( Java_To_Runtime( meth ),
|
|
|
8468 call_epilog, adjust_long_from_native_call );
|
|
|
8469 ins_pc_relative(1);
|
|
|
8470 ins_pipe(simple_call);
|
|
|
8471 %}
|
|
|
8472
|
|
|
8473 // Call runtime without safepoint - same as CallRuntime
|
|
|
8474 instruct CallLeafDirect(method meth, l7RegP l7) %{
|
|
|
8475 match(CallLeaf);
|
|
|
8476 effect(USE meth, KILL l7);
|
|
|
8477 ins_cost(CALL_COST);
|
|
|
8478 format %{ "CALL,runtime leaf" %}
|
|
|
8479 ins_encode( Java_To_Runtime( meth ),
|
|
|
8480 call_epilog,
|
|
|
8481 adjust_long_from_native_call );
|
|
|
8482 ins_pc_relative(1);
|
|
|
8483 ins_pipe(simple_call);
|
|
|
8484 %}
|
|
|
8485
|
|
|
8486 // Call runtime without safepoint - same as CallLeaf
|
|
|
8487 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
|
|
|
8488 match(CallLeafNoFP);
|
|
|
8489 effect(USE meth, KILL l7);
|
|
|
8490 ins_cost(CALL_COST);
|
|
|
8491 format %{ "CALL,runtime leaf nofp" %}
|
|
|
8492 ins_encode( Java_To_Runtime( meth ),
|
|
|
8493 call_epilog,
|
|
|
8494 adjust_long_from_native_call );
|
|
|
8495 ins_pc_relative(1);
|
|
|
8496 ins_pipe(simple_call);
|
|
|
8497 %}
|
|
|
8498
|
|
|
8499 // Tail Call; Jump from runtime stub to Java code.
|
|
|
8500 // Also known as an 'interprocedural jump'.
|
|
|
8501 // Target of jump will eventually return to caller.
|
|
|
8502 // TailJump below removes the return address.
|
|
|
8503 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
|
|
|
8504 match(TailCall jump_target method_oop );
|
|
|
8505
|
|
|
8506 ins_cost(CALL_COST);
|
|
|
8507 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
|
|
|
8508 ins_encode(form_jmpl(jump_target));
|
|
|
8509 ins_pipe(tail_call);
|
|
|
8510 %}
|
|
|
8511
|
|
|
8512
|
|
|
8513 // Return Instruction
|
|
|
8514 instruct Ret() %{
|
|
|
8515 match(Return);
|
|
|
8516
|
|
|
8517 // The epilogue node did the ret already.
|
|
|
8518 size(0);
|
|
|
8519 format %{ "! return" %}
|
|
|
8520 ins_encode();
|
|
|
8521 ins_pipe(empty);
|
|
|
8522 %}
|
|
|
8523
|
|
|
8524
|
|
|
8525 // Tail Jump; remove the return address; jump to target.
|
|
|
8526 // TailCall above leaves the return address around.
|
|
|
8527 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
|
|
|
8528 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
|
|
|
8529 // "restore" before this instruction (in Epilogue), we need to materialize it
|
|
|
8530 // in %i0.
|
|
|
8531 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
|
|
|
8532 match( TailJump jump_target ex_oop );
|
|
|
8533 ins_cost(CALL_COST);
|
|
|
8534 format %{ "! discard R_O7\n\t"
|
|
|
8535 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
|
|
|
8536 ins_encode(form_jmpl_set_exception_pc(jump_target));
|
|
|
8537 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
|
|
|
8538 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
|
|
|
8539 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
|
|
|
8540 ins_pipe(tail_call);
|
|
|
8541 %}
|
|
|
8542
|
|
|
8543 // Create exception oop: created by stack-crawling runtime code.
|
|
|
8544 // Created exception is now available to this handler, and is setup
|
|
|
8545 // just prior to jumping to this handler. No code emitted.
|
|
|
8546 instruct CreateException( o0RegP ex_oop )
|
|
|
8547 %{
|
|
|
8548 match(Set ex_oop (CreateEx));
|
|
|
8549 ins_cost(0);
|
|
|
8550
|
|
|
8551 size(0);
|
|
|
8552 // use the following format syntax
|
|
|
8553 format %{ "! exception oop is in R_O0; no code emitted" %}
|
|
|
8554 ins_encode();
|
|
|
8555 ins_pipe(empty);
|
|
|
8556 %}
|
|
|
8557
|
|
|
8558
|
|
|
8559 // Rethrow exception:
|
|
|
8560 // The exception oop will come in the first argument position.
|
|
|
8561 // Then JUMP (not call) to the rethrow stub code.
|
|
|
8562 instruct RethrowException()
|
|
|
8563 %{
|
|
|
8564 match(Rethrow);
|
|
|
8565 ins_cost(CALL_COST);
|
|
|
8566
|
|
|
8567 // use the following format syntax
|
|
|
8568 format %{ "Jmp rethrow_stub" %}
|
|
|
8569 ins_encode(enc_rethrow);
|
|
|
8570 ins_pipe(tail_call);
|
|
|
8571 %}
|
|
|
8572
|
|
|
8573
|
|
|
8574 // Die now
|
|
|
8575 instruct ShouldNotReachHere( )
|
|
|
8576 %{
|
|
|
8577 match(Halt);
|
|
|
8578 ins_cost(CALL_COST);
|
|
|
8579
|
|
|
8580 size(4);
|
|
|
8581 // Use the following format syntax
|
|
|
8582 format %{ "ILLTRAP ; ShouldNotReachHere" %}
|
|
|
8583 ins_encode( form2_illtrap() );
|
|
|
8584 ins_pipe(tail_call);
|
|
|
8585 %}
|
|
|
8586
|
|
|
8587 // ============================================================================
|
|
|
8588 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
|
|
|
8589 // array for an instance of the superklass. Set a hidden internal cache on a
|
|
|
8590 // hit (cache is checked with exposed code in gen_subtype_check()). Return
|
|
|
8591 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
|
|
|
8592 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
|
|
|
8593 match(Set index (PartialSubtypeCheck sub super));
|
|
|
8594 effect( KILL pcc, KILL o7 );
|
|
|
8595 ins_cost(DEFAULT_COST*10);
|
|
|
8596 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
|
|
|
8597 ins_encode( enc_PartialSubtypeCheck() );
|
|
|
8598 ins_pipe(partial_subtype_check_pipe);
|
|
|
8599 %}
|
|
|
8600
|
|
|
8601 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
|
|
|
8602 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
|
|
|
8603 effect( KILL idx, KILL o7 );
|
|
|
8604 ins_cost(DEFAULT_COST*10);
|
|
|
8605 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
|
|
|
8606 ins_encode( enc_PartialSubtypeCheck() );
|
|
|
8607 ins_pipe(partial_subtype_check_pipe);
|
|
|
8608 %}
|
|
|
8609
|
|
|
8610 // ============================================================================
|
|
|
8611 // inlined locking and unlocking
|
|
|
8612
|
|
|
8613 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
|
|
|
8614 match(Set pcc (FastLock object box));
|
|
|
8615
|
|
|
8616 effect(KILL scratch, TEMP scratch2);
|
|
|
8617 ins_cost(100);
|
|
|
8618
|
|
|
8619 size(4*112); // conservative overestimation ...
|
|
|
8620 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
|
|
|
8621 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
|
|
|
8622 ins_pipe(long_memory_op);
|
|
|
8623 %}
|
|
|
8624
|
|
|
8625
|
|
|
8626 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
|
|
|
8627 match(Set pcc (FastUnlock object box));
|
|
|
8628 effect(KILL scratch, TEMP scratch2);
|
|
|
8629 ins_cost(100);
|
|
|
8630
|
|
|
8631 size(4*120); // conservative overestimation ...
|
|
|
8632 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
|
|
|
8633 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
|
|
|
8634 ins_pipe(long_memory_op);
|
|
|
8635 %}
|
|
|
8636
|
|
|
8637 // Count and Base registers are fixed because the allocator cannot
|
|
|
8638 // kill unknown registers. The encodings are generic.
|
|
|
8639 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
|
|
|
8640 match(Set dummy (ClearArray cnt base));
|
|
|
8641 effect(TEMP temp, KILL ccr);
|
|
|
8642 ins_cost(300);
|
|
|
8643 format %{ "MOV $cnt,$temp\n"
|
|
|
8644 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
|
|
|
8645 " BRge loop\t\t! Clearing loop\n"
|
|
|
8646 " STX G0,[$base+$temp]\t! delay slot" %}
|
|
|
8647 ins_encode( enc_Clear_Array(cnt, base, temp) );
|
|
|
8648 ins_pipe(long_memory_op);
|
|
|
8649 %}
|
|
|
8650
|
|
|
8651 instruct string_compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result, flagsReg ccr) %{
|
|
|
8652 match(Set result (StrComp str1 str2));
|
|
|
8653 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL ccr);
|
|
|
8654 ins_cost(300);
|
|
|
8655 format %{ "String Compare $str1,$str2 -> $result" %}
|
|
|
8656 ins_encode( enc_String_Compare(str1, str2, tmp1, tmp2, result) );
|
|
|
8657 ins_pipe(long_memory_op);
|
|
|
8658 %}
|
|
|
8659
|
|
|
8660 // ============================================================================
|
|
|
8661 //------------Bytes reverse--------------------------------------------------
|
|
|
8662
|
|
|
8663 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
|
|
|
8664 match(Set dst (ReverseBytesI src));
|
|
|
8665 effect(DEF dst, USE src);
|
|
|
8666
|
|
|
8667 // Op cost is artificially doubled to make sure that load or store
|
|
|
8668 // instructions are preferred over this one which requires a spill
|
|
|
8669 // onto a stack slot.
|
|
|
8670 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
|
|
|
8671 size(8);
|
|
|
8672 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
|
|
|
8673 opcode(Assembler::lduwa_op3);
|
|
|
8674 ins_encode( form3_mem_reg_little(src, dst) );
|
|
|
8675 ins_pipe( iload_mem );
|
|
|
8676 %}
|
|
|
8677
|
|
|
8678 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
|
|
|
8679 match(Set dst (ReverseBytesL src));
|
|
|
8680 effect(DEF dst, USE src);
|
|
|
8681
|
|
|
8682 // Op cost is artificially doubled to make sure that load or store
|
|
|
8683 // instructions are preferred over this one which requires a spill
|
|
|
8684 // onto a stack slot.
|
|
|
8685 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
|
|
|
8686 size(8);
|
|
|
8687 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
|
|
|
8688
|
|
|
8689 opcode(Assembler::ldxa_op3);
|
|
|
8690 ins_encode( form3_mem_reg_little(src, dst) );
|
|
|
8691 ins_pipe( iload_mem );
|
|
|
8692 %}
|
|
|
8693
|
|
|
8694 // Load Integer reversed byte order
|
|
|
8695 instruct loadI_reversed(iRegI dst, memory src) %{
|
|
|
8696 match(Set dst (ReverseBytesI (LoadI src)));
|
|
|
8697
|
|
|
8698 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
|
|
|
8699 size(8);
|
|
|
8700 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
|
|
|
8701
|
|
|
8702 opcode(Assembler::lduwa_op3);
|
|
|
8703 ins_encode( form3_mem_reg_little( src, dst) );
|
|
|
8704 ins_pipe(iload_mem);
|
|
|
8705 %}
|
|
|
8706
|
|
|
8707 // Load Long - aligned and reversed
|
|
|
8708 instruct loadL_reversed(iRegL dst, memory src) %{
|
|
|
8709 match(Set dst (ReverseBytesL (LoadL src)));
|
|
|
8710
|
|
|
8711 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
|
|
|
8712 size(8);
|
|
|
8713 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
|
|
|
8714
|
|
|
8715 opcode(Assembler::ldxa_op3);
|
|
|
8716 ins_encode( form3_mem_reg_little( src, dst ) );
|
|
|
8717 ins_pipe(iload_mem);
|
|
|
8718 %}
|
|
|
8719
|
|
|
8720 // Store Integer reversed byte order
|
|
|
8721 instruct storeI_reversed(memory dst, iRegI src) %{
|
|
|
8722 match(Set dst (StoreI dst (ReverseBytesI src)));
|
|
|
8723
|
|
|
8724 ins_cost(MEMORY_REF_COST);
|
|
|
8725 size(8);
|
|
|
8726 format %{ "STWA $src, $dst\t!asi=primary_little" %}
|
|
|
8727
|
|
|
8728 opcode(Assembler::stwa_op3);
|
|
|
8729 ins_encode( form3_mem_reg_little( dst, src) );
|
|
|
8730 ins_pipe(istore_mem_reg);
|
|
|
8731 %}
|
|
|
8732
|
|
|
8733 // Store Long reversed byte order
|
|
|
8734 instruct storeL_reversed(memory dst, iRegL src) %{
|
|
|
8735 match(Set dst (StoreL dst (ReverseBytesL src)));
|
|
|
8736
|
|
|
8737 ins_cost(MEMORY_REF_COST);
|
|
|
8738 size(8);
|
|
|
8739 format %{ "STXA $src, $dst\t!asi=primary_little" %}
|
|
|
8740
|
|
|
8741 opcode(Assembler::stxa_op3);
|
|
|
8742 ins_encode( form3_mem_reg_little( dst, src) );
|
|
|
8743 ins_pipe(istore_mem_reg);
|
|
|
8744 %}
|
|
|
8745
|
|
|
8746 //----------PEEPHOLE RULES-----------------------------------------------------
|
|
|
8747 // These must follow all instruction definitions as they use the names
|
|
|
8748 // defined in the instructions definitions.
|
|
|
8749 //
|
|
|
8750 // peepmatch ( root_instr_name [preceeding_instruction]* );
|
|
|
8751 //
|
|
|
8752 // peepconstraint %{
|
|
|
8753 // (instruction_number.operand_name relational_op instruction_number.operand_name
|
|
|
8754 // [, ...] );
|
|
|
8755 // // instruction numbers are zero-based using left to right order in peepmatch
|
|
|
8756 //
|
|
|
8757 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
|
|
|
8758 // // provide an instruction_number.operand_name for each operand that appears
|
|
|
8759 // // in the replacement instruction's match rule
|
|
|
8760 //
|
|
|
8761 // ---------VM FLAGS---------------------------------------------------------
|
|
|
8762 //
|
|
|
8763 // All peephole optimizations can be turned off using -XX:-OptoPeephole
|
|
|
8764 //
|
|
|
8765 // Each peephole rule is given an identifying number starting with zero and
|
|
|
8766 // increasing by one in the order seen by the parser. An individual peephole
|
|
|
8767 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
|
|
|
8768 // on the command-line.
|
|
|
8769 //
|
|
|
8770 // ---------CURRENT LIMITATIONS----------------------------------------------
|
|
|
8771 //
|
|
|
8772 // Only match adjacent instructions in same basic block
|
|
|
8773 // Only equality constraints
|
|
|
8774 // Only constraints between operands, not (0.dest_reg == EAX_enc)
|
|
|
8775 // Only one replacement instruction
|
|
|
8776 //
|
|
|
8777 // ---------EXAMPLE----------------------------------------------------------
|
|
|
8778 //
|
|
|
8779 // // pertinent parts of existing instructions in architecture description
|
|
|
8780 // instruct movI(eRegI dst, eRegI src) %{
|
|
|
8781 // match(Set dst (CopyI src));
|
|
|
8782 // %}
|
|
|
8783 //
|
|
|
8784 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
|
|
|
8785 // match(Set dst (AddI dst src));
|
|
|
8786 // effect(KILL cr);
|
|
|
8787 // %}
|
|
|
8788 //
|
|
|
8789 // // Change (inc mov) to lea
|
|
|
8790 // peephole %{
|
|
|
8791 // // increment preceeded by register-register move
|
|
|
8792 // peepmatch ( incI_eReg movI );
|
|
|
8793 // // require that the destination register of the increment
|
|
|
8794 // // match the destination register of the move
|
|
|
8795 // peepconstraint ( 0.dst == 1.dst );
|
|
|
8796 // // construct a replacement instruction that sets
|
|
|
8797 // // the destination to ( move's source register + one )
|
|
|
8798 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
|
|
|
8799 // %}
|
|
|
8800 //
|
|
|
8801
|
|
|
8802 // // Change load of spilled value to only a spill
|
|
|
8803 // instruct storeI(memory mem, eRegI src) %{
|
|
|
8804 // match(Set mem (StoreI mem src));
|
|
|
8805 // %}
|
|
|
8806 //
|
|
|
8807 // instruct loadI(eRegI dst, memory mem) %{
|
|
|
8808 // match(Set dst (LoadI mem));
|
|
|
8809 // %}
|
|
|
8810 //
|
|
|
8811 // peephole %{
|
|
|
8812 // peepmatch ( loadI storeI );
|
|
|
8813 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
|
|
|
8814 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
|
|
|
8815 // %}
|
|
|
8816
|
|
|
8817 //----------SMARTSPILL RULES---------------------------------------------------
|
|
|
8818 // These must follow all instruction definitions as they use the names
|
|
|
8819 // defined in the instructions definitions.
|
|
|
8820 //
|
|
|
8821 // SPARC will probably not have any of these rules due to RISC instruction set.
|
|
|
8822
|
|
|
8823 //----------PIPELINE-----------------------------------------------------------
|
|
|
8824 // Rules which define the behavior of the target architectures pipeline.
|
