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1 !!
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2 !! Copyright 2005-2007 Sun Microsystems, Inc. All Rights Reserved.
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3 !! DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 !!
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5 !! This code is free software; you can redistribute it and/or modify it
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6 !! under the terms of the GNU General Public License version 2 only, as
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7 !! published by the Free Software Foundation.
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8 !!
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9 !! This code is distributed in the hope that it will be useful, but WITHOUT
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10 !! ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 !! FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 !! version 2 for more details (a copy is included in the LICENSE file that
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13 !! accompanied this code).
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14 !!
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15 !! You should have received a copy of the GNU General Public License version
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16 !! 2 along with this work; if not, write to the Free Software Foundation,
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17 !! Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 !!
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19 !! Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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20 !! CA 95054 USA or visit www.sun.com if you need additional information or
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21 !! have any questions.
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22 !!
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23
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24 !! Prototype: int SafeFetch32 (int * adr, int ErrValue)
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25 !! The "ld" at Fetch32 is potentially faulting instruction.
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26 !! If the instruction traps the trap handler will arrange
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27 !! for control to resume at Fetch32Resume.
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28 !! By convention with the trap handler we ensure there is a non-CTI
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29 !! instruction in the trap shadow.
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30 !!
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31 !! The reader might be tempted to move this service to .il.
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32 !! Don't. Sun's CC back-end reads and optimize code emitted
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33 !! by the .il "call", in some cases optimizing the code, completely eliding it,
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34 !! or by moving the code from the "call site".
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35
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36
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37 .globl SafeFetch32
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38 .align 32
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39 .global Fetch32PFI, Fetch32Resume
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40 SafeFetch32:
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41 mov %o0, %g1
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42 mov %o1, %o0
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43 Fetch32PFI:
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44 ld [%g1], %o0 !! <-- Potentially faulting instruction
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45 Fetch32Resume:
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46 nop
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47 retl
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48 nop
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49
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50 .globl SafeFetchN
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51 .align 32
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52 .globl FetchNPFI, FetchNResume
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53 SafeFetchN:
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54 mov %o0, %g1
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55 mov %o1, %o0
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56 FetchNPFI:
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57 ldn [%g1], %o0
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58 FetchNResume:
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59 nop
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60 retl
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61 nop
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62
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63 !! Possibilities:
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64 !! -- membar
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65 !! -- CAS (SP + BIAS, G0, G0)
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66 !! -- wr %g0, %asi
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67
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68 .global SpinPause
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69 .align 32
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70 SpinPause:
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71 retl
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72 mov %g0, %o0
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73
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74
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75
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76 .globl _Copy_conjoint_jlongs_atomic
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77 .align 32
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78 .global _Copy_conjoint_jlongs_atomic
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79 _Copy_conjoint_jlongs_atomic:
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80 cmp %o0, %o1
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81 bleu 4f
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82 sll %o2, 3, %o4
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83 ba 2f
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84 1:
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85 subcc %o4, 8, %o4
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86 std %o2, [%o1]
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87 add %o0, 8, %o0
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88 add %o1, 8, %o1
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89 2:
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90 bge,a 1b
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91 ldd [%o0], %o2
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92 ba 5f
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93 nop
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94 3:
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95 std %o2, [%o1+%o4]
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96 4:
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97 subcc %o4, 8, %o4
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98 bge,a 3b
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99 ldd [%o0+%o4], %o2
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100 5:
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101 retl
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102 nop
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103
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104
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105
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106 .globl _raw_thread_id
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107 .align 32
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108 _raw_thread_id:
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109 retl
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110 mov %g7, %o0
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111
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112
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113 .globl _flush_reg_windows
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114 .align 32
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115 _flush_reg_windows:
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116 ta 0x03
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117 retl
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118 mov %fp, %o0
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119
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120
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