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0
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1 /*
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2 * Copyright 2005-2006 Sun Microsystems, Inc. All Rights Reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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20 * CA 95054 USA or visit www.sun.com if you need additional information or
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21 * have any questions.
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22 *
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23 */
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24
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25 #include "incls/_precompiled.incl"
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26 #include "incls/_c1_LinearScan.cpp.incl"
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27
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28
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29 #ifndef PRODUCT
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30
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31 static LinearScanStatistic _stat_before_alloc;
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32 static LinearScanStatistic _stat_after_asign;
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33 static LinearScanStatistic _stat_final;
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34
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35 static LinearScanTimers _total_timer;
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36
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37 // helper macro for short definition of timer
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38 #define TIME_LINEAR_SCAN(timer_name) TraceTime _block_timer("", _total_timer.timer(LinearScanTimers::timer_name), TimeLinearScan || TimeEachLinearScan, Verbose);
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39
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40 // helper macro for short definition of trace-output inside code
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41 #define TRACE_LINEAR_SCAN(level, code) \
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42 if (TraceLinearScanLevel >= level) { \
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43 code; \
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44 }
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45
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46 #else
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47
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48 #define TIME_LINEAR_SCAN(timer_name)
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49 #define TRACE_LINEAR_SCAN(level, code)
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50
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51 #endif
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52
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53 // Map BasicType to spill size in 32-bit words, matching VMReg's notion of words
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54 #ifdef _LP64
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55 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 2, 2, 0, 1, -1};
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56 #else
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57 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 1, 1, 0, 1, -1};
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58 #endif
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59
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60
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61 // Implementation of LinearScan
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62
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63 LinearScan::LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map)
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64 : _compilation(ir->compilation())
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65 , _ir(ir)
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66 , _gen(gen)
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67 , _frame_map(frame_map)
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68 , _num_virtual_regs(gen->max_virtual_register_number())
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69 , _has_fpu_registers(false)
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70 , _num_calls(-1)
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71 , _max_spills(0)
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72 , _unused_spill_slot(-1)
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73 , _intervals(0) // initialized later with correct length
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74 , _new_intervals_from_allocation(new IntervalList())
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75 , _sorted_intervals(NULL)
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76 , _lir_ops(0) // initialized later with correct length
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77 , _block_of_op(0) // initialized later with correct length
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78 , _has_info(0)
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79 , _has_call(0)
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80 , _scope_value_cache(0) // initialized later with correct length
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81 , _interval_in_loop(0, 0) // initialized later with correct length
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82 , _cached_blocks(*ir->linear_scan_order())
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83 #ifdef IA32
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84 , _fpu_stack_allocator(NULL)
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85 #endif
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86 {
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87 // note: to use more than on instance of LinearScan at a time this function call has to
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88 // be moved somewhere outside of this constructor:
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89 Interval::initialize();
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90
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91 assert(this->ir() != NULL, "check if valid");
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92 assert(this->compilation() != NULL, "check if valid");
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93 assert(this->gen() != NULL, "check if valid");
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94 assert(this->frame_map() != NULL, "check if valid");
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95 }
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96
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97
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98 // ********** functions for converting LIR-Operands to register numbers
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99 //
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100 // Emulate a flat register file comprising physical integer registers,
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101 // physical floating-point registers and virtual registers, in that order.
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102 // Virtual registers already have appropriate numbers, since V0 is
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103 // the number of physical registers.
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104 // Returns -1 for hi word if opr is a single word operand.
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105 //
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106 // Note: the inverse operation (calculating an operand for register numbers)
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107 // is done in calc_operand_for_interval()
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108
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109 int LinearScan::reg_num(LIR_Opr opr) {
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110 assert(opr->is_register(), "should not call this otherwise");
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111
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112 if (opr->is_virtual_register()) {
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113 assert(opr->vreg_number() >= nof_regs, "found a virtual register with a fixed-register number");
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114 return opr->vreg_number();
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115 } else if (opr->is_single_cpu()) {
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116 return opr->cpu_regnr();
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117 } else if (opr->is_double_cpu()) {
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118 return opr->cpu_regnrLo();
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119 #ifdef IA32
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120 } else if (opr->is_single_xmm()) {
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121 return opr->fpu_regnr() + pd_first_xmm_reg;
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122 } else if (opr->is_double_xmm()) {
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123 return opr->fpu_regnrLo() + pd_first_xmm_reg;
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124 #endif
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125 } else if (opr->is_single_fpu()) {
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126 return opr->fpu_regnr() + pd_first_fpu_reg;
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127 } else if (opr->is_double_fpu()) {
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128 return opr->fpu_regnrLo() + pd_first_fpu_reg;
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129 } else {
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130 ShouldNotReachHere();
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131 }
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132 }
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133
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134 int LinearScan::reg_numHi(LIR_Opr opr) {
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135 assert(opr->is_register(), "should not call this otherwise");
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136
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137 if (opr->is_virtual_register()) {
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138 return -1;
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139 } else if (opr->is_single_cpu()) {
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140 return -1;
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141 } else if (opr->is_double_cpu()) {
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142 return opr->cpu_regnrHi();
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143 #ifdef IA32
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144 } else if (opr->is_single_xmm()) {
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145 return -1;
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146 } else if (opr->is_double_xmm()) {
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147 return -1;
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148 #endif
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149 } else if (opr->is_single_fpu()) {
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150 return -1;
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151 } else if (opr->is_double_fpu()) {
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152 return opr->fpu_regnrHi() + pd_first_fpu_reg;
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153 } else {
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154 ShouldNotReachHere();
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155 }
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156 }
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157
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158
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159 // ********** functions for classification of intervals
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160
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161 bool LinearScan::is_precolored_interval(const Interval* i) {
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162 return i->reg_num() < LinearScan::nof_regs;
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163 }
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164
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165 bool LinearScan::is_virtual_interval(const Interval* i) {
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166 return i->reg_num() >= LIR_OprDesc::vreg_base;
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167 }
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168
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169 bool LinearScan::is_precolored_cpu_interval(const Interval* i) {
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170 return i->reg_num() < LinearScan::nof_cpu_regs;
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171 }
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172
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173 bool LinearScan::is_virtual_cpu_interval(const Interval* i) {
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174 return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() != T_FLOAT && i->type() != T_DOUBLE);
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175 }
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176
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177 bool LinearScan::is_precolored_fpu_interval(const Interval* i) {
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178 return i->reg_num() >= LinearScan::nof_cpu_regs && i->reg_num() < LinearScan::nof_regs;
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179 }
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180
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181 bool LinearScan::is_virtual_fpu_interval(const Interval* i) {
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182 return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE);
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183 }
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184
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185 bool LinearScan::is_in_fpu_register(const Interval* i) {
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186 // fixed intervals not needed for FPU stack allocation
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187 return i->reg_num() >= nof_regs && pd_first_fpu_reg <= i->assigned_reg() && i->assigned_reg() <= pd_last_fpu_reg;
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188 }
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189
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190 bool LinearScan::is_oop_interval(const Interval* i) {
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191 // fixed intervals never contain oops
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192 return i->reg_num() >= nof_regs && i->type() == T_OBJECT;
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193 }
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194
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195
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196 // ********** General helper functions
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197
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198 // compute next unused stack index that can be used for spilling
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199 int LinearScan::allocate_spill_slot(bool double_word) {
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200 int spill_slot;
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201 if (double_word) {
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202 if ((_max_spills & 1) == 1) {
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203 // alignment of double-word values
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204 // the hole because of the alignment is filled with the next single-word value
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205 assert(_unused_spill_slot == -1, "wasting a spill slot");
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206 _unused_spill_slot = _max_spills;
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207 _max_spills++;
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208 }
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209 spill_slot = _max_spills;
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210 _max_spills += 2;
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211
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212 } else if (_unused_spill_slot != -1) {
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213 // re-use hole that was the result of a previous double-word alignment
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214 spill_slot = _unused_spill_slot;
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215 _unused_spill_slot = -1;
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216
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217 } else {
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218 spill_slot = _max_spills;
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219 _max_spills++;
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220 }
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221
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222 int result = spill_slot + LinearScan::nof_regs + frame_map()->argcount();
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223
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224 // the class OopMapValue uses only 11 bits for storing the name of the
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225 // oop location. So a stack slot bigger than 2^11 leads to an overflow
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226 // that is not reported in product builds. Prevent this by checking the
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227 // spill slot here (altough this value and the later used location name
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228 // are slightly different)
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229 if (result > 2000) {
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230 bailout("too many stack slots used");
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231 }
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232
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233 return result;
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234 }
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235
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236 void LinearScan::assign_spill_slot(Interval* it) {
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237 // assign the canonical spill slot of the parent (if a part of the interval
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238 // is already spilled) or allocate a new spill slot
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239 if (it->canonical_spill_slot() >= 0) {
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240 it->assign_reg(it->canonical_spill_slot());
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241 } else {
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242 int spill = allocate_spill_slot(type2spill_size[it->type()] == 2);
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243 it->set_canonical_spill_slot(spill);
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244 it->assign_reg(spill);
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245 }
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246 }
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247
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248 void LinearScan::propagate_spill_slots() {
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249 if (!frame_map()->finalize_frame(max_spills())) {
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250 bailout("frame too large");
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251 }
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252 }
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253
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254 // create a new interval with a predefined reg_num
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255 // (only used for parent intervals that are created during the building phase)
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256 Interval* LinearScan::create_interval(int reg_num) {
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257 assert(_intervals.at(reg_num) == NULL, "overwriting exisiting interval");
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258
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259 Interval* interval = new Interval(reg_num);
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260 _intervals.at_put(reg_num, interval);
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261
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262 // assign register number for precolored intervals
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263 if (reg_num < LIR_OprDesc::vreg_base) {
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264 interval->assign_reg(reg_num);
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265 }
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266 return interval;
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267 }
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268
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269 // assign a new reg_num to the interval and append it to the list of intervals
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270 // (only used for child intervals that are created during register allocation)
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271 void LinearScan::append_interval(Interval* it) {
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272 it->set_reg_num(_intervals.length());
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273 _intervals.append(it);
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274 _new_intervals_from_allocation->append(it);
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275 }
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276
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277 // copy the vreg-flags if an interval is split
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278 void LinearScan::copy_register_flags(Interval* from, Interval* to) {
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279 if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::byte_reg)) {
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280 gen()->set_vreg_flag(to->reg_num(), LIRGenerator::byte_reg);
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281 }
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282 if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::callee_saved)) {
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283 gen()->set_vreg_flag(to->reg_num(), LIRGenerator::callee_saved);
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284 }
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285
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286 // Note: do not copy the must_start_in_memory flag because it is not necessary for child
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287 // intervals (only the very beginning of the interval must be in memory)
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288 }
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289
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290
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291 // ********** spill move optimization
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292 // eliminate moves from register to stack if stack slot is known to be correct
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293
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294 // called during building of intervals
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295 void LinearScan::change_spill_definition_pos(Interval* interval, int def_pos) {
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296 assert(interval->is_split_parent(), "can only be called for split parents");
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297
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298 switch (interval->spill_state()) {
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299 case noDefinitionFound:
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300 assert(interval->spill_definition_pos() == -1, "must no be set before");
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301 interval->set_spill_definition_pos(def_pos);
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302 interval->set_spill_state(oneDefinitionFound);
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303 break;
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304
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305 case oneDefinitionFound:
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306 assert(def_pos <= interval->spill_definition_pos(), "positions are processed in reverse order when intervals are created");
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307 if (def_pos < interval->spill_definition_pos() - 2) {
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308 // second definition found, so no spill optimization possible for this interval
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309 interval->set_spill_state(noOptimization);
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310 } else {
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311 // two consecutive definitions (because of two-operand LIR form)
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312 assert(block_of_op_with_id(def_pos) == block_of_op_with_id(interval->spill_definition_pos()), "block must be equal");
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313 }
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314 break;
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315
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316 case noOptimization:
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317 // nothing to do
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318 break;
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319
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320 default:
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321 assert(false, "other states not allowed at this time");
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322 }
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323 }
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324
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325 // called during register allocation
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326 void LinearScan::change_spill_state(Interval* interval, int spill_pos) {
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327 switch (interval->spill_state()) {
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328 case oneDefinitionFound: {
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329 int def_loop_depth = block_of_op_with_id(interval->spill_definition_pos())->loop_depth();
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330 int spill_loop_depth = block_of_op_with_id(spill_pos)->loop_depth();
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331
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332 if (def_loop_depth < spill_loop_depth) {
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333 // the loop depth of the spilling position is higher then the loop depth
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334 // at the definition of the interval -> move write to memory out of loop
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335 // by storing at definitin of the interval
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336 interval->set_spill_state(storeAtDefinition);
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337 } else {
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338 // the interval is currently spilled only once, so for now there is no
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339 // reason to store the interval at the definition
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340 interval->set_spill_state(oneMoveInserted);
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341 }
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342 break;
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343 }
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344
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345 case oneMoveInserted: {
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346 // the interval is spilled more then once, so it is better to store it to
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347 // memory at the definition
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348 interval->set_spill_state(storeAtDefinition);
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349 break;
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350 }
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351
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352 case storeAtDefinition:
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353 case startInMemory:
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354 case noOptimization:
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355 case noDefinitionFound:
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356 // nothing to do
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357 break;
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358
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359 default:
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360 assert(false, "other states not allowed at this time");
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361 }
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362 }
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363
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364
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365 bool LinearScan::must_store_at_definition(const Interval* i) {
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366 return i->is_split_parent() && i->spill_state() == storeAtDefinition;
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367 }
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368
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369 // called once before asignment of register numbers
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370 void LinearScan::eliminate_spill_moves() {
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371 TIME_LINEAR_SCAN(timer_eliminate_spill_moves);
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372 TRACE_LINEAR_SCAN(3, tty->print_cr("***** Eliminating unnecessary spill moves"));
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373
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374 // collect all intervals that must be stored after their definion.
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375 // the list is sorted by Interval::spill_definition_pos
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376 Interval* interval;
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377 Interval* temp_list;
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378 create_unhandled_lists(&interval, &temp_list, must_store_at_definition, NULL);
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379
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380 #ifdef ASSERT
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381 Interval* prev = NULL;
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382 Interval* temp = interval;
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383 while (temp != Interval::end()) {
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384 assert(temp->spill_definition_pos() > 0, "invalid spill definition pos");
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385 if (prev != NULL) {
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386 assert(temp->from() >= prev->from(), "intervals not sorted");
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387 assert(temp->spill_definition_pos() >= prev->spill_definition_pos(), "when intervals are sorted by from, then they must also be sorted by spill_definition_pos");
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|
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388 }
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389
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390 assert(temp->canonical_spill_slot() >= LinearScan::nof_regs, "interval has no spill slot assigned");
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391 assert(temp->spill_definition_pos() >= temp->from(), "invalid order");
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392 assert(temp->spill_definition_pos() <= temp->from() + 2, "only intervals defined once at their start-pos can be optimized");
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393
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394 TRACE_LINEAR_SCAN(4, tty->print_cr("interval %d (from %d to %d) must be stored at %d", temp->reg_num(), temp->from(), temp->to(), temp->spill_definition_pos()));
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395
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396 temp = temp->next();
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397 }
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398 #endif
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399
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400 LIR_InsertionBuffer insertion_buffer;
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401 int num_blocks = block_count();
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402 for (int i = 0; i < num_blocks; i++) {
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403 BlockBegin* block = block_at(i);
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404 LIR_OpList* instructions = block->lir()->instructions_list();
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405 int num_inst = instructions->length();
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406 bool has_new = false;
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407
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408 // iterate all instructions of the block. skip the first because it is always a label
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409 for (int j = 1; j < num_inst; j++) {
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410 LIR_Op* op = instructions->at(j);
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411 int op_id = op->id();
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412
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413 if (op_id == -1) {
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414 // remove move from register to stack if the stack slot is guaranteed to be correct.
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415 // only moves that have been inserted by LinearScan can be removed.
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416 assert(op->code() == lir_move, "only moves can have a op_id of -1");
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417 assert(op->as_Op1() != NULL, "move must be LIR_Op1");
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418 assert(op->as_Op1()->result_opr()->is_virtual(), "LinearScan inserts only moves to virtual registers");
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419
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|
420 LIR_Op1* op1 = (LIR_Op1*)op;
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421 Interval* interval = interval_at(op1->result_opr()->vreg_number());
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422
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423 if (interval->assigned_reg() >= LinearScan::nof_regs && interval->always_in_memory()) {
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424 // move target is a stack slot that is always correct, so eliminate instruction
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|
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425 TRACE_LINEAR_SCAN(4, tty->print_cr("eliminating move from interval %d to %d", op1->in_opr()->vreg_number(), op1->result_opr()->vreg_number()));
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426 instructions->at_put(j, NULL); // NULL-instructions are deleted by assign_reg_num
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427 }
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|
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428
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|
|
429 } else {
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|
430 // insert move from register to stack just after the beginning of the interval
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|
431 assert(interval == Interval::end() || interval->spill_definition_pos() >= op_id, "invalid order");
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|
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432 assert(interval == Interval::end() || (interval->is_split_parent() && interval->spill_state() == storeAtDefinition), "invalid interval");
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433
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434 while (interval != Interval::end() && interval->spill_definition_pos() == op_id) {
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|
|
435 if (!has_new) {
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|
436 // prepare insertion buffer (appended when all instructions of the block are processed)
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437 insertion_buffer.init(block->lir());
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438 has_new = true;
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|
|
439 }
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|
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440
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|
|
441 LIR_Opr from_opr = operand_for_interval(interval);
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|
|
442 LIR_Opr to_opr = canonical_spill_opr(interval);
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|
|
443 assert(from_opr->is_fixed_cpu() || from_opr->is_fixed_fpu(), "from operand must be a register");
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|
|
444 assert(to_opr->is_stack(), "to operand must be a stack slot");
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|
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445
|
|
|
446 insertion_buffer.move(j, from_opr, to_opr);
|
|
|
447 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting move after definition of interval %d to stack slot %d at op_id %d", interval->reg_num(), interval->canonical_spill_slot() - LinearScan::nof_regs, op_id));
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|
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448
|
|
|
449 interval = interval->next();
|
|
|
450 }
|
|
|
451 }
|
|
|
452 } // end of instruction iteration
|
|
|
453
|
|
|
454 if (has_new) {
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|
|
455 block->lir()->append(&insertion_buffer);
|
|
|
456 }
|
|
|
457 } // end of block iteration
|
|
|
458
|
|
|
459 assert(interval == Interval::end(), "missed an interval");
|
|
|
460 }
|
|
|
461
|
|
|
462
|
|
|
463 // ********** Phase 1: number all instructions in all blocks
|
|
|
464 // Compute depth-first and linear scan block orders, and number LIR_Op nodes for linear scan.
|
|
|
465
|
|
|
466 void LinearScan::number_instructions() {
|
|
|
467 {
|
|
|
468 // dummy-timer to measure the cost of the timer itself
|
|
|
469 // (this time is then subtracted from all other timers to get the real value)
|
|
|
470 TIME_LINEAR_SCAN(timer_do_nothing);
|
|
|
471 }
|
|
|
472 TIME_LINEAR_SCAN(timer_number_instructions);
|
|
|
473
|
|
|
474 // Assign IDs to LIR nodes and build a mapping, lir_ops, from ID to LIR_Op node.
|
|
|
475 int num_blocks = block_count();
|
|
|
476 int num_instructions = 0;
|
|
|
477 int i;
|
|
|
478 for (i = 0; i < num_blocks; i++) {
|
|
|
479 num_instructions += block_at(i)->lir()->instructions_list()->length();
|
|
|
480 }
|
|
|
481
|
|
|
482 // initialize with correct length
|
|
|
483 _lir_ops = LIR_OpArray(num_instructions);
|
|
|
484 _block_of_op = BlockBeginArray(num_instructions);
|
|
|
485
|
|
|
486 int op_id = 0;
|
|
|
487 int idx = 0;
|
|
|
488
|
|
|
489 for (i = 0; i < num_blocks; i++) {
|
|
|
490 BlockBegin* block = block_at(i);
|
|
|
491 block->set_first_lir_instruction_id(op_id);
|
|
|
492 LIR_OpList* instructions = block->lir()->instructions_list();
|
|
|
493
|
|
|
494 int num_inst = instructions->length();
|
|
|
495 for (int j = 0; j < num_inst; j++) {
|
|
|
496 LIR_Op* op = instructions->at(j);
|
|
|
497 op->set_id(op_id);
|
|
|
498
|
|
|
499 _lir_ops.at_put(idx, op);
|
|
|
500 _block_of_op.at_put(idx, block);
|
|
|
501 assert(lir_op_with_id(op_id) == op, "must match");
|
|
|
502
|
|
|
503 idx++;
|
|
|
504 op_id += 2; // numbering of lir_ops by two
|
|
|
505 }
|
|
|
506 block->set_last_lir_instruction_id(op_id - 2);
|
|
|
507 }
|
|
|
508 assert(idx == num_instructions, "must match");
|
|
|
509 assert(idx * 2 == op_id, "must match");
|
|
|
510
|
|
|
511 _has_call = BitMap(num_instructions); _has_call.clear();
|
|
|
512 _has_info = BitMap(num_instructions); _has_info.clear();
|
|
|
513 }
|
|
|
514
|
|
|
515
|
|
|
516 // ********** Phase 2: compute local live sets separately for each block
|
|
|
517 // (sets live_gen and live_kill for each block)
|
|
|
518
|
|
|
519 void LinearScan::set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill) {
|
|
|
520 LIR_Opr opr = value->operand();
|
|
|
521 Constant* con = value->as_Constant();
|
|
|
522
|
|
|
523 // check some asumptions about debug information
|
|
|
524 assert(!value->type()->is_illegal(), "if this local is used by the interpreter it shouldn't be of indeterminate type");
|
|
|
525 assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands");
|
|
|
526 assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
|
|
|
527
|
|
|
528 if ((con == NULL || con->is_pinned()) && opr->is_register()) {
|
|
|
529 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
|
|
|
530 int reg = opr->vreg_number();
|
|
|
531 if (!live_kill.at(reg)) {
|
|
|
532 live_gen.set_bit(reg);
|
|
|
533 TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for value %c%d, LIR op_id %d, register number %d", value->type()->tchar(), value->id(), op->id(), reg));
|
|
|
534 }
|
|
|
535 }
|
|
|
536 }
|
|
|
537
|
|
|
538
|
|
|
539 void LinearScan::compute_local_live_sets() {
|
|
|
540 TIME_LINEAR_SCAN(timer_compute_local_live_sets);
|
|
|
541
|
|
|
542 int num_blocks = block_count();
|
|
|
543 int live_size = live_set_size();
|
|
|
544 bool local_has_fpu_registers = false;
|
|
|
545 int local_num_calls = 0;
|
|
|
546 LIR_OpVisitState visitor;
|
|
|
547
|
|
|
548 BitMap2D local_interval_in_loop = BitMap2D(_num_virtual_regs, num_loops());
|
|
|
549 local_interval_in_loop.clear();
|
|
|
550
|
|
|
551 // iterate all blocks
|
|
|
552 for (int i = 0; i < num_blocks; i++) {
|
|
|
553 BlockBegin* block = block_at(i);
|
|
|
554
|
|
|
555 BitMap live_gen(live_size); live_gen.clear();
|
|
|
556 BitMap live_kill(live_size); live_kill.clear();
|
|
|
557
|
|
|
558 if (block->is_set(BlockBegin::exception_entry_flag)) {
|
|
|
559 // Phi functions at the begin of an exception handler are
|
|
|
560 // implicitly defined (= killed) at the beginning of the block.
|
|
|
561 for_each_phi_fun(block, phi,
|
|
|
562 live_kill.set_bit(phi->operand()->vreg_number())
|
|
|
563 );
|
|
|
564 }
|
|
|
565
|
|
|
566 LIR_OpList* instructions = block->lir()->instructions_list();
|
|
|
567 int num_inst = instructions->length();
|
|
|
568
|
|
|
569 // iterate all instructions of the block. skip the first because it is always a label
|
|
|
570 assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
|
|
|
571 for (int j = 1; j < num_inst; j++) {
|
|
|
572 LIR_Op* op = instructions->at(j);
|
|
|
573
|
|
|
574 // visit operation to collect all operands
|
|
|
575 visitor.visit(op);
|
|
|
576
|
|
|
577 if (visitor.has_call()) {
|
|
|
578 _has_call.set_bit(op->id() >> 1);
|
|
|
579 local_num_calls++;
|
|
|
580 }
|
|
|
581 if (visitor.info_count() > 0) {
|
|
|
582 _has_info.set_bit(op->id() >> 1);
|
|
|
583 }
|
|
|
584
|
|
|
585 // iterate input operands of instruction
|
|
|
586 int k, n, reg;
|
|
|
587 n = visitor.opr_count(LIR_OpVisitState::inputMode);
|
|
|
588 for (k = 0; k < n; k++) {
|
|
|
589 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
|
|
|
590 assert(opr->is_register(), "visitor should only return register operands");
|
|
|
591
|
|
|
592 if (opr->is_virtual_register()) {
|
|
|
593 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
|
|
|
594 reg = opr->vreg_number();
|
|
|
595 if (!live_kill.at(reg)) {
|
|
|
596 live_gen.set_bit(reg);
|
|
|
597 TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for register %d at instruction %d", reg, op->id()));
|
|
|
598 }
|
|
|
599 if (block->loop_index() >= 0) {
|
|
|
600 local_interval_in_loop.set_bit(reg, block->loop_index());
|
|
|
601 }
|
|
|
602 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
|
|
|
603 }
|
|
|
604
|
|
|
605 #ifdef ASSERT
|
|
|
606 // fixed intervals are never live at block boundaries, so
|
|
|
607 // they need not be processed in live sets.
|
|
|
608 // this is checked by these assertions to be sure about it.
|
|
|
609 // the entry block may have incoming values in registers, which is ok.
|
|
|
610 if (!opr->is_virtual_register() && block != ir()->start()) {
|
|
|
611 reg = reg_num(opr);
|
|
|
612 if (is_processed_reg_num(reg)) {
|
|
|
613 assert(live_kill.at(reg), "using fixed register that is not defined in this block");
|
|
|
614 }
|
|
|
615 reg = reg_numHi(opr);
|
|
|
616 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
|
|
|
617 assert(live_kill.at(reg), "using fixed register that is not defined in this block");
|
|
|
618 }
|
|
|
619 }
|
|
|
620 #endif
|
|
|
621 }
|
|
|
622
|
|
|
623 // Add uses of live locals from interpreter's point of view for proper debug information generation
|
|
|
624 n = visitor.info_count();
|
|
|
625 for (k = 0; k < n; k++) {
|
|
|
626 CodeEmitInfo* info = visitor.info_at(k);
|
|
|
627 ValueStack* stack = info->stack();
|
|
|
628 for_each_state_value(stack, value,
|
|
|
629 set_live_gen_kill(value, op, live_gen, live_kill)
|
|
|
630 );
|
|
|
631 }
|
|
|
632
|
|
|
633 // iterate temp operands of instruction
|
|
|
634 n = visitor.opr_count(LIR_OpVisitState::tempMode);
|
|
|
635 for (k = 0; k < n; k++) {
|
|
|
636 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
|
|
|
637 assert(opr->is_register(), "visitor should only return register operands");
|
|
|
638
|
|
|
639 if (opr->is_virtual_register()) {
|
|
|
640 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
|
|
|
641 reg = opr->vreg_number();
|
|
|
642 live_kill.set_bit(reg);
|
|
|
643 if (block->loop_index() >= 0) {
|
|
|
644 local_interval_in_loop.set_bit(reg, block->loop_index());
|
|
|
645 }
|
|
|
646 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
|
|
|
647 }
|
|
|
648
|
|
|
649 #ifdef ASSERT
|
|
|
650 // fixed intervals are never live at block boundaries, so
|
|
|
651 // they need not be processed in live sets
|
|
|
652 // process them only in debug mode so that this can be checked
|
|
|
653 if (!opr->is_virtual_register()) {
|
|
|
654 reg = reg_num(opr);
|
|
|
655 if (is_processed_reg_num(reg)) {
|
|
|
656 live_kill.set_bit(reg_num(opr));
|
|
|
657 }
|
|
|
658 reg = reg_numHi(opr);
|
|
|
659 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
|
|
|
660 live_kill.set_bit(reg);
|
|
|
661 }
|
|
|
662 }
|
|
|
663 #endif
|
|
|
664 }
|
|
|
665
|
|
|
666 // iterate output operands of instruction
|
|
|
667 n = visitor.opr_count(LIR_OpVisitState::outputMode);
|
|
|
668 for (k = 0; k < n; k++) {
|
|
|
669 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
|
|
|
670 assert(opr->is_register(), "visitor should only return register operands");
|
|
|
671
|
|
|
672 if (opr->is_virtual_register()) {
|
|
|
673 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
|
|
|
674 reg = opr->vreg_number();
|
|
|
675 live_kill.set_bit(reg);
|
|
|
676 if (block->loop_index() >= 0) {
|
|
|
677 local_interval_in_loop.set_bit(reg, block->loop_index());
|
|
|
678 }
|
|
|
679 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
|
|
|
680 }
|
|
|
681
|
|
|
682 #ifdef ASSERT
|
|
|
683 // fixed intervals are never live at block boundaries, so
|
|
|
684 // they need not be processed in live sets
|
|
|
685 // process them only in debug mode so that this can be checked
|
|
|
686 if (!opr->is_virtual_register()) {
|
|
|
687 reg = reg_num(opr);
|
|
|
688 if (is_processed_reg_num(reg)) {
|
|
|
689 live_kill.set_bit(reg_num(opr));
|
|
|
690 }
|
|
|
691 reg = reg_numHi(opr);
|
|
|
692 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
|
|
|
693 live_kill.set_bit(reg);
|
|
|
694 }
|
|
|
695 }
|
|
|
696 #endif
|
|
|
697 }
|
|
|
698 } // end of instruction iteration
|
|
|
699
|
|
|
700 block->set_live_gen (live_gen);
|
|
|
701 block->set_live_kill(live_kill);
|
|
|
702 block->set_live_in (BitMap(live_size)); block->live_in().clear();
|
|
|
703 block->set_live_out (BitMap(live_size)); block->live_out().clear();
|
|
|
704
|
|
|
705 TRACE_LINEAR_SCAN(4, tty->print("live_gen B%d ", block->block_id()); print_bitmap(block->live_gen()));
|
|
|
706 TRACE_LINEAR_SCAN(4, tty->print("live_kill B%d ", block->block_id()); print_bitmap(block->live_kill()));
|
|
|
707 } // end of block iteration
|
|
|
708
|
|
|
709 // propagate local calculated information into LinearScan object
|
|
|
710 _has_fpu_registers = local_has_fpu_registers;
|
|
|
711 compilation()->set_has_fpu_code(local_has_fpu_registers);
|
|
|
712
|
|
|
713 _num_calls = local_num_calls;
|
|
|
714 _interval_in_loop = local_interval_in_loop;
|
|
|
715 }
|
|
|
716
|
|
|
717
|
|
|
718 // ********** Phase 3: perform a backward dataflow analysis to compute global live sets
|
|
|
719 // (sets live_in and live_out for each block)
|
|
|
720
|
|
|
721 void LinearScan::compute_global_live_sets() {
|
|
|
722 TIME_LINEAR_SCAN(timer_compute_global_live_sets);
|
|
|
723
|
|
|
724 int num_blocks = block_count();
|
|
|
725 bool change_occurred;
|
|
|
726 bool change_occurred_in_block;
|
|
|
727 int iteration_count = 0;
|
|
|
728 BitMap live_out(live_set_size()); live_out.clear(); // scratch set for calculations
|
|
|
729
|
|
|
730 // Perform a backward dataflow analysis to compute live_out and live_in for each block.
|
|
|
731 // The loop is executed until a fixpoint is reached (no changes in an iteration)
|
|
|
732 // Exception handlers must be processed because not all live values are
|
|
|
733 // present in the state array, e.g. because of global value numbering
|
|
|
734 do {
|
|
|
735 change_occurred = false;
|
|
|
736
|
|
|
737 // iterate all blocks in reverse order
|
|
|
738 for (int i = num_blocks - 1; i >= 0; i--) {
|
|
|
739 BlockBegin* block = block_at(i);
|
|
|
740
|
|
|
741 change_occurred_in_block = false;
|
|
|
742
|
|
|
743 // live_out(block) is the union of live_in(sux), for successors sux of block
|
|
|
744 int n = block->number_of_sux();
|
|
|
745 int e = block->number_of_exception_handlers();
|
|
|
746 if (n + e > 0) {
|
|
|
747 // block has successors
|
|
|
748 if (n > 0) {
|
|
|
749 live_out.set_from(block->sux_at(0)->live_in());
|
|
|
750 for (int j = 1; j < n; j++) {
|
|
|
751 live_out.set_union(block->sux_at(j)->live_in());
|
|
|
752 }
|
|
|
753 } else {
|
|
|
754 live_out.clear();
|
|
|
755 }
|
|
|
756 for (int j = 0; j < e; j++) {
|
|
|
757 live_out.set_union(block->exception_handler_at(j)->live_in());
|
|
|
758 }
|
|
|
759
|
|
|
760 if (!block->live_out().is_same(live_out)) {
|
|
|
761 // A change occurred. Swap the old and new live out sets to avoid copying.
|
|
|
762 BitMap temp = block->live_out();
|
|
|
763 block->set_live_out(live_out);
|
|
|
764 live_out = temp;
|
|
|
765
|
|
|
766 change_occurred = true;
|
|
|
767 change_occurred_in_block = true;
|
|
|
768 }
|
|
|
769 }
|
|
|
770
|
|
|
771 if (iteration_count == 0 || change_occurred_in_block) {
|
|
|
772 // live_in(block) is the union of live_gen(block) with (live_out(block) & !live_kill(block))
|
|
|
773 // note: live_in has to be computed only in first iteration or if live_out has changed!
|
|
|
774 BitMap live_in = block->live_in();
|
|
|
775 live_in.set_from(block->live_out());
|
|
|
776 live_in.set_difference(block->live_kill());
|
|
|
777 live_in.set_union(block->live_gen());
|
|
|
778 }
|
|
|
779
|
|
|
780 #ifndef PRODUCT
|
|
|
781 if (TraceLinearScanLevel >= 4) {
|
|
|
782 char c = ' ';
|
|
|
783 if (iteration_count == 0 || change_occurred_in_block) {
|
|
|
784 c = '*';
|
|
|
785 }
|
|
|
786 tty->print("(%d) live_in%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_in());
|
|
|
787 tty->print("(%d) live_out%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_out());
|
|
|
788 }
|
|
|
789 #endif
|
|
|
790 }
|
|
|
791 iteration_count++;
|
|
|
792
|
|
|
793 if (change_occurred && iteration_count > 50) {
|
|
|
794 BAILOUT("too many iterations in compute_global_live_sets");
|
|
|
795 }
|
|
|
796 } while (change_occurred);
|
|
|
797
|
|
|
798
|
|
|
799 #ifdef ASSERT
|
|
|
800 // check that fixed intervals are not live at block boundaries
|
|
|
801 // (live set must be empty at fixed intervals)
|
|
|
802 for (int i = 0; i < num_blocks; i++) {
|
|
|
803 BlockBegin* block = block_at(i);
|
|
|
804 for (int j = 0; j < LIR_OprDesc::vreg_base; j++) {
|
|
|
805 assert(block->live_in().at(j) == false, "live_in set of fixed register must be empty");
|
|
|
806 assert(block->live_out().at(j) == false, "live_out set of fixed register must be empty");
|
|
|
807 assert(block->live_gen().at(j) == false, "live_gen set of fixed register must be empty");
|
|
|
808 }
|
|
|
809 }
|
|
|
810 #endif
|
|
|
811
|
|
|
812 // check that the live_in set of the first block is empty
|
|
|
813 BitMap live_in_args(ir()->start()->live_in().size());
|
|
|
814 live_in_args.clear();
|
|
|
815 if (!ir()->start()->live_in().is_same(live_in_args)) {
|
|
|
816 #ifdef ASSERT
|
|
|
817 tty->print_cr("Error: live_in set of first block must be empty (when this fails, virtual registers are used before they are defined)");
|
|
|
818 tty->print_cr("affected registers:");
|
|
|
819 print_bitmap(ir()->start()->live_in());
|
|
|
820
|
|
|
821 // print some additional information to simplify debugging
|
|
|
822 for (unsigned int i = 0; i < ir()->start()->live_in().size(); i++) {
|
|
|
823 if (ir()->start()->live_in().at(i)) {
|
|
|
824 Instruction* instr = gen()->instruction_for_vreg(i);
|
|
|
825 tty->print_cr("* vreg %d (HIR instruction %c%d)", i, instr == NULL ? ' ' : instr->type()->tchar(), instr == NULL ? 0 : instr->id());
|
|
|
826
|
|
|
827 for (int j = 0; j < num_blocks; j++) {
|
|
|
828 BlockBegin* block = block_at(j);
|
|
|
829 if (block->live_gen().at(i)) {
|
|
|
830 tty->print_cr(" used in block B%d", block->block_id());
|
|
|
831 }
|
|
|
832 if (block->live_kill().at(i)) {
|
|
|
833 tty->print_cr(" defined in block B%d", block->block_id());
|
|
|
834 }
|
|
|
835 }
|
|
|
836 }
|
|
|
837 }
|
|
|
838
|
|
|
839 #endif
|
|
|
840 // when this fails, virtual registers are used before they are defined.
|
|
|
841 assert(false, "live_in set of first block must be empty");
|
|
|
842 // bailout of if this occurs in product mode.
|
|
|
843 bailout("live_in set of first block not empty");
|
|
|
844 }
|
|
|
845 }
|
|
|
846
|
|
|
847
|
|
|
848 // ********** Phase 4: build intervals
|
|
|
849 // (fills the list _intervals)
|
|
|
850
|
|
|
851 void LinearScan::add_use(Value value, int from, int to, IntervalUseKind use_kind) {
|
|
|
852 assert(!value->type()->is_illegal(), "if this value is used by the interpreter it shouldn't be of indeterminate type");
|
|
|
853 LIR_Opr opr = value->operand();
|
|
|
854 Constant* con = value->as_Constant();
|
|
|
855
|
|
|
856 if ((con == NULL || con->is_pinned()) && opr->is_register()) {
|
|
|
857 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
|
|
|
858 add_use(opr, from, to, use_kind);
|
|
|
859 }
|
|
|
860 }
|
|
|
861
|
|
|
862
|
|
|
863 void LinearScan::add_def(LIR_Opr opr, int def_pos, IntervalUseKind use_kind) {
|
|
|
864 TRACE_LINEAR_SCAN(2, tty->print(" def "); opr->print(tty); tty->print_cr(" def_pos %d (%d)", def_pos, use_kind));
|
|
|
865 assert(opr->is_register(), "should not be called otherwise");
|
|
|
866
|
|
|
867 if (opr->is_virtual_register()) {
|
|
|
868 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
|
|
|
869 add_def(opr->vreg_number(), def_pos, use_kind, opr->type_register());
|
|
|
870
|
|
|
871 } else {
|
|
|
872 int reg = reg_num(opr);
|
|
|
873 if (is_processed_reg_num(reg)) {
|
|
|
874 add_def(reg, def_pos, use_kind, opr->type_register());
|
|
|
875 }
|
|
|
876 reg = reg_numHi(opr);
|
|
|
877 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
|
|
|
878 add_def(reg, def_pos, use_kind, opr->type_register());
|
|
|
879 }
|
|
|
880 }
|
|
|
881 }
|
|
|
882
|
|
|
883 void LinearScan::add_use(LIR_Opr opr, int from, int to, IntervalUseKind use_kind) {
|
|
|
884 TRACE_LINEAR_SCAN(2, tty->print(" use "); opr->print(tty); tty->print_cr(" from %d to %d (%d)", from, to, use_kind));
|
|
|
885 assert(opr->is_register(), "should not be called otherwise");
|
|
|
886
|
|
|
887 if (opr->is_virtual_register()) {
|
|
|
888 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
|
|
|
889 add_use(opr->vreg_number(), from, to, use_kind, opr->type_register());
|
|
|
890
|
|
|
891 } else {
|
|
|
892 int reg = reg_num(opr);
|
|
|
893 if (is_processed_reg_num(reg)) {
|
|
|
894 add_use(reg, from, to, use_kind, opr->type_register());
|
|
|
895 }
|
|
|
896 reg = reg_numHi(opr);
|
|
|
897 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
|
|
|
898 add_use(reg, from, to, use_kind, opr->type_register());
|
|
|
899 }
|
|
|
900 }
|
|
|
901 }
|
|
|
902
|
|
|
903 void LinearScan::add_temp(LIR_Opr opr, int temp_pos, IntervalUseKind use_kind) {
|
|
|
904 TRACE_LINEAR_SCAN(2, tty->print(" temp "); opr->print(tty); tty->print_cr(" temp_pos %d (%d)", temp_pos, use_kind));
|
|
|
905 assert(opr->is_register(), "should not be called otherwise");
|
|
|
906
|
|
|
907 if (opr->is_virtual_register()) {
|
|
|
908 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
|
|
|
909 add_temp(opr->vreg_number(), temp_pos, use_kind, opr->type_register());
|
|
|
910
|
|
|
911 } else {
|
|
|
912 int reg = reg_num(opr);
|
|
|
913 if (is_processed_reg_num(reg)) {
|
|
|
914 add_temp(reg, temp_pos, use_kind, opr->type_register());
|
|
|
915 }
|
|
|
916 reg = reg_numHi(opr);
|
|
|
917 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
|
|
|
918 add_temp(reg, temp_pos, use_kind, opr->type_register());
|
|
|
919 }
|
|
|
920 }
|
|
|
921 }
|
|
|
922
|
|
|
923
|
|
|
924 void LinearScan::add_def(int reg_num, int def_pos, IntervalUseKind use_kind, BasicType type) {
|
|
|
925 Interval* interval = interval_at(reg_num);
|
|
|
926 if (interval != NULL) {
|
|
|
927 assert(interval->reg_num() == reg_num, "wrong interval");
|
|
|
928
|
|
|
929 if (type != T_ILLEGAL) {
|
|
|
930 interval->set_type(type);
|
|
|
931 }
|
|
|
932
|
|
|
933 Range* r = interval->first();
|
|
|
934 if (r->from() <= def_pos) {
|
|
|
935 // Update the starting point (when a range is first created for a use, its
|
|
|
936 // start is the beginning of the current block until a def is encountered.)
|
|
|
937 r->set_from(def_pos);
|
|
|
938 interval->add_use_pos(def_pos, use_kind);
|
|
|
939
|
|
|
940 } else {
|
|
|
941 // Dead value - make vacuous interval
|
|
|
942 // also add use_kind for dead intervals
|
|
|
943 interval->add_range(def_pos, def_pos + 1);
|
|
|
944 interval->add_use_pos(def_pos, use_kind);
|
|
|
945 TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: def of reg %d at %d occurs without use", reg_num, def_pos));
|
|
|
946 }
|
|
|
947
|
|
|
948 } else {
|
|
|
949 // Dead value - make vacuous interval
|
|
|
950 // also add use_kind for dead intervals
|
|
|
951 interval = create_interval(reg_num);
|
|
|
952 if (type != T_ILLEGAL) {
|
|
|
953 interval->set_type(type);
|
|
|
954 }
|
|
|
955
|
|
|
956 interval->add_range(def_pos, def_pos + 1);
|
|
|
957 interval->add_use_pos(def_pos, use_kind);
|
|
|
958 TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: dead value %d at %d in live intervals", reg_num, def_pos));
|
|
|
959 }
|
|
|
960
|
|
|
961 change_spill_definition_pos(interval, def_pos);
|
|
|
962 if (use_kind == noUse && interval->spill_state() <= startInMemory) {
|
|
|
963 // detection of method-parameters and roundfp-results
|
|
|
964 // TODO: move this directly to position where use-kind is computed
|
|
|
965 interval->set_spill_state(startInMemory);
|
|
|
966 }
|
|
|
967 }
|
|
|
968
|
|
|
969 void LinearScan::add_use(int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type) {
|
|
|
970 Interval* interval = interval_at(reg_num);
|
|
|
971 if (interval == NULL) {
|
|
|
972 interval = create_interval(reg_num);
|
|
|
973 }
|
|
|
974 assert(interval->reg_num() == reg_num, "wrong interval");
|
|
|
975
|
|
|
976 if (type != T_ILLEGAL) {
|
|
|
977 interval->set_type(type);
|
|
|
978 }
|
|
|
979
|
|
|
980 interval->add_range(from, to);
|
|
|
981 interval->add_use_pos(to, use_kind);
|
|
|
982 }
|
|
|
983
|
|
|
984 void LinearScan::add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type) {
|
|
|
985 Interval* interval = interval_at(reg_num);
|
|
|
986 if (interval == NULL) {
|
|
|
987 interval = create_interval(reg_num);
|
|
|
988 }
|
|
|
989 assert(interval->reg_num() == reg_num, "wrong interval");
|
|
|
990
|
|
|
991 if (type != T_ILLEGAL) {
|
|
|
992 interval->set_type(type);
|
|
|
993 }
|
|
|
994
|
|
|
995 interval->add_range(temp_pos, temp_pos + 1);
|
|
|
996 interval->add_use_pos(temp_pos, use_kind);
|
|
|
997 }
|
|
|
998
|
|
|
999
|
|
|
1000 // the results of this functions are used for optimizing spilling and reloading
|
|
|
1001 // if the functions return shouldHaveRegister and the interval is spilled,
|
|
|
1002 // it is not reloaded to a register.
|
|
|
1003 IntervalUseKind LinearScan::use_kind_of_output_operand(LIR_Op* op, LIR_Opr opr) {
|
|
|
1004 if (op->code() == lir_move) {
|
|
|
1005 assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
|
|
|
1006 LIR_Op1* move = (LIR_Op1*)op;
|
|
|
1007 LIR_Opr res = move->result_opr();
|
|
|
1008 bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
|
|
|
1009
|
|
|
1010 if (result_in_memory) {
|
|
|
1011 // Begin of an interval with must_start_in_memory set.
|
|
|
1012 // This interval will always get a stack slot first, so return noUse.
|
|
|
1013 return noUse;
|
|
|
1014
|
|
|
1015 } else if (move->in_opr()->is_stack()) {
|
|
|
1016 // method argument (condition must be equal to handle_method_arguments)
|
|
|
1017 return noUse;
|
|
|
1018
|
|
|
1019 } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
|
|
|
1020 // Move from register to register
|
|
|
1021 if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
|
|
|
1022 // special handling of phi-function moves inside osr-entry blocks
|
|
|
1023 // input operand must have a register instead of output operand (leads to better register allocation)
|
|
|
1024 return shouldHaveRegister;
|
|
|
1025 }
|
|
|
1026 }
|
|
|
1027 }
|
|
|
1028
|
|
|
1029 if (opr->is_virtual() &&
|
|
|
1030 gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::must_start_in_memory)) {
|
|
|
1031 // result is a stack-slot, so prevent immediate reloading
|
|
|
1032 return noUse;
|
|
|
1033 }
|
|
|
1034
|
|
|
1035 // all other operands require a register
|
|
|
1036 return mustHaveRegister;
|
|
|
1037 }
|
|
|
1038
|
|
|
1039 IntervalUseKind LinearScan::use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr) {
|
|
|
1040 if (op->code() == lir_move) {
|
|
|
1041 assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
|
|
|
1042 LIR_Op1* move = (LIR_Op1*)op;
|
|
|
1043 LIR_Opr res = move->result_opr();
|
|
|
1044 bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
|
|
|
1045
|
|
|
1046 if (result_in_memory) {
|
|
|
1047 // Move to an interval with must_start_in_memory set.
|
|
|
1048 // To avoid moves from stack to stack (not allowed) force the input operand to a register
|
|
|
1049 return mustHaveRegister;
|
|
|
1050
|
|
|
1051 } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
|
|
|
1052 // Move from register to register
|
|
|
1053 if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
|
|
|
1054 // special handling of phi-function moves inside osr-entry blocks
|
|
|
1055 // input operand must have a register instead of output operand (leads to better register allocation)
|
|
|
1056 return mustHaveRegister;
|
|
|
1057 }
|
|
|
1058
|
|
|
1059 // The input operand is not forced to a register (moves from stack to register are allowed),
|
|
|
1060 // but it is faster if the input operand is in a register
|
|
|
1061 return shouldHaveRegister;
|
|
|
1062 }
|
|
|
1063 }
|
|
|
1064
|
|
|
1065
|
|
|
1066 #ifdef IA32
|
|
|
1067 if (op->code() == lir_cmove) {
|
|
|
1068 // conditional moves can handle stack operands
|
|
|
1069 assert(op->result_opr()->is_register(), "result must always be in a register");
|
|
|
1070 return shouldHaveRegister;
|
|
|
1071 }
|
|
|
1072
|
|
|
1073 // optimizations for second input operand of arithmehtic operations on Intel
|
|
|
1074 // this operand is allowed to be on the stack in some cases
|
|
|
1075 BasicType opr_type = opr->type_register();
|
|
|
1076 if (opr_type == T_FLOAT || opr_type == T_DOUBLE) {
|
|
|
1077 if ((UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2) {
|
|
|
1078 // SSE float instruction (T_DOUBLE only supported with SSE2)
|
|
|
1079 switch (op->code()) {
|
|
|
1080 case lir_cmp:
|
|
|
1081 case lir_add:
|
|
|
1082 case lir_sub:
|
|
|
1083 case lir_mul:
|
|
|
1084 case lir_div:
|
|
|
1085 {
|
|
|
1086 assert(op->as_Op2() != NULL, "must be LIR_Op2");
|
|
|
1087 LIR_Op2* op2 = (LIR_Op2*)op;
|
|
|
1088 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
|
|
|
1089 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
|
|
|
1090 return shouldHaveRegister;
|
|
|
1091 }
|
|
|
1092 }
|
|
|
1093 }
|
|
|
1094 } else {
|
|
|
1095 // FPU stack float instruction
|
|
|
1096 switch (op->code()) {
|
|
|
1097 case lir_add:
|
|
|
1098 case lir_sub:
|
|
|
1099 case lir_mul:
|
|
|
1100 case lir_div:
|
|
|
1101 {
|
|
|
1102 assert(op->as_Op2() != NULL, "must be LIR_Op2");
|
|
|
1103 LIR_Op2* op2 = (LIR_Op2*)op;
|
|
|
1104 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
|
|
|
1105 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
|
|
|
1106 return shouldHaveRegister;
|
|
|
1107 }
|
|
|
1108 }
|
|
|
1109 }
|
|
|
1110 }
|
|
|
1111
|
|
|
1112 } else if (opr_type != T_LONG) {
|
|
|
1113 // integer instruction (note: long operands must always be in register)
|
|
|
1114 switch (op->code()) {
|
|
|
1115 case lir_cmp:
|
|
|
1116 case lir_add:
|
|
|
1117 case lir_sub:
|
|
|
1118 case lir_logic_and:
|
|
|
1119 case lir_logic_or:
|
|
|
1120 case lir_logic_xor:
|
|
|
1121 {
|
|
|
1122 assert(op->as_Op2() != NULL, "must be LIR_Op2");
|
|
|
1123 LIR_Op2* op2 = (LIR_Op2*)op;
|
|
|
1124 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
|
|
|
1125 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
|
|
|
1126 return shouldHaveRegister;
|
|
|
1127 }
|
|
|
1128 }
|
|
|
1129 }
|
|
|
1130 }
|
|
|
1131 #endif // IA32
|
|
|
1132
|
|
|
1133 // all other operands require a register
|
|
|
1134 return mustHaveRegister;
|
|
|
1135 }
|
|
|
1136
|
|
|
1137
|
|
|
1138 void LinearScan::handle_method_arguments(LIR_Op* op) {
|
|
|
1139 // special handling for method arguments (moves from stack to virtual register):
|
|
|
1140 // the interval gets no register assigned, but the stack slot.
|
|
|
1141 // it is split before the first use by the register allocator.
|
|
|
1142
|
|
|
1143 if (op->code() == lir_move) {
|
|
|
1144 assert(op->as_Op1() != NULL, "must be LIR_Op1");
|
|
|
1145 LIR_Op1* move = (LIR_Op1*)op;
|
|
|
1146
|
|
|
1147 if (move->in_opr()->is_stack()) {
|
|
|
1148 #ifdef ASSERT
|
|
|
1149 int arg_size = compilation()->method()->arg_size();
|
|
|
1150 LIR_Opr o = move->in_opr();
|
|
|
1151 if (o->is_single_stack()) {
|
|
|
1152 assert(o->single_stack_ix() >= 0 && o->single_stack_ix() < arg_size, "out of range");
|
|
|
1153 } else if (o->is_double_stack()) {
|
|
|
1154 assert(o->double_stack_ix() >= 0 && o->double_stack_ix() < arg_size, "out of range");
|
|
|
1155 } else {
|
|
|
1156 ShouldNotReachHere();
|
|
|
1157 }
|
|
|
1158
|
|
|
1159 assert(move->id() > 0, "invalid id");
|
|
|
1160 assert(block_of_op_with_id(move->id())->number_of_preds() == 0, "move from stack must be in first block");
|
|
|
1161 assert(move->result_opr()->is_virtual(), "result of move must be a virtual register");
|
|
|
1162
|
|
|
1163 TRACE_LINEAR_SCAN(4, tty->print_cr("found move from stack slot %d to vreg %d", o->is_single_stack() ? o->single_stack_ix() : o->double_stack_ix(), reg_num(move->result_opr())));
|
|
|
1164 #endif
|
|
|
1165
|
|
|
1166 Interval* interval = interval_at(reg_num(move->result_opr()));
|
|
|
1167
|
|
|
1168 int stack_slot = LinearScan::nof_regs + (move->in_opr()->is_single_stack() ? move->in_opr()->single_stack_ix() : move->in_opr()->double_stack_ix());
|
|
|
1169 interval->set_canonical_spill_slot(stack_slot);
|
|
|
1170 interval->assign_reg(stack_slot);
|
|
|
1171 }
|
|
|
1172 }
|
|
|
1173 }
|
|
|
1174
|
|
|
1175 void LinearScan::handle_doubleword_moves(LIR_Op* op) {
|
|
|
1176 // special handling for doubleword move from memory to register:
|
|
|
1177 // in this case the registers of the input address and the result
|
|
|
1178 // registers must not overlap -> add a temp range for the input registers
|
|
|
1179 if (op->code() == lir_move) {
|
|
|
1180 assert(op->as_Op1() != NULL, "must be LIR_Op1");
|
|
|
1181 LIR_Op1* move = (LIR_Op1*)op;
|
|
|
1182
|
|
|
1183 if (move->result_opr()->is_double_cpu() && move->in_opr()->is_pointer()) {
|
|
|
1184 LIR_Address* address = move->in_opr()->as_address_ptr();
|
|
|
1185 if (address != NULL) {
|
|
|
1186 if (address->base()->is_valid()) {
|
|
|
1187 add_temp(address->base(), op->id(), noUse);
|
|
|
1188 }
|
|
|
1189 if (address->index()->is_valid()) {
|
|
|
1190 add_temp(address->index(), op->id(), noUse);
|
|
|
1191 }
|
|
|
1192 }
|
|
|
1193 }
|
|
|
1194 }
|
|
|
1195 }
|
|
|
1196
|
|
|
1197 void LinearScan::add_register_hints(LIR_Op* op) {
|
|
|
1198 switch (op->code()) {
|
|
|
1199 case lir_move: // fall through
|
|
|
1200 case lir_convert: {
|
|
|
1201 assert(op->as_Op1() != NULL, "lir_move, lir_convert must be LIR_Op1");
|
|
|
1202 LIR_Op1* move = (LIR_Op1*)op;
|
|
|
1203
|
|
|
1204 LIR_Opr move_from = move->in_opr();
|
|
|
1205 LIR_Opr move_to = move->result_opr();
|
|
|
1206
|
|
|
1207 if (move_to->is_register() && move_from->is_register()) {
|
|
|
1208 Interval* from = interval_at(reg_num(move_from));
|
|
|
1209 Interval* to = interval_at(reg_num(move_to));
|
|
|
1210 if (from != NULL && to != NULL) {
|
|
|
1211 to->set_register_hint(from);
|
|
|
1212 TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", move->id(), from->reg_num(), to->reg_num()));
|
|
|
1213 }
|
|
|
1214 }
|
|
|
1215 break;
|
|
|
1216 }
|
|
|
1217 case lir_cmove: {
|
|
|
1218 assert(op->as_Op2() != NULL, "lir_cmove must be LIR_Op2");
|
|
|
1219 LIR_Op2* cmove = (LIR_Op2*)op;
|
|
|
1220
|
|
|
1221 LIR_Opr move_from = cmove->in_opr1();
|
|
|
1222 LIR_Opr move_to = cmove->result_opr();
|
|
|
1223
|
|
|
1224 if (move_to->is_register() && move_from->is_register()) {
|
|
|
1225 Interval* from = interval_at(reg_num(move_from));
|
|
|
1226 Interval* to = interval_at(reg_num(move_to));
|
|
|
1227 if (from != NULL && to != NULL) {
|
|
|
1228 to->set_register_hint(from);
|
|
|
1229 TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num()));
|
|
|
1230 }
|
|
|
1231 }
|
|
|
1232 break;
|
|
|
1233 }
|
|
|
1234 }
|
|
|
1235 }
|
|
|
1236
|
|
|
1237
|
|
|
1238 void LinearScan::build_intervals() {
|
|
|
1239 TIME_LINEAR_SCAN(timer_build_intervals);
|
|
|
1240
|
|
|
1241 // initialize interval list with expected number of intervals
|
|
|
1242 // (32 is added to have some space for split children without having to resize the list)
|
|
|
1243 _intervals = IntervalList(num_virtual_regs() + 32);
|
|
|
1244 // initialize all slots that are used by build_intervals
|
|
|
1245 _intervals.at_put_grow(num_virtual_regs() - 1, NULL, NULL);
|
|
|
1246
|
|
|
1247 // create a list with all caller-save registers (cpu, fpu, xmm)
|
|
|
1248 // when an instruction is a call, a temp range is created for all these registers
|
|
|
1249 int num_caller_save_registers = 0;
|
|
|
1250 int caller_save_registers[LinearScan::nof_regs];
|
|
|
1251
|
|
|
1252 int i;
|
|
|
1253 for (i = 0; i < FrameMap::nof_caller_save_cpu_regs; i++) {
|
|
|
1254 LIR_Opr opr = FrameMap::caller_save_cpu_reg_at(i);
|
|
|
1255 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
|
|
|
1256 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
|
|
|
1257 caller_save_registers[num_caller_save_registers++] = reg_num(opr);
|
|
|
1258 }
|
|
|
1259
|
|
|
1260 // temp ranges for fpu registers are only created when the method has
|
|
|
1261 // virtual fpu operands. Otherwise no allocation for fpu registers is
|
|
|
1262 // perfomed and so the temp ranges would be useless
|
|
|
1263 if (has_fpu_registers()) {
|
|
|
1264 #ifdef IA32
|
|
|
1265 if (UseSSE < 2) {
|
|
|
1266 #endif
|
|
|
1267 for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) {
|
|
|
1268 LIR_Opr opr = FrameMap::caller_save_fpu_reg_at(i);
|
|
|
1269 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
|
|
|
1270 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
|
|
|
1271 caller_save_registers[num_caller_save_registers++] = reg_num(opr);
|
|
|
1272 }
|
|
|
1273 #ifdef IA32
|
|
|
1274 }
|
|
|
1275 if (UseSSE > 0) {
|
|
|
1276 for (i = 0; i < FrameMap::nof_caller_save_xmm_regs; i++) {
|
|
|
1277 LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(i);
|
|
|
1278 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
|
|
|
1279 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
|
|
|
1280 caller_save_registers[num_caller_save_registers++] = reg_num(opr);
|
|
|
1281 }
|
|
|
1282 }
|
|
|
1283 #endif
|
|
|
1284 }
|
|
|
1285 assert(num_caller_save_registers <= LinearScan::nof_regs, "out of bounds");
|
|
|
1286
|
|
|
1287
|
|
|
1288 LIR_OpVisitState visitor;
|
|
|
1289
|
|
|
1290 // iterate all blocks in reverse order
|
|
|
1291 for (i = block_count() - 1; i >= 0; i--) {
|
|
|
1292 BlockBegin* block = block_at(i);
|
|
|
1293 LIR_OpList* instructions = block->lir()->instructions_list();
|
|
|
1294 int block_from = block->first_lir_instruction_id();
|
|
|
1295 int block_to = block->last_lir_instruction_id();
|
|
|
1296
|
|
|
1297 assert(block_from == instructions->at(0)->id(), "must be");
|
|
|
1298 assert(block_to == instructions->at(instructions->length() - 1)->id(), "must be");
|
|
|
1299
|
|
|
1300 // Update intervals for registers live at the end of this block;
|
|
|
1301 BitMap live = block->live_out();
|
|
|
1302 int size = live.size();
|
|
|
1303 for (int number = live.get_next_one_offset(0, size); number < size; number = live.get_next_one_offset(number + 1, size)) {
|
|
|
1304 assert(live.at(number), "should not stop here otherwise");
|
|
|
1305 assert(number >= LIR_OprDesc::vreg_base, "fixed intervals must not be live on block bounds");
|
|
|
1306 TRACE_LINEAR_SCAN(2, tty->print_cr("live in %d to %d", number, block_to + 2));
|
|
|
1307
|
|
|
1308 add_use(number, block_from, block_to + 2, noUse, T_ILLEGAL);
|
|
|
1309
|
|
|
1310 // add special use positions for loop-end blocks when the
|
|
|
1311 // interval is used anywhere inside this loop. It's possible
|
|
|
1312 // that the block was part of a non-natural loop, so it might
|
|
|
1313 // have an invalid loop index.
|
|
|
1314 if (block->is_set(BlockBegin::linear_scan_loop_end_flag) &&
|
|
|
1315 block->loop_index() != -1 &&
|
|
|
1316 is_interval_in_loop(number, block->loop_index())) {
|
|
|
1317 interval_at(number)->add_use_pos(block_to + 1, loopEndMarker);
|
|
|
1318 }
|
|
|
1319 }
|
|
|
1320
|
|
|
1321 // iterate all instructions of the block in reverse order.
|
|
|
1322 // skip the first instruction because it is always a label
|
|
|
1323 // definitions of intervals are processed before uses
|
|
|
1324 assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
|
|
|
1325 for (int j = instructions->length() - 1; j >= 1; j--) {
|
|
|
1326 LIR_Op* op = instructions->at(j);
|
|
|
1327 int op_id = op->id();
|
|
|
1328
|
|
|
1329 // visit operation to collect all operands
|
|
|
1330 visitor.visit(op);
|
|
|
1331
|
|
|
1332 // add a temp range for each register if operation destroys caller-save registers
|
|
|
1333 if (visitor.has_call()) {
|
|
|
1334 for (int k = 0; k < num_caller_save_registers; k++) {
|
|
|
1335 add_temp(caller_save_registers[k], op_id, noUse, T_ILLEGAL);
|
|
|
1336 }
|
|
|
1337 TRACE_LINEAR_SCAN(4, tty->print_cr("operation destroys all caller-save registers"));
|
|
|
1338 }
|
|
|
1339
|
|
|
1340 // Add any platform dependent temps
|
|
|
1341 pd_add_temps(op);
|
|
|
1342
|
|
|
1343 // visit definitions (output and temp operands)
|
|
|
1344 int k, n;
|
|
|
1345 n = visitor.opr_count(LIR_OpVisitState::outputMode);
|
|
|
1346 for (k = 0; k < n; k++) {
|
|
|
1347 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
|
|
|
1348 assert(opr->is_register(), "visitor should only return register operands");
|
|
|
1349 add_def(opr, op_id, use_kind_of_output_operand(op, opr));
|
|
|
1350 }
|
|
|
1351
|
|
|
1352 n = visitor.opr_count(LIR_OpVisitState::tempMode);
|
|
|
1353 for (k = 0; k < n; k++) {
|
|
|
1354 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
|
|
|
1355 assert(opr->is_register(), "visitor should only return register operands");
|
|
|
1356 add_temp(opr, op_id, mustHaveRegister);
|
|
|
1357 }
|
|
|
1358
|
|
|
1359 // visit uses (input operands)
|
|
|
1360 n = visitor.opr_count(LIR_OpVisitState::inputMode);
|
|
|
1361 for (k = 0; k < n; k++) {
|
|
|
1362 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
|
|
|
1363 assert(opr->is_register(), "visitor should only return register operands");
|
|
|
1364 add_use(opr, block_from, op_id, use_kind_of_input_operand(op, opr));
|
|
|
1365 }
|
|
|
1366
|
|
|
1367 // Add uses of live locals from interpreter's point of view for proper
|
|
|
1368 // debug information generation
|
|
|
1369 // Treat these operands as temp values (if the life range is extended
|
|
|
1370 // to a call site, the value would be in a register at the call otherwise)
|
|
|
1371 n = visitor.info_count();
|
|
|
1372 for (k = 0; k < n; k++) {
|
|
|
1373 CodeEmitInfo* info = visitor.info_at(k);
|
|
|
1374 ValueStack* stack = info->stack();
|
|
|
1375 for_each_state_value(stack, value,
|
|
|
1376 add_use(value, block_from, op_id + 1, noUse);
|
|
|
1377 );
|
|
|
1378 }
|
|
|
1379
|
|
|
1380 // special steps for some instructions (especially moves)
|
|
|
1381 handle_method_arguments(op);
|
|
|
1382 handle_doubleword_moves(op);
|
|
|
1383 add_register_hints(op);
|
|
|
1384
|
|
|
1385 } // end of instruction iteration
|
|
|
1386 } // end of block iteration
|
|
|
1387
|
|
|
1388
|
|
|
1389 // add the range [0, 1[ to all fixed intervals
|
|
|
1390 // -> the register allocator need not handle unhandled fixed intervals
|
|
|
1391 for (int n = 0; n < LinearScan::nof_regs; n++) {
|
|
|
1392 Interval* interval = interval_at(n);
|
|
|
1393 if (interval != NULL) {
|
|
|
1394 interval->add_range(0, 1);
|
|
|
1395 }
|
|
|
1396 }
|
|
|
1397 }
|
|
|
1398
|
|
|
1399
|
|
|
1400 // ********** Phase 5: actual register allocation
|
|
|
1401
|
|
|
1402 int LinearScan::interval_cmp(Interval** a, Interval** b) {
|
|
|
1403 if (*a != NULL) {
|
|
|
1404 if (*b != NULL) {
|
|
|
1405 return (*a)->from() - (*b)->from();
|
|
|
1406 } else {
|
|
|
1407 return -1;
|
|
|
1408 }
|
|
|
1409 } else {
|
|
|
1410 if (*b != NULL) {
|
|
|
1411 return 1;
|
|
|
1412 } else {
|
|
|
1413 return 0;
|
|
|
1414 }
|
|
|
1415 }
|
|
|
1416 }
|
|
|
1417
|
|
|
1418 #ifndef PRODUCT
|
|
|
1419 bool LinearScan::is_sorted(IntervalArray* intervals) {
|
|
|
1420 int from = -1;
|
|
|
1421 int i, j;
|
|
|
1422 for (i = 0; i < intervals->length(); i ++) {
|
|
|
1423 Interval* it = intervals->at(i);
|
|
|
1424 if (it != NULL) {
|
|
|
1425 if (from > it->from()) {
|
|
|
1426 assert(false, "");
|
|
|
1427 return false;
|
|
|
1428 }
|
|
|
1429 from = it->from();
|
|
|
1430 }
|
|
|
1431 }
|
|
|
1432
|
|
|
1433 // check in both directions if sorted list and unsorted list contain same intervals
|
|
|
1434 for (i = 0; i < interval_count(); i++) {
|
|
|
1435 if (interval_at(i) != NULL) {
|
|
|
1436 int num_found = 0;
|
|
|
1437 for (j = 0; j < intervals->length(); j++) {
|
|
|
1438 if (interval_at(i) == intervals->at(j)) {
|
|
|
1439 num_found++;
|
|
|
1440 }
|
|
|
1441 }
|
|
|
1442 assert(num_found == 1, "lists do not contain same intervals");
|
|
|
1443 }
|
|
|
1444 }
|
|
|
1445 for (j = 0; j < intervals->length(); j++) {
|
|
|
1446 int num_found = 0;
|
|
|
1447 for (i = 0; i < interval_count(); i++) {
|
|
|
1448 if (interval_at(i) == intervals->at(j)) {
|
|
|
1449 num_found++;
|
|
|
1450 }
|
|
|
1451 }
|
|
|
1452 assert(num_found == 1, "lists do not contain same intervals");
|
|
|
1453 }
|
|
|
1454
|
|
|
1455 return true;
|
|
|
1456 }
|
|
|
1457 #endif
|
|
|
1458
|
|
|
1459 void LinearScan::add_to_list(Interval** first, Interval** prev, Interval* interval) {
|
|
|
1460 if (*prev != NULL) {
|
|
|
1461 (*prev)->set_next(interval);
|
|
|
1462 } else {
|
|
|
1463 *first = interval;
|
|
|
1464 }
|
|
|
1465 *prev = interval;
|
|
|
1466 }
|
|
|
1467
|
|
|
1468 void LinearScan::create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)) {
|
|
|
1469 assert(is_sorted(_sorted_intervals), "interval list is not sorted");
|
|
|
1470
|
|
|
1471 *list1 = *list2 = Interval::end();
|
|
|
1472
|
|
|
1473 Interval* list1_prev = NULL;
|
|
|
1474 Interval* list2_prev = NULL;
|
|
|
1475 Interval* v;
|
|
|
1476
|
|
|
1477 const int n = _sorted_intervals->length();
|
|
|
1478 for (int i = 0; i < n; i++) {
|
|
|
1479 v = _sorted_intervals->at(i);
|
|
|
1480 if (v == NULL) continue;
|
|
|
1481
|
|
|
1482 if (is_list1(v)) {
|
|
|
1483 add_to_list(list1, &list1_prev, v);
|
|
|
1484 } else if (is_list2 == NULL || is_list2(v)) {
|
|
|
1485 add_to_list(list2, &list2_prev, v);
|
|
|
1486 }
|
|
|
1487 }
|
|
|
1488
|
|
|
1489 if (list1_prev != NULL) list1_prev->set_next(Interval::end());
|
|
|
1490 if (list2_prev != NULL) list2_prev->set_next(Interval::end());
|
|
|
1491
|
|
|
1492 assert(list1_prev == NULL || list1_prev->next() == Interval::end(), "linear list ends not with sentinel");
|
|
|
1493 assert(list2_prev == NULL || list2_prev->next() == Interval::end(), "linear list ends not with sentinel");
|
|
|
1494 }
|
|
|
1495
|
|
|
1496
|
|
|
1497 void LinearScan::sort_intervals_before_allocation() {
|
|
|
1498 TIME_LINEAR_SCAN(timer_sort_intervals_before);
|
|
|
1499
|
|
|
1500 IntervalList* unsorted_list = &_intervals;
|
|
|
1501 int unsorted_len = unsorted_list->length();
|
|
|
1502 int sorted_len = 0;
|
|
|
1503 int unsorted_idx;
|
|
|
1504 int sorted_idx = 0;
|
|
|
1505 int sorted_from_max = -1;
|
|
|
1506
|
|
|
1507 // calc number of items for sorted list (sorted list must not contain NULL values)
|
|
|
1508 for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
|
|
|
1509 if (unsorted_list->at(unsorted_idx) != NULL) {
|
|
|
1510 sorted_len++;
|
|
|
1511 }
|
|
|
1512 }
|
|
|
1513 IntervalArray* sorted_list = new IntervalArray(sorted_len);
|
|
|
1514
|
|
|
1515 // special sorting algorithm: the original interval-list is almost sorted,
|
|
|
1516 // only some intervals are swapped. So this is much faster than a complete QuickSort
|
|
|
1517 for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
|
|
|
1518 Interval* cur_interval = unsorted_list->at(unsorted_idx);
|
|
|
1519
|
|
|
1520 if (cur_interval != NULL) {
|
|
|
1521 int cur_from = cur_interval->from();
|
|
|
1522
|
|
|
1523 if (sorted_from_max <= cur_from) {
|
|
|
1524 sorted_list->at_put(sorted_idx++, cur_interval);
|
|
|
1525 sorted_from_max = cur_interval->from();
|
|
|
1526 } else {
|
|
|
1527 // the asumption that the intervals are already sorted failed,
|
|
|
1528 // so this interval must be sorted in manually
|
|
|
1529 int j;
|
|
|
1530 for (j = sorted_idx - 1; j >= 0 && cur_from < sorted_list->at(j)->from(); j--) {
|
|
|
1531 sorted_list->at_put(j + 1, sorted_list->at(j));
|
|
|
1532 }
|
|
|
1533 sorted_list->at_put(j + 1, cur_interval);
|
|
|
1534 sorted_idx++;
|
|
|
1535 }
|
|
|
1536 }
|
|
|
1537 }
|
|
|
1538 _sorted_intervals = sorted_list;
|
|
|
1539 }
|
|
|
1540
|
|
|
1541 void LinearScan::sort_intervals_after_allocation() {
|
|
|
1542 TIME_LINEAR_SCAN(timer_sort_intervals_after);
|
|
|
1543
|
|
|
1544 IntervalArray* old_list = _sorted_intervals;
|
|
|
1545 IntervalList* new_list = _new_intervals_from_allocation;
|
|
|
1546 int old_len = old_list->length();
|
|
|
1547 int new_len = new_list->length();
|
|
|
1548
|
|
|
1549 if (new_len == 0) {
|
|
|
1550 // no intervals have been added during allocation, so sorted list is already up to date
|
|
|
1551 return;
|
|
|
1552 }
|
|
|
1553
|
|
|
1554 // conventional sort-algorithm for new intervals
|
|
|
1555 new_list->sort(interval_cmp);
|
|
|
1556
|
|
|
1557 // merge old and new list (both already sorted) into one combined list
|
|
|
1558 IntervalArray* combined_list = new IntervalArray(old_len + new_len);
|
|
|
1559 int old_idx = 0;
|
|
|
1560 int new_idx = 0;
|
|
|
1561
|
|
|
1562 while (old_idx + new_idx < old_len + new_len) {
|
|
|
1563 if (new_idx >= new_len || (old_idx < old_len && old_list->at(old_idx)->from() <= new_list->at(new_idx)->from())) {
|
|
|
1564 combined_list->at_put(old_idx + new_idx, old_list->at(old_idx));
|
|
|
1565 old_idx++;
|
|
|
1566 } else {
|
|
|
1567 combined_list->at_put(old_idx + new_idx, new_list->at(new_idx));
|
|
|
1568 new_idx++;
|
|
|
1569 }
|
|
|
1570 }
|
|
|
1571
|
|
|
1572 _sorted_intervals = combined_list;
|
|
|
1573 }
|
|
|
1574
|
|
|
1575
|
|
|
1576 void LinearScan::allocate_registers() {
|
|
|
1577 TIME_LINEAR_SCAN(timer_allocate_registers);
|
|
|
1578
|
|
|
1579 Interval* precolored_cpu_intervals, *not_precolored_cpu_intervals;
|
|
|
1580 Interval* precolored_fpu_intervals, *not_precolored_fpu_intervals;
|
|
|
1581
|
|
|
1582 create_unhandled_lists(&precolored_cpu_intervals, ¬_precolored_cpu_intervals, is_precolored_cpu_interval, is_virtual_cpu_interval);
|
|
|
1583 if (has_fpu_registers()) {
|
|
|
1584 create_unhandled_lists(&precolored_fpu_intervals, ¬_precolored_fpu_intervals, is_precolored_fpu_interval, is_virtual_fpu_interval);
|
|
|
1585 #ifdef ASSERT
|
|
|
1586 } else {
|
|
|
1587 // fpu register allocation is omitted because no virtual fpu registers are present
|
|
|
1588 // just check this again...
|
|
|
1589 create_unhandled_lists(&precolored_fpu_intervals, ¬_precolored_fpu_intervals, is_precolored_fpu_interval, is_virtual_fpu_interval);
|
|
|
1590 assert(not_precolored_fpu_intervals == Interval::end(), "missed an uncolored fpu interval");
|
|
|
1591 #endif
|
|
|
1592 }
|
|
|
1593
|
|
|
1594 // allocate cpu registers
|
|
|
1595 LinearScanWalker cpu_lsw(this, precolored_cpu_intervals, not_precolored_cpu_intervals);
|
|
|
1596 cpu_lsw.walk();
|
|
|
1597 cpu_lsw.finish_allocation();
|
|
|
1598
|
|
|
1599 if (has_fpu_registers()) {
|
|
|
1600 // allocate fpu registers
|
|
|
1601 LinearScanWalker fpu_lsw(this, precolored_fpu_intervals, not_precolored_fpu_intervals);
|
|
|
1602 fpu_lsw.walk();
|
|
|
1603 fpu_lsw.finish_allocation();
|
|
|
1604 }
|
|
|
1605 }
|
|
|
1606
|
|
|
1607
|
|
|
1608 // ********** Phase 6: resolve data flow
|
|
|
1609 // (insert moves at edges between blocks if intervals have been split)
|
|
|
1610
|
|
|
1611 // wrapper for Interval::split_child_at_op_id that performs a bailout in product mode
|
|
|
1612 // instead of returning NULL
|
|
|
1613 Interval* LinearScan::split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode) {
|
|
|
1614 Interval* result = interval->split_child_at_op_id(op_id, mode);
|
|
|
1615 if (result != NULL) {
|
|
|
1616 return result;
|
|
|
1617 }
|
|
|
1618
|
|
|
1619 assert(false, "must find an interval, but do a clean bailout in product mode");
|
|
|
1620 result = new Interval(LIR_OprDesc::vreg_base);
|
|
|
1621 result->assign_reg(0);
|
|
|
1622 result->set_type(T_INT);
|
|
|
1623 BAILOUT_("LinearScan: interval is NULL", result);
|
|
|
1624 }
|
|
|
1625
|
|
|
1626
|
|
|
1627 Interval* LinearScan::interval_at_block_begin(BlockBegin* block, int reg_num) {
|
|
|
1628 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
|
|
|
1629 assert(interval_at(reg_num) != NULL, "no interval found");
|
|
|
1630
|
|
|
1631 return split_child_at_op_id(interval_at(reg_num), block->first_lir_instruction_id(), LIR_OpVisitState::outputMode);
|
|
|
1632 }
|
|
|
1633
|
|
|
1634 Interval* LinearScan::interval_at_block_end(BlockBegin* block, int reg_num) {
|
|
|
1635 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
|
|
|
1636 assert(interval_at(reg_num) != NULL, "no interval found");
|
|
|
1637
|
|
|
1638 return split_child_at_op_id(interval_at(reg_num), block->last_lir_instruction_id() + 1, LIR_OpVisitState::outputMode);
|
|
|
1639 }
|
|
|
1640
|
|
|
1641 Interval* LinearScan::interval_at_op_id(int reg_num, int op_id) {
|
|
|
1642 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
|
|
|
1643 assert(interval_at(reg_num) != NULL, "no interval found");
|
|
|
1644
|
|
|
1645 return split_child_at_op_id(interval_at(reg_num), op_id, LIR_OpVisitState::inputMode);
|
|
|
1646 }
|
|
|
1647
|
|
|
1648
|
|
|
1649 void LinearScan::resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
|
|
|
1650 DEBUG_ONLY(move_resolver.check_empty());
|
|
|
1651
|
|
|
1652 const int num_regs = num_virtual_regs();
|
|
|
1653 const int size = live_set_size();
|
|
|
1654 const BitMap live_at_edge = to_block->live_in();
|
|
|
1655
|
|
|
1656 // visit all registers where the live_at_edge bit is set
|
|
|
1657 for (int r = live_at_edge.get_next_one_offset(0, size); r < size; r = live_at_edge.get_next_one_offset(r + 1, size)) {
|
|
|
1658 assert(r < num_regs, "live information set for not exisiting interval");
|
|
|
1659 assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge");
|
|
|
1660
|
|
|
1661 Interval* from_interval = interval_at_block_end(from_block, r);
|
|
|
1662 Interval* to_interval = interval_at_block_begin(to_block, r);
|
|
|
1663
|
|
|
1664 if (from_interval != to_interval && (from_interval->assigned_reg() != to_interval->assigned_reg() || from_interval->assigned_regHi() != to_interval->assigned_regHi())) {
|
|
|
1665 // need to insert move instruction
|
|
|
1666 move_resolver.add_mapping(from_interval, to_interval);
|
|
|
1667 }
|
|
|
1668 }
|
|
|
1669 }
|
|
|
1670
|
|
|
1671
|
|
|
1672 void LinearScan::resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
|
|
|
1673 if (from_block->number_of_sux() <= 1) {
|
|
|
1674 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at end of from_block B%d", from_block->block_id()));
|
|
|
1675
|
|
|
1676 LIR_OpList* instructions = from_block->lir()->instructions_list();
|
|
|
1677 LIR_OpBranch* branch = instructions->last()->as_OpBranch();
|
|
|
1678 if (branch != NULL) {
|
|
|
1679 // insert moves before branch
|
|
|
1680 assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
|
|
|
1681 move_resolver.set_insert_position(from_block->lir(), instructions->length() - 2);
|
|
|
1682 } else {
|
|
|
1683 move_resolver.set_insert_position(from_block->lir(), instructions->length() - 1);
|
|
|
1684 }
|
|
|
1685
|
|
|
1686 } else {
|
|
|
1687 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at beginning of to_block B%d", to_block->block_id()));
|
|
|
1688 #ifdef ASSERT
|
|
|
1689 assert(from_block->lir()->instructions_list()->at(0)->as_OpLabel() != NULL, "block does not start with a label");
|
|
|
1690
|
|
|
1691 // because the number of predecessor edges matches the number of
|
|
|
1692 // successor edges, blocks which are reached by switch statements
|
|
|
1693 // may have be more than one predecessor but it will be guaranteed
|
|
|
1694 // that all predecessors will be the same.
|
|
|
1695 for (int i = 0; i < to_block->number_of_preds(); i++) {
|
|
|
1696 assert(from_block == to_block->pred_at(i), "all critical edges must be broken");
|
|
|
1697 }
|
|
|
1698 #endif
|
|
|
1699
|
|
|
1700 move_resolver.set_insert_position(to_block->lir(), 0);
|
|
|
1701 }
|
|
|
1702 }
|
|
|
1703
|
|
|
1704
|
|
|
1705 // insert necessary moves (spilling or reloading) at edges between blocks if interval has been split
|
|
|
1706 void LinearScan::resolve_data_flow() {
|
|
|
1707 TIME_LINEAR_SCAN(timer_resolve_data_flow);
|
|
|
1708
|
|
|
1709 int num_blocks = block_count();
|
|
|
1710 MoveResolver move_resolver(this);
|
|
|
1711 BitMap block_completed(num_blocks); block_completed.clear();
|
|
|
1712 BitMap already_resolved(num_blocks); already_resolved.clear();
|
|
|
1713
|
|
|
1714 int i;
|
|
|
1715 for (i = 0; i < num_blocks; i++) {
|
|
|
1716 BlockBegin* block = block_at(i);
|
|
|
1717
|
|
|
1718 // check if block has only one predecessor and only one successor
|
|
|
1719 if (block->number_of_preds() == 1 && block->number_of_sux() == 1 && block->number_of_exception_handlers() == 0) {
|
|
|
1720 LIR_OpList* instructions = block->lir()->instructions_list();
|
|
|
1721 assert(instructions->at(0)->code() == lir_label, "block must start with label");
|
|
|
1722 assert(instructions->last()->code() == lir_branch, "block with successors must end with branch");
|
|
|
1723 assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block with successor must end with unconditional branch");
|
|
|
1724
|
|
|
1725 // check if block is empty (only label and branch)
|
|
|
1726 if (instructions->length() == 2) {
|
|
|
1727 BlockBegin* pred = block->pred_at(0);
|
|
|
1728 BlockBegin* sux = block->sux_at(0);
|
|
|
1729
|
|
|
1730 // prevent optimization of two consecutive blocks
|
|
|
1731 if (!block_completed.at(pred->linear_scan_number()) && !block_completed.at(sux->linear_scan_number())) {
|
|
|
1732 TRACE_LINEAR_SCAN(3, tty->print_cr("**** optimizing empty block B%d (pred: B%d, sux: B%d)", block->block_id(), pred->block_id(), sux->block_id()));
|
|
|
1733 block_completed.set_bit(block->linear_scan_number());
|
|
|
1734
|
|
|
1735 // directly resolve between pred and sux (without looking at the empty block between)
|
|
|
1736 resolve_collect_mappings(pred, sux, move_resolver);
|
|
|
1737 if (move_resolver.has_mappings()) {
|
|
|
1738 move_resolver.set_insert_position(block->lir(), 0);
|
|
|
1739 move_resolver.resolve_and_append_moves();
|
|
|
1740 }
|
|
|
1741 }
|
|
|
1742 }
|
|
|
1743 }
|
|
|
1744 }
|
|
|
1745
|
|
|
1746
|
|
|
1747 for (i = 0; i < num_blocks; i++) {
|
|
|
1748 if (!block_completed.at(i)) {
|
|
|
1749 BlockBegin* from_block = block_at(i);
|
|
|
1750 already_resolved.set_from(block_completed);
|
|
|
1751
|
|
|
1752 int num_sux = from_block->number_of_sux();
|
|
|
1753 for (int s = 0; s < num_sux; s++) {
|
|
|
1754 BlockBegin* to_block = from_block->sux_at(s);
|
|
|
1755
|
|
|
1756 // check for duplicate edges between the same blocks (can happen with switch blocks)
|
|
|
1757 if (!already_resolved.at(to_block->linear_scan_number())) {
|
|
|
1758 TRACE_LINEAR_SCAN(3, tty->print_cr("**** processing edge between B%d and B%d", from_block->block_id(), to_block->block_id()));
|
|
|
1759 already_resolved.set_bit(to_block->linear_scan_number());
|
|
|
1760
|
|
|
1761 // collect all intervals that have been split between from_block and to_block
|
|
|
1762 resolve_collect_mappings(from_block, to_block, move_resolver);
|
|
|
1763 if (move_resolver.has_mappings()) {
|
|
|
1764 resolve_find_insert_pos(from_block, to_block, move_resolver);
|
|
|
1765 move_resolver.resolve_and_append_moves();
|
|
|
1766 }
|
|
|
1767 }
|
|
|
1768 }
|
|
|
1769 }
|
|
|
1770 }
|
|
|
1771 }
|
|
|
1772
|
|
|
1773
|
|
|
1774 void LinearScan::resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver) {
|
|
|
1775 if (interval_at(reg_num) == NULL) {
|
|
|
1776 // if a phi function is never used, no interval is created -> ignore this
|
|
|
1777 return;
|
|
|
1778 }
|
|
|
1779
|
|
|
1780 Interval* interval = interval_at_block_begin(block, reg_num);
|
|
|
1781 int reg = interval->assigned_reg();
|
|
|
1782 int regHi = interval->assigned_regHi();
|
|
|
1783
|
|
|
1784 if ((reg < nof_regs && interval->always_in_memory()) ||
|
|
|
1785 (use_fpu_stack_allocation() && reg >= pd_first_fpu_reg && reg <= pd_last_fpu_reg)) {
|
|
|
1786 // the interval is split to get a short range that is located on the stack
|
|
|
1787 // in the following two cases:
|
|
|
1788 // * the interval started in memory (e.g. method parameter), but is currently in a register
|
|
|
1789 // this is an optimization for exception handling that reduces the number of moves that
|
|
|
1790 // are necessary for resolving the states when an exception uses this exception handler
|
|
|
1791 // * the interval would be on the fpu stack at the begin of the exception handler
|
|
|
1792 // this is not allowed because of the complicated fpu stack handling on Intel
|
|
|
1793
|
|
|
1794 // range that will be spilled to memory
|
|
|
1795 int from_op_id = block->first_lir_instruction_id();
|
|
|
1796 int to_op_id = from_op_id + 1; // short live range of length 1
|
|
|
1797 assert(interval->from() <= from_op_id && interval->to() >= to_op_id,
|
|
|
1798 "no split allowed between exception entry and first instruction");
|
|
|
1799
|
|
|
1800 if (interval->from() != from_op_id) {
|
|
|
1801 // the part before from_op_id is unchanged
|
|
|
1802 interval = interval->split(from_op_id);
|
|
|
1803 interval->assign_reg(reg, regHi);
|
|
|
1804 append_interval(interval);
|
|
|
1805 }
|
|
|
1806 assert(interval->from() == from_op_id, "must be true now");
|
|
|
1807
|
|
|
1808 Interval* spilled_part = interval;
|
|
|
1809 if (interval->to() != to_op_id) {
|
|
|
1810 // the part after to_op_id is unchanged
|
|
|
1811 spilled_part = interval->split_from_start(to_op_id);
|
|
|
1812 append_interval(spilled_part);
|
|
|
1813 move_resolver.add_mapping(spilled_part, interval);
|
|
|
1814 }
|
|
|
1815 assign_spill_slot(spilled_part);
|
|
|
1816
|
|
|
1817 assert(spilled_part->from() == from_op_id && spilled_part->to() == to_op_id, "just checking");
|
|
|
1818 }
|
|
|
1819 }
|
|
|
1820
|
|
|
1821 void LinearScan::resolve_exception_entry(BlockBegin* block, MoveResolver &move_resolver) {
|
|
|
1822 assert(block->is_set(BlockBegin::exception_entry_flag), "should not call otherwise");
|
|
|
1823 DEBUG_ONLY(move_resolver.check_empty());
|
|
|
1824
|
|
|
1825 // visit all registers where the live_in bit is set
|
|
|
1826 int size = live_set_size();
|
|
|
1827 for (int r = block->live_in().get_next_one_offset(0, size); r < size; r = block->live_in().get_next_one_offset(r + 1, size)) {
|
|
|
1828 resolve_exception_entry(block, r, move_resolver);
|
|
|
1829 }
|
|
|
1830
|
|
|
1831 // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
|
|
|
1832 for_each_phi_fun(block, phi,
|
|
|
1833 resolve_exception_entry(block, phi->operand()->vreg_number(), move_resolver)
|
|
|
1834 );
|
|
|
1835
|
|
|
1836 if (move_resolver.has_mappings()) {
|
|
|
1837 // insert moves after first instruction
|
|
|
1838 move_resolver.set_insert_position(block->lir(), 1);
|
|
|
1839 move_resolver.resolve_and_append_moves();
|
|
|
1840 }
|
|
|
1841 }
|
|
|
1842
|
|
|
1843
|
|
|
1844 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver) {
|
|
|
1845 if (interval_at(reg_num) == NULL) {
|
|
|
1846 // if a phi function is never used, no interval is created -> ignore this
|
|
|
1847 return;
|
|
|
1848 }
|
|
|
1849
|
|
|
1850 // the computation of to_interval is equal to resolve_collect_mappings,
|
|
|
1851 // but from_interval is more complicated because of phi functions
|
|
|
1852 BlockBegin* to_block = handler->entry_block();
|
|
|
1853 Interval* to_interval = interval_at_block_begin(to_block, reg_num);
|
|
|
1854
|
|
|
1855 if (phi != NULL) {
|
|
|
1856 // phi function of the exception entry block
|
|
|
1857 // no moves are created for this phi function in the LIR_Generator, so the
|
|
|
1858 // interval at the throwing instruction must be searched using the operands
|
|
|
1859 // of the phi function
|
|
|
1860 Value from_value = phi->operand_at(handler->phi_operand());
|
|
|
1861
|
|
|
1862 // with phi functions it can happen that the same from_value is used in
|
|
|
1863 // multiple mappings, so notify move-resolver that this is allowed
|
|
|
1864 move_resolver.set_multiple_reads_allowed();
|
|
|
1865
|
|
|
1866 Constant* con = from_value->as_Constant();
|
|
|
1867 if (con != NULL && !con->is_pinned()) {
|
|
|
1868 // unpinned constants may have no register, so add mapping from constant to interval
|
|
|
1869 move_resolver.add_mapping(LIR_OprFact::value_type(con->type()), to_interval);
|
|
|
1870 } else {
|
|
|
1871 // search split child at the throwing op_id
|
|
|
1872 Interval* from_interval = interval_at_op_id(from_value->operand()->vreg_number(), throwing_op_id);
|
|
|
1873 move_resolver.add_mapping(from_interval, to_interval);
|
|
|
1874 }
|
|
|
1875
|
|
|
1876 } else {
|
|
|
1877 // no phi function, so use reg_num also for from_interval
|
|
|
1878 // search split child at the throwing op_id
|
|
|
1879 Interval* from_interval = interval_at_op_id(reg_num, throwing_op_id);
|
|
|
1880 if (from_interval != to_interval) {
|
|
|
1881 // optimization to reduce number of moves: when to_interval is on stack and
|
|
|
1882 // the stack slot is known to be always correct, then no move is necessary
|
|
|
1883 if (!from_interval->always_in_memory() || from_interval->canonical_spill_slot() != to_interval->assigned_reg()) {
|
|
|
1884 move_resolver.add_mapping(from_interval, to_interval);
|
|
|
1885 }
|
|
|
1886 }
|
|
|
1887 }
|
|
|
1888 }
|
|
|
1889
|
|
|
1890 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver) {
|
|
|
1891 TRACE_LINEAR_SCAN(4, tty->print_cr("resolving exception handler B%d: throwing_op_id=%d", handler->entry_block()->block_id(), throwing_op_id));
|
|
|
1892
|
|
|
1893 DEBUG_ONLY(move_resolver.check_empty());
|
|
|
1894 assert(handler->lir_op_id() == -1, "already processed this xhandler");
|
|
|
1895 DEBUG_ONLY(handler->set_lir_op_id(throwing_op_id));
|
|
|
1896 assert(handler->entry_code() == NULL, "code already present");
|
|
|
1897
|
|
|
1898 // visit all registers where the live_in bit is set
|
|
|
1899 BlockBegin* block = handler->entry_block();
|
|
|
1900 int size = live_set_size();
|
|
|
1901 for (int r = block->live_in().get_next_one_offset(0, size); r < size; r = block->live_in().get_next_one_offset(r + 1, size)) {
|
|
|
1902 resolve_exception_edge(handler, throwing_op_id, r, NULL, move_resolver);
|
|
|
1903 }
|
|
|
1904
|
|
|
1905 // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
|
|
|
1906 for_each_phi_fun(block, phi,
|
|
|
1907 resolve_exception_edge(handler, throwing_op_id, phi->operand()->vreg_number(), phi, move_resolver)
|
|
|
1908 );
|
|
|
1909
|
|
|
1910 if (move_resolver.has_mappings()) {
|
|
|
1911 LIR_List* entry_code = new LIR_List(compilation());
|
|
|
1912 move_resolver.set_insert_position(entry_code, 0);
|
|
|
1913 move_resolver.resolve_and_append_moves();
|
|
|
1914
|
|
|
1915 entry_code->jump(handler->entry_block());
|
|
|
1916 handler->set_entry_code(entry_code);
|
|
|
1917 }
|
|
|
1918 }
|
|
|
1919
|
|
|
1920
|
|
|
1921 void LinearScan::resolve_exception_handlers() {
|
|
|
1922 MoveResolver move_resolver(this);
|
|
|
1923 LIR_OpVisitState visitor;
|
|
|
1924 int num_blocks = block_count();
|
|
|
1925
|
|
|
1926 int i;
|
|
|
1927 for (i = 0; i < num_blocks; i++) {
|
|
|
1928 BlockBegin* block = block_at(i);
|
|
|
1929 if (block->is_set(BlockBegin::exception_entry_flag)) {
|
|
|
1930 resolve_exception_entry(block, move_resolver);
|
|
|
1931 }
|
|
|
1932 }
|
|
|
1933
|
|
|
1934 for (i = 0; i < num_blocks; i++) {
|
|
|
1935 BlockBegin* block = block_at(i);
|
|
|
1936 LIR_List* ops = block->lir();
|
|
|
1937 int num_ops = ops->length();
|
|
|
1938
|
|
|
1939 // iterate all instructions of the block. skip the first because it is always a label
|
|
|
1940 assert(visitor.no_operands(ops->at(0)), "first operation must always be a label");
|
|
|
1941 for (int j = 1; j < num_ops; j++) {
|
|
|
1942 LIR_Op* op = ops->at(j);
|
|
|
1943 int op_id = op->id();
|
|
|
1944
|
|
|
1945 if (op_id != -1 && has_info(op_id)) {
|
|
|
1946 // visit operation to collect all operands
|
|
|
1947 visitor.visit(op);
|
|
|
1948 assert(visitor.info_count() > 0, "should not visit otherwise");
|
|
|
1949
|
|
|
1950 XHandlers* xhandlers = visitor.all_xhandler();
|
|
|
1951 int n = xhandlers->length();
|
|
|
1952 for (int k = 0; k < n; k++) {
|
|
|
1953 resolve_exception_edge(xhandlers->handler_at(k), op_id, move_resolver);
|
|
|
1954 }
|
|
|
1955
|
|
|
1956 #ifdef ASSERT
|
|
|
1957 } else {
|
|
|
1958 visitor.visit(op);
|
|
|
1959 assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
|
|
|
1960 #endif
|
|
|
1961 }
|
|
|
1962 }
|
|
|
1963 }
|
|
|
1964 }
|
|
|
1965
|
|
|
1966
|
|
|
1967 // ********** Phase 7: assign register numbers back to LIR
|
|
|
1968 // (includes computation of debug information and oop maps)
|
|
|
1969
|
|
|
1970 VMReg LinearScan::vm_reg_for_interval(Interval* interval) {
|
|
|
1971 VMReg reg = interval->cached_vm_reg();
|
|
|
1972 if (!reg->is_valid() ) {
|
|
|
1973 reg = vm_reg_for_operand(operand_for_interval(interval));
|
|
|
1974 interval->set_cached_vm_reg(reg);
|
|
|
1975 }
|
|
|
1976 assert(reg == vm_reg_for_operand(operand_for_interval(interval)), "wrong cached value");
|
|
|
1977 return reg;
|
|
|
1978 }
|
|
|
1979
|
|
|
1980 VMReg LinearScan::vm_reg_for_operand(LIR_Opr opr) {
|
|
|
1981 assert(opr->is_oop(), "currently only implemented for oop operands");
|
|
|
1982 return frame_map()->regname(opr);
|
|
|
1983 }
|
|
|
1984
|
|
|
1985
|
|
|
1986 LIR_Opr LinearScan::operand_for_interval(Interval* interval) {
|
|
|
1987 LIR_Opr opr = interval->cached_opr();
|
|
|
1988 if (opr->is_illegal()) {
|
|
|
1989 opr = calc_operand_for_interval(interval);
|
|
|
1990 interval->set_cached_opr(opr);
|
|
|
1991 }
|
|
|
1992
|
|
|
1993 assert(opr == calc_operand_for_interval(interval), "wrong cached value");
|
|
|
1994 return opr;
|
|
|
1995 }
|
|
|
1996
|
|
|
1997 LIR_Opr LinearScan::calc_operand_for_interval(const Interval* interval) {
|
|
|
1998 int assigned_reg = interval->assigned_reg();
|
|
|
1999 BasicType type = interval->type();
|
|
|
2000
|
|
|
2001 if (assigned_reg >= nof_regs) {
|
|
|
2002 // stack slot
|
|
|
2003 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
|
|
|
2004 return LIR_OprFact::stack(assigned_reg - nof_regs, type);
|
|
|
2005
|
|
|
2006 } else {
|
|
|
2007 // register
|
|
|
2008 switch (type) {
|
|
|
2009 case T_OBJECT: {
|
|
|
2010 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
|
|
|
2011 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
|
|
|
2012 return LIR_OprFact::single_cpu_oop(assigned_reg);
|
|
|
2013 }
|
|
|
2014
|
|
|
2015 case T_INT: {
|
|
|
2016 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
|
|
|
2017 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
|
|
|
2018 return LIR_OprFact::single_cpu(assigned_reg);
|
|
|
2019 }
|
|
|
2020
|
|
|
2021 case T_LONG: {
|
|
|
2022 int assigned_regHi = interval->assigned_regHi();
|
|
|
2023 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
|
|
|
2024 assert(num_physical_regs(T_LONG) == 1 ||
|
|
|
2025 (assigned_regHi >= pd_first_cpu_reg && assigned_regHi <= pd_last_cpu_reg), "no cpu register");
|
|
|
2026
|
|
|
2027 assert(assigned_reg != assigned_regHi, "invalid allocation");
|
|
|
2028 assert(num_physical_regs(T_LONG) == 1 || assigned_reg < assigned_regHi,
|
|
|
2029 "register numbers must be sorted (ensure that e.g. a move from eax,ebx to ebx,eax can not occur)");
|
|
|
2030 assert((assigned_regHi != any_reg) ^ (num_physical_regs(T_LONG) == 1), "must be match");
|
|
|
2031 if (requires_adjacent_regs(T_LONG)) {
|
|
|
2032 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even");
|
|
|
2033 }
|
|
|
2034
|
|
|
2035 #ifdef SPARC
|
|
|
2036 #ifdef _LP64
|
|
|
2037 return LIR_OprFact::double_cpu(assigned_reg, assigned_reg);
|
|
|
2038 #else
|
|
|
2039 return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg);
|
|
|
2040 #endif
|
|
|
2041 #else
|
|
|
2042 return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi);
|
|
|
2043 #endif
|
|
|
2044 }
|
|
|
2045
|
|
|
2046 case T_FLOAT: {
|
|
|
2047 #ifdef IA32
|
|
|
2048 if (UseSSE >= 1) {
|
|
|
2049 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register");
|
|
|
2050 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
|
|
|
2051 return LIR_OprFact::single_xmm(assigned_reg - pd_first_xmm_reg);
|
|
|
2052 }
|
|
|
2053 #endif
|
|
|
2054
|
|
|
2055 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
|
|
|
2056 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
|
|
|
2057 return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg);
|
|
|
2058 }
|
|
|
2059
|
|
|
2060 case T_DOUBLE: {
|
|
|
2061 #ifdef IA32
|
|
|
2062 if (UseSSE >= 2) {
|
|
|
2063 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register");
|
|
|
2064 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
|
|
|
2065 return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg);
|
|
|
2066 }
|
|
|
2067 #endif
|
|
|
2068
|
|
|
2069 #ifdef SPARC
|
|
|
2070 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
|
|
|
2071 assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
|
|
|
2072 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
|
|
|
2073 LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg);
|
|
|
2074 #else
|
|
|
2075 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
|
|
|
2076 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)");
|
|
|
2077 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg);
|
|
|
2078 #endif
|
|
|
2079 return result;
|
|
|
2080 }
|
|
|
2081
|
|
|
2082 default: {
|
|
|
2083 ShouldNotReachHere();
|
|
|
2084 return LIR_OprFact::illegalOpr;
|
|
|
2085 }
|
|
|
2086 }
|
|
|
2087 }
|
|
|
2088 }
|
|
|
2089
|
|
|
2090 LIR_Opr LinearScan::canonical_spill_opr(Interval* interval) {
|
|
|
2091 assert(interval->canonical_spill_slot() >= nof_regs, "canonical spill slot not set");
|
|
|
2092 return LIR_OprFact::stack(interval->canonical_spill_slot() - nof_regs, interval->type());
|
|
|
2093 }
|
|
|
2094
|
|
|
2095 LIR_Opr LinearScan::color_lir_opr(LIR_Opr opr, int op_id, LIR_OpVisitState::OprMode mode) {
|
|
|
2096 assert(opr->is_virtual(), "should not call this otherwise");
|
|
|
2097
|
|
|
2098 Interval* interval = interval_at(opr->vreg_number());
|
|
|
2099 assert(interval != NULL, "interval must exist");
|
|
|
2100
|
|
|
2101 if (op_id != -1) {
|
|
|
2102 #ifdef ASSERT
|
|
|
2103 BlockBegin* block = block_of_op_with_id(op_id);
|
|
|
2104 if (block->number_of_sux() <= 1 && op_id == block->last_lir_instruction_id()) {
|
|
|
2105 // check if spill moves could have been appended at the end of this block, but
|
|
|
2106 // before the branch instruction. So the split child information for this branch would
|
|
|
2107 // be incorrect.
|
|
|
2108 LIR_OpBranch* branch = block->lir()->instructions_list()->last()->as_OpBranch();
|
|
|
2109 if (branch != NULL) {
|
|
|
2110 if (block->live_out().at(opr->vreg_number())) {
|
|
|
2111 assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
|
|
|
2112 assert(false, "can't get split child for the last branch of a block because the information would be incorrect (moves are inserted before the branch in resolve_data_flow)");
|
|
|
2113 }
|
|
|
2114 }
|
|
|
2115 }
|
|
|
2116 #endif
|
|
|
2117
|
|
|
2118 // operands are not changed when an interval is split during allocation,
|
|
|
2119 // so search the right interval here
|
|
|
2120 interval = split_child_at_op_id(interval, op_id, mode);
|
|
|
2121 }
|
|
|
2122
|
|
|
2123 LIR_Opr res = operand_for_interval(interval);
|
|
|
2124
|
|
|
2125 #ifdef IA32
|
|
|
2126 // new semantic for is_last_use: not only set on definite end of interval,
|
|
|
2127 // but also before hole
|
|
|
2128 // This may still miss some cases (e.g. for dead values), but it is not necessary that the
|
|
|
2129 // last use information is completely correct
|
|
|
2130 // information is only needed for fpu stack allocation
|
|
|
2131 if (res->is_fpu_register()) {
|
|
|
2132 if (opr->is_last_use() || op_id == interval->to() || (op_id != -1 && interval->has_hole_between(op_id, op_id + 1))) {
|
|
|
2133 assert(op_id == -1 || !is_block_begin(op_id), "holes at begin of block may also result from control flow");
|
|
|
2134 res = res->make_last_use();
|
|
|
2135 }
|
|
|
2136 }
|
|
|
2137 #endif
|
|
|
2138
|
|
|
2139 assert(!gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::callee_saved) || !FrameMap::is_caller_save_register(res), "bad allocation");
|
|
|
2140
|
|
|
2141 return res;
|
|
|
2142 }
|
|
|
2143
|
|
|
2144
|
|
|
2145 #ifdef ASSERT
|
|
|
2146 // some methods used to check correctness of debug information
|
|
|
2147
|
|
|
2148 void assert_no_register_values(GrowableArray<ScopeValue*>* values) {
|
|
|
2149 if (values == NULL) {
|
|
|
2150 return;
|
|
|
2151 }
|
|
|
2152
|
|
|
2153 for (int i = 0; i < values->length(); i++) {
|
|
|
2154 ScopeValue* value = values->at(i);
|
|
|
2155
|
|
|
2156 if (value->is_location()) {
|
|
|
2157 Location location = ((LocationValue*)value)->location();
|
|
|
2158 assert(location.where() == Location::on_stack, "value is in register");
|
|
|
2159 }
|
|
|
2160 }
|
|
|
2161 }
|
|
|
2162
|
|
|
2163 void assert_no_register_values(GrowableArray<MonitorValue*>* values) {
|
|
|
2164 if (values == NULL) {
|
|
|
2165 return;
|
|
|
2166 }
|
|
|
2167
|
|
|
2168 for (int i = 0; i < values->length(); i++) {
|
|
|
2169 MonitorValue* value = values->at(i);
|
|
|
2170
|
|
|
2171 if (value->owner()->is_location()) {
|
|
|
2172 Location location = ((LocationValue*)value->owner())->location();
|
|
|
2173 assert(location.where() == Location::on_stack, "owner is in register");
|
|
|
2174 }
|
|
|
2175 assert(value->basic_lock().where() == Location::on_stack, "basic_lock is in register");
|
|
|
2176 }
|
|
|
2177 }
|
|
|
2178
|
|
|
2179 void assert_equal(Location l1, Location l2) {
|
|
|
2180 assert(l1.where() == l2.where() && l1.type() == l2.type() && l1.offset() == l2.offset(), "");
|
|
|
2181 }
|
|
|
2182
|
|
|
2183 void assert_equal(ScopeValue* v1, ScopeValue* v2) {
|
|
|
2184 if (v1->is_location()) {
|
|
|
2185 assert(v2->is_location(), "");
|
|
|
2186 assert_equal(((LocationValue*)v1)->location(), ((LocationValue*)v2)->location());
|
|
|
2187 } else if (v1->is_constant_int()) {
|
|
|
2188 assert(v2->is_constant_int(), "");
|
|
|
2189 assert(((ConstantIntValue*)v1)->value() == ((ConstantIntValue*)v2)->value(), "");
|
|
|
2190 } else if (v1->is_constant_double()) {
|
|
|
2191 assert(v2->is_constant_double(), "");
|
|
|
2192 assert(((ConstantDoubleValue*)v1)->value() == ((ConstantDoubleValue*)v2)->value(), "");
|
|
|
2193 } else if (v1->is_constant_long()) {
|
|
|
2194 assert(v2->is_constant_long(), "");
|
|
|
2195 assert(((ConstantLongValue*)v1)->value() == ((ConstantLongValue*)v2)->value(), "");
|
|
|
2196 } else if (v1->is_constant_oop()) {
|
|
|
2197 assert(v2->is_constant_oop(), "");
|
|
|
2198 assert(((ConstantOopWriteValue*)v1)->value() == ((ConstantOopWriteValue*)v2)->value(), "");
|
|
|
2199 } else {
|
|
|
2200 ShouldNotReachHere();
|
|
|
2201 }
|
|
|
2202 }
|
|
|
2203
|
|
|
2204 void assert_equal(MonitorValue* m1, MonitorValue* m2) {
|
|
|
2205 assert_equal(m1->owner(), m2->owner());
|
|
|
2206 assert_equal(m1->basic_lock(), m2->basic_lock());
|
|
|
2207 }
|
|
|
2208
|
|
|
2209 void assert_equal(IRScopeDebugInfo* d1, IRScopeDebugInfo* d2) {
|
|
|
2210 assert(d1->scope() == d2->scope(), "not equal");
|
|
|
2211 assert(d1->bci() == d2->bci(), "not equal");
|
|
|
2212
|
|
|
2213 if (d1->locals() != NULL) {
|
|
|
2214 assert(d1->locals() != NULL && d2->locals() != NULL, "not equal");
|
|
|
2215 assert(d1->locals()->length() == d2->locals()->length(), "not equal");
|
|
|
2216 for (int i = 0; i < d1->locals()->length(); i++) {
|
|
|
2217 assert_equal(d1->locals()->at(i), d2->locals()->at(i));
|
|
|
2218 }
|
|
|
2219 } else {
|
|
|
2220 assert(d1->locals() == NULL && d2->locals() == NULL, "not equal");
|
|
|
2221 }
|
|
|
2222
|
|
|
2223 if (d1->expressions() != NULL) {
|
|
|
2224 assert(d1->expressions() != NULL && d2->expressions() != NULL, "not equal");
|
|
|
2225 assert(d1->expressions()->length() == d2->expressions()->length(), "not equal");
|
|
|
2226 for (int i = 0; i < d1->expressions()->length(); i++) {
|
|
|
2227 assert_equal(d1->expressions()->at(i), d2->expressions()->at(i));
|
|
|
2228 }
|
|
|
2229 } else {
|
|
|
2230 assert(d1->expressions() == NULL && d2->expressions() == NULL, "not equal");
|
|
|
2231 }
|
|
|
2232
|
|
|
2233 if (d1->monitors() != NULL) {
|
|
|
2234 assert(d1->monitors() != NULL && d2->monitors() != NULL, "not equal");
|
|
|
2235 assert(d1->monitors()->length() == d2->monitors()->length(), "not equal");
|
|
|
2236 for (int i = 0; i < d1->monitors()->length(); i++) {
|
|
|
2237 assert_equal(d1->monitors()->at(i), d2->monitors()->at(i));
|
|
|
2238 }
|
|
|
2239 } else {
|
|
|
2240 assert(d1->monitors() == NULL && d2->monitors() == NULL, "not equal");
|
|
|
2241 }
|
|
|
2242
|
|
|
2243 if (d1->caller() != NULL) {
|
|
|
2244 assert(d1->caller() != NULL && d2->caller() != NULL, "not equal");
|
|
|
2245 assert_equal(d1->caller(), d2->caller());
|
|
|
2246 } else {
|
|
|
2247 assert(d1->caller() == NULL && d2->caller() == NULL, "not equal");
|
|
|
2248 }
|
|
|
2249 }
|
|
|
2250
|
|
|
2251 void check_stack_depth(CodeEmitInfo* info, int stack_end) {
|
|
|
2252 if (info->bci() != SynchronizationEntryBCI && !info->scope()->method()->is_native()) {
|
|
|
2253 Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->bci());
|
|
|
2254 switch (code) {
|
|
|
2255 case Bytecodes::_ifnull : // fall through
|
|
|
2256 case Bytecodes::_ifnonnull : // fall through
|
|
|
2257 case Bytecodes::_ifeq : // fall through
|
|
|
2258 case Bytecodes::_ifne : // fall through
|
|
|
2259 case Bytecodes::_iflt : // fall through
|
|
|
2260 case Bytecodes::_ifge : // fall through
|
|
|
2261 case Bytecodes::_ifgt : // fall through
|
|
|
2262 case Bytecodes::_ifle : // fall through
|
|
|
2263 case Bytecodes::_if_icmpeq : // fall through
|
|
|
2264 case Bytecodes::_if_icmpne : // fall through
|
|
|
2265 case Bytecodes::_if_icmplt : // fall through
|
|
|
2266 case Bytecodes::_if_icmpge : // fall through
|
|
|
2267 case Bytecodes::_if_icmpgt : // fall through
|
|
|
2268 case Bytecodes::_if_icmple : // fall through
|
|
|
2269 case Bytecodes::_if_acmpeq : // fall through
|
|
|
2270 case Bytecodes::_if_acmpne :
|
|
|
2271 assert(stack_end >= -Bytecodes::depth(code), "must have non-empty expression stack at if bytecode");
|
|
|
2272 break;
|
|
|
2273 }
|
|
|
2274 }
|
|
|
2275 }
|
|
|
2276
|
|
|
2277 #endif // ASSERT
|
|
|
2278
|
|
|
2279
|
|
|
2280 IntervalWalker* LinearScan::init_compute_oop_maps() {
|
|
|
2281 // setup lists of potential oops for walking
|
|
|
2282 Interval* oop_intervals;
|
|
|
2283 Interval* non_oop_intervals;
|
|
|
2284
|
|
|
2285 create_unhandled_lists(&oop_intervals, &non_oop_intervals, is_oop_interval, NULL);
|
|
|
2286
|
|
|
2287 // intervals that have no oops inside need not to be processed
|
|
|
2288 // to ensure a walking until the last instruction id, add a dummy interval
|
|
|
2289 // with a high operation id
|
|
|
2290 non_oop_intervals = new Interval(any_reg);
|
|
|
2291 non_oop_intervals->add_range(max_jint - 2, max_jint - 1);
|
|
|
2292
|
|
|
2293 return new IntervalWalker(this, oop_intervals, non_oop_intervals);
|
|
|
2294 }
|
|
|
2295
|
|
|
2296
|
|
|
2297 OopMap* LinearScan::compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site) {
|
|
|
2298 TRACE_LINEAR_SCAN(3, tty->print_cr("creating oop map at op_id %d", op->id()));
|
|
|
2299
|
|
|
2300 // walk before the current operation -> intervals that start at
|
|
|
2301 // the operation (= output operands of the operation) are not
|
|
|
2302 // included in the oop map
|
|
|
2303 iw->walk_before(op->id());
|
|
|
2304
|
|
|
2305 int frame_size = frame_map()->framesize();
|
|
|
2306 int arg_count = frame_map()->oop_map_arg_count();
|
|
|
2307 OopMap* map = new OopMap(frame_size, arg_count);
|
|
|
2308
|
|
|
2309 // Check if this is a patch site.
|
|
|
2310 bool is_patch_info = false;
|
|
|
2311 if (op->code() == lir_move) {
|
|
|
2312 assert(!is_call_site, "move must not be a call site");
|
|
|
2313 assert(op->as_Op1() != NULL, "move must be LIR_Op1");
|
|
|
2314 LIR_Op1* move = (LIR_Op1*)op;
|
|
|
2315
|
|
|
2316 is_patch_info = move->patch_code() != lir_patch_none;
|
|
|
2317 }
|
|
|
2318
|
|
|
2319 // Iterate through active intervals
|
|
|
2320 for (Interval* interval = iw->active_first(fixedKind); interval != Interval::end(); interval = interval->next()) {
|
|
|
2321 int assigned_reg = interval->assigned_reg();
|
|
|
2322
|
|
|
2323 assert(interval->current_from() <= op->id() && op->id() <= interval->current_to(), "interval should not be active otherwise");
|
|
|
2324 assert(interval->assigned_regHi() == any_reg, "oop must be single word");
|
|
|
2325 assert(interval->reg_num() >= LIR_OprDesc::vreg_base, "fixed interval found");
|
|
|
2326
|
|
|
2327 // Check if this range covers the instruction. Intervals that
|
|
|
2328 // start or end at the current operation are not included in the
|
|
|
2329 // oop map, except in the case of patching moves. For patching
|
|
|
2330 // moves, any intervals which end at this instruction are included
|
|
|
2331 // in the oop map since we may safepoint while doing the patch
|
|
|
2332 // before we've consumed the inputs.
|
|
|
2333 if (is_patch_info || op->id() < interval->current_to()) {
|
|
|
2334
|
|
|
2335 // caller-save registers must not be included into oop-maps at calls
|
|
|
2336 assert(!is_call_site || assigned_reg >= nof_regs || !is_caller_save(assigned_reg), "interval is in a caller-save register at a call -> register will be overwritten");
|
|
|
2337
|
|
|
2338 VMReg name = vm_reg_for_interval(interval);
|
|
|
2339 map->set_oop(name);
|
|
|
2340
|
|
|
2341 // Spill optimization: when the stack value is guaranteed to be always correct,
|
|
|
2342 // then it must be added to the oop map even if the interval is currently in a register
|
|
|
2343 if (interval->always_in_memory() &&
|
|
|
2344 op->id() > interval->spill_definition_pos() &&
|
|
|
2345 interval->assigned_reg() != interval->canonical_spill_slot()) {
|
|
|
2346 assert(interval->spill_definition_pos() > 0, "position not set correctly");
|
|
|
2347 assert(interval->canonical_spill_slot() >= LinearScan::nof_regs, "no spill slot assigned");
|
|
|
2348 assert(interval->assigned_reg() < LinearScan::nof_regs, "interval is on stack, so stack slot is registered twice");
|
|
|
2349
|
|
|
2350 map->set_oop(frame_map()->slot_regname(interval->canonical_spill_slot() - LinearScan::nof_regs));
|
|
|
2351 }
|
|
|
2352 }
|
|
|
2353 }
|
|
|
2354
|
|
|
2355 // add oops from lock stack
|
|
|
2356 assert(info->stack() != NULL, "CodeEmitInfo must always have a stack");
|
|
|
2357 int locks_count = info->stack()->locks_size();
|
|
|
2358 for (int i = 0; i < locks_count; i++) {
|
|
|
2359 map->set_oop(frame_map()->monitor_object_regname(i));
|
|
|
2360 }
|
|
|
2361
|
|
|
2362 return map;
|
|
|
2363 }
|
|
|
2364
|
|
|
2365
|
|
|
2366 void LinearScan::compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op) {
|
|
|
2367 assert(visitor.info_count() > 0, "no oop map needed");
|
|
|
2368
|
|
|
2369 // compute oop_map only for first CodeEmitInfo
|
|
|
2370 // because it is (in most cases) equal for all other infos of the same operation
|
|
|
2371 CodeEmitInfo* first_info = visitor.info_at(0);
|
|
|
2372 OopMap* first_oop_map = compute_oop_map(iw, op, first_info, visitor.has_call());
|
|
|
2373
|
|
|
2374 for (int i = 0; i < visitor.info_count(); i++) {
|
|
|
2375 CodeEmitInfo* info = visitor.info_at(i);
|
|
|
2376 OopMap* oop_map = first_oop_map;
|
|
|
2377
|
|
|
2378 if (info->stack()->locks_size() != first_info->stack()->locks_size()) {
|
|
|
2379 // this info has a different number of locks then the precomputed oop map
|
|
|
2380 // (possible for lock and unlock instructions) -> compute oop map with
|
|
|
2381 // correct lock information
|
|
|
2382 oop_map = compute_oop_map(iw, op, info, visitor.has_call());
|
|
|
2383 }
|
|
|
2384
|
|
|
2385 if (info->_oop_map == NULL) {
|
|
|
2386 info->_oop_map = oop_map;
|
|
|
2387 } else {
|
|
|
2388 // a CodeEmitInfo can not be shared between different LIR-instructions
|
|
|
2389 // because interval splitting can occur anywhere between two instructions
|
|
|
2390 // and so the oop maps must be different
|
|
|
2391 // -> check if the already set oop_map is exactly the one calculated for this operation
|
|
|
2392 assert(info->_oop_map == oop_map, "same CodeEmitInfo used for multiple LIR instructions");
|
|
|
2393 }
|
|
|
2394 }
|
|
|
2395 }
|
|
|
2396
|
|
|
2397
|
|
|
2398 // frequently used constants
|
|
|
2399 ConstantOopWriteValue LinearScan::_oop_null_scope_value = ConstantOopWriteValue(NULL);
|
|
|
2400 ConstantIntValue LinearScan::_int_m1_scope_value = ConstantIntValue(-1);
|
|
|
2401 ConstantIntValue LinearScan::_int_0_scope_value = ConstantIntValue(0);
|
|
|
2402 ConstantIntValue LinearScan::_int_1_scope_value = ConstantIntValue(1);
|
|
|
2403 ConstantIntValue LinearScan::_int_2_scope_value = ConstantIntValue(2);
|
|
|
2404 LocationValue _illegal_value = LocationValue(Location());
|
|
|
2405
|
|
|
2406 void LinearScan::init_compute_debug_info() {
|
|
|
2407 // cache for frequently used scope values
|
|
|
2408 // (cpu registers and stack slots)
|
|
|
2409 _scope_value_cache = ScopeValueArray((LinearScan::nof_cpu_regs + frame_map()->argcount() + max_spills()) * 2, NULL);
|
|
|
2410 }
|
|
|
2411
|
|
|
2412 MonitorValue* LinearScan::location_for_monitor_index(int monitor_index) {
|
|
|
2413 Location loc;
|
|
|
2414 if (!frame_map()->location_for_monitor_object(monitor_index, &loc)) {
|
|
|
2415 bailout("too large frame");
|
|
|
2416 }
|
|
|
2417 ScopeValue* object_scope_value = new LocationValue(loc);
|
|
|
2418
|
|
|
2419 if (!frame_map()->location_for_monitor_lock(monitor_index, &loc)) {
|
|
|
2420 bailout("too large frame");
|
|
|
2421 }
|
|
|
2422 return new MonitorValue(object_scope_value, loc);
|
|
|
2423 }
|
|
|
2424
|
|
|
2425 LocationValue* LinearScan::location_for_name(int name, Location::Type loc_type) {
|
|
|
2426 Location loc;
|
|
|
2427 if (!frame_map()->locations_for_slot(name, loc_type, &loc)) {
|
|
|
2428 bailout("too large frame");
|
|
|
2429 }
|
|
|
2430 return new LocationValue(loc);
|
|
|
2431 }
|
|
|
2432
|
|
|
2433
|
|
|
2434 int LinearScan::append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
|
|
|
2435 assert(opr->is_constant(), "should not be called otherwise");
|
|
|
2436
|
|
|
2437 LIR_Const* c = opr->as_constant_ptr();
|
|
|
2438 BasicType t = c->type();
|
|
|
2439 switch (t) {
|
|
|
2440 case T_OBJECT: {
|
|
|
2441 jobject value = c->as_jobject();
|
|
|
2442 if (value == NULL) {
|
|
|
2443 scope_values->append(&_oop_null_scope_value);
|
|
|
2444 } else {
|
|
|
2445 scope_values->append(new ConstantOopWriteValue(c->as_jobject()));
|
|
|
2446 }
|
|
|
2447 return 1;
|
|
|
2448 }
|
|
|
2449
|
|
|
2450 case T_INT: // fall through
|
|
|
2451 case T_FLOAT: {
|
|
|
2452 int value = c->as_jint_bits();
|
|
|
2453 switch (value) {
|
|
|
2454 case -1: scope_values->append(&_int_m1_scope_value); break;
|
|
|
2455 case 0: scope_values->append(&_int_0_scope_value); break;
|
|
|
2456 case 1: scope_values->append(&_int_1_scope_value); break;
|
|
|
2457 case 2: scope_values->append(&_int_2_scope_value); break;
|
|
|
2458 default: scope_values->append(new ConstantIntValue(c->as_jint_bits())); break;
|
|
|
2459 }
|
|
|
2460 return 1;
|
|
|
2461 }
|
|
|
2462
|
|
|
2463 case T_LONG: // fall through
|
|
|
2464 case T_DOUBLE: {
|
|
|
2465 if (hi_word_offset_in_bytes > lo_word_offset_in_bytes) {
|
|
|
2466 scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
|
|
|
2467 scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
|
|
|
2468 } else {
|
|
|
2469 scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
|
|
|
2470 scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
|
|
|
2471 }
|
|
|
2472
|
|
|
2473 return 2;
|
|
|
2474 }
|
|
|
2475
|
|
|
2476 default:
|
|
|
2477 ShouldNotReachHere();
|
|
|
2478 }
|
|
|
2479 }
|
|
|
2480
|
|
|
2481 int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
|
|
|
2482 if (opr->is_single_stack()) {
|
|
|
2483 int stack_idx = opr->single_stack_ix();
|
|
|
2484 bool is_oop = opr->is_oop_register();
|
|
|
2485 int cache_idx = (stack_idx + LinearScan::nof_cpu_regs) * 2 + (is_oop ? 1 : 0);
|
|
|
2486
|
|
|
2487 ScopeValue* sv = _scope_value_cache.at(cache_idx);
|
|
|
2488 if (sv == NULL) {
|
|
|
2489 Location::Type loc_type = is_oop ? Location::oop : Location::normal;
|
|
|
2490 sv = location_for_name(stack_idx, loc_type);
|
|
|
2491 _scope_value_cache.at_put(cache_idx, sv);
|
|
|
2492 }
|
|
|
2493
|
|
|
2494 // check if cached value is correct
|
|
|
2495 DEBUG_ONLY(assert_equal(sv, location_for_name(stack_idx, is_oop ? Location::oop : Location::normal)));
|
|
|
2496
|
|
|
2497 scope_values->append(sv);
|
|
|
2498 return 1;
|
|
|
2499
|
|
|
2500 } else if (opr->is_single_cpu()) {
|
|
|
2501 bool is_oop = opr->is_oop_register();
|
|
|
2502 int cache_idx = opr->cpu_regnr() * 2 + (is_oop ? 1 : 0);
|
|
|
2503
|
|
|
2504 ScopeValue* sv = _scope_value_cache.at(cache_idx);
|
|
|
2505 if (sv == NULL) {
|
|
|
2506 Location::Type loc_type = is_oop ? Location::oop : Location::normal;
|
|
|
2507 VMReg rname = frame_map()->regname(opr);
|
|
|
2508 sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
|
|
|
2509 _scope_value_cache.at_put(cache_idx, sv);
|
|
|
2510 }
|
|
|
2511
|
|
|
2512 // check if cached value is correct
|
|
|
2513 DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : Location::normal, frame_map()->regname(opr)))));
|
|
|
2514
|
|
|
2515 scope_values->append(sv);
|
|
|
2516 return 1;
|
|
|
2517
|
|
|
2518 #ifdef IA32
|
|
|
2519 } else if (opr->is_single_xmm()) {
|
|
|
2520 VMReg rname = opr->as_xmm_float_reg()->as_VMReg();
|
|
|
2521 LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname));
|
|
|
2522
|
|
|
2523 scope_values->append(sv);
|
|
|
2524 return 1;
|
|
|
2525 #endif
|
|
|
2526
|
|
|
2527 } else if (opr->is_single_fpu()) {
|
|
|
2528 #ifdef IA32
|
|
|
2529 // the exact location of fpu stack values is only known
|
|
|
2530 // during fpu stack allocation, so the stack allocator object
|
|
|
2531 // must be present
|
|
|
2532 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
|
|
|
2533 assert(_fpu_stack_allocator != NULL, "must be present");
|
|
|
2534 opr = _fpu_stack_allocator->to_fpu_stack(opr);
|
|
|
2535 #endif
|
|
|
2536
|
|
|
2537 Location::Type loc_type = float_saved_as_double ? Location::float_in_dbl : Location::normal;
|
|
|
2538 VMReg rname = frame_map()->fpu_regname(opr->fpu_regnr());
|
|
|
2539 LocationValue* sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
|
|
|
2540
|
|
|
2541 scope_values->append(sv);
|
|
|
2542 return 1;
|
|
|
2543
|
|
|
2544 } else {
|
|
|
2545 // double-size operands
|
|
|
2546
|
|
|
2547 ScopeValue* first;
|
|
|
2548 ScopeValue* second;
|
|
|
2549
|
|
|
2550 if (opr->is_double_stack()) {
|
|
|
2551 Location loc1, loc2;
|
|
|
2552 if (!frame_map()->locations_for_slot(opr->double_stack_ix(), Location::normal, &loc1, &loc2)) {
|
|
|
2553 bailout("too large frame");
|
|
|
2554 }
|
|
|
2555 first = new LocationValue(loc1);
|
|
|
2556 second = new LocationValue(loc2);
|
|
|
2557
|
|
|
2558 } else if (opr->is_double_cpu()) {
|
|
|
2559 #ifdef _LP64
|
|
|
2560 VMReg rname_first = opr->as_register_lo()->as_VMReg();
|
|
|
2561 first = new LocationValue(Location::new_reg_loc(Location::lng, rname_first));
|
|
|
2562 second = &_int_0_scope_value;
|
|
|
2563 #else
|
|
|
2564 VMReg rname_first = opr->as_register_lo()->as_VMReg();
|
|
|
2565 VMReg rname_second = opr->as_register_hi()->as_VMReg();
|
|
|
2566
|
|
|
2567 if (hi_word_offset_in_bytes < lo_word_offset_in_bytes) {
|
|
|
2568 // lo/hi and swapped relative to first and second, so swap them
|
|
|
2569 VMReg tmp = rname_first;
|
|
|
2570 rname_first = rname_second;
|
|
|
2571 rname_second = tmp;
|
|
|
2572 }
|
|
|
2573
|
|
|
2574 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
|
|
|
2575 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
|
|
|
2576 #endif
|
|
|
2577
|
|
|
2578 #ifdef IA32
|
|
|
2579 } else if (opr->is_double_xmm()) {
|
|
|
2580 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation");
|
|
|
2581 VMReg rname_first = opr->as_xmm_double_reg()->as_VMReg();
|
|
|
2582 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
|
|
|
2583 // %%% This is probably a waste but we'll keep things as they were for now
|
|
|
2584 if (true) {
|
|
|
2585 VMReg rname_second = rname_first->next();
|
|
|
2586 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
|
|
|
2587 }
|
|
|
2588 #endif
|
|
|
2589
|
|
|
2590 } else if (opr->is_double_fpu()) {
|
|
|
2591 // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
|
|
|
2592 // the double as float registers in the native ordering. On IA32,
|
|
|
2593 // fpu_regnrLo is a FPU stack slot whose VMReg represents
|
|
|
2594 // the low-order word of the double and fpu_regnrLo + 1 is the
|
|
|
2595 // name for the other half. *first and *second must represent the
|
|
|
2596 // least and most significant words, respectively.
|
|
|
2597
|
|
|
2598 #ifdef IA32
|
|
|
2599 // the exact location of fpu stack values is only known
|
|
|
2600 // during fpu stack allocation, so the stack allocator object
|
|
|
2601 // must be present
|
|
|
2602 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
|
|
|
2603 assert(_fpu_stack_allocator != NULL, "must be present");
|
|
|
2604 opr = _fpu_stack_allocator->to_fpu_stack(opr);
|
|
|
2605
|
|
|
2606 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
|
|
|
2607 #endif
|
|
|
2608 #ifdef SPARC
|
|
|
2609 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)");
|
|
|
2610 #endif
|
|
|
2611
|
|
|
2612 VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi());
|
|
|
2613
|
|
|
2614 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
|
|
|
2615 // %%% This is probably a waste but we'll keep things as they were for now
|
|
|
2616 if (true) {
|
|
|
2617 VMReg rname_second = rname_first->next();
|
|
|
2618 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
|
|
|
2619 }
|
|
|
2620
|
|
|
2621 } else {
|
|
|
2622 ShouldNotReachHere();
|
|
|
2623 first = NULL;
|
|
|
2624 second = NULL;
|
|
|
2625 }
|
|
|
2626
|
|
|
2627 assert(first != NULL && second != NULL, "must be set");
|
|
|
2628 // The convention the interpreter uses is that the second local
|
|
|
2629 // holds the first raw word of the native double representation.
|
|
|
2630 // This is actually reasonable, since locals and stack arrays
|
|
|
2631 // grow downwards in all implementations.
|
|
|
2632 // (If, on some machine, the interpreter's Java locals or stack
|
|
|
2633 // were to grow upwards, the embedded doubles would be word-swapped.)
|
|
|
2634 scope_values->append(second);
|
|
|
2635 scope_values->append(first);
|
|
|
2636 return 2;
|
|
|
2637 }
|
|
|
2638 }
|
|
|
2639
|
|
|
2640
|
|
|
2641 int LinearScan::append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values) {
|
|
|
2642 if (value != NULL) {
|
|
|
2643 LIR_Opr opr = value->operand();
|
|
|
2644 Constant* con = value->as_Constant();
|
|
|
2645
|
|
|
2646 assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands (or illegal if constant is optimized away)");
|
|
|
2647 assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
|
|
|
2648
|
|
|
2649 if (con != NULL && !con->is_pinned() && !opr->is_constant()) {
|
|
|
2650 // Unpinned constants may have a virtual operand for a part of the lifetime
|
|
|
2651 // or may be illegal when it was optimized away,
|
|
|
2652 // so always use a constant operand
|
|
|
2653 opr = LIR_OprFact::value_type(con->type());
|
|
|
2654 }
|
|
|
2655 assert(opr->is_virtual() || opr->is_constant(), "other cases not allowed here");
|
|
|
2656
|
|
|
2657 if (opr->is_virtual()) {
|
|
|
2658 LIR_OpVisitState::OprMode mode = LIR_OpVisitState::inputMode;
|
|
|
2659
|
|
|
2660 BlockBegin* block = block_of_op_with_id(op_id);
|
|
|
2661 if (block->number_of_sux() == 1 && op_id == block->last_lir_instruction_id()) {
|
|
|
2662 // generating debug information for the last instruction of a block.
|
|
|
2663 // if this instruction is a branch, spill moves are inserted before this branch
|
|
|
2664 // and so the wrong operand would be returned (spill moves at block boundaries are not
|
|
|
2665 // considered in the live ranges of intervals)
|
|
|
2666 // Solution: use the first op_id of the branch target block instead.
|
|
|
2667 if (block->lir()->instructions_list()->last()->as_OpBranch() != NULL) {
|
|
|
2668 if (block->live_out().at(opr->vreg_number())) {
|
|
|
2669 op_id = block->sux_at(0)->first_lir_instruction_id();
|
|
|
2670 mode = LIR_OpVisitState::outputMode;
|
|
|
2671 }
|
|
|
2672 }
|
|
|
2673 }
|
|
|
2674
|
|
|
2675 // Get current location of operand
|
|
|
2676 // The operand must be live because debug information is considered when building the intervals
|
|
|
2677 // if the interval is not live, color_lir_opr will cause an assertion failure
|
|
|
2678 opr = color_lir_opr(opr, op_id, mode);
|
|
|
2679 assert(!has_call(op_id) || opr->is_stack() || !is_caller_save(reg_num(opr)), "can not have caller-save register operands at calls");
|
|
|
2680
|
|
|
2681 // Append to ScopeValue array
|
|
|
2682 return append_scope_value_for_operand(opr, scope_values);
|
|
|
2683
|
|
|
2684 } else {
|
|
|
2685 assert(value->as_Constant() != NULL, "all other instructions have only virtual operands");
|
|
|
2686 assert(opr->is_constant(), "operand must be constant");
|
|
|
2687
|
|
|
2688 return append_scope_value_for_constant(opr, scope_values);
|
|
|
2689 }
|
|
|
2690 } else {
|
|
|
2691 // append a dummy value because real value not needed
|
|
|
2692 scope_values->append(&_illegal_value);
|
|
|
2693 return 1;
|
|
|
2694 }
|
|
|
2695 }
|
|
|
2696
|
|
|
2697
|
|
|
2698 IRScopeDebugInfo* LinearScan::compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state, int cur_bci, int stack_end, int locks_end) {
|
|
|
2699 IRScopeDebugInfo* caller_debug_info = NULL;
|
|
|
2700 int stack_begin, locks_begin;
|
|
|
2701
|
|
|
2702 ValueStack* caller_state = cur_scope->caller_state();
|
|
|
2703 if (caller_state != NULL) {
|
|
|
2704 // process recursively to compute outermost scope first
|
|
|
2705 stack_begin = caller_state->stack_size();
|
|
|
2706 locks_begin = caller_state->locks_size();
|
|
|
2707 caller_debug_info = compute_debug_info_for_scope(op_id, cur_scope->caller(), caller_state, innermost_state, cur_scope->caller_bci(), stack_begin, locks_begin);
|
|
|
2708 } else {
|
|
|
2709 stack_begin = 0;
|
|
|
2710 locks_begin = 0;
|
|
|
2711 }
|
|
|
2712
|
|
|
2713 // initialize these to null.
|
|
|
2714 // If we don't need deopt info or there are no locals, expressions or monitors,
|
|
|
2715 // then these get recorded as no information and avoids the allocation of 0 length arrays.
|
|
|
2716 GrowableArray<ScopeValue*>* locals = NULL;
|
|
|
2717 GrowableArray<ScopeValue*>* expressions = NULL;
|
|
|
2718 GrowableArray<MonitorValue*>* monitors = NULL;
|
|
|
2719
|
|
|
2720 // describe local variable values
|
|
|
2721 int nof_locals = cur_scope->method()->max_locals();
|
|
|
2722 if (nof_locals > 0) {
|
|
|
2723 locals = new GrowableArray<ScopeValue*>(nof_locals);
|
|
|
2724
|
|
|
2725 int pos = 0;
|
|
|
2726 while (pos < nof_locals) {
|
|
|
2727 assert(pos < cur_state->locals_size(), "why not?");
|
|
|
2728
|
|
|
2729 Value local = cur_state->local_at(pos);
|
|
|
2730 pos += append_scope_value(op_id, local, locals);
|
|
|
2731
|
|
|
2732 assert(locals->length() == pos, "must match");
|
|
|
2733 }
|
|
|
2734 assert(locals->length() == cur_scope->method()->max_locals(), "wrong number of locals");
|
|
|
2735 assert(locals->length() == cur_state->locals_size(), "wrong number of locals");
|
|
|
2736 }
|
|
|
2737
|
|
|
2738
|
|
|
2739 // describe expression stack
|
|
|
2740 //
|
|
|
2741 // When we inline methods containing exception handlers, the
|
|
|
2742 // "lock_stacks" are changed to preserve expression stack values
|
|
|
2743 // in caller scopes when exception handlers are present. This
|
|
|
2744 // can cause callee stacks to be smaller than caller stacks.
|
|
|
2745 if (stack_end > innermost_state->stack_size()) {
|
|
|
2746 stack_end = innermost_state->stack_size();
|
|
|
2747 }
|
|
|
2748
|
|
|
2749
|
|
|
2750
|
|
|
2751 int nof_stack = stack_end - stack_begin;
|
|
|
2752 if (nof_stack > 0) {
|
|
|
2753 expressions = new GrowableArray<ScopeValue*>(nof_stack);
|
|
|
2754
|
|
|
2755 int pos = stack_begin;
|
|
|
2756 while (pos < stack_end) {
|
|
|
2757 Value expression = innermost_state->stack_at_inc(pos);
|
|
|
2758 append_scope_value(op_id, expression, expressions);
|
|
|
2759
|
|
|
2760 assert(expressions->length() + stack_begin == pos, "must match");
|
|
|
2761 }
|
|
|
2762 }
|
|
|
2763
|
|
|
2764 // describe monitors
|
|
|
2765 assert(locks_begin <= locks_end, "error in scope iteration");
|
|
|
2766 int nof_locks = locks_end - locks_begin;
|
|
|
2767 if (nof_locks > 0) {
|
|
|
2768 monitors = new GrowableArray<MonitorValue*>(nof_locks);
|
|
|
2769 for (int i = locks_begin; i < locks_end; i++) {
|
|
|
2770 monitors->append(location_for_monitor_index(i));
|
|
|
2771 }
|
|
|
2772 }
|
|
|
2773
|
|
|
2774 return new IRScopeDebugInfo(cur_scope, cur_bci, locals, expressions, monitors, caller_debug_info);
|
|
|
2775 }
|
|
|
2776
|
|
|
2777
|
|
|
2778 void LinearScan::compute_debug_info(CodeEmitInfo* info, int op_id) {
|
|
|
2779 if (!compilation()->needs_debug_information()) {
|
|
|
2780 return;
|
|
|
2781 }
|
|
|
2782 TRACE_LINEAR_SCAN(3, tty->print_cr("creating debug information at op_id %d", op_id));
|
|
|
2783
|
|
|
2784 IRScope* innermost_scope = info->scope();
|
|
|
2785 ValueStack* innermost_state = info->stack();
|
|
|
2786
|
|
|
2787 assert(innermost_scope != NULL && innermost_state != NULL, "why is it missing?");
|
|
|
2788
|
|
|
2789 int stack_end = innermost_state->stack_size();
|
|
|
2790 int locks_end = innermost_state->locks_size();
|
|
|
2791
|
|
|
2792 DEBUG_ONLY(check_stack_depth(info, stack_end));
|
|
|
2793
|
|
|
2794 if (info->_scope_debug_info == NULL) {
|
|
|
2795 // compute debug information
|
|
|
2796 info->_scope_debug_info = compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state, info->bci(), stack_end, locks_end);
|
|
|
2797 } else {
|
|
|
2798 // debug information already set. Check that it is correct from the current point of view
|
|
|
2799 DEBUG_ONLY(assert_equal(info->_scope_debug_info, compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state, info->bci(), stack_end, locks_end)));
|
|
|
2800 }
|
|
|
2801 }
|
|
|
2802
|
|
|
2803
|
|
|
2804 void LinearScan::assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw) {
|
|
|
2805 LIR_OpVisitState visitor;
|
|
|
2806 int num_inst = instructions->length();
|
|
|
2807 bool has_dead = false;
|
|
|
2808
|
|
|
2809 for (int j = 0; j < num_inst; j++) {
|
|
|
2810 LIR_Op* op = instructions->at(j);
|
|
|
2811 if (op == NULL) { // this can happen when spill-moves are removed in eliminate_spill_moves
|
|
|
2812 has_dead = true;
|
|
|
2813 continue;
|
|
|
2814 }
|
|
|
2815 int op_id = op->id();
|
|
|
2816
|
|
|
2817 // visit instruction to get list of operands
|
|
|
2818 visitor.visit(op);
|
|
|
2819
|
|
|
2820 // iterate all modes of the visitor and process all virtual operands
|
|
|
2821 for_each_visitor_mode(mode) {
|
|
|
2822 int n = visitor.opr_count(mode);
|
|
|
2823 for (int k = 0; k < n; k++) {
|
|
|
2824 LIR_Opr opr = visitor.opr_at(mode, k);
|
|
|
2825 if (opr->is_virtual_register()) {
|
|
|
2826 visitor.set_opr_at(mode, k, color_lir_opr(opr, op_id, mode));
|
|
|
2827 }
|
|
|
2828 }
|
|
|
2829 }
|
|
|
2830
|
|
|
2831 if (visitor.info_count() > 0) {
|
|
|
2832 // exception handling
|
|
|
2833 if (compilation()->has_exception_handlers()) {
|
|
|
2834 XHandlers* xhandlers = visitor.all_xhandler();
|
|
|
2835 int n = xhandlers->length();
|
|
|
2836 for (int k = 0; k < n; k++) {
|
|
|
2837 XHandler* handler = xhandlers->handler_at(k);
|
|
|
2838 if (handler->entry_code() != NULL) {
|
|
|
2839 assign_reg_num(handler->entry_code()->instructions_list(), NULL);
|
|
|
2840 }
|
|
|
2841 }
|
|
|
2842 } else {
|
|
|
2843 assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
|
|
|
2844 }
|
|
|
2845
|
|
|
2846 // compute oop map
|
|
|
2847 assert(iw != NULL, "needed for compute_oop_map");
|
|
|
2848 compute_oop_map(iw, visitor, op);
|
|
|
2849
|
|
|
2850 // compute debug information
|
|
|
2851 if (!use_fpu_stack_allocation()) {
|
|
|
2852 // compute debug information if fpu stack allocation is not needed.
|
|
|
2853 // when fpu stack allocation is needed, the debug information can not
|
|
|
2854 // be computed here because the exact location of fpu operands is not known
|
|
|
2855 // -> debug information is created inside the fpu stack allocator
|
|
|
2856 int n = visitor.info_count();
|
|
|
2857 for (int k = 0; k < n; k++) {
|
|
|
2858 compute_debug_info(visitor.info_at(k), op_id);
|
|
|
2859 }
|
|
|
2860 }
|
|
|
2861 }
|
|
|
2862
|
|
|
2863 #ifdef ASSERT
|
|
|
2864 // make sure we haven't made the op invalid.
|
|
|
2865 op->verify();
|
|
|
2866 #endif
|
|
|
2867
|
|
|
2868 #ifndef _LP64
|
|
|
2869 // remove useless moves
|
|
|
2870 if (op->code() == lir_move) {
|
|
|
2871 assert(op->as_Op1() != NULL, "move must be LIR_Op1");
|
|
|
2872 LIR_Op1* move = (LIR_Op1*)op;
|
|
|
2873 LIR_Opr src = move->in_opr();
|
|
|
2874 LIR_Opr dst = move->result_opr();
|
|
|
2875 if (dst == src ||
|
|
|
2876 !dst->is_pointer() && !src->is_pointer() &&
|
|
|
2877 src->is_same_register(dst)) {
|
|
|
2878 instructions->at_put(j, NULL);
|
|
|
2879 has_dead = true;
|
|
|
2880 }
|
|
|
2881 }
|
|
|
2882 #endif
|
|
|
2883 }
|
|
|
2884
|
|
|
2885 if (has_dead) {
|
|
|
2886 // iterate all instructions of the block and remove all null-values.
|
|
|
2887 int insert_point = 0;
|
|
|
2888 for (int j = 0; j < num_inst; j++) {
|
|
|
2889 LIR_Op* op = instructions->at(j);
|
|
|
2890 if (op != NULL) {
|
|
|
2891 if (insert_point != j) {
|
|
|
2892 instructions->at_put(insert_point, op);
|
|
|
2893 }
|
|
|
2894 insert_point++;
|
|
|
2895 }
|
|
|
2896 }
|
|
|
2897 instructions->truncate(insert_point);
|
|
|
2898 }
|
|
|
2899 }
|
|
|
2900
|
|
|
2901 void LinearScan::assign_reg_num() {
|
|
|
2902 TIME_LINEAR_SCAN(timer_assign_reg_num);
|
|
|
2903
|
|
|
2904 init_compute_debug_info();
|
|
|
2905 IntervalWalker* iw = init_compute_oop_maps();
|
|
|
2906
|
|
|
2907 int num_blocks = block_count();
|
|
|
2908 for (int i = 0; i < num_blocks; i++) {
|
|
|
2909 BlockBegin* block = block_at(i);
|
|
|
2910 assign_reg_num(block->lir()->instructions_list(), iw);
|
|
|
2911 }
|
|
|
2912 }
|
|
|
2913
|
|
|
2914
|
|
|
2915 void LinearScan::do_linear_scan() {
|
|
|
2916 NOT_PRODUCT(_total_timer.begin_method());
|
|
|
2917
|
|
|
2918 number_instructions();
|
|
|
2919
|
|
|
2920 NOT_PRODUCT(print_lir(1, "Before Register Allocation"));
|
|
|
2921
|
|
|
2922 compute_local_live_sets();
|
|
|
2923 compute_global_live_sets();
|
|
|
2924 CHECK_BAILOUT();
|
|
|
2925
|
|
|
2926 build_intervals();
|
|
|
2927 CHECK_BAILOUT();
|
|
|
2928 sort_intervals_before_allocation();
|
|
|
2929
|
|
|
2930 NOT_PRODUCT(print_intervals("Before Register Allocation"));
|
|
|
2931 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_before_alloc));
|
|
|
2932
|
|
|
2933 allocate_registers();
|
|
|
2934 CHECK_BAILOUT();
|
|
|
2935
|
|
|
2936 resolve_data_flow();
|
|
|
2937 if (compilation()->has_exception_handlers()) {
|
|
|
2938 resolve_exception_handlers();
|
|
|
2939 }
|
|
|
2940 // fill in number of spill slots into frame_map
|
|
|
2941 propagate_spill_slots();
|
|
|
2942 CHECK_BAILOUT();
|
|
|
2943
|
|
|
2944 NOT_PRODUCT(print_intervals("After Register Allocation"));
|
|
|
2945 NOT_PRODUCT(print_lir(2, "LIR after register allocation:"));
|
|
|
2946 DEBUG_ONLY(verify());
|
|
|
2947
|
|
|
2948 sort_intervals_after_allocation();
|
|
|
2949 eliminate_spill_moves();
|
|
|
2950 assign_reg_num();
|
|
|
2951 CHECK_BAILOUT();
|
|
|
2952
|
|
|
2953 NOT_PRODUCT(print_lir(2, "LIR after assignment of register numbers:"));
|
|
|
2954 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_after_asign));
|
|
|
2955
|
|
|
2956 { TIME_LINEAR_SCAN(timer_allocate_fpu_stack);
|
|
|
2957
|
|
|
2958 if (use_fpu_stack_allocation()) {
|
|
|
2959 allocate_fpu_stack(); // Only has effect on Intel
|
|
|
2960 NOT_PRODUCT(print_lir(2, "LIR after FPU stack allocation:"));
|
|
|
2961 }
|
|
|
2962 }
|
|
|
2963
|
|
|
2964 { TIME_LINEAR_SCAN(timer_optimize_lir);
|
|
|
2965
|
|
|
2966 EdgeMoveOptimizer::optimize(ir()->code());
|
|
|
2967 ControlFlowOptimizer::optimize(ir()->code());
|
|
|
2968 // check that cfg is still correct after optimizations
|
|
|
2969 ir()->verify();
|
|
|
2970 }
|
|
|
2971
|
|
|
2972 NOT_PRODUCT(print_lir(1, "Before Code Generation", false));
|
|
|
2973 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_final));
|
|
|
2974 NOT_PRODUCT(_total_timer.end_method(this));
|
|
|
2975 }
|
|
|
2976
|
|
|
2977
|
|
|
2978 // ********** Printing functions
|
|
|
2979
|
|
|
2980 #ifndef PRODUCT
|
|
|
2981
|
|
|
2982 void LinearScan::print_timers(double total) {
|
|
|
2983 _total_timer.print(total);
|
|
|
2984 }
|
|
|
2985
|
|
|
2986 void LinearScan::print_statistics() {
|
|
|
2987 _stat_before_alloc.print("before allocation");
|
|
|
2988 _stat_after_asign.print("after assignment of register");
|
|
|
2989 _stat_final.print("after optimization");
|
|
|
2990 }
|
|
|
2991
|
|
|
2992 void LinearScan::print_bitmap(BitMap& b) {
|
|
|
2993 for (unsigned int i = 0; i < b.size(); i++) {
|
|
|
2994 if (b.at(i)) tty->print("%d ", i);
|
|
|
2995 }
|
|
|
2996 tty->cr();
|
|
|
2997 }
|
|
|
2998
|
|
|
2999 void LinearScan::print_intervals(const char* label) {
|
|
|
3000 if (TraceLinearScanLevel >= 1) {
|
|
|
3001 int i;
|
|
|
3002 tty->cr();
|
|
|
3003 tty->print_cr("%s", label);
|
|
|
3004
|
|
|
3005 for (i = 0; i < interval_count(); i++) {
|
|
|
3006 Interval* interval = interval_at(i);
|
|
|
3007 if (interval != NULL) {
|
|
|
3008 interval->print();
|
|
|
3009 }
|
|
|
3010 }
|
|
|
3011
|
|
|
3012 tty->cr();
|
|
|
3013 tty->print_cr("--- Basic Blocks ---");
|
|
|
3014 for (i = 0; i < block_count(); i++) {
|
|
|
3015 BlockBegin* block = block_at(i);
|
|
|
3016 tty->print("B%d [%d, %d, %d, %d] ", block->block_id(), block->first_lir_instruction_id(), block->last_lir_instruction_id(), block->loop_index(), block->loop_depth());
|
|
|
3017 }
|
|
|
3018 tty->cr();
|
|
|
3019 tty->cr();
|
|
|
3020 }
|
|
|
3021
|
|
|
3022 if (PrintCFGToFile) {
|
|
|
3023 CFGPrinter::print_intervals(&_intervals, label);
|
|
|
3024 }
|
|
|
3025 }
|
|
|
3026
|
|
|
3027 void LinearScan::print_lir(int level, const char* label, bool hir_valid) {
|
|
|
3028 if (TraceLinearScanLevel >= level) {
|
|
|
3029 tty->cr();
|
|
|
3030 tty->print_cr("%s", label);
|
|
|
3031 print_LIR(ir()->linear_scan_order());
|
|
|
3032 tty->cr();
|
|
|
3033 }
|
|
|
3034
|
|
|
3035 if (level == 1 && PrintCFGToFile) {
|
|
|
3036 CFGPrinter::print_cfg(ir()->linear_scan_order(), label, hir_valid, true);
|
|
|
3037 }
|
|
|
3038 }
|
|
|
3039
|
|
|
3040 #endif //PRODUCT
|
|
|
3041
|
|
|
3042
|
|
|
3043 // ********** verification functions for allocation
|
|
|
3044 // (check that all intervals have a correct register and that no registers are overwritten)
|
|
|
3045 #ifdef ASSERT
|
|
|
3046
|
|
|
3047 void LinearScan::verify() {
|
|
|
3048 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying intervals ******************************************"));
|
|
|
3049 verify_intervals();
|
|
|
3050
|
|
|
3051 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that no oops are in fixed intervals ****************"));
|
|
|
3052 verify_no_oops_in_fixed_intervals();
|
|
|
3053
|
|
|
3054 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that unpinned constants are not alive across block boundaries"));
|
|
|
3055 verify_constants();
|
|
|
3056
|
|
|
3057 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying register allocation ********************************"));
|
|
|
3058 verify_registers();
|
|
|
3059
|
|
|
3060 TRACE_LINEAR_SCAN(2, tty->print_cr("********* no errors found **********************************************"));
|
|
|
3061 }
|
|
|
3062
|
|
|
3063 void LinearScan::verify_intervals() {
|
|
|
3064 int len = interval_count();
|
|
|
3065 bool has_error = false;
|
|
|
3066
|
|
|
3067 for (int i = 0; i < len; i++) {
|
|
|
3068 Interval* i1 = interval_at(i);
|
|
|
3069 if (i1 == NULL) continue;
|
|
|
3070
|
|
|
3071 i1->check_split_children();
|
|
|
3072
|
|
|
3073 if (i1->reg_num() != i) {
|
|
|
3074 tty->print_cr("Interval %d is on position %d in list", i1->reg_num(), i); i1->print(); tty->cr();
|
|
|
3075 has_error = true;
|
|
|
3076 }
|
|
|
3077
|
|
|
3078 if (i1->reg_num() >= LIR_OprDesc::vreg_base && i1->type() == T_ILLEGAL) {
|
|
|
3079 tty->print_cr("Interval %d has no type assigned", i1->reg_num()); i1->print(); tty->cr();
|
|
|
3080 has_error = true;
|
|
|
3081 }
|
|
|
3082
|
|
|
3083 if (i1->assigned_reg() == any_reg) {
|
|
|
3084 tty->print_cr("Interval %d has no register assigned", i1->reg_num()); i1->print(); tty->cr();
|
|
|
3085 has_error = true;
|
|
|
3086 }
|
|
|
3087
|
|
|
3088 if (i1->assigned_reg() == i1->assigned_regHi()) {
|
|
|
3089 tty->print_cr("Interval %d: low and high register equal", i1->reg_num()); i1->print(); tty->cr();
|
|
|
3090 has_error = true;
|
|
|
3091 }
|
|
|
3092
|
|
|
3093 if (!is_processed_reg_num(i1->assigned_reg())) {
|
|
|
3094 tty->print_cr("Can not have an Interval for an ignored register"); i1->print(); tty->cr();
|
|
|
3095 has_error = true;
|
|
|
3096 }
|
|
|
3097
|
|
|
3098 if (i1->first() == Range::end()) {
|
|
|
3099 tty->print_cr("Interval %d has no Range", i1->reg_num()); i1->print(); tty->cr();
|
|
|
3100 has_error = true;
|
|
|
3101 }
|
|
|
3102
|
|
|
3103 for (Range* r = i1->first(); r != Range::end(); r = r->next()) {
|
|
|
3104 if (r->from() >= r->to()) {
|
|
|
3105 tty->print_cr("Interval %d has zero length range", i1->reg_num()); i1->print(); tty->cr();
|
|
|
3106 has_error = true;
|
|
|
3107 }
|
|
|
3108 }
|
|
|
3109
|
|
|
3110 for (int j = i + 1; j < len; j++) {
|
|
|
3111 Interval* i2 = interval_at(j);
|
|
|
3112 if (i2 == NULL) continue;
|
|
|
3113
|
|
|
3114 // special intervals that are created in MoveResolver
|
|
|
3115 // -> ignore them because the range information has no meaning there
|
|
|
3116 if (i1->from() == 1 && i1->to() == 2) continue;
|
|
|
3117 if (i2->from() == 1 && i2->to() == 2) continue;
|
|
|
3118
|
|
|
3119 int r1 = i1->assigned_reg();
|
|
|
3120 int r1Hi = i1->assigned_regHi();
|
|
|
3121 int r2 = i2->assigned_reg();
|
|
|
3122 int r2Hi = i2->assigned_regHi();
|
|
|
3123 if (i1->intersects(i2) && (r1 == r2 || r1 == r2Hi || (r1Hi != any_reg && (r1Hi == r2 || r1Hi == r2Hi)))) {
|
|
|
3124 tty->print_cr("Intervals %d and %d overlap and have the same register assigned", i1->reg_num(), i2->reg_num());
|
|
|
3125 i1->print(); tty->cr();
|
|
|
3126 i2->print(); tty->cr();
|
|
|
3127 has_error = true;
|
|
|
3128 }
|
|
|
3129 }
|
|
|
3130 }
|
|
|
3131
|
|
|
3132 assert(has_error == false, "register allocation invalid");
|
|
|
3133 }
|
|
|
3134
|
|
|
3135
|
|
|
3136 void LinearScan::verify_no_oops_in_fixed_intervals() {
|
|
|
3137 LIR_OpVisitState visitor;
|
|
|
3138 for (int i = 0; i < block_count(); i++) {
|
|
|
3139 BlockBegin* block = block_at(i);
|
|
|
3140
|
|
|
3141 LIR_OpList* instructions = block->lir()->instructions_list();
|
|
|
3142
|
|
|
3143 for (int j = 0; j < instructions->length(); j++) {
|
|
|
3144 LIR_Op* op = instructions->at(j);
|
|
|
3145 int op_id = op->id();
|
|
|
3146
|
|
|
3147 visitor.visit(op);
|
|
|
3148
|
|
|
3149 // oop-maps at calls do not contain registers, so check is not needed
|
|
|
3150 if (!visitor.has_call()) {
|
|
|
3151
|
|
|
3152 for_each_visitor_mode(mode) {
|
|
|
3153 int n = visitor.opr_count(mode);
|
|
|
3154 for (int k = 0; k < n; k++) {
|
|
|
3155 LIR_Opr opr = visitor.opr_at(mode, k);
|
|
|
3156
|
|
|
3157 if (opr->is_fixed_cpu() && opr->is_oop()) {
|
|
|
3158 // operand is a non-virtual cpu register and contains an oop
|
|
|
3159 TRACE_LINEAR_SCAN(4, op->print_on(tty); tty->print("checking operand "); opr->print(); tty->cr());
|
|
|
3160
|
|
|
3161 Interval* interval = interval_at(reg_num(opr));
|
|
|
3162 assert(interval != NULL, "no interval");
|
|
|
3163
|
|
|
3164 if (mode == LIR_OpVisitState::inputMode) {
|
|
|
3165 if (interval->to() >= op_id + 1) {
|
|
|
3166 assert(interval->to() < op_id + 2 ||
|
|
|
3167 interval->has_hole_between(op_id, op_id + 2),
|
|
|
3168 "oop input operand live after instruction");
|
|
|
3169 }
|
|
|
3170 } else if (mode == LIR_OpVisitState::outputMode) {
|
|
|
3171 if (interval->from() <= op_id - 1) {
|
|
|
3172 assert(interval->has_hole_between(op_id - 1, op_id),
|
|
|
3173 "oop input operand live after instruction");
|
|
|
3174 }
|
|
|
3175 }
|
|
|
3176 }
|
|
|
3177 }
|
|
|
3178 }
|
|
|
3179 }
|
|
|
3180 }
|
|
|
3181 }
|
|
|
3182 }
|
|
|
3183
|
|
|
3184
|
|
|
3185 void LinearScan::verify_constants() {
|
|
|
3186 int num_regs = num_virtual_regs();
|
|
|
3187 int size = live_set_size();
|
|
|
3188 int num_blocks = block_count();
|
|
|
3189
|
|
|
3190 for (int i = 0; i < num_blocks; i++) {
|
|
|
3191 BlockBegin* block = block_at(i);
|
|
|
3192 BitMap live_at_edge = block->live_in();
|
|
|
3193
|
|
|
3194 // visit all registers where the live_at_edge bit is set
|
|
|
3195 for (int r = live_at_edge.get_next_one_offset(0, size); r < size; r = live_at_edge.get_next_one_offset(r + 1, size)) {
|
|
|
3196 TRACE_LINEAR_SCAN(4, tty->print("checking interval %d of block B%d", r, block->block_id()));
|
|
|
3197
|
|
|
3198 Value value = gen()->instruction_for_vreg(r);
|
|
|
3199
|
|
|
3200 assert(value != NULL, "all intervals live across block boundaries must have Value");
|
|
|
3201 assert(value->operand()->is_register() && value->operand()->is_virtual(), "value must have virtual operand");
|
|
|
3202 assert(value->operand()->vreg_number() == r, "register number must match");
|
|
|
3203 // TKR assert(value->as_Constant() == NULL || value->is_pinned(), "only pinned constants can be alive accross block boundaries");
|
|
|
3204 }
|
|
|
3205 }
|
|
|
3206 }
|
|
|
3207
|
|
|
3208
|
|
|
3209 class RegisterVerifier: public StackObj {
|
|
|
3210 private:
|
|
|
3211 LinearScan* _allocator;
|
|
|
3212 BlockList _work_list; // all blocks that must be processed
|
|
|
3213 IntervalsList _saved_states; // saved information of previous check
|
|
|
3214
|
|
|
3215 // simplified access to methods of LinearScan
|
|
|
3216 Compilation* compilation() const { return _allocator->compilation(); }
|
|
|
3217 Interval* interval_at(int reg_num) const { return _allocator->interval_at(reg_num); }
|
|
|
3218 int reg_num(LIR_Opr opr) const { return _allocator->reg_num(opr); }
|
|
|
3219
|
|
|
3220 // currently, only registers are processed
|
|
|
3221 int state_size() { return LinearScan::nof_regs; }
|
|
|
3222
|
|
|
3223 // accessors
|
|
|
3224 IntervalList* state_for_block(BlockBegin* block) { return _saved_states.at(block->block_id()); }
|
|
|
3225 void set_state_for_block(BlockBegin* block, IntervalList* saved_state) { _saved_states.at_put(block->block_id(), saved_state); }
|
|
|
3226 void add_to_work_list(BlockBegin* block) { if (!_work_list.contains(block)) _work_list.append(block); }
|
|
|
3227
|
|
|
3228 // helper functions
|
|
|
3229 IntervalList* copy(IntervalList* input_state);
|
|
|
3230 void state_put(IntervalList* input_state, int reg, Interval* interval);
|
|
|
3231 bool check_state(IntervalList* input_state, int reg, Interval* interval);
|
|
|
3232
|
|
|
3233 void process_block(BlockBegin* block);
|
|
|
3234 void process_xhandler(XHandler* xhandler, IntervalList* input_state);
|
|
|
3235 void process_successor(BlockBegin* block, IntervalList* input_state);
|
|
|
3236 void process_operations(LIR_List* ops, IntervalList* input_state);
|
|
|
3237
|
|
|
3238 public:
|
|
|
3239 RegisterVerifier(LinearScan* allocator)
|
|
|
3240 : _allocator(allocator)
|
|
|
3241 , _work_list(16)
|
|
|
3242 , _saved_states(BlockBegin::number_of_blocks(), NULL)
|
|
|
3243 { }
|
|
|
3244
|
|
|
3245 void verify(BlockBegin* start);
|
|
|
3246 };
|
|
|
3247
|
|
|
3248
|
|
|
3249 // entry function from LinearScan that starts the verification
|
|
|
3250 void LinearScan::verify_registers() {
|
|
|
3251 RegisterVerifier verifier(this);
|
|
|
3252 verifier.verify(block_at(0));
|
|
|
3253 }
|
|
|
3254
|
|
|
3255
|
|
|
3256 void RegisterVerifier::verify(BlockBegin* start) {
|
|
|
3257 // setup input registers (method arguments) for first block
|
|
|
3258 IntervalList* input_state = new IntervalList(state_size(), NULL);
|
|
|
3259 CallingConvention* args = compilation()->frame_map()->incoming_arguments();
|
|
|
3260 for (int n = 0; n < args->length(); n++) {
|
|
|
3261 LIR_Opr opr = args->at(n);
|
|
|
3262 if (opr->is_register()) {
|
|
|
3263 Interval* interval = interval_at(reg_num(opr));
|
|
|
3264
|
|
|
3265 if (interval->assigned_reg() < state_size()) {
|
|
|
3266 input_state->at_put(interval->assigned_reg(), interval);
|
|
|
3267 }
|
|
|
3268 if (interval->assigned_regHi() != LinearScan::any_reg && interval->assigned_regHi() < state_size()) {
|
|
|
3269 input_state->at_put(interval->assigned_regHi(), interval);
|
|
|
3270 }
|
|
|
3271 }
|
|
|
3272 }
|
|
|
3273
|
|
|
3274 set_state_for_block(start, input_state);
|
|
|
3275 add_to_work_list(start);
|
|
|
3276
|
|
|
3277 // main loop for verification
|
|
|
3278 do {
|
|
|
3279 BlockBegin* block = _work_list.at(0);
|
|
|
3280 _work_list.remove_at(0);
|
|
|
3281
|
|
|
3282 process_block(block);
|
|
|
3283 } while (!_work_list.is_empty());
|
|
|
3284 }
|
|
|
3285
|
|
|
3286 void RegisterVerifier::process_block(BlockBegin* block) {
|
|
|
3287 TRACE_LINEAR_SCAN(2, tty->cr(); tty->print_cr("process_block B%d", block->block_id()));
|
|
|
3288
|
|
|
3289 // must copy state because it is modified
|
|
|
3290 IntervalList* input_state = copy(state_for_block(block));
|
|
|
3291
|
|
|
3292 if (TraceLinearScanLevel >= 4) {
|
|
|
3293 tty->print_cr("Input-State of intervals:");
|
|
|
3294 tty->print(" ");
|
|
|
3295 for (int i = 0; i < state_size(); i++) {
|
|
|
3296 if (input_state->at(i) != NULL) {
|
|
|
3297 tty->print(" %4d", input_state->at(i)->reg_num());
|
|
|
3298 } else {
|
|
|
3299 tty->print(" __");
|
|
|
3300 }
|
|
|
3301 }
|
|
|
3302 tty->cr();
|
|
|
3303 tty->cr();
|
|
|
3304 }
|
|
|
3305
|
|
|
3306 // process all operations of the block
|
|
|
3307 process_operations(block->lir(), input_state);
|
|
|
3308
|
|
|
3309 // iterate all successors
|
|
|
3310 for (int i = 0; i < block->number_of_sux(); i++) {
|
|
|
3311 process_successor(block->sux_at(i), input_state);
|
|
|
3312 }
|
|
|
3313 }
|
|
|
3314
|
|
|
3315 void RegisterVerifier::process_xhandler(XHandler* xhandler, IntervalList* input_state) {
|
|
|
3316 TRACE_LINEAR_SCAN(2, tty->print_cr("process_xhandler B%d", xhandler->entry_block()->block_id()));
|
|
|
3317
|
|
|
3318 // must copy state because it is modified
|
|
|
3319 input_state = copy(input_state);
|
|
|
3320
|
|
|
3321 if (xhandler->entry_code() != NULL) {
|
|
|
3322 process_operations(xhandler->entry_code(), input_state);
|
|
|
3323 }
|
|
|
3324 process_successor(xhandler->entry_block(), input_state);
|
|
|
3325 }
|
|
|
3326
|
|
|
3327 void RegisterVerifier::process_successor(BlockBegin* block, IntervalList* input_state) {
|
|
|
3328 IntervalList* saved_state = state_for_block(block);
|
|
|
3329
|
|
|
3330 if (saved_state != NULL) {
|
|
|
3331 // this block was already processed before.
|
|
|
3332 // check if new input_state is consistent with saved_state
|
|
|
3333
|
|
|
3334 bool saved_state_correct = true;
|
|
|
3335 for (int i = 0; i < state_size(); i++) {
|
|
|
3336 if (input_state->at(i) != saved_state->at(i)) {
|
|
|
3337 // current input_state and previous saved_state assume a different
|
|
|
3338 // interval in this register -> assume that this register is invalid
|
|
|
3339 if (saved_state->at(i) != NULL) {
|
|
|
3340 // invalidate old calculation only if it assumed that
|
|
|
3341 // register was valid. when the register was already invalid,
|
|
|
3342 // then the old calculation was correct.
|
|
|
3343 saved_state_correct = false;
|
|
|
3344 saved_state->at_put(i, NULL);
|
|
|
3345
|
|
|
3346 TRACE_LINEAR_SCAN(4, tty->print_cr("process_successor B%d: invalidating slot %d", block->block_id(), i));
|
|
|
3347 }
|
|
|
3348 }
|
|
|
3349 }
|
|
|
3350
|
|
|
3351 if (saved_state_correct) {
|
|
|
3352 // already processed block with correct input_state
|
|
|
3353 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: previous visit already correct", block->block_id()));
|
|
|
3354 } else {
|
|
|
3355 // must re-visit this block
|
|
|
3356 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: must re-visit because input state changed", block->block_id()));
|
|
|
3357 add_to_work_list(block);
|
|
|
3358 }
|
|
|
3359
|
|
|
3360 } else {
|
|
|
3361 // block was not processed before, so set initial input_state
|
|
|
3362 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: initial visit", block->block_id()));
|
|
|
3363
|
|
|
3364 set_state_for_block(block, copy(input_state));
|
|
|
3365 add_to_work_list(block);
|
|
|
3366 }
|
|
|
3367 }
|
|
|
3368
|
|
|
3369
|
|
|
3370 IntervalList* RegisterVerifier::copy(IntervalList* input_state) {
|
|
|
3371 IntervalList* copy_state = new IntervalList(input_state->length());
|
|
|
3372 copy_state->push_all(input_state);
|
|
|
3373 return copy_state;
|
|
|
3374 }
|
|
|
3375
|
|
|
3376 void RegisterVerifier::state_put(IntervalList* input_state, int reg, Interval* interval) {
|
|
|
3377 if (reg != LinearScan::any_reg && reg < state_size()) {
|
|
|
3378 if (interval != NULL) {
|
|
|
3379 TRACE_LINEAR_SCAN(4, tty->print_cr(" reg[%d] = %d", reg, interval->reg_num()));
|
|
|
3380 } else if (input_state->at(reg) != NULL) {
|
|
|
3381 TRACE_LINEAR_SCAN(4, tty->print_cr(" reg[%d] = NULL", reg));
|
|
|
3382 }
|
|
|
3383
|
|
|
3384 input_state->at_put(reg, interval);
|
|
|
3385 }
|
|
|
3386 }
|
|
|
3387
|
|
|
3388 bool RegisterVerifier::check_state(IntervalList* input_state, int reg, Interval* interval) {
|
|
|
3389 if (reg != LinearScan::any_reg && reg < state_size()) {
|
|
|
3390 if (input_state->at(reg) != interval) {
|
|
|
3391 tty->print_cr("!! Error in register allocation: register %d does not contain interval %d", reg, interval->reg_num());
|
|
|
3392 return true;
|
|
|
3393 }
|
|
|
3394 }
|
|
|
3395 return false;
|
|
|
3396 }
|
|
|
3397
|
|
|
3398 void RegisterVerifier::process_operations(LIR_List* ops, IntervalList* input_state) {
|
|
|
3399 // visit all instructions of the block
|
|
|
3400 LIR_OpVisitState visitor;
|
|
|
3401 bool has_error = false;
|
|
|
3402
|
|
|
3403 for (int i = 0; i < ops->length(); i++) {
|
|
|
3404 LIR_Op* op = ops->at(i);
|
|
|
3405 visitor.visit(op);
|
|
|
3406
|
|
|
3407 TRACE_LINEAR_SCAN(4, op->print_on(tty));
|
|
|
3408
|
|
|
3409 // check if input operands are correct
|
|
|
3410 int j;
|
|
|
3411 int n = visitor.opr_count(LIR_OpVisitState::inputMode);
|
|
|
3412 for (j = 0; j < n; j++) {
|
|
|
3413 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, j);
|
|
|
3414 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
|
|
|
3415 Interval* interval = interval_at(reg_num(opr));
|
|
|
3416 if (op->id() != -1) {
|
|
|
3417 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::inputMode);
|
|
|
3418 }
|
|
|
3419
|
|
|
3420 has_error |= check_state(input_state, interval->assigned_reg(), interval->split_parent());
|
|
|
3421 has_error |= check_state(input_state, interval->assigned_regHi(), interval->split_parent());
|
|
|
3422
|
|
|
3423 // When an operand is marked with is_last_use, then the fpu stack allocator
|
|
|
3424 // removes the register from the fpu stack -> the register contains no value
|
|
|
3425 if (opr->is_last_use()) {
|
|
|
3426 state_put(input_state, interval->assigned_reg(), NULL);
|
|
|
3427 state_put(input_state, interval->assigned_regHi(), NULL);
|
|
|
3428 }
|
|
|
3429 }
|
|
|
3430 }
|
|
|
3431
|
|
|
3432 // invalidate all caller save registers at calls
|
|
|
3433 if (visitor.has_call()) {
|
|
|
3434 for (j = 0; j < FrameMap::nof_caller_save_cpu_regs; j++) {
|
|
|
3435 state_put(input_state, reg_num(FrameMap::caller_save_cpu_reg_at(j)), NULL);
|
|
|
3436 }
|
|
|
3437 for (j = 0; j < FrameMap::nof_caller_save_fpu_regs; j++) {
|
|
|
3438 state_put(input_state, reg_num(FrameMap::caller_save_fpu_reg_at(j)), NULL);
|
|
|
3439 }
|
|
|
3440
|
|
|
3441 #ifdef IA32
|
|
|
3442 for (j = 0; j < FrameMap::nof_caller_save_xmm_regs; j++) {
|
|
|
3443 state_put(input_state, reg_num(FrameMap::caller_save_xmm_reg_at(j)), NULL);
|
|
|
3444 }
|
|
|
3445 #endif
|
|
|
3446 }
|
|
|
3447
|
|
|
3448 // process xhandler before output and temp operands
|
|
|
3449 XHandlers* xhandlers = visitor.all_xhandler();
|
|
|
3450 n = xhandlers->length();
|
|
|
3451 for (int k = 0; k < n; k++) {
|
|
|
3452 process_xhandler(xhandlers->handler_at(k), input_state);
|
|
|
3453 }
|
|
|
3454
|
|
|
3455 // set temp operands (some operations use temp operands also as output operands, so can't set them NULL)
|
|
|
3456 n = visitor.opr_count(LIR_OpVisitState::tempMode);
|
|
|
3457 for (j = 0; j < n; j++) {
|
|
|
3458 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, j);
|
|
|
3459 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
|
|
|
3460 Interval* interval = interval_at(reg_num(opr));
|
|
|
3461 if (op->id() != -1) {
|
|
|
3462 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::tempMode);
|
|
|
3463 }
|
|
|
3464
|
|
|
3465 state_put(input_state, interval->assigned_reg(), interval->split_parent());
|
|
|
3466 state_put(input_state, interval->assigned_regHi(), interval->split_parent());
|
|
|
3467 }
|
|
|
3468 }
|
|
|
3469
|
|
|
3470 // set output operands
|
|
|
3471 n = visitor.opr_count(LIR_OpVisitState::outputMode);
|
|
|
3472 for (j = 0; j < n; j++) {
|
|
|
3473 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, j);
|
|
|
3474 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
|
|
|
3475 Interval* interval = interval_at(reg_num(opr));
|
|
|
3476 if (op->id() != -1) {
|
|
|
3477 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::outputMode);
|
|
|
3478 }
|
|
|
3479
|
|
|
3480 state_put(input_state, interval->assigned_reg(), interval->split_parent());
|
|
|
3481 state_put(input_state, interval->assigned_regHi(), interval->split_parent());
|
|
|
3482 }
|
|
|
3483 }
|
|
|
3484 }
|
|
|
3485 assert(has_error == false, "Error in register allocation");
|
|
|
3486 }
|
|
|
3487
|
|
|
3488 #endif // ASSERT
|
|
|
3489
|
|
|
3490
|
|
|
3491
|
|
|
3492 // **** Implementation of MoveResolver ******************************
|
|
|
3493
|
|
|
3494 MoveResolver::MoveResolver(LinearScan* allocator) :
|
|
|
3495 _allocator(allocator),
|
|
|
3496 _multiple_reads_allowed(false),
|
|
|
3497 _mapping_from(8),
|
|
|
3498 _mapping_from_opr(8),
|
|
|
3499 _mapping_to(8),
|
|
|
3500 _insert_list(NULL),
|
|
|
3501 _insert_idx(-1),
|
|
|
3502 _insertion_buffer()
|
|
|
3503 {
|
|
|
3504 for (int i = 0; i < LinearScan::nof_regs; i++) {
|
|
|
3505 _register_blocked[i] = 0;
|
|
|
3506 }
|
|
|
3507 DEBUG_ONLY(check_empty());
|
|
|
3508 }
|
|
|
3509
|
|
|
3510
|
|
|
3511 #ifdef ASSERT
|
|
|
3512
|
|
|
3513 void MoveResolver::check_empty() {
|
|
|
3514 assert(_mapping_from.length() == 0 && _mapping_from_opr.length() == 0 && _mapping_to.length() == 0, "list must be empty before and after processing");
|
|
|
3515 for (int i = 0; i < LinearScan::nof_regs; i++) {
|
|
|
3516 assert(register_blocked(i) == 0, "register map must be empty before and after processing");
|
|
|
3517 }
|
|
|
3518 assert(_multiple_reads_allowed == false, "must have default value");
|
|
|
3519 }
|
|
|
3520
|
|
|
3521 void MoveResolver::verify_before_resolve() {
|
|
|
3522 assert(_mapping_from.length() == _mapping_from_opr.length(), "length must be equal");
|
|
|
3523 assert(_mapping_from.length() == _mapping_to.length(), "length must be equal");
|
|
|
3524 assert(_insert_list != NULL && _insert_idx != -1, "insert position not set");
|
|
|
3525
|
|
|
3526 int i, j;
|
|
|
3527 if (!_multiple_reads_allowed) {
|
|
|
3528 for (i = 0; i < _mapping_from.length(); i++) {
|
|
|
3529 for (j = i + 1; j < _mapping_from.length(); j++) {
|
|
|
3530 assert(_mapping_from.at(i) == NULL || _mapping_from.at(i) != _mapping_from.at(j), "cannot read from same interval twice");
|
|
|
3531 }
|
|
|
3532 }
|
|
|
3533 }
|
|
|
3534
|
|
|
3535 for (i = 0; i < _mapping_to.length(); i++) {
|
|
|
3536 for (j = i + 1; j < _mapping_to.length(); j++) {
|
|
|
3537 assert(_mapping_to.at(i) != _mapping_to.at(j), "cannot write to same interval twice");
|
|
|
3538 }
|
|
|
3539 }
|
|
|
3540
|
|
|
3541
|
|
|
3542 BitMap used_regs(LinearScan::nof_regs + allocator()->frame_map()->argcount() + allocator()->max_spills());
|
|
|
3543 used_regs.clear();
|
|
|
3544 if (!_multiple_reads_allowed) {
|
|
|
3545 for (i = 0; i < _mapping_from.length(); i++) {
|
|
|
3546 Interval* it = _mapping_from.at(i);
|
|
|
3547 if (it != NULL) {
|
|
|
3548 assert(!used_regs.at(it->assigned_reg()), "cannot read from same register twice");
|
|
|
3549 used_regs.set_bit(it->assigned_reg());
|
|
|
3550
|
|
|
3551 if (it->assigned_regHi() != LinearScan::any_reg) {
|
|
|
3552 assert(!used_regs.at(it->assigned_regHi()), "cannot read from same register twice");
|
|
|
3553 used_regs.set_bit(it->assigned_regHi());
|
|
|
3554 }
|
|
|
3555 }
|
|
|
3556 }
|
|
|
3557 }
|
|
|
3558
|
|
|
3559 used_regs.clear();
|
|
|
3560 for (i = 0; i < _mapping_to.length(); i++) {
|
|
|
3561 Interval* it = _mapping_to.at(i);
|
|
|
3562 assert(!used_regs.at(it->assigned_reg()), "cannot write to same register twice");
|
|
|
3563 used_regs.set_bit(it->assigned_reg());
|
|
|
3564
|
|
|
3565 if (it->assigned_regHi() != LinearScan::any_reg) {
|
|
|
3566 assert(!used_regs.at(it->assigned_regHi()), "cannot write to same register twice");
|
|
|
3567 used_regs.set_bit(it->assigned_regHi());
|
|
|
3568 }
|
|
|
3569 }
|
|
|
3570
|
|
|
3571 used_regs.clear();
|
|
|
3572 for (i = 0; i < _mapping_from.length(); i++) {
|
|
|
3573 Interval* it = _mapping_from.at(i);
|
|
|
3574 if (it != NULL && it->assigned_reg() >= LinearScan::nof_regs) {
|
|
|
3575 used_regs.set_bit(it->assigned_reg());
|
|
|
3576 }
|
|
|
3577 }
|
|
|
3578 for (i = 0; i < _mapping_to.length(); i++) {
|
|
|
3579 Interval* it = _mapping_to.at(i);
|
|
|
3580 assert(!used_regs.at(it->assigned_reg()) || it->assigned_reg() == _mapping_from.at(i)->assigned_reg(), "stack slots used in _mapping_from must be disjoint to _mapping_to");
|
|
|
3581 }
|
|
|
3582 }
|
|
|
3583
|
|
|
3584 #endif // ASSERT
|
|
|
3585
|
|
|
3586
|
|
|
3587 // mark assigned_reg and assigned_regHi of the interval as blocked
|
|
|
3588 void MoveResolver::block_registers(Interval* it) {
|
|
|
3589 int reg = it->assigned_reg();
|
|
|
3590 if (reg < LinearScan::nof_regs) {
|
|
|
3591 assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
|
|
|
3592 set_register_blocked(reg, 1);
|
|
|
3593 }
|
|
|
3594 reg = it->assigned_regHi();
|
|
|
3595 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
|
|
|
3596 assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
|
|
|
3597 set_register_blocked(reg, 1);
|
|
|
3598 }
|
|
|
3599 }
|
|
|
3600
|
|
|
3601 // mark assigned_reg and assigned_regHi of the interval as unblocked
|
|
|
3602 void MoveResolver::unblock_registers(Interval* it) {
|
|
|
3603 int reg = it->assigned_reg();
|
|
|
3604 if (reg < LinearScan::nof_regs) {
|
|
|
3605 assert(register_blocked(reg) > 0, "register already marked as unused");
|
|
|
3606 set_register_blocked(reg, -1);
|
|
|
3607 }
|
|
|
3608 reg = it->assigned_regHi();
|
|
|
3609 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
|
|
|
3610 assert(register_blocked(reg) > 0, "register already marked as unused");
|
|
|
3611 set_register_blocked(reg, -1);
|
|
|
3612 }
|
|
|
3613 }
|
|
|
3614
|
|
|
3615 // check if assigned_reg and assigned_regHi of the to-interval are not blocked (or only blocked by from)
|
|
|
3616 bool MoveResolver::save_to_process_move(Interval* from, Interval* to) {
|
|
|
3617 int from_reg = -1;
|
|
|
3618 int from_regHi = -1;
|
|
|
3619 if (from != NULL) {
|
|
|
3620 from_reg = from->assigned_reg();
|
|
|
3621 from_regHi = from->assigned_regHi();
|
|
|
3622 }
|
|
|
3623
|
|
|
3624 int reg = to->assigned_reg();
|
|
|
3625 if (reg < LinearScan::nof_regs) {
|
|
|
3626 if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
|
|
|
3627 return false;
|
|
|
3628 }
|
|
|
3629 }
|
|
|
3630 reg = to->assigned_regHi();
|
|
|
3631 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
|
|
|
3632 if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
|
|
|
3633 return false;
|
|
|
3634 }
|
|
|
3635 }
|
|
|
3636
|
|
|
3637 return true;
|
|
|
3638 }
|
|
|
3639
|
|
|
3640
|
|
|
3641 void MoveResolver::create_insertion_buffer(LIR_List* list) {
|
|
|
3642 assert(!_insertion_buffer.initialized(), "overwriting existing buffer");
|
|
|
3643 _insertion_buffer.init(list);
|
|
|
3644 }
|
|
|
3645
|
|
|
3646 void MoveResolver::append_insertion_buffer() {
|
|
|
3647 if (_insertion_buffer.initialized()) {
|
|
|
3648 _insertion_buffer.lir_list()->append(&_insertion_buffer);
|
|
|
3649 }
|
|
|
3650 assert(!_insertion_buffer.initialized(), "must be uninitialized now");
|
|
|
3651
|
|
|
3652 _insert_list = NULL;
|
|
|
3653 _insert_idx = -1;
|
|
|
3654 }
|
|
|
3655
|
|
|
3656 void MoveResolver::insert_move(Interval* from_interval, Interval* to_interval) {
|
|
|
3657 assert(from_interval->reg_num() != to_interval->reg_num(), "from and to interval equal");
|
|
|
3658 assert(from_interval->type() == to_interval->type(), "move between different types");
|
|
|
3659 assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
|
|
|
3660 assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
|
|
|
3661
|
|
|
3662 LIR_Opr from_opr = LIR_OprFact::virtual_register(from_interval->reg_num(), from_interval->type());
|
|
|
3663 LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type());
|
|
|
3664
|
|
|
3665 if (!_multiple_reads_allowed) {
|
|
|
3666 // the last_use flag is an optimization for FPU stack allocation. When the same
|
|
|
3667 // input interval is used in more than one move, then it is too difficult to determine
|
|
|
3668 // if this move is really the last use.
|
|
|
3669 from_opr = from_opr->make_last_use();
|
|
|
3670 }
|
|
|
3671 _insertion_buffer.move(_insert_idx, from_opr, to_opr);
|
|
|
3672
|
|
|
3673 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: inserted move from register %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
|
|
|
3674 }
|
|
|
3675
|
|
|
3676 void MoveResolver::insert_move(LIR_Opr from_opr, Interval* to_interval) {
|
|
|
3677 assert(from_opr->type() == to_interval->type(), "move between different types");
|
|
|
3678 assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
|
|
|
3679 assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
|
|
|
3680
|
|
|
3681 LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type());
|
|
|
3682 _insertion_buffer.move(_insert_idx, from_opr, to_opr);
|
|
|
3683
|
|
|
3684 TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: inserted move from constant "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
|
|
|
3685 }
|
|
|
3686
|
|
|
3687
|
|
|
3688 void MoveResolver::resolve_mappings() {
|
|
|
3689 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: resolving mappings for Block B%d, index %d", _insert_list->block() != NULL ? _insert_list->block()->block_id() : -1, _insert_idx));
|
|
|
3690 DEBUG_ONLY(verify_before_resolve());
|
|
|
3691
|
|
|
3692 // Block all registers that are used as input operands of a move.
|
|
|
3693 // When a register is blocked, no move to this register is emitted.
|
|
|
3694 // This is necessary for detecting cycles in moves.
|
|
|
3695 int i;
|
|
|
3696 for (i = _mapping_from.length() - 1; i >= 0; i--) {
|
|
|
3697 Interval* from_interval = _mapping_from.at(i);
|
|
|
3698 if (from_interval != NULL) {
|
|
|
3699 block_registers(from_interval);
|
|
|
3700 }
|
|
|
3701 }
|
|
|
3702
|
|
|
3703 int spill_candidate = -1;
|
|
|
3704 while (_mapping_from.length() > 0) {
|
|
|
3705 bool processed_interval = false;
|
|
|
3706
|
|
|
3707 for (i = _mapping_from.length() - 1; i >= 0; i--) {
|
|
|
3708 Interval* from_interval = _mapping_from.at(i);
|
|
|
3709 Interval* to_interval = _mapping_to.at(i);
|
|
|
3710
|
|
|
3711 if (save_to_process_move(from_interval, to_interval)) {
|
|
|
3712 // this inverval can be processed because target is free
|
|
|
3713 if (from_interval != NULL) {
|
|
|
3714 insert_move(from_interval, to_interval);
|
|
|
3715 unblock_registers(from_interval);
|
|
|
3716 } else {
|
|
|
3717 insert_move(_mapping_from_opr.at(i), to_interval);
|
|
|
3718 }
|
|
|
3719 _mapping_from.remove_at(i);
|
|
|
3720 _mapping_from_opr.remove_at(i);
|
|
|
3721 _mapping_to.remove_at(i);
|
|
|
3722
|
|
|
3723 processed_interval = true;
|
|
|
3724 } else if (from_interval != NULL && from_interval->assigned_reg() < LinearScan::nof_regs) {
|
|
|
3725 // this interval cannot be processed now because target is not free
|
|
|
3726 // it starts in a register, so it is a possible candidate for spilling
|
|
|
3727 spill_candidate = i;
|
|
|
3728 }
|
|
|
3729 }
|
|
|
3730
|
|
|
3731 if (!processed_interval) {
|
|
|
3732 // no move could be processed because there is a cycle in the move list
|
|
|
3733 // (e.g. r1 -> r2, r2 -> r1), so one interval must be spilled to memory
|
|
|
3734 assert(spill_candidate != -1, "no interval in register for spilling found");
|
|
|
3735
|
|
|
3736 // create a new spill interval and assign a stack slot to it
|
|
|
3737 Interval* from_interval = _mapping_from.at(spill_candidate);
|
|
|
3738 Interval* spill_interval = new Interval(-1);
|
|
|
3739 spill_interval->set_type(from_interval->type());
|
|
|
3740
|
|
|
3741 // add a dummy range because real position is difficult to calculate
|
|
|
3742 // Note: this range is a special case when the integrity of the allocation is checked
|
|
|
3743 spill_interval->add_range(1, 2);
|
|
|
3744
|
|
|
3745 // do not allocate a new spill slot for temporary interval, but
|
|
|
3746 // use spill slot assigned to from_interval. Otherwise moves from
|
|
|
3747 // one stack slot to another can happen (not allowed by LIR_Assembler
|
|
|
3748 int spill_slot = from_interval->canonical_spill_slot();
|
|
|
3749 if (spill_slot < 0) {
|
|
|
3750 spill_slot = allocator()->allocate_spill_slot(type2spill_size[spill_interval->type()] == 2);
|
|
|
3751 from_interval->set_canonical_spill_slot(spill_slot);
|
|
|
3752 }
|
|
|
3753 spill_interval->assign_reg(spill_slot);
|
|
|
3754 allocator()->append_interval(spill_interval);
|
|
|
3755
|
|
|
3756 TRACE_LINEAR_SCAN(4, tty->print_cr("created new Interval %d for spilling", spill_interval->reg_num()));
|
|
|
3757
|
|
|
3758 // insert a move from register to stack and update the mapping
|
|
|
3759 insert_move(from_interval, spill_interval);
|
|
|
3760 _mapping_from.at_put(spill_candidate, spill_interval);
|
|
|
3761 unblock_registers(from_interval);
|
|
|
3762 }
|
|
|
3763 }
|
|
|
3764
|
|
|
3765 // reset to default value
|
|
|
3766 _multiple_reads_allowed = false;
|
|
|
3767
|
|
|
3768 // check that all intervals have been processed
|
|
|
3769 DEBUG_ONLY(check_empty());
|
|
|
3770 }
|
|
|
3771
|
|
|
3772
|
|
|
3773 void MoveResolver::set_insert_position(LIR_List* insert_list, int insert_idx) {
|
|
|
3774 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: setting insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
|
|
|
3775 assert(_insert_list == NULL && _insert_idx == -1, "use move_insert_position instead of set_insert_position when data already set");
|
|
|
3776
|
|
|
3777 create_insertion_buffer(insert_list);
|
|
|
3778 _insert_list = insert_list;
|
|
|
3779 _insert_idx = insert_idx;
|
|
|
3780 }
|
|
|
3781
|
|
|
3782 void MoveResolver::move_insert_position(LIR_List* insert_list, int insert_idx) {
|
|
|
3783 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: moving insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
|
|
|
3784
|
|
|
3785 if (_insert_list != NULL && (insert_list != _insert_list || insert_idx != _insert_idx)) {
|
|
|
3786 // insert position changed -> resolve current mappings
|
|
|
3787 resolve_mappings();
|
|
|
3788 }
|
|
|
3789
|
|
|
3790 if (insert_list != _insert_list) {
|
|
|
3791 // block changed -> append insertion_buffer because it is
|
|
|
3792 // bound to a specific block and create a new insertion_buffer
|
|
|
3793 append_insertion_buffer();
|
|
|
3794 create_insertion_buffer(insert_list);
|
|
|
3795 }
|
|
|
3796
|
|
|
3797 _insert_list = insert_list;
|
|
|
3798 _insert_idx = insert_idx;
|
|
|
3799 }
|
|
|
3800
|
|
|
3801 void MoveResolver::add_mapping(Interval* from_interval, Interval* to_interval) {
|
|
|
3802 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: adding mapping from %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
|
|
|
3803
|
|
|
3804 _mapping_from.append(from_interval);
|
|
|
3805 _mapping_from_opr.append(LIR_OprFact::illegalOpr);
|
|
|
3806 _mapping_to.append(to_interval);
|
|
|
3807 }
|
|
|
3808
|
|
|
3809
|
|
|
3810 void MoveResolver::add_mapping(LIR_Opr from_opr, Interval* to_interval) {
|
|
|
3811 TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: adding mapping from "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
|
|
|
3812 assert(from_opr->is_constant(), "only for constants");
|
|
|
3813
|
|
|
3814 _mapping_from.append(NULL);
|
|
|
3815 _mapping_from_opr.append(from_opr);
|
|
|
3816 _mapping_to.append(to_interval);
|
|
|
3817 }
|
|
|
3818
|
|
|
3819 void MoveResolver::resolve_and_append_moves() {
|
|
|
3820 if (has_mappings()) {
|
|
|
3821 resolve_mappings();
|
|
|
3822 }
|
|
|
3823 append_insertion_buffer();
|
|
|
3824 }
|
|
|
3825
|
|
|
3826
|
|
|
3827
|
|
|
3828 // **** Implementation of Range *************************************
|
|
|
3829
|
|
|
3830 Range::Range(int from, int to, Range* next) :
|
|
|
3831 _from(from),
|
|
|
3832 _to(to),
|
|
|
3833 _next(next)
|
|
|
3834 {
|
|
|
3835 }
|
|
|
3836
|
|
|
3837 // initialize sentinel
|
|
|
3838 Range* Range::_end = NULL;
|
|
|
3839 void Range::initialize() {
|
|
|
3840 _end = new Range(max_jint, max_jint, NULL);
|
|
|
3841 }
|
|
|
3842
|
|
|
3843 int Range::intersects_at(Range* r2) const {
|
|
|
3844 const Range* r1 = this;
|
|
|
3845
|
|
|
3846 assert(r1 != NULL && r2 != NULL, "null ranges not allowed");
|
|
|
3847 assert(r1 != _end && r2 != _end, "empty ranges not allowed");
|
|
|
3848
|
|
|
3849 do {
|
|
|
3850 if (r1->from() < r2->from()) {
|
|
|
3851 if (r1->to() <= r2->from()) {
|
|
|
3852 r1 = r1->next(); if (r1 == _end) return -1;
|
|
|
3853 } else {
|
|
|
3854 return r2->from();
|
|
|
3855 }
|
|
|
3856 } else if (r2->from() < r1->from()) {
|
|
|
3857 if (r2->to() <= r1->from()) {
|
|
|
3858 r2 = r2->next(); if (r2 == _end) return -1;
|
|
|
3859 } else {
|
|
|
3860 return r1->from();
|
|
|
3861 }
|
|
|
3862 } else { // r1->from() == r2->from()
|
|
|
3863 if (r1->from() == r1->to()) {
|
|
|
3864 r1 = r1->next(); if (r1 == _end) return -1;
|
|
|
3865 } else if (r2->from() == r2->to()) {
|
|
|
3866 r2 = r2->next(); if (r2 == _end) return -1;
|
|
|
3867 } else {
|
|
|
3868 return r1->from();
|
|
|
3869 }
|
|
|
3870 }
|
|
|
3871 } while (true);
|
|
|
3872 }
|
|
|
3873
|
|
|
3874 #ifndef PRODUCT
|
|
|
3875 void Range::print(outputStream* out) const {
|
|
|
3876 out->print("[%d, %d[ ", _from, _to);
|
|
|
3877 }
|
|
|
3878 #endif
|
|
|
3879
|
|
|
3880
|
|
|
3881
|
|
|
3882 // **** Implementation of Interval **********************************
|
|
|
3883
|
|
|
3884 // initialize sentinel
|
|
|
3885 Interval* Interval::_end = NULL;
|
|
|
3886 void Interval::initialize() {
|
|
|
3887 Range::initialize();
|
|
|
3888 _end = new Interval(-1);
|
|
|
3889 }
|
|
|
3890
|
|
|
3891 Interval::Interval(int reg_num) :
|
|
|
3892 _reg_num(reg_num),
|
|
|
3893 _type(T_ILLEGAL),
|
|
|
3894 _first(Range::end()),
|
|
|
3895 _use_pos_and_kinds(12),
|
|
|
3896 _current(Range::end()),
|
|
|
3897 _next(_end),
|
|
|
3898 _state(invalidState),
|
|
|
3899 _assigned_reg(LinearScan::any_reg),
|
|
|
3900 _assigned_regHi(LinearScan::any_reg),
|
|
|
3901 _cached_to(-1),
|
|
|
3902 _cached_opr(LIR_OprFact::illegalOpr),
|
|
|
3903 _cached_vm_reg(VMRegImpl::Bad()),
|
|
|
3904 _split_children(0),
|
|
|
3905 _canonical_spill_slot(-1),
|
|
|
3906 _insert_move_when_activated(false),
|
|
|
3907 _register_hint(NULL),
|
|
|
3908 _spill_state(noDefinitionFound),
|
|
|
3909 _spill_definition_pos(-1)
|
|
|
3910 {
|
|
|
3911 _split_parent = this;
|
|
|
3912 _current_split_child = this;
|
|
|
3913 }
|
|
|
3914
|
|
|
3915 int Interval::calc_to() {
|
|
|
3916 assert(_first != Range::end(), "interval has no range");
|
|
|
3917
|
|
|
3918 Range* r = _first;
|
|
|
3919 while (r->next() != Range::end()) {
|
|
|
3920 r = r->next();
|
|
|
3921 }
|
|
|
3922 return r->to();
|
|
|
3923 }
|
|
|
3924
|
|
|
3925
|
|
|
3926 #ifdef ASSERT
|
|
|
3927 // consistency check of split-children
|
|
|
3928 void Interval::check_split_children() {
|
|
|
3929 if (_split_children.length() > 0) {
|
|
|
3930 assert(is_split_parent(), "only split parents can have children");
|
|
|
3931
|
|
|
3932 for (int i = 0; i < _split_children.length(); i++) {
|
|
|
3933 Interval* i1 = _split_children.at(i);
|
|
|
3934
|
|
|
3935 assert(i1->split_parent() == this, "not a split child of this interval");
|
|
|
3936 assert(i1->type() == type(), "must be equal for all split children");
|
|
|
3937 assert(i1->canonical_spill_slot() == canonical_spill_slot(), "must be equal for all split children");
|
|
|
3938
|
|
|
3939 for (int j = i + 1; j < _split_children.length(); j++) {
|
|
|
3940 Interval* i2 = _split_children.at(j);
|
|
|
3941
|
|
|
3942 assert(i1->reg_num() != i2->reg_num(), "same register number");
|
|
|
3943
|
|
|
3944 if (i1->from() < i2->from()) {
|
|
|
3945 assert(i1->to() <= i2->from() && i1->to() < i2->to(), "intervals overlapping");
|
|
|
3946 } else {
|
|
|
3947 assert(i2->from() < i1->from(), "intervals start at same op_id");
|
|
|
3948 assert(i2->to() <= i1->from() && i2->to() < i1->to(), "intervals overlapping");
|
|
|
3949 }
|
|
|
3950 }
|
|
|
3951 }
|
|
|
3952 }
|
|
|
3953 }
|
|
|
3954 #endif // ASSERT
|
|
|
3955
|
|
|
3956 Interval* Interval::register_hint(bool search_split_child) const {
|
|
|
3957 if (!search_split_child) {
|
|
|
3958 return _register_hint;
|
|
|
3959 }
|
|
|
3960
|
|
|
3961 if (_register_hint != NULL) {
|
|
|
3962 assert(_register_hint->is_split_parent(), "ony split parents are valid hint registers");
|
|
|
3963
|
|
|
3964 if (_register_hint->assigned_reg() >= 0 && _register_hint->assigned_reg() < LinearScan::nof_regs) {
|
|
|
3965 return _register_hint;
|
|
|
3966
|
|
|
3967 } else if (_register_hint->_split_children.length() > 0) {
|
|
|
3968 // search the first split child that has a register assigned
|
|
|
3969 int len = _register_hint->_split_children.length();
|
|
|
3970 for (int i = 0; i < len; i++) {
|
|
|
3971 Interval* cur = _register_hint->_split_children.at(i);
|
|
|
3972
|
|
|
3973 if (cur->assigned_reg() >= 0 && cur->assigned_reg() < LinearScan::nof_regs) {
|
|
|
3974 return cur;
|
|
|
3975 }
|
|
|
3976 }
|
|
|
3977 }
|
|
|
3978 }
|
|
|
3979
|
|
|
3980 // no hint interval found that has a register assigned
|
|
|
3981 return NULL;
|
|
|
3982 }
|
|
|
3983
|
|
|
3984
|
|
|
3985 Interval* Interval::split_child_at_op_id(int op_id, LIR_OpVisitState::OprMode mode) {
|
|
|
3986 assert(is_split_parent(), "can only be called for split parents");
|
|
|
3987 assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)");
|
|
|
3988
|
|
|
3989 Interval* result;
|
|
|
3990 if (_split_children.length() == 0) {
|
|
|
3991 result = this;
|
|
|
3992 } else {
|
|
|
3993 result = NULL;
|
|
|
3994 int len = _split_children.length();
|
|
|
3995
|
|
|
3996 // in outputMode, the end of the interval (op_id == cur->to()) is not valid
|
|
|
3997 int to_offset = (mode == LIR_OpVisitState::outputMode ? 0 : 1);
|
|
|
3998
|
|
|
3999 int i;
|
|
|
4000 for (i = 0; i < len; i++) {
|
|
|
4001 Interval* cur = _split_children.at(i);
|
|
|
4002 if (cur->from() <= op_id && op_id < cur->to() + to_offset) {
|
|
|
4003 if (i > 0) {
|
|
|
4004 // exchange current split child to start of list (faster access for next call)
|
|
|
4005 _split_children.at_put(i, _split_children.at(0));
|
|
|
4006 _split_children.at_put(0, cur);
|
|
|
4007 }
|
|
|
4008
|
|
|
4009 // interval found
|
|
|
4010 result = cur;
|
|
|
4011 break;
|
|
|
4012 }
|
|
|
4013 }
|
|
|
4014
|
|
|
4015 #ifdef ASSERT
|
|
|
4016 for (i = 0; i < len; i++) {
|
|
|
4017 Interval* tmp = _split_children.at(i);
|
|
|
4018 if (tmp != result && tmp->from() <= op_id && op_id < tmp->to() + to_offset) {
|
|
|
4019 tty->print_cr("two valid result intervals found for op_id %d: %d and %d", op_id, result->reg_num(), tmp->reg_num());
|
|
|
4020 result->print();
|
|
|
4021 tmp->print();
|
|
|
4022 assert(false, "two valid result intervals found");
|
|
|
4023 }
|
|
|
4024 }
|
|
|
4025 #endif
|
|
|
4026 }
|
|
|
4027
|
|
|
4028 assert(result != NULL, "no matching interval found");
|
|
|
4029 assert(result->covers(op_id, mode), "op_id not covered by interval");
|
|
|
4030
|
|
|
4031 return result;
|
|
|
4032 }
|
|
|
4033
|
|
|
4034
|
|
|
4035 // returns the last split child that ends before the given op_id
|
|
|
4036 Interval* Interval::split_child_before_op_id(int op_id) {
|
|
|
4037 assert(op_id >= 0, "invalid op_id");
|
|
|
4038
|
|
|
4039 Interval* parent = split_parent();
|
|
|
4040 Interval* result = NULL;
|
|
|
4041
|
|
|
4042 int len = parent->_split_children.length();
|
|
|
4043 assert(len > 0, "no split children available");
|
|
|
4044
|
|
|
4045 for (int i = len - 1; i >= 0; i--) {
|
|
|
4046 Interval* cur = parent->_split_children.at(i);
|
|
|
4047 if (cur->to() <= op_id && (result == NULL || result->to() < cur->to())) {
|
|
|
4048 result = cur;
|
|
|
4049 }
|
|
|
4050 }
|
|
|
4051
|
|
|
4052 assert(result != NULL, "no split child found");
|
|
|
4053 return result;
|
|
|
4054 }
|
|
|
4055
|
|
|
4056
|
|
|
4057 // checks if op_id is covered by any split child
|
|
|
4058 bool Interval::split_child_covers(int op_id, LIR_OpVisitState::OprMode mode) {
|
|
|
4059 assert(is_split_parent(), "can only be called for split parents");
|
|
|
4060 assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)");
|
|
|
4061
|
|
|
4062 if (_split_children.length() == 0) {
|
|
|
4063 // simple case if interval was not split
|
|
|
4064 return covers(op_id, mode);
|
|
|
4065
|
|
|
4066 } else {
|
|
|
4067 // extended case: check all split children
|
|
|
4068 int len = _split_children.length();
|
|
|
4069 for (int i = 0; i < len; i++) {
|
|
|
4070 Interval* cur = _split_children.at(i);
|
|
|
4071 if (cur->covers(op_id, mode)) {
|
|
|
4072 return true;
|
|
|
4073 }
|
|
|
4074 }
|
|
|
4075 return false;
|
|
|
4076 }
|
|
|
4077 }
|
|
|
4078
|
|
|
4079
|
|
|
4080 // Note: use positions are sorted descending -> first use has highest index
|
|
|
4081 int Interval::first_usage(IntervalUseKind min_use_kind) const {
|
|
|
4082 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
|
|
|
4083
|
|
|
4084 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
|
|
|
4085 if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
|
|
|
4086 return _use_pos_and_kinds.at(i);
|
|
|
4087 }
|
|
|
4088 }
|
|
|
4089 return max_jint;
|
|
|
4090 }
|
|
|
4091
|
|
|
4092 int Interval::next_usage(IntervalUseKind min_use_kind, int from) const {
|
|
|
4093 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
|
|
|
4094
|
|
|
4095 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
|
|
|
4096 if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) >= min_use_kind) {
|
|
|
4097 return _use_pos_and_kinds.at(i);
|
|
|
4098 }
|
|
|
4099 }
|
|
|
4100 return max_jint;
|
|
|
4101 }
|
|
|
4102
|
|
|
4103 int Interval::next_usage_exact(IntervalUseKind exact_use_kind, int from) const {
|
|
|
4104 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
|
|
|
4105
|
|
|
4106 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
|
|
|
4107 if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) == exact_use_kind) {
|
|
|
4108 return _use_pos_and_kinds.at(i);
|
|
|
4109 }
|
|
|
4110 }
|
|
|
4111 return max_jint;
|
|
|
4112 }
|
|
|
4113
|
|
|
4114 int Interval::previous_usage(IntervalUseKind min_use_kind, int from) const {
|
|
|
4115 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
|
|
|
4116
|
|
|
4117 int prev = 0;
|
|
|
4118 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
|
|
|
4119 if (_use_pos_and_kinds.at(i) > from) {
|
|
|
4120 return prev;
|
|
|
4121 }
|
|
|
4122 if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
|
|
|
4123 prev = _use_pos_and_kinds.at(i);
|
|
|
4124 }
|
|
|
4125 }
|
|
|
4126 return prev;
|
|
|
4127 }
|
|
|
4128
|
|
|
4129 void Interval::add_use_pos(int pos, IntervalUseKind use_kind) {
|
|
|
4130 assert(covers(pos, LIR_OpVisitState::inputMode), "use position not covered by live range");
|
|
|
4131
|
|
|
4132 // do not add use positions for precolored intervals because
|
|
|
4133 // they are never used
|
|
|
4134 if (use_kind != noUse && reg_num() >= LIR_OprDesc::vreg_base) {
|
|
|
4135 #ifdef ASSERT
|
|
|
4136 assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
|
|
|
4137 for (int i = 0; i < _use_pos_and_kinds.length(); i += 2) {
|
|
|
4138 assert(pos <= _use_pos_and_kinds.at(i), "already added a use-position with lower position");
|
|
|
4139 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
|
|
|
4140 if (i > 0) {
|
|
|
4141 assert(_use_pos_and_kinds.at(i) < _use_pos_and_kinds.at(i - 2), "not sorted descending");
|
|
|
4142 }
|
|
|
4143 }
|
|
|
4144 #endif
|
|
|
4145
|
|
|
4146 // Note: add_use is called in descending order, so list gets sorted
|
|
|
4147 // automatically by just appending new use positions
|
|
|
4148 int len = _use_pos_and_kinds.length();
|
|
|
4149 if (len == 0 || _use_pos_and_kinds.at(len - 2) > pos) {
|
|
|
4150 _use_pos_and_kinds.append(pos);
|
|
|
4151 _use_pos_and_kinds.append(use_kind);
|
|
|
4152 } else if (_use_pos_and_kinds.at(len - 1) < use_kind) {
|
|
|
4153 assert(_use_pos_and_kinds.at(len - 2) == pos, "list not sorted correctly");
|
|
|
4154 _use_pos_and_kinds.at_put(len - 1, use_kind);
|
|
|
4155 }
|
|
|
4156 }
|
|
|
4157 }
|
|
|
4158
|
|
|
4159 void Interval::add_range(int from, int to) {
|
|
|
4160 assert(from < to, "invalid range");
|
|
|
4161 assert(first() == Range::end() || to < first()->next()->from(), "not inserting at begin of interval");
|
|
|
4162 assert(from <= first()->to(), "not inserting at begin of interval");
|
|
|
4163
|
|
|
4164 if (first()->from() <= to) {
|
|
|
4165 // join intersecting ranges
|
|
|
4166 first()->set_from(MIN2(from, first()->from()));
|
|
|
4167 first()->set_to (MAX2(to, first()->to()));
|
|
|
4168 } else {
|
|
|
4169 // insert new range
|
|
|
4170 _first = new Range(from, to, first());
|
|
|
4171 }
|
|
|
4172 }
|
|
|
4173
|
|
|
4174 Interval* Interval::new_split_child() {
|
|
|
4175 // allocate new interval
|
|
|
4176 Interval* result = new Interval(-1);
|
|
|
4177 result->set_type(type());
|
|
|
4178
|
|
|
4179 Interval* parent = split_parent();
|
|
|
4180 result->_split_parent = parent;
|
|
|
4181 result->set_register_hint(parent);
|
|
|
4182
|
|
|
4183 // insert new interval in children-list of parent
|
|
|
4184 if (parent->_split_children.length() == 0) {
|
|
|
4185 assert(is_split_parent(), "list must be initialized at first split");
|
|
|
4186
|
|
|
4187 parent->_split_children = IntervalList(4);
|
|
|
4188 parent->_split_children.append(this);
|
|
|
4189 }
|
|
|
4190 parent->_split_children.append(result);
|
|
|
4191
|
|
|
4192 return result;
|
|
|
4193 }
|
|
|
4194
|
|
|
4195 // split this interval at the specified position and return
|
|
|
4196 // the remainder as a new interval.
|
|
|
4197 //
|
|
|
4198 // when an interval is split, a bi-directional link is established between the original interval
|
|
|
4199 // (the split parent) and the intervals that are split off this interval (the split children)
|
|
|
4200 // When a split child is split again, the new created interval is also a direct child
|
|
|
4201 // of the original parent (there is no tree of split children stored, but a flat list)
|
|
|
4202 // All split children are spilled to the same stack slot (stored in _canonical_spill_slot)
|
|
|
4203 //
|
|
|
4204 // Note: The new interval has no valid reg_num
|
|
|
4205 Interval* Interval::split(int split_pos) {
|
|
|
4206 assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
|
|
|
4207
|
|
|
4208 // allocate new interval
|
|
|
4209 Interval* result = new_split_child();
|
|
|
4210
|
|
|
4211 // split the ranges
|
|
|
4212 Range* prev = NULL;
|
|
|
4213 Range* cur = _first;
|
|
|
4214 while (cur != Range::end() && cur->to() <= split_pos) {
|
|
|
4215 prev = cur;
|
|
|
4216 cur = cur->next();
|
|
|
4217 }
|
|
|
4218 assert(cur != Range::end(), "split interval after end of last range");
|
|
|
4219
|
|
|
4220 if (cur->from() < split_pos) {
|
|
|
4221 result->_first = new Range(split_pos, cur->to(), cur->next());
|
|
|
4222 cur->set_to(split_pos);
|
|
|
4223 cur->set_next(Range::end());
|
|
|
4224
|
|
|
4225 } else {
|
|
|
4226 assert(prev != NULL, "split before start of first range");
|
|
|
4227 result->_first = cur;
|
|
|
4228 prev->set_next(Range::end());
|
|
|
4229 }
|
|
|
4230 result->_current = result->_first;
|
|
|
4231 _cached_to = -1; // clear cached value
|
|
|
4232
|
|
|
4233 // split list of use positions
|
|
|
4234 int total_len = _use_pos_and_kinds.length();
|
|
|
4235 int start_idx = total_len - 2;
|
|
|
4236 while (start_idx >= 0 && _use_pos_and_kinds.at(start_idx) < split_pos) {
|
|
|
4237 start_idx -= 2;
|
|
|
4238 }
|
|
|
4239
|
|
|
4240 intStack new_use_pos_and_kinds(total_len - start_idx);
|
|
|
4241 int i;
|
|
|
4242 for (i = start_idx + 2; i < total_len; i++) {
|
|
|
4243 new_use_pos_and_kinds.append(_use_pos_and_kinds.at(i));
|
|
|
4244 }
|
|
|
4245
|
|
|
4246 _use_pos_and_kinds.truncate(start_idx + 2);
|
|
|
4247 result->_use_pos_and_kinds = _use_pos_and_kinds;
|
|
|
4248 _use_pos_and_kinds = new_use_pos_and_kinds;
|
|
|
4249
|
|
|
4250 #ifdef ASSERT
|
|
|
4251 assert(_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
|
|
|
4252 assert(result->_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
|
|
|
4253 assert(_use_pos_and_kinds.length() + result->_use_pos_and_kinds.length() == total_len, "missed some entries");
|
|
|
4254
|
|
|
4255 for (i = 0; i < _use_pos_and_kinds.length(); i += 2) {
|
|
|
4256 assert(_use_pos_and_kinds.at(i) < split_pos, "must be");
|
|
|
4257 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
|
|
|
4258 }
|
|
|
4259 for (i = 0; i < result->_use_pos_and_kinds.length(); i += 2) {
|
|
|
4260 assert(result->_use_pos_and_kinds.at(i) >= split_pos, "must be");
|
|
|
4261 assert(result->_use_pos_and_kinds.at(i + 1) >= firstValidKind && result->_use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
|
|
|
4262 }
|
|
|
4263 #endif
|
|
|
4264
|
|
|
4265 return result;
|
|
|
4266 }
|
|
|
4267
|
|
|
4268 // split this interval at the specified position and return
|
|
|
4269 // the head as a new interval (the original interval is the tail)
|
|
|
4270 //
|
|
|
4271 // Currently, only the first range can be split, and the new interval
|
|
|
4272 // must not have split positions
|
|
|
4273 Interval* Interval::split_from_start(int split_pos) {
|
|
|
4274 assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
|
|
|
4275 assert(split_pos > from() && split_pos < to(), "can only split inside interval");
|
|
|
4276 assert(split_pos > _first->from() && split_pos <= _first->to(), "can only split inside first range");
|
|
|
4277 assert(first_usage(noUse) > split_pos, "can not split when use positions are present");
|
|
|
4278
|
|
|
4279 // allocate new interval
|
|
|
4280 Interval* result = new_split_child();
|
|
|
4281
|
|
|
4282 // the new created interval has only one range (checked by assertion above),
|
|
|
4283 // so the splitting of the ranges is very simple
|
|
|
4284 result->add_range(_first->from(), split_pos);
|
|
|
4285
|
|
|
4286 if (split_pos == _first->to()) {
|
|
|
4287 assert(_first->next() != Range::end(), "must not be at end");
|
|
|
4288 _first = _first->next();
|
|
|
4289 } else {
|
|
|
4290 _first->set_from(split_pos);
|
|
|
4291 }
|
|
|
4292
|
|
|
4293 return result;
|
|
|
4294 }
|
|
|
4295
|
|
|
4296
|
|
|
4297 // returns true if the op_id is inside the interval
|
|
|
4298 bool Interval::covers(int op_id, LIR_OpVisitState::OprMode mode) const {
|
|
|
4299 Range* cur = _first;
|
|
|
4300
|
|
|
4301 while (cur != Range::end() && cur->to() < op_id) {
|
|
|
4302 cur = cur->next();
|
|
|
4303 }
|
|
|
4304 if (cur != Range::end()) {
|
|
|
4305 assert(cur->to() != cur->next()->from(), "ranges not separated");
|
|
|
4306
|
|
|
4307 if (mode == LIR_OpVisitState::outputMode) {
|
|
|
4308 return cur->from() <= op_id && op_id < cur->to();
|
|
|
4309 } else {
|
|
|
4310 return cur->from() <= op_id && op_id <= cur->to();
|
|
|
4311 }
|
|
|
4312 }
|
|
|
4313 return false;
|
|
|
4314 }
|
|
|
4315
|
|
|
4316 // returns true if the interval has any hole between hole_from and hole_to
|
|
|
4317 // (even if the hole has only the length 1)
|
|
|
4318 bool Interval::has_hole_between(int hole_from, int hole_to) {
|
|
|
4319 assert(hole_from < hole_to, "check");
|
|
|
4320 assert(from() <= hole_from && hole_to <= to(), "index out of interval");
|
|
|
4321
|
|
|
4322 Range* cur = _first;
|
|
|
4323 while (cur != Range::end()) {
|
|
|
4324 assert(cur->to() < cur->next()->from(), "no space between ranges");
|
|
|
4325
|
|
|
4326 // hole-range starts before this range -> hole
|
|
|
4327 if (hole_from < cur->from()) {
|
|
|
4328 return true;
|
|
|
4329
|
|
|
4330 // hole-range completely inside this range -> no hole
|
|
|
4331 } else if (hole_to <= cur->to()) {
|
|
|
4332 return false;
|
|
|
4333
|
|
|
4334 // overlapping of hole-range with this range -> hole
|
|
|
4335 } else if (hole_from <= cur->to()) {
|
|
|
4336 return true;
|
|
|
4337 }
|
|
|
4338
|
|
|
4339 cur = cur->next();
|
|
|
4340 }
|
|
|
4341
|
|
|
4342 return false;
|
|
|
4343 }
|
|
|
4344
|
|
|
4345
|
|
|
4346 #ifndef PRODUCT
|
|
|
4347 void Interval::print(outputStream* out) const {
|
|
|
4348 const char* SpillState2Name[] = { "no definition", "no spill store", "one spill store", "store at definition", "start in memory", "no optimization" };
|
|
|
4349 const char* UseKind2Name[] = { "N", "L", "S", "M" };
|
|
|
4350
|
|
|
4351 const char* type_name;
|
|
|
4352 LIR_Opr opr = LIR_OprFact::illegal();
|
|
|
4353 if (reg_num() < LIR_OprDesc::vreg_base) {
|
|
|
4354 type_name = "fixed";
|
|
|
4355 // need a temporary operand for fixed intervals because type() cannot be called
|
|
|
4356 if (assigned_reg() >= pd_first_cpu_reg && assigned_reg() <= pd_last_cpu_reg) {
|
|
|
4357 opr = LIR_OprFact::single_cpu(assigned_reg());
|
|
|
4358 } else if (assigned_reg() >= pd_first_fpu_reg && assigned_reg() <= pd_last_fpu_reg) {
|
|
|
4359 opr = LIR_OprFact::single_fpu(assigned_reg() - pd_first_fpu_reg);
|
|
|
4360 #ifdef IA32
|
|
|
4361 } else if (assigned_reg() >= pd_first_xmm_reg && assigned_reg() <= pd_last_xmm_reg) {
|
|
|
4362 opr = LIR_OprFact::single_xmm(assigned_reg() - pd_first_xmm_reg);
|
|
|
4363 #endif
|
|
|
4364 } else {
|
|
|
4365 ShouldNotReachHere();
|
|
|
4366 }
|
|
|
4367 } else {
|
|
|
4368 type_name = type2name(type());
|
|
|
4369 if (assigned_reg() != -1) {
|
|
|
4370 opr = LinearScan::calc_operand_for_interval(this);
|
|
|
4371 }
|
|
|
4372 }
|
|
|
4373
|
|
|
4374 out->print("%d %s ", reg_num(), type_name);
|
|
|
4375 if (opr->is_valid()) {
|
|
|
4376 out->print("\"");
|
|
|
4377 opr->print(out);
|
|
|
4378 out->print("\" ");
|
|
|
4379 }
|
|
|
4380 out->print("%d %d ", split_parent()->reg_num(), (register_hint(false) != NULL ? register_hint(false)->reg_num() : -1));
|
|
|
4381
|
|
|
4382 // print ranges
|
|
|
4383 Range* cur = _first;
|
|
|
4384 while (cur != Range::end()) {
|
|
|
4385 cur->print(out);
|
|
|
4386 cur = cur->next();
|
|
|
4387 assert(cur != NULL, "range list not closed with range sentinel");
|
|
|
4388 }
|
|
|
4389
|
|
|
4390 // print use positions
|
|
|
4391 int prev = 0;
|
|
|
4392 assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
|
|
|
4393 for (int i =_use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
|
|
|
4394 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
|
|
|
4395 assert(prev < _use_pos_and_kinds.at(i), "use positions not sorted");
|
|
|
4396
|
|
|
4397 out->print("%d %s ", _use_pos_and_kinds.at(i), UseKind2Name[_use_pos_and_kinds.at(i + 1)]);
|
|
|
4398 prev = _use_pos_and_kinds.at(i);
|
|
|
4399 }
|
|
|
4400
|
|
|
4401 out->print(" \"%s\"", SpillState2Name[spill_state()]);
|
|
|
4402 out->cr();
|
|
|
4403 }
|
|
|
4404 #endif
|
|
|
4405
|
|
|
4406
|
|
|
4407
|
|
|
4408 // **** Implementation of IntervalWalker ****************************
|
|
|
4409
|
|
|
4410 IntervalWalker::IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
|
|
|
4411 : _compilation(allocator->compilation())
|
|
|
4412 , _allocator(allocator)
|
|
|
4413 {
|
|
|
4414 _unhandled_first[fixedKind] = unhandled_fixed_first;
|
|
|
4415 _unhandled_first[anyKind] = unhandled_any_first;
|
|
|
4416 _active_first[fixedKind] = Interval::end();
|
|
|
4417 _inactive_first[fixedKind] = Interval::end();
|
|
|
4418 _active_first[anyKind] = Interval::end();
|
|
|
4419 _inactive_first[anyKind] = Interval::end();
|
|
|
4420 _current_position = -1;
|
|
|
4421 _current = NULL;
|
|
|
4422 next_interval();
|
|
|
4423 }
|
|
|
4424
|
|
|
4425
|
|
|
4426 // append interval at top of list
|
|
|
4427 void IntervalWalker::append_unsorted(Interval** list, Interval* interval) {
|
|
|
4428 interval->set_next(*list); *list = interval;
|
|
|
4429 }
|
|
|
4430
|
|
|
4431
|
|
|
4432 // append interval in order of current range from()
|
|
|
4433 void IntervalWalker::append_sorted(Interval** list, Interval* interval) {
|
|
|
4434 Interval* prev = NULL;
|
|
|
4435 Interval* cur = *list;
|
|
|
4436 while (cur->current_from() < interval->current_from()) {
|
|
|
4437 prev = cur; cur = cur->next();
|
|
|
4438 }
|
|
|
4439 if (prev == NULL) {
|
|
|
4440 *list = interval;
|
|
|
4441 } else {
|
|
|
4442 prev->set_next(interval);
|
|
|
4443 }
|
|
|
4444 interval->set_next(cur);
|
|
|
4445 }
|
|
|
4446
|
|
|
4447 void IntervalWalker::append_to_unhandled(Interval** list, Interval* interval) {
|
|
|
4448 assert(interval->from() >= current()->current_from(), "cannot append new interval before current walk position");
|
|
|
4449
|
|
|
4450 Interval* prev = NULL;
|
|
|
4451 Interval* cur = *list;
|
|
|
4452 while (cur->from() < interval->from() || (cur->from() == interval->from() && cur->first_usage(noUse) < interval->first_usage(noUse))) {
|
|
|
4453 prev = cur; cur = cur->next();
|
|
|
4454 }
|
|
|
4455 if (prev == NULL) {
|
|
|
4456 *list = interval;
|
|
|
4457 } else {
|
|
|
4458 prev->set_next(interval);
|
|
|
4459 }
|
|
|
4460 interval->set_next(cur);
|
|
|
4461 }
|
|
|
4462
|
|
|
4463
|
|
|
4464 inline bool IntervalWalker::remove_from_list(Interval** list, Interval* i) {
|
|
|
4465 while (*list != Interval::end() && *list != i) {
|
|
|
4466 list = (*list)->next_addr();
|
|
|
4467 }
|
|
|
4468 if (*list != Interval::end()) {
|
|
|
4469 assert(*list == i, "check");
|
|
|
4470 *list = (*list)->next();
|
|
|
4471 return true;
|
|
|
4472 } else {
|
|
|
4473 return false;
|
|
|
4474 }
|
|
|
4475 }
|
|
|
4476
|
|
|
4477 void IntervalWalker::remove_from_list(Interval* i) {
|
|
|
4478 bool deleted;
|
|
|
4479
|
|
|
4480 if (i->state() == activeState) {
|
|
|
4481 deleted = remove_from_list(active_first_addr(anyKind), i);
|
|
|
4482 } else {
|
|
|
4483 assert(i->state() == inactiveState, "invalid state");
|
|
|
4484 deleted = remove_from_list(inactive_first_addr(anyKind), i);
|
|
|
4485 }
|
|
|
4486
|
|
|
4487 assert(deleted, "interval has not been found in list");
|
|
|
4488 }
|
|
|
4489
|
|
|
4490
|
|
|
4491 void IntervalWalker::walk_to(IntervalState state, int from) {
|
|
|
4492 assert (state == activeState || state == inactiveState, "wrong state");
|
|
|
4493 for_each_interval_kind(kind) {
|
|
|
4494 Interval** prev = state == activeState ? active_first_addr(kind) : inactive_first_addr(kind);
|
|
|
4495 Interval* next = *prev;
|
|
|
4496 while (next->current_from() <= from) {
|
|
|
4497 Interval* cur = next;
|
|
|
4498 next = cur->next();
|
|
|
4499
|
|
|
4500 bool range_has_changed = false;
|
|
|
4501 while (cur->current_to() <= from) {
|
|
|
4502 cur->next_range();
|
|
|
4503 range_has_changed = true;
|
|
|
4504 }
|
|
|
4505
|
|
|
4506 // also handle move from inactive list to active list
|
|
|
4507 range_has_changed = range_has_changed || (state == inactiveState && cur->current_from() <= from);
|
|
|
4508
|
|
|
4509 if (range_has_changed) {
|
|
|
4510 // remove cur from list
|
|
|
4511 *prev = next;
|
|
|
4512 if (cur->current_at_end()) {
|
|
|
4513 // move to handled state (not maintained as a list)
|
|
|
4514 cur->set_state(handledState);
|
|
|
4515 interval_moved(cur, kind, state, handledState);
|
|
|
4516 } else if (cur->current_from() <= from){
|
|
|
4517 // sort into active list
|
|
|
4518 append_sorted(active_first_addr(kind), cur);
|
|
|
4519 cur->set_state(activeState);
|
|
|
4520 if (*prev == cur) {
|
|
|
4521 assert(state == activeState, "check");
|
|
|
4522 prev = cur->next_addr();
|
|
|
4523 }
|
|
|
4524 interval_moved(cur, kind, state, activeState);
|
|
|
4525 } else {
|
|
|
4526 // sort into inactive list
|
|
|
4527 append_sorted(inactive_first_addr(kind), cur);
|
|
|
4528 cur->set_state(inactiveState);
|
|
|
4529 if (*prev == cur) {
|
|
|
4530 assert(state == inactiveState, "check");
|
|
|
4531 prev = cur->next_addr();
|
|
|
4532 }
|
|
|
4533 interval_moved(cur, kind, state, inactiveState);
|
|
|
4534 }
|
|
|
4535 } else {
|
|
|
4536 prev = cur->next_addr();
|
|
|
4537 continue;
|
|
|
4538 }
|
|
|
4539 }
|
|
|
4540 }
|
|
|
4541 }
|
|
|
4542
|
|
|
4543
|
|
|
4544 void IntervalWalker::next_interval() {
|
|
|
4545 IntervalKind kind;
|
|
|
4546 Interval* any = _unhandled_first[anyKind];
|
|
|
4547 Interval* fixed = _unhandled_first[fixedKind];
|
|
|
4548
|
|
|
4549 if (any != Interval::end()) {
|
|
|
4550 // intervals may start at same position -> prefer fixed interval
|
|
|
4551 kind = fixed != Interval::end() && fixed->from() <= any->from() ? fixedKind : anyKind;
|
|
|
4552
|
|
|
4553 assert (kind == fixedKind && fixed->from() <= any->from() ||
|
|
|
4554 kind == anyKind && any->from() <= fixed->from(), "wrong interval!!!");
|
|
|
4555 assert(any == Interval::end() || fixed == Interval::end() || any->from() != fixed->from() || kind == fixedKind, "if fixed and any-Interval start at same position, fixed must be processed first");
|
|
|
4556
|
|
|
4557 } else if (fixed != Interval::end()) {
|
|
|
4558 kind = fixedKind;
|
|
|
4559 } else {
|
|
|
4560 _current = NULL; return;
|
|
|
4561 }
|
|
|
4562 _current_kind = kind;
|
|
|
4563 _current = _unhandled_first[kind];
|
|
|
4564 _unhandled_first[kind] = _current->next();
|
|
|
4565 _current->set_next(Interval::end());
|
|
|
4566 _current->rewind_range();
|
|
|
4567 }
|
|
|
4568
|
|
|
4569
|
|
|
4570 void IntervalWalker::walk_to(int lir_op_id) {
|
|
|
4571 assert(_current_position <= lir_op_id, "can not walk backwards");
|
|
|
4572 while (current() != NULL) {
|
|
|
4573 bool is_active = current()->from() <= lir_op_id;
|
|
|
4574 int id = is_active ? current()->from() : lir_op_id;
|
|
|
4575
|
|
|
4576 TRACE_LINEAR_SCAN(2, if (_current_position < id) { tty->cr(); tty->print_cr("walk_to(%d) **************************************************************", id); })
|
|
|
4577
|
|
|
4578 // set _current_position prior to call of walk_to
|
|
|
4579 _current_position = id;
|
|
|
4580
|
|
|
4581 // call walk_to even if _current_position == id
|
|
|
4582 walk_to(activeState, id);
|
|
|
4583 walk_to(inactiveState, id);
|
|
|
4584
|
|
|
4585 if (is_active) {
|
|
|
4586 current()->set_state(activeState);
|
|
|
4587 if (activate_current()) {
|
|
|
4588 append_sorted(active_first_addr(current_kind()), current());
|
|
|
4589 interval_moved(current(), current_kind(), unhandledState, activeState);
|
|
|
4590 }
|
|
|
4591
|
|
|
4592 next_interval();
|
|
|
4593 } else {
|
|
|
4594 return;
|
|
|
4595 }
|
|
|
4596 }
|
|
|
4597 }
|
|
|
4598
|
|
|
4599 void IntervalWalker::interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to) {
|
|
|
4600 #ifndef PRODUCT
|
|
|
4601 if (TraceLinearScanLevel >= 4) {
|
|
|
4602 #define print_state(state) \
|
|
|
4603 switch(state) {\
|
|
|
4604 case unhandledState: tty->print("unhandled"); break;\
|
|
|
4605 case activeState: tty->print("active"); break;\
|
|
|
4606 case inactiveState: tty->print("inactive"); break;\
|
|
|
4607 case handledState: tty->print("handled"); break;\
|
|
|
4608 default: ShouldNotReachHere(); \
|
|
|
4609 }
|
|
|
4610
|
|
|
4611 print_state(from); tty->print(" to "); print_state(to);
|
|
|
4612 tty->fill_to(23);
|
|
|
4613 interval->print();
|
|
|
4614
|
|
|
4615 #undef print_state
|
|
|
4616 }
|
|
|
4617 #endif
|
|
|
4618 }
|
|
|
4619
|
|
|
4620
|
|
|
4621
|
|
|
4622 // **** Implementation of LinearScanWalker **************************
|
|
|
4623
|
|
|
4624 LinearScanWalker::LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
|
|
|
4625 : IntervalWalker(allocator, unhandled_fixed_first, unhandled_any_first)
|
|
|
4626 , _move_resolver(allocator)
|
|
|
4627 {
|
|
|
4628 for (int i = 0; i < LinearScan::nof_regs; i++) {
|
|
|
4629 _spill_intervals[i] = new IntervalList(2);
|
|
|
4630 }
|
|
|
4631 }
|
|
|
4632
|
|
|
4633
|
|
|
4634 inline void LinearScanWalker::init_use_lists(bool only_process_use_pos) {
|
|
|
4635 for (int i = _first_reg; i <= _last_reg; i++) {
|
|
|
4636 _use_pos[i] = max_jint;
|
|
|
4637
|
|
|
4638 if (!only_process_use_pos) {
|
|
|
4639 _block_pos[i] = max_jint;
|
|
|
4640 _spill_intervals[i]->clear();
|
|
|
4641 }
|
|
|
4642 }
|
|
|
4643 }
|
|
|
4644
|
|
|
4645 inline void LinearScanWalker::exclude_from_use(int reg) {
|
|
|
4646 assert(reg < LinearScan::nof_regs, "interval must have a register assigned (stack slots not allowed)");
|
|
|
4647 if (reg >= _first_reg && reg <= _last_reg) {
|
|
|
4648 _use_pos[reg] = 0;
|
|
|
4649 }
|
|
|
4650 }
|
|
|
4651 inline void LinearScanWalker::exclude_from_use(Interval* i) {
|
|
|
4652 assert(i->assigned_reg() != any_reg, "interval has no register assigned");
|
|
|
4653
|
|
|
4654 exclude_from_use(i->assigned_reg());
|
|
|
4655 exclude_from_use(i->assigned_regHi());
|
|
|
4656 }
|
|
|
4657
|
|
|
4658 inline void LinearScanWalker::set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos) {
|
|
|
4659 assert(use_pos != 0, "must use exclude_from_use to set use_pos to 0");
|
|
|
4660
|
|
|
4661 if (reg >= _first_reg && reg <= _last_reg) {
|
|
|
4662 if (_use_pos[reg] > use_pos) {
|
|
|
4663 _use_pos[reg] = use_pos;
|
|
|
4664 }
|
|
|
4665 if (!only_process_use_pos) {
|
|
|
4666 _spill_intervals[reg]->append(i);
|
|
|
4667 }
|
|
|
4668 }
|
|
|
4669 }
|
|
|
4670 inline void LinearScanWalker::set_use_pos(Interval* i, int use_pos, bool only_process_use_pos) {
|
|
|
4671 assert(i->assigned_reg() != any_reg, "interval has no register assigned");
|
|
|
4672 if (use_pos != -1) {
|
|
|
4673 set_use_pos(i->assigned_reg(), i, use_pos, only_process_use_pos);
|
|
|
4674 set_use_pos(i->assigned_regHi(), i, use_pos, only_process_use_pos);
|
|
|
4675 }
|
|
|
4676 }
|
|
|
4677
|
|
|
4678 inline void LinearScanWalker::set_block_pos(int reg, Interval* i, int block_pos) {
|
|
|
4679 if (reg >= _first_reg && reg <= _last_reg) {
|
|
|
4680 if (_block_pos[reg] > block_pos) {
|
|
|
4681 _block_pos[reg] = block_pos;
|
|
|
4682 }
|
|
|
4683 if (_use_pos[reg] > block_pos) {
|
|
|
4684 _use_pos[reg] = block_pos;
|
|
|
4685 }
|
|
|
4686 }
|
|
|
4687 }
|
|
|
4688 inline void LinearScanWalker::set_block_pos(Interval* i, int block_pos) {
|
|
|
4689 assert(i->assigned_reg() != any_reg, "interval has no register assigned");
|
|
|
4690 if (block_pos != -1) {
|
|
|
4691 set_block_pos(i->assigned_reg(), i, block_pos);
|
|
|
4692 set_block_pos(i->assigned_regHi(), i, block_pos);
|
|
|
4693 }
|
|
|
4694 }
|
|
|
4695
|
|
|
4696
|
|
|
4697 void LinearScanWalker::free_exclude_active_fixed() {
|
|
|
4698 Interval* list = active_first(fixedKind);
|
|
|
4699 while (list != Interval::end()) {
|
|
|
4700 assert(list->assigned_reg() < LinearScan::nof_regs, "active interval must have a register assigned");
|
|
|
4701 exclude_from_use(list);
|
|
|
4702 list = list->next();
|
|
|
4703 }
|
|
|
4704 }
|
|
|
4705
|
|
|
4706 void LinearScanWalker::free_exclude_active_any() {
|
|
|
4707 Interval* list = active_first(anyKind);
|
|
|
4708 while (list != Interval::end()) {
|
|
|
4709 exclude_from_use(list);
|
|
|
4710 list = list->next();
|
|
|
4711 }
|
|
|
4712 }
|
|
|
4713
|
|
|
4714 void LinearScanWalker::free_collect_inactive_fixed(Interval* cur) {
|
|
|
4715 Interval* list = inactive_first(fixedKind);
|
|
|
4716 while (list != Interval::end()) {
|
|
|
4717 if (cur->to() <= list->current_from()) {
|
|
|
4718 assert(list->current_intersects_at(cur) == -1, "must not intersect");
|
|
|
4719 set_use_pos(list, list->current_from(), true);
|
|
|
4720 } else {
|
|
|
4721 set_use_pos(list, list->current_intersects_at(cur), true);
|
|
|
4722 }
|
|
|
4723 list = list->next();
|
|
|
4724 }
|
|
|
4725 }
|
|
|
4726
|
|
|
4727 void LinearScanWalker::free_collect_inactive_any(Interval* cur) {
|
|
|
4728 Interval* list = inactive_first(anyKind);
|
|
|
4729 while (list != Interval::end()) {
|
|
|
4730 set_use_pos(list, list->current_intersects_at(cur), true);
|
|
|
4731 list = list->next();
|
|
|
4732 }
|
|
|
4733 }
|
|
|
4734
|
|
|
4735 void LinearScanWalker::free_collect_unhandled(IntervalKind kind, Interval* cur) {
|
|
|
4736 Interval* list = unhandled_first(kind);
|
|
|
4737 while (list != Interval::end()) {
|
|
|
4738 set_use_pos(list, list->intersects_at(cur), true);
|
|
|
4739 if (kind == fixedKind && cur->to() <= list->from()) {
|
|
|
4740 set_use_pos(list, list->from(), true);
|
|
|
4741 }
|
|
|
4742 list = list->next();
|
|
|
4743 }
|
|
|
4744 }
|
|
|
4745
|
|
|
4746 void LinearScanWalker::spill_exclude_active_fixed() {
|
|
|
4747 Interval* list = active_first(fixedKind);
|
|
|
4748 while (list != Interval::end()) {
|
|
|
4749 exclude_from_use(list);
|
|
|
4750 list = list->next();
|
|
|
4751 }
|
|
|
4752 }
|
|
|
4753
|
|
|
4754 void LinearScanWalker::spill_block_unhandled_fixed(Interval* cur) {
|
|
|
4755 Interval* list = unhandled_first(fixedKind);
|
|
|
4756 while (list != Interval::end()) {
|
|
|
4757 set_block_pos(list, list->intersects_at(cur));
|
|
|
4758 list = list->next();
|
|
|
4759 }
|
|
|
4760 }
|
|
|
4761
|
|
|
4762 void LinearScanWalker::spill_block_inactive_fixed(Interval* cur) {
|
|
|
4763 Interval* list = inactive_first(fixedKind);
|
|
|
4764 while (list != Interval::end()) {
|
|
|
4765 if (cur->to() > list->current_from()) {
|
|
|
4766 set_block_pos(list, list->current_intersects_at(cur));
|
|
|
4767 } else {
|
|
|
4768 assert(list->current_intersects_at(cur) == -1, "invalid optimization: intervals intersect");
|
|
|
4769 }
|
|
|
4770
|
|
|
4771 list = list->next();
|
|
|
4772 }
|
|
|
4773 }
|
|
|
4774
|
|
|
4775 void LinearScanWalker::spill_collect_active_any() {
|
|
|
4776 Interval* list = active_first(anyKind);
|
|
|
4777 while (list != Interval::end()) {
|
|
|
4778 set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
|
|
|
4779 list = list->next();
|
|
|
4780 }
|
|
|
4781 }
|
|
|
4782
|
|
|
4783 void LinearScanWalker::spill_collect_inactive_any(Interval* cur) {
|
|
|
4784 Interval* list = inactive_first(anyKind);
|
|
|
4785 while (list != Interval::end()) {
|
|
|
4786 if (list->current_intersects(cur)) {
|
|
|
4787 set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
|
|
|
4788 }
|
|
|
4789 list = list->next();
|
|
|
4790 }
|
|
|
4791 }
|
|
|
4792
|
|
|
4793
|
|
|
4794 void LinearScanWalker::insert_move(int op_id, Interval* src_it, Interval* dst_it) {
|
|
|
4795 // output all moves here. When source and target are equal, the move is
|
|
|
4796 // optimized away later in assign_reg_nums
|
|
|
4797
|
|
|
4798 op_id = (op_id + 1) & ~1;
|
|
|
4799 BlockBegin* op_block = allocator()->block_of_op_with_id(op_id);
|
|
|
4800 assert(op_id > 0 && allocator()->block_of_op_with_id(op_id - 2) == op_block, "cannot insert move at block boundary");
|
|
|
4801
|
|
|
4802 // calculate index of instruction inside instruction list of current block
|
|
|
4803 // the minimal index (for a block with no spill moves) can be calculated because the
|
|
|
4804 // numbering of instructions is known.
|
|
|
4805 // When the block already contains spill moves, the index must be increased until the
|
|
|
4806 // correct index is reached.
|
|
|
4807 LIR_OpList* list = op_block->lir()->instructions_list();
|
|
|
4808 int index = (op_id - list->at(0)->id()) / 2;
|
|
|
4809 assert(list->at(index)->id() <= op_id, "error in calculation");
|
|
|
4810
|
|
|
4811 while (list->at(index)->id() != op_id) {
|
|
|
4812 index++;
|
|
|
4813 assert(0 <= index && index < list->length(), "index out of bounds");
|
|
|
4814 }
|
|
|
4815 assert(1 <= index && index < list->length(), "index out of bounds");
|
|
|
4816 assert(list->at(index)->id() == op_id, "error in calculation");
|
|
|
4817
|
|
|
4818 // insert new instruction before instruction at position index
|
|
|
4819 _move_resolver.move_insert_position(op_block->lir(), index - 1);
|
|
|
4820 _move_resolver.add_mapping(src_it, dst_it);
|
|
|
4821 }
|
|
|
4822
|
|
|
4823
|
|
|
4824 int LinearScanWalker::find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos) {
|
|
|
4825 int from_block_nr = min_block->linear_scan_number();
|
|
|
4826 int to_block_nr = max_block->linear_scan_number();
|
|
|
4827
|
|
|
4828 assert(0 <= from_block_nr && from_block_nr < block_count(), "out of range");
|
|
|
4829 assert(0 <= to_block_nr && to_block_nr < block_count(), "out of range");
|
|
|
4830 assert(from_block_nr < to_block_nr, "must cross block boundary");
|
|
|
4831
|
|
|
4832 // Try to split at end of max_block. If this would be after
|
|
|
4833 // max_split_pos, then use the begin of max_block
|
|
|
4834 int optimal_split_pos = max_block->last_lir_instruction_id() + 2;
|
|
|
4835 if (optimal_split_pos > max_split_pos) {
|
|
|
4836 optimal_split_pos = max_block->first_lir_instruction_id();
|
|
|
4837 }
|
|
|
4838
|
|
|
4839 int min_loop_depth = max_block->loop_depth();
|
|
|
4840 for (int i = to_block_nr - 1; i >= from_block_nr; i--) {
|
|
|
4841 BlockBegin* cur = block_at(i);
|
|
|
4842
|
|
|
4843 if (cur->loop_depth() < min_loop_depth) {
|
|
|
4844 // block with lower loop-depth found -> split at the end of this block
|
|
|
4845 min_loop_depth = cur->loop_depth();
|
|
|
4846 optimal_split_pos = cur->last_lir_instruction_id() + 2;
|
|
|
4847 }
|
|
|
4848 }
|
|
|
4849 assert(optimal_split_pos > allocator()->max_lir_op_id() || allocator()->is_block_begin(optimal_split_pos), "algorithm must move split pos to block boundary");
|
|
|
4850
|
|
|
4851 return optimal_split_pos;
|
|
|
4852 }
|
|
|
4853
|
|
|
4854
|
|
|
4855 int LinearScanWalker::find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization) {
|
|
|
4856 int optimal_split_pos = -1;
|
|
|
4857 if (min_split_pos == max_split_pos) {
|
|
|
4858 // trivial case, no optimization of split position possible
|
|
|
4859 TRACE_LINEAR_SCAN(4, tty->print_cr(" min-pos and max-pos are equal, no optimization possible"));
|
|
|
4860 optimal_split_pos = min_split_pos;
|
|
|
4861
|
|
|
4862 } else {
|
|
|
4863 assert(min_split_pos < max_split_pos, "must be true then");
|
|
|
4864 assert(min_split_pos > 0, "cannot access min_split_pos - 1 otherwise");
|
|
|
4865
|
|
|
4866 // reason for using min_split_pos - 1: when the minimal split pos is exactly at the
|
|
|
4867 // beginning of a block, then min_split_pos is also a possible split position.
|
|
|
4868 // Use the block before as min_block, because then min_block->last_lir_instruction_id() + 2 == min_split_pos
|
|
|
4869 BlockBegin* min_block = allocator()->block_of_op_with_id(min_split_pos - 1);
|
|
|
4870
|
|
|
4871 // reason for using max_split_pos - 1: otherwise there would be an assertion failure
|
|
|
4872 // when an interval ends at the end of the last block of the method
|
|
|
4873 // (in this case, max_split_pos == allocator()->max_lir_op_id() + 2, and there is no
|
|
|
4874 // block at this op_id)
|
|
|
4875 BlockBegin* max_block = allocator()->block_of_op_with_id(max_split_pos - 1);
|
|
|
4876
|
|
|
4877 assert(min_block->linear_scan_number() <= max_block->linear_scan_number(), "invalid order");
|
|
|
4878 if (min_block == max_block) {
|
|
|
4879 // split position cannot be moved to block boundary, so split as late as possible
|
|
|
4880 TRACE_LINEAR_SCAN(4, tty->print_cr(" cannot move split pos to block boundary because min_pos and max_pos are in same block"));
|
|
|
4881 optimal_split_pos = max_split_pos;
|
|
|
4882
|
|
|
4883 } else if (it->has_hole_between(max_split_pos - 1, max_split_pos) && !allocator()->is_block_begin(max_split_pos)) {
|
|
|
4884 // Do not move split position if the interval has a hole before max_split_pos.
|
|
|
4885 // Intervals resulting from Phi-Functions have more than one definition (marked
|
|
|
4886 // as mustHaveRegister) with a hole before each definition. When the register is needed
|
|
|
4887 // for the second definition, an earlier reloading is unnecessary.
|
|
|
4888 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has hole just before max_split_pos, so splitting at max_split_pos"));
|
|
|
4889 optimal_split_pos = max_split_pos;
|
|
|
4890
|
|
|
4891 } else {
|
|
|
4892 // seach optimal block boundary between min_split_pos and max_split_pos
|
|
|
4893 TRACE_LINEAR_SCAN(4, tty->print_cr(" moving split pos to optimal block boundary between block B%d and B%d", min_block->block_id(), max_block->block_id()));
|
|
|
4894
|
|
|
4895 if (do_loop_optimization) {
|
|
|
4896 // Loop optimization: if a loop-end marker is found between min- and max-position,
|
|
|
4897 // then split before this loop
|
|
|
4898 int loop_end_pos = it->next_usage_exact(loopEndMarker, min_block->last_lir_instruction_id() + 2);
|
|
|
4899 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization: loop end found at pos %d", loop_end_pos));
|
|
|
4900
|
|
|
4901 assert(loop_end_pos > min_split_pos, "invalid order");
|
|
|
4902 if (loop_end_pos < max_split_pos) {
|
|
|
4903 // loop-end marker found between min- and max-position
|
|
|
4904 // if it is not the end marker for the same loop as the min-position, then move
|
|
|
4905 // the max-position to this loop block.
|
|
|
4906 // Desired result: uses tagged as shouldHaveRegister inside a loop cause a reloading
|
|
|
4907 // of the interval (normally, only mustHaveRegister causes a reloading)
|
|
|
4908 BlockBegin* loop_block = allocator()->block_of_op_with_id(loop_end_pos);
|
|
|
4909
|
|
|
4910 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval is used in loop that ends in block B%d, so trying to move max_block back from B%d to B%d", loop_block->block_id(), max_block->block_id(), loop_block->block_id()));
|
|
|
4911 assert(loop_block != min_block, "loop_block and min_block must be different because block boundary is needed between");
|
|
|
4912
|
|
|
4913 optimal_split_pos = find_optimal_split_pos(min_block, loop_block, loop_block->last_lir_instruction_id() + 2);
|
|
|
4914 if (optimal_split_pos == loop_block->last_lir_instruction_id() + 2) {
|
|
|
4915 optimal_split_pos = -1;
|
|
|
4916 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization not necessary"));
|
|
|
4917 } else {
|
|
|
4918 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization successful"));
|
|
|
4919 }
|
|
|
4920 }
|
|
|
4921 }
|
|
|
4922
|
|
|
4923 if (optimal_split_pos == -1) {
|
|
|
4924 // not calculated by loop optimization
|
|
|
4925 optimal_split_pos = find_optimal_split_pos(min_block, max_block, max_split_pos);
|
|
|
4926 }
|
|
|
4927 }
|
|
|
4928 }
|
|
|
4929 TRACE_LINEAR_SCAN(4, tty->print_cr(" optimal split position: %d", optimal_split_pos));
|
|
|
4930
|
|
|
4931 return optimal_split_pos;
|
|
|
4932 }
|
|
|
4933
|
|
|
4934
|
|
|
4935 /*
|
|
|
4936 split an interval at the optimal position between min_split_pos and
|
|
|
4937 max_split_pos in two parts:
|
|
|
4938 1) the left part has already a location assigned
|
|
|
4939 2) the right part is sorted into to the unhandled-list
|
|
|
4940 */
|
|
|
4941 void LinearScanWalker::split_before_usage(Interval* it, int min_split_pos, int max_split_pos) {
|
|
|
4942 TRACE_LINEAR_SCAN(2, tty->print ("----- splitting interval: "); it->print());
|
|
|
4943 TRACE_LINEAR_SCAN(2, tty->print_cr(" between %d and %d", min_split_pos, max_split_pos));
|
|
|
4944
|
|
|
4945 assert(it->from() < min_split_pos, "cannot split at start of interval");
|
|
|
4946 assert(current_position() < min_split_pos, "cannot split before current position");
|
|
|
4947 assert(min_split_pos <= max_split_pos, "invalid order");
|
|
|
4948 assert(max_split_pos <= it->to(), "cannot split after end of interval");
|
|
|
4949
|
|
|
4950 int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, true);
|
|
|
4951
|
|
|
4952 assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
|
|
|
4953 assert(optimal_split_pos <= it->to(), "cannot split after end of interval");
|
|
|
4954 assert(optimal_split_pos > it->from(), "cannot split at start of interval");
|
|
|
4955
|
|
|
4956 if (optimal_split_pos == it->to() && it->next_usage(mustHaveRegister, min_split_pos) == max_jint) {
|
|
|
4957 // the split position would be just before the end of the interval
|
|
|
4958 // -> no split at all necessary
|
|
|
4959 TRACE_LINEAR_SCAN(4, tty->print_cr(" no split necessary because optimal split position is at end of interval"));
|
|
|
4960 return;
|
|
|
4961 }
|
|
|
4962
|
|
|
4963 // must calculate this before the actual split is performed and before split position is moved to odd op_id
|
|
|
4964 bool move_necessary = !allocator()->is_block_begin(optimal_split_pos) && !it->has_hole_between(optimal_split_pos - 1, optimal_split_pos);
|
|
|
4965
|
|
|
4966 if (!allocator()->is_block_begin(optimal_split_pos)) {
|
|
|
4967 // move position before actual instruction (odd op_id)
|
|
|
4968 optimal_split_pos = (optimal_split_pos - 1) | 1;
|
|
|
4969 }
|
|
|
4970
|
|
|
4971 TRACE_LINEAR_SCAN(4, tty->print_cr(" splitting at position %d", optimal_split_pos));
|
|
|
4972 assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
|
|
|
4973 assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
|
|
|
4974
|
|
|
4975 Interval* split_part = it->split(optimal_split_pos);
|
|
|
4976
|
|
|
4977 allocator()->append_interval(split_part);
|
|
|
4978 allocator()->copy_register_flags(it, split_part);
|
|
|
4979 split_part->set_insert_move_when_activated(move_necessary);
|
|
|
4980 append_to_unhandled(unhandled_first_addr(anyKind), split_part);
|
|
|
4981
|
|
|
4982 TRACE_LINEAR_SCAN(2, tty->print_cr(" split interval in two parts (insert_move_when_activated: %d)", move_necessary));
|
|
|
4983 TRACE_LINEAR_SCAN(2, tty->print (" "); it->print());
|
|
|
4984 TRACE_LINEAR_SCAN(2, tty->print (" "); split_part->print());
|
|
|
4985 }
|
|
|
4986
|
|
|
4987 /*
|
|
|
4988 split an interval at the optimal position between min_split_pos and
|
|
|
4989 max_split_pos in two parts:
|
|
|
4990 1) the left part has already a location assigned
|
|
|
4991 2) the right part is always on the stack and therefore ignored in further processing
|
|
|
4992 */
|
|
|
4993 void LinearScanWalker::split_for_spilling(Interval* it) {
|
|
|
4994 // calculate allowed range of splitting position
|
|
|
4995 int max_split_pos = current_position();
|
|
|
4996 int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, max_split_pos) + 1, it->from());
|
|
|
4997
|
|
|
4998 TRACE_LINEAR_SCAN(2, tty->print ("----- splitting and spilling interval: "); it->print());
|
|
|
4999 TRACE_LINEAR_SCAN(2, tty->print_cr(" between %d and %d", min_split_pos, max_split_pos));
|
|
|
5000
|
|
|
5001 assert(it->state() == activeState, "why spill interval that is not active?");
|
|
|
5002 assert(it->from() <= min_split_pos, "cannot split before start of interval");
|
|
|
5003 assert(min_split_pos <= max_split_pos, "invalid order");
|
|
|
5004 assert(max_split_pos < it->to(), "cannot split at end end of interval");
|
|
|
5005 assert(current_position() < it->to(), "interval must not end before current position");
|
|
|
5006
|
|
|
5007 if (min_split_pos == it->from()) {
|
|
|
5008 // the whole interval is never used, so spill it entirely to memory
|
|
|
5009 TRACE_LINEAR_SCAN(2, tty->print_cr(" spilling entire interval because split pos is at beginning of interval"));
|
|
|
5010 assert(it->first_usage(shouldHaveRegister) > current_position(), "interval must not have use position before current_position");
|
|
|
5011
|
|
|
5012 allocator()->assign_spill_slot(it);
|
|
|
5013 allocator()->change_spill_state(it, min_split_pos);
|
|
|
5014
|
|
|
5015 // Also kick parent intervals out of register to memory when they have no use
|
|
|
5016 // position. This avoids short interval in register surrounded by intervals in
|
|
|
5017 // memory -> avoid useless moves from memory to register and back
|
|
|
5018 Interval* parent = it;
|
|
|
5019 while (parent != NULL && parent->is_split_child()) {
|
|
|
5020 parent = parent->split_child_before_op_id(parent->from());
|
|
|
5021
|
|
|
5022 if (parent->assigned_reg() < LinearScan::nof_regs) {
|
|
|
5023 if (parent->first_usage(shouldHaveRegister) == max_jint) {
|
|
|
5024 // parent is never used, so kick it out of its assigned register
|
|
|
5025 TRACE_LINEAR_SCAN(4, tty->print_cr(" kicking out interval %d out of its register because it is never used", parent->reg_num()));
|
|
|
5026 allocator()->assign_spill_slot(parent);
|
|
|
5027 } else {
|
|
|
5028 // do not go further back because the register is actually used by the interval
|
|
|
5029 parent = NULL;
|
|
|
5030 }
|
|
|
5031 }
|
|
|
5032 }
|
|
|
5033
|
|
|
5034 } else {
|
|
|
5035 // search optimal split pos, split interval and spill only the right hand part
|
|
|
5036 int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, false);
|
|
|
5037
|
|
|
5038 assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
|
|
|
5039 assert(optimal_split_pos < it->to(), "cannot split at end of interval");
|
|
|
5040 assert(optimal_split_pos >= it->from(), "cannot split before start of interval");
|
|
|
5041
|
|
|
5042 if (!allocator()->is_block_begin(optimal_split_pos)) {
|
|
|
5043 // move position before actual instruction (odd op_id)
|
|
|
5044 optimal_split_pos = (optimal_split_pos - 1) | 1;
|
|
|
5045 }
|
|
|
5046
|
|
|
5047 TRACE_LINEAR_SCAN(4, tty->print_cr(" splitting at position %d", optimal_split_pos));
|
|
|
5048 assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
|
|
|
5049 assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
|
|
|
5050
|
|
|
5051 Interval* spilled_part = it->split(optimal_split_pos);
|
|
|
5052 allocator()->append_interval(spilled_part);
|
|
|
5053 allocator()->assign_spill_slot(spilled_part);
|
|
|
5054 allocator()->change_spill_state(spilled_part, optimal_split_pos);
|
|
|
5055
|
|
|
5056 if (!allocator()->is_block_begin(optimal_split_pos)) {
|
|
|
5057 TRACE_LINEAR_SCAN(4, tty->print_cr(" inserting move from interval %d to %d", it->reg_num(), spilled_part->reg_num()));
|
|
|
5058 insert_move(optimal_split_pos, it, spilled_part);
|
|
|
5059 }
|
|
|
5060
|
|
|
5061 // the current_split_child is needed later when moves are inserted for reloading
|
|
|
5062 assert(spilled_part->current_split_child() == it, "overwriting wrong current_split_child");
|
|
|
5063 spilled_part->make_current_split_child();
|
|
|
5064
|
|
|
5065 TRACE_LINEAR_SCAN(2, tty->print_cr(" split interval in two parts"));
|
|
|
5066 TRACE_LINEAR_SCAN(2, tty->print (" "); it->print());
|
|
|
5067 TRACE_LINEAR_SCAN(2, tty->print (" "); spilled_part->print());
|
|
|
5068 }
|
|
|
5069 }
|
|
|
5070
|
|
|
5071
|
|
|
5072 void LinearScanWalker::split_stack_interval(Interval* it) {
|
|
|
5073 int min_split_pos = current_position() + 1;
|
|
|
5074 int max_split_pos = MIN2(it->first_usage(shouldHaveRegister), it->to());
|
|
|
5075
|
|
|
5076 split_before_usage(it, min_split_pos, max_split_pos);
|
|
|
5077 }
|
|
|
5078
|
|
|
5079 void LinearScanWalker::split_when_partial_register_available(Interval* it, int register_available_until) {
|
|
|
5080 int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, register_available_until), it->from() + 1);
|
|
|
5081 int max_split_pos = register_available_until;
|
|
|
5082
|
|
|
5083 split_before_usage(it, min_split_pos, max_split_pos);
|
|
|
5084 }
|
|
|
5085
|
|
|
5086 void LinearScanWalker::split_and_spill_interval(Interval* it) {
|
|
|
5087 assert(it->state() == activeState || it->state() == inactiveState, "other states not allowed");
|
|
|
5088
|
|
|
5089 int current_pos = current_position();
|
|
|
5090 if (it->state() == inactiveState) {
|
|
|
5091 // the interval is currently inactive, so no spill slot is needed for now.
|
|
|
5092 // when the split part is activated, the interval has a new chance to get a register,
|
|
|
5093 // so in the best case no stack slot is necessary
|
|
|
5094 assert(it->has_hole_between(current_pos - 1, current_pos + 1), "interval can not be inactive otherwise");
|
|
|
5095 split_before_usage(it, current_pos + 1, current_pos + 1);
|
|
|
5096
|
|
|
5097 } else {
|
|
|
5098 // search the position where the interval must have a register and split
|
|
|
5099 // at the optimal position before.
|
|
|
5100 // The new created part is added to the unhandled list and will get a register
|
|
|
5101 // when it is activated
|
|
|
5102 int min_split_pos = current_pos + 1;
|
|
|
5103 int max_split_pos = MIN2(it->next_usage(mustHaveRegister, min_split_pos), it->to());
|
|
|
5104
|
|
|
5105 split_before_usage(it, min_split_pos, max_split_pos);
|
|
|
5106
|
|
|
5107 assert(it->next_usage(mustHaveRegister, current_pos) == max_jint, "the remaining part is spilled to stack and therefore has no register");
|
|
|
5108 split_for_spilling(it);
|
|
|
5109 }
|
|
|
5110 }
|
|
|
5111
|
|
|
5112
|
|
|
5113 int LinearScanWalker::find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
|
|
|
5114 int min_full_reg = any_reg;
|
|
|
5115 int max_partial_reg = any_reg;
|
|
|
5116
|
|
|
5117 for (int i = _first_reg; i <= _last_reg; i++) {
|
|
|
5118 if (i == ignore_reg) {
|
|
|
5119 // this register must be ignored
|
|
|
5120
|
|
|
5121 } else if (_use_pos[i] >= interval_to) {
|
|
|
5122 // this register is free for the full interval
|
|
|
5123 if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
|
|
|
5124 min_full_reg = i;
|
|
|
5125 }
|
|
|
5126 } else if (_use_pos[i] > reg_needed_until) {
|
|
|
5127 // this register is at least free until reg_needed_until
|
|
|
5128 if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
|
|
|
5129 max_partial_reg = i;
|
|
|
5130 }
|
|
|
5131 }
|
|
|
5132 }
|
|
|
5133
|
|
|
5134 if (min_full_reg != any_reg) {
|
|
|
5135 return min_full_reg;
|
|
|
5136 } else if (max_partial_reg != any_reg) {
|
|
|
5137 *need_split = true;
|
|
|
5138 return max_partial_reg;
|
|
|
5139 } else {
|
|
|
5140 return any_reg;
|
|
|
5141 }
|
|
|
5142 }
|
|
|
5143
|
|
|
5144 int LinearScanWalker::find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
|
|
|
5145 assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
|
|
|
5146
|
|
|
5147 int min_full_reg = any_reg;
|
|
|
5148 int max_partial_reg = any_reg;
|
|
|
5149
|
|
|
5150 for (int i = _first_reg; i < _last_reg; i+=2) {
|
|
|
5151 if (_use_pos[i] >= interval_to && _use_pos[i + 1] >= interval_to) {
|
|
|
5152 // this register is free for the full interval
|
|
|
5153 if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
|
|
|
5154 min_full_reg = i;
|
|
|
5155 }
|
|
|
5156 } else if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
|
|
|
5157 // this register is at least free until reg_needed_until
|
|
|
5158 if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
|
|
|
5159 max_partial_reg = i;
|
|
|
5160 }
|
|
|
5161 }
|
|
|
5162 }
|
|
|
5163
|
|
|
5164 if (min_full_reg != any_reg) {
|
|
|
5165 return min_full_reg;
|
|
|
5166 } else if (max_partial_reg != any_reg) {
|
|
|
5167 *need_split = true;
|
|
|
5168 return max_partial_reg;
|
|
|
5169 } else {
|
|
|
5170 return any_reg;
|
|
|
5171 }
|
|
|
5172 }
|
|
|
5173
|
|
|
5174
|
|
|
5175 bool LinearScanWalker::alloc_free_reg(Interval* cur) {
|
|
|
5176 TRACE_LINEAR_SCAN(2, tty->print("trying to find free register for "); cur->print());
|
|
|
5177
|
|
|
5178 init_use_lists(true);
|
|
|
5179 free_exclude_active_fixed();
|
|
|
5180 free_exclude_active_any();
|
|
|
5181 free_collect_inactive_fixed(cur);
|
|
|
5182 free_collect_inactive_any(cur);
|
|
|
5183 // free_collect_unhandled(fixedKind, cur);
|
|
|
5184 assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
|
|
|
5185
|
|
|
5186 // _use_pos contains the start of the next interval that has this register assigned
|
|
|
5187 // (either as a fixed register or a normal allocated register in the past)
|
|
|
5188 // only intervals overlapping with cur are processed, non-overlapping invervals can be ignored safely
|
|
|
5189 TRACE_LINEAR_SCAN(4, tty->print_cr(" state of registers:"));
|
|
|
5190 TRACE_LINEAR_SCAN(4, for (int i = _first_reg; i <= _last_reg; i++) tty->print_cr(" reg %d: use_pos: %d", i, _use_pos[i]));
|
|
|
5191
|
|
|
5192 int hint_reg, hint_regHi;
|
|
|
5193 Interval* register_hint = cur->register_hint();
|
|
|
5194 if (register_hint != NULL) {
|
|
|
5195 hint_reg = register_hint->assigned_reg();
|
|
|
5196 hint_regHi = register_hint->assigned_regHi();
|
|
|
5197
|
|
|
5198 if (allocator()->is_precolored_cpu_interval(register_hint)) {
|
|
|
5199 assert(hint_reg != any_reg && hint_regHi == any_reg, "must be for fixed intervals");
|
|
|
5200 hint_regHi = hint_reg + 1; // connect e.g. eax-edx
|
|
|
5201 }
|
|
|
5202 TRACE_LINEAR_SCAN(4, tty->print(" hint registers %d, %d from interval ", hint_reg, hint_regHi); register_hint->print());
|
|
|
5203
|
|
|
5204 } else {
|
|
|
5205 hint_reg = any_reg;
|
|
|
5206 hint_regHi = any_reg;
|
|
|
5207 }
|
|
|
5208 assert(hint_reg == any_reg || hint_reg != hint_regHi, "hint reg and regHi equal");
|
|
|
5209 assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned to interval");
|
|
|
5210
|
|
|
5211 // the register must be free at least until this position
|
|
|
5212 int reg_needed_until = cur->from() + 1;
|
|
|
5213 int interval_to = cur->to();
|
|
|
5214
|
|
|
5215 bool need_split = false;
|
|
|
5216 int split_pos = -1;
|
|
|
5217 int reg = any_reg;
|
|
|
5218 int regHi = any_reg;
|
|
|
5219
|
|
|
5220 if (_adjacent_regs) {
|
|
|
5221 reg = find_free_double_reg(reg_needed_until, interval_to, hint_reg, &need_split);
|
|
|
5222 regHi = reg + 1;
|
|
|
5223 if (reg == any_reg) {
|
|
|
5224 return false;
|
|
|
5225 }
|
|
|
5226 split_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
|
|
|
5227
|
|
|
5228 } else {
|
|
|
5229 reg = find_free_reg(reg_needed_until, interval_to, hint_reg, any_reg, &need_split);
|
|
|
5230 if (reg == any_reg) {
|
|
|
5231 return false;
|
|
|
5232 }
|
|
|
5233 split_pos = _use_pos[reg];
|
|
|
5234
|
|
|
5235 if (_num_phys_regs == 2) {
|
|
|
5236 regHi = find_free_reg(reg_needed_until, interval_to, hint_regHi, reg, &need_split);
|
|
|
5237
|
|
|
5238 if (_use_pos[reg] < interval_to && regHi == any_reg) {
|
|
|
5239 // do not split interval if only one register can be assigned until the split pos
|
|
|
5240 // (when one register is found for the whole interval, split&spill is only
|
|
|
5241 // performed for the hi register)
|
|
|
5242 return false;
|
|
|
5243
|
|
|
5244 } else if (regHi != any_reg) {
|
|
|
5245 split_pos = MIN2(split_pos, _use_pos[regHi]);
|
|
|
5246
|
|
|
5247 // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
|
|
|
5248 if (reg > regHi) {
|
|
|
5249 int temp = reg;
|
|
|
5250 reg = regHi;
|
|
|
5251 regHi = temp;
|
|
|
5252 }
|
|
|
5253 }
|
|
|
5254 }
|
|
|
5255 }
|
|
|
5256
|
|
|
5257 cur->assign_reg(reg, regHi);
|
|
|
5258 TRACE_LINEAR_SCAN(2, tty->print_cr("selected register %d, %d", reg, regHi));
|
|
|
5259
|
|
|
5260 assert(split_pos > 0, "invalid split_pos");
|
|
|
5261 if (need_split) {
|
|
|
5262 // register not available for full interval, so split it
|
|
|
5263 split_when_partial_register_available(cur, split_pos);
|
|
|
5264 }
|
|
|
5265
|
|
|
5266 // only return true if interval is completely assigned
|
|
|
5267 return _num_phys_regs == 1 || regHi != any_reg;
|
|
|
5268 }
|
|
|
5269
|
|
|
5270
|
|
|
5271 int LinearScanWalker::find_locked_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
|
|
|
5272 int max_reg = any_reg;
|
|
|
5273
|
|
|
5274 for (int i = _first_reg; i <= _last_reg; i++) {
|
|
|
5275 if (i == ignore_reg) {
|
|
|
5276 // this register must be ignored
|
|
|
5277
|
|
|
5278 } else if (_use_pos[i] > reg_needed_until) {
|
|
|
5279 if (max_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_reg] && max_reg != hint_reg)) {
|
|
|
5280 max_reg = i;
|
|
|
5281 }
|
|
|
5282 }
|
|
|
5283 }
|
|
|
5284
|
|
|
5285 if (max_reg != any_reg && _block_pos[max_reg] <= interval_to) {
|
|
|
5286 *need_split = true;
|
|
|
5287 }
|
|
|
5288
|
|
|
5289 return max_reg;
|
|
|
5290 }
|
|
|
5291
|
|
|
5292 int LinearScanWalker::find_locked_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
|
|
|
5293 assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
|
|
|
5294
|
|
|
5295 int max_reg = any_reg;
|
|
|
5296
|
|
|
5297 for (int i = _first_reg; i < _last_reg; i+=2) {
|
|
|
5298 if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
|
|
|
5299 if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) {
|
|
|
5300 max_reg = i;
|
|
|
5301 }
|
|
|
5302 }
|
|
|
5303 }
|
|
|
5304
|
|
|
5305 if (_block_pos[max_reg] <= interval_to || _block_pos[max_reg + 1] <= interval_to) {
|
|
|
5306 *need_split = true;
|
|
|
5307 }
|
|
|
5308
|
|
|
5309 return max_reg;
|
|
|
5310 }
|
|
|
5311
|
|
|
5312 void LinearScanWalker::split_and_spill_intersecting_intervals(int reg, int regHi) {
|
|
|
5313 assert(reg != any_reg, "no register assigned");
|
|
|
5314
|
|
|
5315 for (int i = 0; i < _spill_intervals[reg]->length(); i++) {
|
|
|
5316 Interval* it = _spill_intervals[reg]->at(i);
|
|
|
5317 remove_from_list(it);
|
|
|
5318 split_and_spill_interval(it);
|
|
|
5319 }
|
|
|
5320
|
|
|
5321 if (regHi != any_reg) {
|
|
|
5322 IntervalList* processed = _spill_intervals[reg];
|
|
|
5323 for (int i = 0; i < _spill_intervals[regHi]->length(); i++) {
|
|
|
5324 Interval* it = _spill_intervals[regHi]->at(i);
|
|
|
5325 if (processed->index_of(it) == -1) {
|
|
|
5326 remove_from_list(it);
|
|
|
5327 split_and_spill_interval(it);
|
|
|
5328 }
|
|
|
5329 }
|
|
|
5330 }
|
|
|
5331 }
|
|
|
5332
|
|
|
5333
|
|
|
5334 // Split an Interval and spill it to memory so that cur can be placed in a register
|
|
|
5335 void LinearScanWalker::alloc_locked_reg(Interval* cur) {
|
|
|
5336 TRACE_LINEAR_SCAN(2, tty->print("need to split and spill to get register for "); cur->print());
|
|
|
5337
|
|
|
5338 // collect current usage of registers
|
|
|
5339 init_use_lists(false);
|
|
|
5340 spill_exclude_active_fixed();
|
|
|
5341 // spill_block_unhandled_fixed(cur);
|
|
|
5342 assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
|
|
|
5343 spill_block_inactive_fixed(cur);
|
|
|
5344 spill_collect_active_any();
|
|
|
5345 spill_collect_inactive_any(cur);
|
|
|
5346
|
|
|
5347 #ifndef PRODUCT
|
|
|
5348 if (TraceLinearScanLevel >= 4) {
|
|
|
5349 tty->print_cr(" state of registers:");
|
|
|
5350 for (int i = _first_reg; i <= _last_reg; i++) {
|
|
|
5351 tty->print(" reg %d: use_pos: %d, block_pos: %d, intervals: ", i, _use_pos[i], _block_pos[i]);
|
|
|
5352 for (int j = 0; j < _spill_intervals[i]->length(); j++) {
|
|
|
5353 tty->print("%d ", _spill_intervals[i]->at(j)->reg_num());
|
|
|
5354 }
|
|
|
5355 tty->cr();
|
|
|
5356 }
|
|
|
5357 }
|
|
|
5358 #endif
|
|
|
5359
|
|
|
5360 // the register must be free at least until this position
|
|
|
5361 int reg_needed_until = MIN2(cur->first_usage(mustHaveRegister), cur->from() + 1);
|
|
|
5362 int interval_to = cur->to();
|
|
|
5363 assert (reg_needed_until > 0 && reg_needed_until < max_jint, "interval has no use");
|
|
|
5364
|
|
|
5365 int split_pos = 0;
|
|
|
5366 int use_pos = 0;
|
|
|
5367 bool need_split = false;
|
|
|
5368 int reg, regHi;
|
|
|
5369
|
|
|
5370 if (_adjacent_regs) {
|
|
|
5371 reg = find_locked_double_reg(reg_needed_until, interval_to, any_reg, &need_split);
|
|
|
5372 regHi = reg + 1;
|
|
|
5373
|
|
|
5374 if (reg != any_reg) {
|
|
|
5375 use_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
|
|
|
5376 split_pos = MIN2(_block_pos[reg], _block_pos[regHi]);
|
|
|
5377 }
|
|
|
5378 } else {
|
|
|
5379 reg = find_locked_reg(reg_needed_until, interval_to, any_reg, cur->assigned_reg(), &need_split);
|
|
|
5380 regHi = any_reg;
|
|
|
5381
|
|
|
5382 if (reg != any_reg) {
|
|
|
5383 use_pos = _use_pos[reg];
|
|
|
5384 split_pos = _block_pos[reg];
|
|
|
5385
|
|
|
5386 if (_num_phys_regs == 2) {
|
|
|
5387 if (cur->assigned_reg() != any_reg) {
|
|
|
5388 regHi = reg;
|
|
|
5389 reg = cur->assigned_reg();
|
|
|
5390 } else {
|
|
|
5391 regHi = find_locked_reg(reg_needed_until, interval_to, any_reg, reg, &need_split);
|
|
|
5392 if (regHi != any_reg) {
|
|
|
5393 use_pos = MIN2(use_pos, _use_pos[regHi]);
|
|
|
5394 split_pos = MIN2(split_pos, _block_pos[regHi]);
|
|
|
5395 }
|
|
|
5396 }
|
|
|
5397
|
|
|
5398 if (regHi != any_reg && reg > regHi) {
|
|
|
5399 // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
|
|
|
5400 int temp = reg;
|
|
|
5401 reg = regHi;
|
|
|
5402 regHi = temp;
|
|
|
5403 }
|
|
|
5404 }
|
|
|
5405 }
|
|
|
5406 }
|
|
|
5407
|
|
|
5408 if (reg == any_reg || (_num_phys_regs == 2 && regHi == any_reg) || use_pos <= cur->first_usage(mustHaveRegister)) {
|
|
|
5409 // the first use of cur is later than the spilling position -> spill cur
|
|
|
5410 TRACE_LINEAR_SCAN(4, tty->print_cr("able to spill current interval. first_usage(register): %d, use_pos: %d", cur->first_usage(mustHaveRegister), use_pos));
|
|
|
5411
|
|
|
5412 if (cur->first_usage(mustHaveRegister) <= cur->from() + 1) {
|
|
|
5413 assert(false, "cannot spill interval that is used in first instruction (possible reason: no register found)");
|
|
|
5414 // assign a reasonable register and do a bailout in product mode to avoid errors
|
|
|
5415 allocator()->assign_spill_slot(cur);
|
|
|
5416 BAILOUT("LinearScan: no register found");
|
|
|
5417 }
|
|
|
5418
|
|
|
5419 split_and_spill_interval(cur);
|
|
|
5420 } else {
|
|
|
5421 TRACE_LINEAR_SCAN(4, tty->print_cr("decided to use register %d, %d", reg, regHi));
|
|
|
5422 assert(reg != any_reg && (_num_phys_regs == 1 || regHi != any_reg), "no register found");
|
|
|
5423 assert(split_pos > 0, "invalid split_pos");
|
|
|
5424 assert(need_split == false || split_pos > cur->from(), "splitting interval at from");
|
|
|
5425
|
|
|
5426 cur->assign_reg(reg, regHi);
|
|
|
5427 if (need_split) {
|
|
|
5428 // register not available for full interval, so split it
|
|
|
5429 split_when_partial_register_available(cur, split_pos);
|
|
|
5430 }
|
|
|
5431
|
|
|
5432 // perform splitting and spilling for all affected intervalls
|
|
|
5433 split_and_spill_intersecting_intervals(reg, regHi);
|
|
|
5434 }
|
|
|
5435 }
|
|
|
5436
|
|
|
5437 bool LinearScanWalker::no_allocation_possible(Interval* cur) {
|
|
|
5438 #ifdef IA32
|
|
|
5439 // fast calculation of intervals that can never get a register because the
|
|
|
5440 // the next instruction is a call that blocks all registers
|
|
|
5441 // Note: this does not work if callee-saved registers are available (e.g. on Sparc)
|
|
|
5442
|
|
|
5443 // check if this interval is the result of a split operation
|
|
|
5444 // (an interval got a register until this position)
|
|
|
5445 int pos = cur->from();
|
|
|
5446 if ((pos & 1) == 1) {
|
|
|
5447 // the current instruction is a call that blocks all registers
|
|
|
5448 if (pos < allocator()->max_lir_op_id() && allocator()->has_call(pos + 1)) {
|
|
|
5449 TRACE_LINEAR_SCAN(4, tty->print_cr(" free register cannot be available because all registers blocked by following call"));
|
|
|
5450
|
|
|
5451 // safety check that there is really no register available
|
|
|
5452 assert(alloc_free_reg(cur) == false, "found a register for this interval");
|
|
|
5453 return true;
|
|
|
5454 }
|
|
|
5455
|
|
|
5456 }
|
|
|
5457 #endif
|
|
|
5458 return false;
|
|
|
5459 }
|
|
|
5460
|
|
|
5461 void LinearScanWalker::init_vars_for_alloc(Interval* cur) {
|
|
|
5462 BasicType type = cur->type();
|
|
|
5463 _num_phys_regs = LinearScan::num_physical_regs(type);
|
|
|
5464 _adjacent_regs = LinearScan::requires_adjacent_regs(type);
|
|
|
5465
|
|
|
5466 if (pd_init_regs_for_alloc(cur)) {
|
|
|
5467 // the appropriate register range was selected.
|
|
|
5468 } else if (type == T_FLOAT || type == T_DOUBLE) {
|
|
|
5469 _first_reg = pd_first_fpu_reg;
|
|
|
5470 _last_reg = pd_last_fpu_reg;
|
|
|
5471 } else {
|
|
|
5472 _first_reg = pd_first_cpu_reg;
|
|
|
5473 _last_reg = pd_last_cpu_reg;
|
|
|
5474 }
|
|
|
5475
|
|
|
5476 assert(0 <= _first_reg && _first_reg < LinearScan::nof_regs, "out of range");
|
|
|
5477 assert(0 <= _last_reg && _last_reg < LinearScan::nof_regs, "out of range");
|
|
|
5478 }
|
|
|
5479
|
|
|
5480
|
|
|
5481 bool LinearScanWalker::is_move(LIR_Op* op, Interval* from, Interval* to) {
|
|
|
5482 if (op->code() != lir_move) {
|
|
|
5483 return false;
|
|
|
5484 }
|
|
|
5485 assert(op->as_Op1() != NULL, "move must be LIR_Op1");
|
|
|
5486
|
|
|
5487 LIR_Opr in = ((LIR_Op1*)op)->in_opr();
|
|
|
5488 LIR_Opr res = ((LIR_Op1*)op)->result_opr();
|
|
|
5489 return in->is_virtual() && res->is_virtual() && in->vreg_number() == from->reg_num() && res->vreg_number() == to->reg_num();
|
|
|
5490 }
|
|
|
5491
|
|
|
5492 // optimization (especially for phi functions of nested loops):
|
|
|
5493 // assign same spill slot to non-intersecting intervals
|
|
|
5494 void LinearScanWalker::combine_spilled_intervals(Interval* cur) {
|
|
|
5495 if (cur->is_split_child()) {
|
|
|
5496 // optimization is only suitable for split parents
|
|
|
5497 return;
|
|
|
5498 }
|
|
|
5499
|
|
|
5500 Interval* register_hint = cur->register_hint(false);
|
|
|
5501 if (register_hint == NULL) {
|
|
|
5502 // cur is not the target of a move, otherwise register_hint would be set
|
|
|
5503 return;
|
|
|
5504 }
|
|
|
5505 assert(register_hint->is_split_parent(), "register hint must be split parent");
|
|
|
5506
|
|
|
5507 if (cur->spill_state() != noOptimization || register_hint->spill_state() != noOptimization) {
|
|
|
5508 // combining the stack slots for intervals where spill move optimization is applied
|
|
|
5509 // is not benefitial and would cause problems
|
|
|
5510 return;
|
|
|
5511 }
|
|
|
5512
|
|
|
5513 int begin_pos = cur->from();
|
|
|
5514 int end_pos = cur->to();
|
|
|
5515 if (end_pos > allocator()->max_lir_op_id() || (begin_pos & 1) != 0 || (end_pos & 1) != 0) {
|
|
|
5516 // safety check that lir_op_with_id is allowed
|
|
|
5517 return;
|
|
|
5518 }
|
|
|
5519
|
|
|
5520 if (!is_move(allocator()->lir_op_with_id(begin_pos), register_hint, cur) || !is_move(allocator()->lir_op_with_id(end_pos), cur, register_hint)) {
|
|
|
5521 // cur and register_hint are not connected with two moves
|
|
|
5522 return;
|
|
|
5523 }
|
|
|
5524
|
|
|
5525 Interval* begin_hint = register_hint->split_child_at_op_id(begin_pos, LIR_OpVisitState::inputMode);
|
|
|
5526 Interval* end_hint = register_hint->split_child_at_op_id(end_pos, LIR_OpVisitState::outputMode);
|
|
|
5527 if (begin_hint == end_hint || begin_hint->to() != begin_pos || end_hint->from() != end_pos) {
|
|
|
5528 // register_hint must be split, otherwise the re-writing of use positions does not work
|
|
|
5529 return;
|
|
|
5530 }
|
|
|
5531
|
|
|
5532 assert(begin_hint->assigned_reg() != any_reg, "must have register assigned");
|
|
|
5533 assert(end_hint->assigned_reg() == any_reg, "must not have register assigned");
|
|
|
5534 assert(cur->first_usage(mustHaveRegister) == begin_pos, "must have use position at begin of interval because of move");
|
|
|
5535 assert(end_hint->first_usage(mustHaveRegister) == end_pos, "must have use position at begin of interval because of move");
|
|
|
5536
|
|
|
5537 if (begin_hint->assigned_reg() < LinearScan::nof_regs) {
|
|
|
5538 // register_hint is not spilled at begin_pos, so it would not be benefitial to immediately spill cur
|
|
|
5539 return;
|
|
|
5540 }
|
|
|
5541 assert(register_hint->canonical_spill_slot() != -1, "must be set when part of interval was spilled");
|
|
|
5542
|
|
|
5543 // modify intervals such that cur gets the same stack slot as register_hint
|
|
|
5544 // delete use positions to prevent the intervals to get a register at beginning
|
|
|
5545 cur->set_canonical_spill_slot(register_hint->canonical_spill_slot());
|
|
|
5546 cur->remove_first_use_pos();
|
|
|
5547 end_hint->remove_first_use_pos();
|
|
|
5548 }
|
|
|
5549
|
|
|
5550
|
|
|
5551 // allocate a physical register or memory location to an interval
|
|
|
5552 bool LinearScanWalker::activate_current() {
|
|
|
5553 Interval* cur = current();
|
|
|
5554 bool result = true;
|
|
|
5555
|
|
|
5556 TRACE_LINEAR_SCAN(2, tty->print ("+++++ activating interval "); cur->print());
|
|
|
5557 TRACE_LINEAR_SCAN(4, tty->print_cr(" split_parent: %d, insert_move_when_activated: %d", cur->split_parent()->reg_num(), cur->insert_move_when_activated()));
|
|
|
5558
|
|
|
5559 if (cur->assigned_reg() >= LinearScan::nof_regs) {
|
|
|
5560 // activating an interval that has a stack slot assigned -> split it at first use position
|
|
|
5561 // used for method parameters
|
|
|
5562 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has spill slot assigned (method parameter) -> split it before first use"));
|
|
|
5563
|
|
|
5564 split_stack_interval(cur);
|
|
|
5565 result = false;
|
|
|
5566
|
|
|
5567 } else if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::must_start_in_memory)) {
|
|
|
5568 // activating an interval that must start in a stack slot, but may get a register later
|
|
|
5569 // used for lir_roundfp: rounding is done by store to stack and reload later
|
|
|
5570 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval must start in stack slot -> split it before first use"));
|
|
|
5571 assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned");
|
|
|
5572
|
|
|
5573 allocator()->assign_spill_slot(cur);
|
|
|
5574 split_stack_interval(cur);
|
|
|
5575 result = false;
|
|
|
5576
|
|
|
5577 } else if (cur->assigned_reg() == any_reg) {
|
|
|
5578 // interval has not assigned register -> normal allocation
|
|
|
5579 // (this is the normal case for most intervals)
|
|
|
5580 TRACE_LINEAR_SCAN(4, tty->print_cr(" normal allocation of register"));
|
|
|
5581
|
|
|
5582 // assign same spill slot to non-intersecting intervals
|
|
|
5583 combine_spilled_intervals(cur);
|
|
|
5584
|
|
|
5585 init_vars_for_alloc(cur);
|
|
|
5586 if (no_allocation_possible(cur) || !alloc_free_reg(cur)) {
|
|
|
5587 // no empty register available.
|
|
|
5588 // split and spill another interval so that this interval gets a register
|
|
|
5589 alloc_locked_reg(cur);
|
|
|
5590 }
|
|
|
5591
|
|
|
5592 // spilled intervals need not be move to active-list
|
|
|
5593 if (cur->assigned_reg() >= LinearScan::nof_regs) {
|
|
|
5594 result = false;
|
|
|
5595 }
|
|
|
5596 }
|
|
|
5597
|
|
|
5598 // load spilled values that become active from stack slot to register
|
|
|
5599 if (cur->insert_move_when_activated()) {
|
|
|
5600 assert(cur->is_split_child(), "must be");
|
|
|
5601 assert(cur->current_split_child() != NULL, "must be");
|
|
|
5602 assert(cur->current_split_child()->reg_num() != cur->reg_num(), "cannot insert move between same interval");
|
|
|
5603 TRACE_LINEAR_SCAN(4, tty->print_cr("Inserting move from interval %d to %d because insert_move_when_activated is set", cur->current_split_child()->reg_num(), cur->reg_num()));
|
|
|
5604
|
|
|
5605 insert_move(cur->from(), cur->current_split_child(), cur);
|
|
|
5606 }
|
|
|
5607 cur->make_current_split_child();
|
|
|
5608
|
|
|
5609 return result; // true = interval is moved to active list
|
|
|
5610 }
|
|
|
5611
|
|
|
5612
|
|
|
5613 // Implementation of EdgeMoveOptimizer
|
|
|
5614
|
|
|
5615 EdgeMoveOptimizer::EdgeMoveOptimizer() :
|
|
|
5616 _edge_instructions(4),
|
|
|
5617 _edge_instructions_idx(4)
|
|
|
5618 {
|
|
|
5619 }
|
|
|
5620
|
|
|
5621 void EdgeMoveOptimizer::optimize(BlockList* code) {
|
|
|
5622 EdgeMoveOptimizer optimizer = EdgeMoveOptimizer();
|
|
|
5623
|
|
|
5624 // ignore the first block in the list (index 0 is not processed)
|
|
|
5625 for (int i = code->length() - 1; i >= 1; i--) {
|
|
|
5626 BlockBegin* block = code->at(i);
|
|
|
5627
|
|
|
5628 if (block->number_of_preds() > 1 && !block->is_set(BlockBegin::exception_entry_flag)) {
|
|
|
5629 optimizer.optimize_moves_at_block_end(block);
|
|
|
5630 }
|
|
|
5631 if (block->number_of_sux() == 2) {
|
|
|
5632 optimizer.optimize_moves_at_block_begin(block);
|
|
|
5633 }
|
|
|
5634 }
|
|
|
5635 }
|
|
|
5636
|
|
|
5637
|
|
|
5638 // clear all internal data structures
|
|
|
5639 void EdgeMoveOptimizer::init_instructions() {
|
|
|
5640 _edge_instructions.clear();
|
|
|
5641 _edge_instructions_idx.clear();
|
|
|
5642 }
|
|
|
5643
|
|
|
5644 // append a lir-instruction-list and the index of the current operation in to the list
|
|
|
5645 void EdgeMoveOptimizer::append_instructions(LIR_OpList* instructions, int instructions_idx) {
|
|
|
5646 _edge_instructions.append(instructions);
|
|
|
5647 _edge_instructions_idx.append(instructions_idx);
|
|
|
5648 }
|
|
|
5649
|
|
|
5650 // return the current operation of the given edge (predecessor or successor)
|
|
|
5651 LIR_Op* EdgeMoveOptimizer::instruction_at(int edge) {
|
|
|
5652 LIR_OpList* instructions = _edge_instructions.at(edge);
|
|
|
5653 int idx = _edge_instructions_idx.at(edge);
|
|
|
5654
|
|
|
5655 if (idx < instructions->length()) {
|
|
|
5656 return instructions->at(idx);
|
|
|
5657 } else {
|
|
|
5658 return NULL;
|
|
|
5659 }
|
|
|
5660 }
|
|
|
5661
|
|
|
5662 // removes the current operation of the given edge (predecessor or successor)
|
|
|
5663 void EdgeMoveOptimizer::remove_cur_instruction(int edge, bool decrement_index) {
|
|
|
5664 LIR_OpList* instructions = _edge_instructions.at(edge);
|
|
|
5665 int idx = _edge_instructions_idx.at(edge);
|
|
|
5666 instructions->remove_at(idx);
|
|
|
5667
|
|
|
5668 if (decrement_index) {
|
|
|
5669 _edge_instructions_idx.at_put(edge, idx - 1);
|
|
|
5670 }
|
|
|
5671 }
|
|
|
5672
|
|
|
5673
|
|
|
5674 bool EdgeMoveOptimizer::operations_different(LIR_Op* op1, LIR_Op* op2) {
|
|
|
5675 if (op1 == NULL || op2 == NULL) {
|
|
|
5676 // at least one block is already empty -> no optimization possible
|
|
|
5677 return true;
|
|
|
5678 }
|
|
|
5679
|
|
|
5680 if (op1->code() == lir_move && op2->code() == lir_move) {
|
|
|
5681 assert(op1->as_Op1() != NULL, "move must be LIR_Op1");
|
|
|
5682 assert(op2->as_Op1() != NULL, "move must be LIR_Op1");
|
|
|
5683 LIR_Op1* move1 = (LIR_Op1*)op1;
|
|
|
5684 LIR_Op1* move2 = (LIR_Op1*)op2;
|
|
|
5685 if (move1->info() == move2->info() && move1->in_opr() == move2->in_opr() && move1->result_opr() == move2->result_opr()) {
|
|
|
5686 // these moves are exactly equal and can be optimized
|
|
|
5687 return false;
|
|
|
5688 }
|
|
|
5689
|
|
|
5690 } else if (op1->code() == lir_fxch && op2->code() == lir_fxch) {
|
|
|
5691 assert(op1->as_Op1() != NULL, "fxch must be LIR_Op1");
|
|
|
5692 assert(op2->as_Op1() != NULL, "fxch must be LIR_Op1");
|
|
|
5693 LIR_Op1* fxch1 = (LIR_Op1*)op1;
|
|
|
5694 LIR_Op1* fxch2 = (LIR_Op1*)op2;
|
|
|
5695 if (fxch1->in_opr()->as_jint() == fxch2->in_opr()->as_jint()) {
|
|
|
5696 // equal FPU stack operations can be optimized
|
|
|
5697 return false;
|
|
|
5698 }
|
|
|
5699
|
|
|
5700 } else if (op1->code() == lir_fpop_raw && op2->code() == lir_fpop_raw) {
|
|
|
5701 // equal FPU stack operations can be optimized
|
|
|
5702 return false;
|
|
|
5703 }
|
|
|
5704
|
|
|
5705 // no optimization possible
|
|
|
5706 return true;
|
|
|
5707 }
|
|
|
5708
|
|
|
5709 void EdgeMoveOptimizer::optimize_moves_at_block_end(BlockBegin* block) {
|
|
|
5710 TRACE_LINEAR_SCAN(4, tty->print_cr("optimizing moves at end of block B%d", block->block_id()));
|
|
|
5711
|
|
|
5712 if (block->is_predecessor(block)) {
|
|
|
5713 // currently we can't handle this correctly.
|
|
|
5714 return;
|
|
|
5715 }
|
|
|
5716
|
|
|
5717 init_instructions();
|
|
|
5718 int num_preds = block->number_of_preds();
|
|
|
5719 assert(num_preds > 1, "do not call otherwise");
|
|
|
5720 assert(!block->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
|
|
|
5721
|
|
|
5722 // setup a list with the lir-instructions of all predecessors
|
|
|
5723 int i;
|
|
|
5724 for (i = 0; i < num_preds; i++) {
|
|
|
5725 BlockBegin* pred = block->pred_at(i);
|
|
|
5726 LIR_OpList* pred_instructions = pred->lir()->instructions_list();
|
|
|
5727
|
|
|
5728 if (pred->number_of_sux() != 1) {
|
|
|
5729 // this can happen with switch-statements where multiple edges are between
|
|
|
5730 // the same blocks.
|
|
|
5731 return;
|
|
|
5732 }
|
|
|
5733
|
|
|
5734 assert(pred->number_of_sux() == 1, "can handle only one successor");
|
|
|
5735 assert(pred->sux_at(0) == block, "invalid control flow");
|
|
|
5736 assert(pred_instructions->last()->code() == lir_branch, "block with successor must end with branch");
|
|
|
5737 assert(pred_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
|
|
|
5738 assert(pred_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
|
|
|
5739
|
|
|
5740 if (pred_instructions->last()->info() != NULL) {
|
|
|
5741 // can not optimize instructions when debug info is needed
|
|
|
5742 return;
|
|
|
5743 }
|
|
|
5744
|
|
|
5745 // ignore the unconditional branch at the end of the block
|
|
|
5746 append_instructions(pred_instructions, pred_instructions->length() - 2);
|
|
|
5747 }
|
|
|
5748
|
|
|
5749
|
|
|
5750 // process lir-instructions while all predecessors end with the same instruction
|
|
|
5751 while (true) {
|
|
|
5752 LIR_Op* op = instruction_at(0);
|
|
|
5753 for (i = 1; i < num_preds; i++) {
|
|
|
5754 if (operations_different(op, instruction_at(i))) {
|
|
|
5755 // these instructions are different and cannot be optimized ->
|
|
|
5756 // no further optimization possible
|
|
|
5757 return;
|
|
|
5758 }
|
|
|
5759 }
|
|
|
5760
|
|
|
5761 TRACE_LINEAR_SCAN(4, tty->print("found instruction that is equal in all %d predecessors: ", num_preds); op->print());
|
|
|
5762
|
|
|
5763 // insert the instruction at the beginning of the current block
|
|
|
5764 block->lir()->insert_before(1, op);
|
|
|
5765
|
|
|
5766 // delete the instruction at the end of all predecessors
|
|
|
5767 for (i = 0; i < num_preds; i++) {
|
|
|
5768 remove_cur_instruction(i, true);
|
|
|
5769 }
|
|
|
5770 }
|
|
|
5771 }
|
|
|
5772
|
|
|
5773
|
|
|
5774 void EdgeMoveOptimizer::optimize_moves_at_block_begin(BlockBegin* block) {
|
|
|
5775 TRACE_LINEAR_SCAN(4, tty->print_cr("optimization moves at begin of block B%d", block->block_id()));
|
|
|
5776
|
|
|
5777 init_instructions();
|
|
|
5778 int num_sux = block->number_of_sux();
|
|
|
5779
|
|
|
5780 LIR_OpList* cur_instructions = block->lir()->instructions_list();
|
|
|
5781
|
|
|
5782 assert(num_sux == 2, "method should not be called otherwise");
|
|
|
5783 assert(cur_instructions->last()->code() == lir_branch, "block with successor must end with branch");
|
|
|
5784 assert(cur_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
|
|
|
5785 assert(cur_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
|
|
|
5786
|
|
|
5787 if (cur_instructions->last()->info() != NULL) {
|
|
|
5788 // can no optimize instructions when debug info is needed
|
|
|
5789 return;
|
|
|
5790 }
|
|
|
5791
|
|
|
5792 LIR_Op* branch = cur_instructions->at(cur_instructions->length() - 2);
|
|
|
5793 if (branch->info() != NULL || (branch->code() != lir_branch && branch->code() != lir_cond_float_branch)) {
|
|
|
5794 // not a valid case for optimization
|
|
|
5795 // currently, only blocks that end with two branches (conditional branch followed
|
|
|
5796 // by unconditional branch) are optimized
|
|
|
5797 return;
|
|
|
5798 }
|
|
|
5799
|
|
|
5800 // now it is guaranteed that the block ends with two branch instructions.
|
|
|
5801 // the instructions are inserted at the end of the block before these two branches
|
|
|
5802 int insert_idx = cur_instructions->length() - 2;
|
|
|
5803
|
|
|
5804 int i;
|
|
|
5805 #ifdef ASSERT
|
|
|
5806 for (i = insert_idx - 1; i >= 0; i--) {
|
|
|
5807 LIR_Op* op = cur_instructions->at(i);
|
|
|
5808 if ((op->code() == lir_branch || op->code() == lir_cond_float_branch) && ((LIR_OpBranch*)op)->block() != NULL) {
|
|
|
5809 assert(false, "block with two successors can have only two branch instructions");
|
|
|
5810 }
|
|
|
5811 }
|
|
|
5812 #endif
|
|
|
5813
|
|
|
5814 // setup a list with the lir-instructions of all successors
|
|
|
5815 for (i = 0; i < num_sux; i++) {
|
|
|
5816 BlockBegin* sux = block->sux_at(i);
|
|
|
5817 LIR_OpList* sux_instructions = sux->lir()->instructions_list();
|
|
|
5818
|
|
|
5819 assert(sux_instructions->at(0)->code() == lir_label, "block must start with label");
|
|
|
5820
|
|
|
5821 if (sux->number_of_preds() != 1) {
|
|
|
5822 // this can happen with switch-statements where multiple edges are between
|
|
|
5823 // the same blocks.
|
|
|
5824 return;
|
|
|
5825 }
|
|
|
5826 assert(sux->pred_at(0) == block, "invalid control flow");
|
|
|
5827 assert(!sux->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
|
|
|
5828
|
|
|
5829 // ignore the label at the beginning of the block
|
|
|
5830 append_instructions(sux_instructions, 1);
|
|
|
5831 }
|
|
|
5832
|
|
|
5833 // process lir-instructions while all successors begin with the same instruction
|
|
|
5834 while (true) {
|
|
|
5835 LIR_Op* op = instruction_at(0);
|
|
|
5836 for (i = 1; i < num_sux; i++) {
|
|
|
5837 if (operations_different(op, instruction_at(i))) {
|
|
|
5838 // these instructions are different and cannot be optimized ->
|
|
|
5839 // no further optimization possible
|
|
|
5840 return;
|
|
|
5841 }
|
|
|
5842 }
|
|
|
5843
|
|
|
5844 TRACE_LINEAR_SCAN(4, tty->print("----- found instruction that is equal in all %d successors: ", num_sux); op->print());
|
|
|
5845
|
|
|
5846 // insert instruction at end of current block
|
|
|
5847 block->lir()->insert_before(insert_idx, op);
|
|
|
5848 insert_idx++;
|
|
|
5849
|
|
|
5850 // delete the instructions at the beginning of all successors
|
|
|
5851 for (i = 0; i < num_sux; i++) {
|
|
|
5852 remove_cur_instruction(i, false);
|
|
|
5853 }
|
|
|
5854 }
|
|
|
5855 }
|
|
|
5856
|
|
|
5857
|
|
|
5858 // Implementation of ControlFlowOptimizer
|
|
|
5859
|
|
|
5860 ControlFlowOptimizer::ControlFlowOptimizer() :
|
|
|
5861 _original_preds(4)
|
|
|
5862 {
|
|
|
5863 }
|
|
|
5864
|
|
|
5865 void ControlFlowOptimizer::optimize(BlockList* code) {
|
|
|
5866 ControlFlowOptimizer optimizer = ControlFlowOptimizer();
|
|
|
5867
|
|
|
5868 // push the OSR entry block to the end so that we're not jumping over it.
|
|
|
5869 BlockBegin* osr_entry = code->at(0)->end()->as_Base()->osr_entry();
|
|
|
5870 if (osr_entry) {
|
|
|
5871 int index = osr_entry->linear_scan_number();
|
|
|
5872 assert(code->at(index) == osr_entry, "wrong index");
|
|
|
5873 code->remove_at(index);
|
|
|
5874 code->append(osr_entry);
|
|
|
5875 }
|
|
|
5876
|
|
|
5877 optimizer.reorder_short_loops(code);
|
|
|
5878 optimizer.delete_empty_blocks(code);
|
|
|
5879 optimizer.delete_unnecessary_jumps(code);
|
|
|
5880 optimizer.delete_jumps_to_return(code);
|
|
|
5881 }
|
|
|
5882
|
|
|
5883 void ControlFlowOptimizer::reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx) {
|
|
|
5884 int i = header_idx + 1;
|
|
|
5885 int max_end = MIN2(header_idx + ShortLoopSize, code->length());
|
|
|
5886 while (i < max_end && code->at(i)->loop_depth() >= header_block->loop_depth()) {
|
|
|
5887 i++;
|
|
|
5888 }
|
|
|
5889
|
|
|
5890 if (i == code->length() || code->at(i)->loop_depth() < header_block->loop_depth()) {
|
|
|
5891 int end_idx = i - 1;
|
|
|
5892 BlockBegin* end_block = code->at(end_idx);
|
|
|
5893
|
|
|
5894 if (end_block->number_of_sux() == 1 && end_block->sux_at(0) == header_block) {
|
|
|
5895 // short loop from header_idx to end_idx found -> reorder blocks such that
|
|
|
5896 // the header_block is the last block instead of the first block of the loop
|
|
|
5897 TRACE_LINEAR_SCAN(1, tty->print_cr("Reordering short loop: length %d, header B%d, end B%d",
|
|
|
5898 end_idx - header_idx + 1,
|
|
|
5899 header_block->block_id(), end_block->block_id()));
|
|
|
5900
|
|
|
5901 for (int j = header_idx; j < end_idx; j++) {
|
|
|
5902 code->at_put(j, code->at(j + 1));
|
|
|
5903 }
|
|
|
5904 code->at_put(end_idx, header_block);
|
|
|
5905
|
|
|
5906 // correct the flags so that any loop alignment occurs in the right place.
|
|
|
5907 assert(code->at(end_idx)->is_set(BlockBegin::backward_branch_target_flag), "must be backward branch target");
|
|
|
5908 code->at(end_idx)->clear(BlockBegin::backward_branch_target_flag);
|
|
|
5909 code->at(header_idx)->set(BlockBegin::backward_branch_target_flag);
|
|
|
5910 }
|
|
|
5911 }
|
|
|
5912 }
|
|
|
5913
|
|
|
5914 void ControlFlowOptimizer::reorder_short_loops(BlockList* code) {
|
|
|
5915 for (int i = code->length() - 1; i >= 0; i--) {
|
|
|
5916 BlockBegin* block = code->at(i);
|
|
|
5917
|
|
|
5918 if (block->is_set(BlockBegin::linear_scan_loop_header_flag)) {
|
|
|
5919 reorder_short_loop(code, block, i);
|
|
|
5920 }
|
|
|
5921 }
|
|
|
5922
|
|
|
5923 DEBUG_ONLY(verify(code));
|
|
|
5924 }
|
|
|
5925
|
|
|
5926 // only blocks with exactly one successor can be deleted. Such blocks
|
|
|
5927 // must always end with an unconditional branch to this successor
|
|
|
5928 bool ControlFlowOptimizer::can_delete_block(BlockBegin* block) {
|
|
|
5929 if (block->number_of_sux() != 1 || block->number_of_exception_handlers() != 0 || block->is_entry_block()) {
|
|
|
5930 return false;
|
|
|
5931 }
|
|
|
5932
|
|
|
5933 LIR_OpList* instructions = block->lir()->instructions_list();
|
|
|
5934
|
|
|
5935 assert(instructions->length() >= 2, "block must have label and branch");
|
|
|
5936 assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
|
|
|
5937 assert(instructions->last()->as_OpBranch() != NULL, "last instrcution must always be a branch");
|
|
|
5938 assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "branch must be unconditional");
|
|
|
5939 assert(instructions->last()->as_OpBranch()->block() == block->sux_at(0), "branch target must be the successor");
|
|
|
5940
|
|
|
5941 // block must have exactly one successor
|
|
|
5942
|
|
|
5943 if (instructions->length() == 2 && instructions->last()->info() == NULL) {
|
|
|
5944 return true;
|
|
|
5945 }
|
|
|
5946 return false;
|
|
|
5947 }
|
|
|
5948
|
|
|
5949 // substitute branch targets in all branch-instructions of this blocks
|
|
|
5950 void ControlFlowOptimizer::substitute_branch_target(BlockBegin* block, BlockBegin* target_from, BlockBegin* target_to) {
|
|
|
5951 TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting empty block: substituting from B%d to B%d inside B%d", target_from->block_id(), target_to->block_id(), block->block_id()));
|
|
|
5952
|
|
|
5953 LIR_OpList* instructions = block->lir()->instructions_list();
|
|
|
5954
|
|
|
5955 assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
|
|
|
5956 for (int i = instructions->length() - 1; i >= 1; i--) {
|
|
|
5957 LIR_Op* op = instructions->at(i);
|
|
|
5958
|
|
|
5959 if (op->code() == lir_branch || op->code() == lir_cond_float_branch) {
|
|
|
5960 assert(op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
|
|
|
5961 LIR_OpBranch* branch = (LIR_OpBranch*)op;
|
|
|
5962
|
|
|
5963 if (branch->block() == target_from) {
|
|
|
5964 branch->change_block(target_to);
|
|
|
5965 }
|
|
|
5966 if (branch->ublock() == target_from) {
|
|
|
5967 branch->change_ublock(target_to);
|
|
|
5968 }
|
|
|
5969 }
|
|
|
5970 }
|
|
|
5971 }
|
|
|
5972
|
|
|
5973 void ControlFlowOptimizer::delete_empty_blocks(BlockList* code) {
|
|
|
5974 int old_pos = 0;
|
|
|
5975 int new_pos = 0;
|
|
|
5976 int num_blocks = code->length();
|
|
|
5977
|
|
|
5978 while (old_pos < num_blocks) {
|
|
|
5979 BlockBegin* block = code->at(old_pos);
|
|
|
5980
|
|
|
5981 if (can_delete_block(block)) {
|
|
|
5982 BlockBegin* new_target = block->sux_at(0);
|
|
|
5983
|
|
|
5984 // propagate backward branch target flag for correct code alignment
|
|
|
5985 if (block->is_set(BlockBegin::backward_branch_target_flag)) {
|
|
|
5986 new_target->set(BlockBegin::backward_branch_target_flag);
|
|
|
5987 }
|
|
|
5988
|
|
|
5989 // collect a list with all predecessors that contains each predecessor only once
|
|
|
5990 // the predecessors of cur are changed during the substitution, so a copy of the
|
|
|
5991 // predecessor list is necessary
|
|
|
5992 int j;
|
|
|
5993 _original_preds.clear();
|
|
|
5994 for (j = block->number_of_preds() - 1; j >= 0; j--) {
|
|
|
5995 BlockBegin* pred = block->pred_at(j);
|
|
|
5996 if (_original_preds.index_of(pred) == -1) {
|
|
|
5997 _original_preds.append(pred);
|
|
|
5998 }
|
|
|
5999 }
|
|
|
6000
|
|
|
6001 for (j = _original_preds.length() - 1; j >= 0; j--) {
|
|
|
6002 BlockBegin* pred = _original_preds.at(j);
|
|
|
6003 substitute_branch_target(pred, block, new_target);
|
|
|
6004 pred->substitute_sux(block, new_target);
|
|
|
6005 }
|
|
|
6006 } else {
|
|
|
6007 // adjust position of this block in the block list if blocks before
|
|
|
6008 // have been deleted
|
|
|
6009 if (new_pos != old_pos) {
|
|
|
6010 code->at_put(new_pos, code->at(old_pos));
|
|
|
6011 }
|
|
|
6012 new_pos++;
|
|
|
6013 }
|
|
|
6014 old_pos++;
|
|
|
6015 }
|
|
|
6016 code->truncate(new_pos);
|
|
|
6017
|
|
|
6018 DEBUG_ONLY(verify(code));
|
|
|
6019 }
|
|
|
6020
|
|
|
6021 void ControlFlowOptimizer::delete_unnecessary_jumps(BlockList* code) {
|
|
|
6022 // skip the last block because there a branch is always necessary
|
|
|
6023 for (int i = code->length() - 2; i >= 0; i--) {
|
|
|
6024 BlockBegin* block = code->at(i);
|
|
|
6025 LIR_OpList* instructions = block->lir()->instructions_list();
|
|
|
6026
|
|
|
6027 LIR_Op* last_op = instructions->last();
|
|
|
6028 if (last_op->code() == lir_branch) {
|
|
|
6029 assert(last_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
|
|
|
6030 LIR_OpBranch* last_branch = (LIR_OpBranch*)last_op;
|
|
|
6031
|
|
|
6032 assert(last_branch->block() != NULL, "last branch must always have a block as target");
|
|
|
6033 assert(last_branch->label() == last_branch->block()->label(), "must be equal");
|
|
|
6034
|
|
|
6035 if (last_branch->info() == NULL) {
|
|
|
6036 if (last_branch->block() == code->at(i + 1)) {
|
|
|
6037
|
|
|
6038 TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting unconditional branch at end of block B%d", block->block_id()));
|
|
|
6039
|
|
|
6040 // delete last branch instruction
|
|
|
6041 instructions->truncate(instructions->length() - 1);
|
|
|
6042
|
|
|
6043 } else {
|
|
|
6044 LIR_Op* prev_op = instructions->at(instructions->length() - 2);
|
|
|
6045 if (prev_op->code() == lir_branch || prev_op->code() == lir_cond_float_branch) {
|
|
|
6046 assert(prev_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
|
|
|
6047 LIR_OpBranch* prev_branch = (LIR_OpBranch*)prev_op;
|
|
|
6048
|
|
|
6049 if (prev_branch->block() == code->at(i + 1) && prev_branch->info() == NULL) {
|
|
|
6050
|
|
|
6051 TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id()));
|
|
|
6052
|
|
|
6053 // eliminate a conditional branch to the immediate successor
|
|
|
6054 prev_branch->change_block(last_branch->block());
|
|
|
6055 prev_branch->negate_cond();
|
|
|
6056 instructions->truncate(instructions->length() - 1);
|
|
|
6057 }
|
|
|
6058 }
|
|
|
6059 }
|
|
|
6060 }
|
|
|
6061 }
|
|
|
6062 }
|
|
|
6063
|
|
|
6064 DEBUG_ONLY(verify(code));
|
|
|
6065 }
|
|
|
6066
|
|
|
6067 void ControlFlowOptimizer::delete_jumps_to_return(BlockList* code) {
|
|
|
6068 #ifdef ASSERT
|
|
|
6069 BitMap return_converted(BlockBegin::number_of_blocks());
|
|
|
6070 return_converted.clear();
|
|
|
6071 #endif
|
|
|
6072
|
|
|
6073 for (int i = code->length() - 1; i >= 0; i--) {
|
|
|
6074 BlockBegin* block = code->at(i);
|
|
|
6075 LIR_OpList* cur_instructions = block->lir()->instructions_list();
|
|
|
6076 LIR_Op* cur_last_op = cur_instructions->last();
|
|
|
6077
|
|
|
6078 assert(cur_instructions->at(0)->code() == lir_label, "first instruction must always be a label");
|
|
|
6079 if (cur_instructions->length() == 2 && cur_last_op->code() == lir_return) {
|
|
|
6080 // the block contains only a label and a return
|
|
|
6081 // if a predecessor ends with an unconditional jump to this block, then the jump
|
|
|
6082 // can be replaced with a return instruction
|
|
|
6083 //
|
|
|
6084 // Note: the original block with only a return statement cannot be deleted completely
|
|
|
6085 // because the predecessors might have other (conditional) jumps to this block
|
|
|
6086 // -> this may lead to unnecesary return instructions in the final code
|
|
|
6087
|
|
|
6088 assert(cur_last_op->info() == NULL, "return instructions do not have debug information");
|
|
|
6089 assert(block->number_of_sux() == 0 ||
|
|
|
6090 (return_converted.at(block->block_id()) && block->number_of_sux() == 1),
|
|
|
6091 "blocks that end with return must not have successors");
|
|
|
6092
|
|
|
6093 assert(cur_last_op->as_Op1() != NULL, "return must be LIR_Op1");
|
|
|
6094 LIR_Opr return_opr = ((LIR_Op1*)cur_last_op)->in_opr();
|
|
|
6095
|
|
|
6096 for (int j = block->number_of_preds() - 1; j >= 0; j--) {
|
|
|
6097 BlockBegin* pred = block->pred_at(j);
|
|
|
6098 LIR_OpList* pred_instructions = pred->lir()->instructions_list();
|
|
|
6099 LIR_Op* pred_last_op = pred_instructions->last();
|
|
|
6100
|
|
|
6101 if (pred_last_op->code() == lir_branch) {
|
|
|
6102 assert(pred_last_op->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
|
|
|
6103 LIR_OpBranch* pred_last_branch = (LIR_OpBranch*)pred_last_op;
|
|
|
6104
|
|
|
6105 if (pred_last_branch->block() == block && pred_last_branch->cond() == lir_cond_always && pred_last_branch->info() == NULL) {
|
|
|
6106 // replace the jump to a return with a direct return
|
|
|
6107 // Note: currently the edge between the blocks is not deleted
|
|
|
6108 pred_instructions->at_put(pred_instructions->length() - 1, new LIR_Op1(lir_return, return_opr));
|
|
|
6109 #ifdef ASSERT
|
|
|
6110 return_converted.set_bit(pred->block_id());
|
|
|
6111 #endif
|
|
|
6112 }
|
|
|
6113 }
|
|
|
6114 }
|
|
|
6115 }
|
|
|
6116 }
|
|
|
6117 }
|
|
|
6118
|
|
|
6119
|
|
|
6120 #ifdef ASSERT
|
|
|
6121 void ControlFlowOptimizer::verify(BlockList* code) {
|
|
|
6122 for (int i = 0; i < code->length(); i++) {
|
|
|
6123 BlockBegin* block = code->at(i);
|
|
|
6124 LIR_OpList* instructions = block->lir()->instructions_list();
|
|
|
6125
|
|
|
6126 int j;
|
|
|
6127 for (j = 0; j < instructions->length(); j++) {
|
|
|
6128 LIR_OpBranch* op_branch = instructions->at(j)->as_OpBranch();
|
|
|
6129
|
|
|
6130 if (op_branch != NULL) {
|
|
|
6131 assert(op_branch->block() == NULL || code->index_of(op_branch->block()) != -1, "branch target not valid");
|
|
|
6132 assert(op_branch->ublock() == NULL || code->index_of(op_branch->ublock()) != -1, "branch target not valid");
|
|
|
6133 }
|
|
|
6134 }
|
|
|
6135
|
|
|
6136 for (j = 0; j < block->number_of_sux() - 1; j++) {
|
|
|
6137 BlockBegin* sux = block->sux_at(j);
|
|
|
6138 assert(code->index_of(sux) != -1, "successor not valid");
|
|
|
6139 }
|
|
|
6140
|
|
|
6141 for (j = 0; j < block->number_of_preds() - 1; j++) {
|
|
|
6142 BlockBegin* pred = block->pred_at(j);
|
|
|
6143 assert(code->index_of(pred) != -1, "successor not valid");
|
|
|
6144 }
|
|
|
6145 }
|
|
|
6146 }
|
|
|
6147 #endif
|
|
|
6148
|
|
|
6149
|
|
|
6150 #ifndef PRODUCT
|
|
|
6151
|
|
|
6152 // Implementation of LinearStatistic
|
|
|
6153
|
|
|
6154 const char* LinearScanStatistic::counter_name(int counter_idx) {
|
|
|
6155 switch (counter_idx) {
|
|
|
6156 case counter_method: return "compiled methods";
|
|
|
6157 case counter_fpu_method: return "methods using fpu";
|
|
|
6158 case counter_loop_method: return "methods with loops";
|
|
|
6159 case counter_exception_method:return "methods with xhandler";
|
|
|
6160
|
|
|
6161 case counter_loop: return "loops";
|
|
|
6162 case counter_block: return "blocks";
|
|
|
6163 case counter_loop_block: return "blocks inside loop";
|
|
|
6164 case counter_exception_block: return "exception handler entries";
|
|
|
6165 case counter_interval: return "intervals";
|
|
|
6166 case counter_fixed_interval: return "fixed intervals";
|
|
|
6167 case counter_range: return "ranges";
|
|
|
6168 case counter_fixed_range: return "fixed ranges";
|
|
|
6169 case counter_use_pos: return "use positions";
|
|
|
6170 case counter_fixed_use_pos: return "fixed use positions";
|
|
|
6171 case counter_spill_slots: return "spill slots";
|
|
|
6172
|
|
|
6173 // counter for classes of lir instructions
|
|
|
6174 case counter_instruction: return "total instructions";
|
|
|
6175 case counter_label: return "labels";
|
|
|
6176 case counter_entry: return "method entries";
|
|
|
6177 case counter_return: return "method returns";
|
|
|
6178 case counter_call: return "method calls";
|
|
|
6179 case counter_move: return "moves";
|
|
|
6180 case counter_cmp: return "compare";
|
|
|
6181 case counter_cond_branch: return "conditional branches";
|
|
|
6182 case counter_uncond_branch: return "unconditional branches";
|
|
|
6183 case counter_stub_branch: return "branches to stub";
|
|
|
6184 case counter_alu: return "artithmetic + logic";
|
|
|
6185 case counter_alloc: return "allocations";
|
|
|
6186 case counter_sync: return "synchronisation";
|
|
|
6187 case counter_throw: return "throw";
|
|
|
6188 case counter_unwind: return "unwind";
|
|
|
6189 case counter_typecheck: return "type+null-checks";
|
|
|
6190 case counter_fpu_stack: return "fpu-stack";
|
|
|
6191 case counter_misc_inst: return "other instructions";
|
|
|
6192 case counter_other_inst: return "misc. instructions";
|
|
|
6193
|
|
|
6194 // counter for different types of moves
|
|
|
6195 case counter_move_total: return "total moves";
|
|
|
6196 case counter_move_reg_reg: return "register->register";
|
|
|
6197 case counter_move_reg_stack: return "register->stack";
|
|
|
6198 case counter_move_stack_reg: return "stack->register";
|
|
|
6199 case counter_move_stack_stack:return "stack->stack";
|
|
|
6200 case counter_move_reg_mem: return "register->memory";
|
|
|
6201 case counter_move_mem_reg: return "memory->register";
|
|
|
6202 case counter_move_const_any: return "constant->any";
|
|
|
6203
|
|
|
6204 case blank_line_1: return "";
|
|
|
6205 case blank_line_2: return "";
|
|
|
6206
|
|
|
6207 default: ShouldNotReachHere(); return "";
|
|
|
6208 }
|
|
|
6209 }
|
|
|
6210
|
|
|
6211 LinearScanStatistic::Counter LinearScanStatistic::base_counter(int counter_idx) {
|
|
|
6212 if (counter_idx == counter_fpu_method || counter_idx == counter_loop_method || counter_idx == counter_exception_method) {
|
|
|
6213 return counter_method;
|
|
|
6214 } else if (counter_idx == counter_loop_block || counter_idx == counter_exception_block) {
|
|
|
6215 return counter_block;
|
|
|
6216 } else if (counter_idx >= counter_instruction && counter_idx <= counter_other_inst) {
|
|
|
6217 return counter_instruction;
|
|
|
6218 } else if (counter_idx >= counter_move_total && counter_idx <= counter_move_const_any) {
|
|
|
6219 return counter_move_total;
|
|
|
6220 }
|
|
|
6221 return invalid_counter;
|
|
|
6222 }
|
|
|
6223
|
|
|
6224 LinearScanStatistic::LinearScanStatistic() {
|
|
|
6225 for (int i = 0; i < number_of_counters; i++) {
|
|
|
6226 _counters_sum[i] = 0;
|
|
|
6227 _counters_max[i] = -1;
|
|
|
6228 }
|
|
|
6229
|
|
|
6230 }
|
|
|
6231
|
|
|
6232 // add the method-local numbers to the total sum
|
|
|
6233 void LinearScanStatistic::sum_up(LinearScanStatistic &method_statistic) {
|
|
|
6234 for (int i = 0; i < number_of_counters; i++) {
|
|
|
6235 _counters_sum[i] += method_statistic._counters_sum[i];
|
|
|
6236 _counters_max[i] = MAX2(_counters_max[i], method_statistic._counters_sum[i]);
|
|
|
6237 }
|
|
|
6238 }
|
|
|
6239
|
|
|
6240 void LinearScanStatistic::print(const char* title) {
|
|
|
6241 if (CountLinearScan || TraceLinearScanLevel > 0) {
|
|
|
6242 tty->cr();
|
|
|
6243 tty->print_cr("***** LinearScan statistic - %s *****", title);
|
|
|
6244
|
|
|
6245 for (int i = 0; i < number_of_counters; i++) {
|
|
|
6246 if (_counters_sum[i] > 0 || _counters_max[i] >= 0) {
|
|
|
6247 tty->print("%25s: %8d", counter_name(i), _counters_sum[i]);
|
|
|
6248
|
|
|
6249 if (base_counter(i) != invalid_counter) {
|
|
|
6250 tty->print(" (%5.1f%%) ", _counters_sum[i] * 100.0 / _counters_sum[base_counter(i)]);
|
|
|
6251 } else {
|
|
|
6252 tty->print(" ");
|
|
|
6253 }
|
|
|
6254
|
|
|
6255 if (_counters_max[i] >= 0) {
|
|
|
6256 tty->print("%8d", _counters_max[i]);
|
|
|
6257 }
|
|
|
6258 }
|
|
|
6259 tty->cr();
|
|
|
6260 }
|
|
|
6261 }
|
|
|
6262 }
|
|
|
6263
|
|
|
6264 void LinearScanStatistic::collect(LinearScan* allocator) {
|
|
|
6265 inc_counter(counter_method);
|
|
|
6266 if (allocator->has_fpu_registers()) {
|
|
|
6267 inc_counter(counter_fpu_method);
|
|
|
6268 }
|
|
|
6269 if (allocator->num_loops() > 0) {
|
|
|
6270 inc_counter(counter_loop_method);
|
|
|
6271 }
|
|
|
6272 inc_counter(counter_loop, allocator->num_loops());
|
|
|
6273 inc_counter(counter_spill_slots, allocator->max_spills());
|
|
|
6274
|
|
|
6275 int i;
|
|
|
6276 for (i = 0; i < allocator->interval_count(); i++) {
|
|
|
6277 Interval* cur = allocator->interval_at(i);
|
|
|
6278
|
|
|
6279 if (cur != NULL) {
|
|
|
6280 inc_counter(counter_interval);
|
|
|
6281 inc_counter(counter_use_pos, cur->num_use_positions());
|
|
|
6282 if (LinearScan::is_precolored_interval(cur)) {
|
|
|
6283 inc_counter(counter_fixed_interval);
|
|
|
6284 inc_counter(counter_fixed_use_pos, cur->num_use_positions());
|
|
|
6285 }
|
|
|
6286
|
|
|
6287 Range* range = cur->first();
|
|
|
6288 while (range != Range::end()) {
|
|
|
6289 inc_counter(counter_range);
|
|
|
6290 if (LinearScan::is_precolored_interval(cur)) {
|
|
|
6291 inc_counter(counter_fixed_range);
|
|
|
6292 }
|
|
|
6293 range = range->next();
|
|
|
6294 }
|
|
|
6295 }
|
|
|
6296 }
|
|
|
6297
|
|
|
6298 bool has_xhandlers = false;
|
|
|
6299 // Note: only count blocks that are in code-emit order
|
|
|
6300 for (i = 0; i < allocator->ir()->code()->length(); i++) {
|
|
|
6301 BlockBegin* cur = allocator->ir()->code()->at(i);
|
|
|
6302
|
|
|
6303 inc_counter(counter_block);
|
|
|
6304 if (cur->loop_depth() > 0) {
|
|
|
6305 inc_counter(counter_loop_block);
|
|
|
6306 }
|
|
|
6307 if (cur->is_set(BlockBegin::exception_entry_flag)) {
|
|
|
6308 inc_counter(counter_exception_block);
|
|
|
6309 has_xhandlers = true;
|
|
|
6310 }
|
|
|
6311
|
|
|
6312 LIR_OpList* instructions = cur->lir()->instructions_list();
|
|
|
6313 for (int j = 0; j < instructions->length(); j++) {
|
|
|
6314 LIR_Op* op = instructions->at(j);
|
|
|
6315
|
|
|
6316 inc_counter(counter_instruction);
|
|
|
6317
|
|
|
6318 switch (op->code()) {
|
|
|
6319 case lir_label: inc_counter(counter_label); break;
|
|
|
6320 case lir_std_entry:
|
|
|
6321 case lir_osr_entry: inc_counter(counter_entry); break;
|
|
|
6322 case lir_return: inc_counter(counter_return); break;
|
|
|
6323
|
|
|
6324 case lir_rtcall:
|
|
|
6325 case lir_static_call:
|
|
|
6326 case lir_optvirtual_call:
|
|
|
6327 case lir_virtual_call: inc_counter(counter_call); break;
|
|
|
6328
|
|
|
6329 case lir_move: {
|
|
|
6330 inc_counter(counter_move);
|
|
|
6331 inc_counter(counter_move_total);
|
|
|
6332
|
|
|
6333 LIR_Opr in = op->as_Op1()->in_opr();
|
|
|
6334 LIR_Opr res = op->as_Op1()->result_opr();
|
|
|
6335 if (in->is_register()) {
|
|
|
6336 if (res->is_register()) {
|
|
|
6337 inc_counter(counter_move_reg_reg);
|
|
|
6338 } else if (res->is_stack()) {
|
|
|
6339 inc_counter(counter_move_reg_stack);
|
|
|
6340 } else if (res->is_address()) {
|
|
|
6341 inc_counter(counter_move_reg_mem);
|
|
|
6342 } else {
|
|
|
6343 ShouldNotReachHere();
|
|
|
6344 }
|
|
|
6345 } else if (in->is_stack()) {
|
|
|
6346 if (res->is_register()) {
|
|
|
6347 inc_counter(counter_move_stack_reg);
|
|
|
6348 } else {
|
|
|
6349 inc_counter(counter_move_stack_stack);
|
|
|
6350 }
|
|
|
6351 } else if (in->is_address()) {
|
|
|
6352 assert(res->is_register(), "must be");
|
|
|
6353 inc_counter(counter_move_mem_reg);
|
|
|
6354 } else if (in->is_constant()) {
|
|
|
6355 inc_counter(counter_move_const_any);
|
|
|
6356 } else {
|
|
|
6357 ShouldNotReachHere();
|
|
|
6358 }
|
|
|
6359 break;
|
|
|
6360 }
|
|
|
6361
|
|
|
6362 case lir_cmp: inc_counter(counter_cmp); break;
|
|
|
6363
|
|
|
6364 case lir_branch:
|
|
|
6365 case lir_cond_float_branch: {
|
|
|
6366 LIR_OpBranch* branch = op->as_OpBranch();
|
|
|
6367 if (branch->block() == NULL) {
|
|
|
6368 inc_counter(counter_stub_branch);
|
|
|
6369 } else if (branch->cond() == lir_cond_always) {
|
|
|
6370 inc_counter(counter_uncond_branch);
|
|
|
6371 } else {
|
|
|
6372 inc_counter(counter_cond_branch);
|
|
|
6373 }
|
|
|
6374 break;
|
|
|
6375 }
|
|
|
6376
|
|
|
6377 case lir_neg:
|
|
|
6378 case lir_add:
|
|
|
6379 case lir_sub:
|
|
|
6380 case lir_mul:
|
|
|
6381 case lir_mul_strictfp:
|
|
|
6382 case lir_div:
|
|
|
6383 case lir_div_strictfp:
|
|
|
6384 case lir_rem:
|
|
|
6385 case lir_sqrt:
|
|
|
6386 case lir_sin:
|
|
|
6387 case lir_cos:
|
|
|
6388 case lir_abs:
|
|
|
6389 case lir_log10:
|
|
|
6390 case lir_log:
|
|
|
6391 case lir_logic_and:
|
|
|
6392 case lir_logic_or:
|
|
|
6393 case lir_logic_xor:
|
|
|
6394 case lir_shl:
|
|
|
6395 case lir_shr:
|
|
|
6396 case lir_ushr: inc_counter(counter_alu); break;
|
|
|
6397
|
|
|
6398 case lir_alloc_object:
|
|
|
6399 case lir_alloc_array: inc_counter(counter_alloc); break;
|
|
|
6400
|
|
|
6401 case lir_monaddr:
|
|
|
6402 case lir_lock:
|
|
|
6403 case lir_unlock: inc_counter(counter_sync); break;
|
|
|
6404
|
|
|
6405 case lir_throw: inc_counter(counter_throw); break;
|
|
|
6406
|
|
|
6407 case lir_unwind: inc_counter(counter_unwind); break;
|
|
|
6408
|
|
|
6409 case lir_null_check:
|
|
|
6410 case lir_leal:
|
|
|
6411 case lir_instanceof:
|
|
|
6412 case lir_checkcast:
|
|
|
6413 case lir_store_check: inc_counter(counter_typecheck); break;
|
|
|
6414
|
|
|
6415 case lir_fpop_raw:
|
|
|
6416 case lir_fxch:
|
|
|
6417 case lir_fld: inc_counter(counter_fpu_stack); break;
|
|
|
6418
|
|
|
6419 case lir_nop:
|
|
|
6420 case lir_push:
|
|
|
6421 case lir_pop:
|
|
|
6422 case lir_convert:
|
|
|
6423 case lir_roundfp:
|
|
|
6424 case lir_cmove: inc_counter(counter_misc_inst); break;
|
|
|
6425
|
|
|
6426 default: inc_counter(counter_other_inst); break;
|
|
|
6427 }
|
|
|
6428 }
|
|
|
6429 }
|
|
|
6430
|
|
|
6431 if (has_xhandlers) {
|
|
|
6432 inc_counter(counter_exception_method);
|
|
|
6433 }
|
|
|
6434 }
|
|
|
6435
|
|
|
6436 void LinearScanStatistic::compute(LinearScan* allocator, LinearScanStatistic &global_statistic) {
|
|
|
6437 if (CountLinearScan || TraceLinearScanLevel > 0) {
|
|
|
6438
|
|
|
6439 LinearScanStatistic local_statistic = LinearScanStatistic();
|
|
|
6440
|
|
|
6441 local_statistic.collect(allocator);
|
|
|
6442 global_statistic.sum_up(local_statistic);
|
|
|
6443
|
|
|
6444 if (TraceLinearScanLevel > 2) {
|
|
|
6445 local_statistic.print("current local statistic");
|
|
|
6446 }
|
|
|
6447 }
|
|
|
6448 }
|
|
|
6449
|
|
|
6450
|
|
|
6451 // Implementation of LinearTimers
|
|
|
6452
|
|
|
6453 LinearScanTimers::LinearScanTimers() {
|
|
|
6454 for (int i = 0; i < number_of_timers; i++) {
|
|
|
6455 timer(i)->reset();
|
|
|
6456 }
|
|
|
6457 }
|
|
|
6458
|
|
|
6459 const char* LinearScanTimers::timer_name(int idx) {
|
|
|
6460 switch (idx) {
|
|
|
6461 case timer_do_nothing: return "Nothing (Time Check)";
|
|
|
6462 case timer_number_instructions: return "Number Instructions";
|
|
|
6463 case timer_compute_local_live_sets: return "Local Live Sets";
|
|
|
6464 case timer_compute_global_live_sets: return "Global Live Sets";
|
|
|
6465 case timer_build_intervals: return "Build Intervals";
|
|
|
6466 case timer_sort_intervals_before: return "Sort Intervals Before";
|
|
|
6467 case timer_allocate_registers: return "Allocate Registers";
|
|
|
6468 case timer_resolve_data_flow: return "Resolve Data Flow";
|
|
|
6469 case timer_sort_intervals_after: return "Sort Intervals After";
|
|
|
6470 case timer_eliminate_spill_moves: return "Spill optimization";
|
|
|
6471 case timer_assign_reg_num: return "Assign Reg Num";
|
|
|
6472 case timer_allocate_fpu_stack: return "Allocate FPU Stack";
|
|
|
6473 case timer_optimize_lir: return "Optimize LIR";
|
|
|
6474 default: ShouldNotReachHere(); return "";
|
|
|
6475 }
|
|
|
6476 }
|
|
|
6477
|
|
|
6478 void LinearScanTimers::begin_method() {
|
|
|
6479 if (TimeEachLinearScan) {
|
|
|
6480 // reset all timers to measure only current method
|
|
|
6481 for (int i = 0; i < number_of_timers; i++) {
|
|
|
6482 timer(i)->reset();
|
|
|
6483 }
|
|
|
6484 }
|
|
|
6485 }
|
|
|
6486
|
|
|
6487 void LinearScanTimers::end_method(LinearScan* allocator) {
|
|
|
6488 if (TimeEachLinearScan) {
|
|
|
6489
|
|
|
6490 double c = timer(timer_do_nothing)->seconds();
|
|
|
6491 double total = 0;
|
|
|
6492 for (int i = 1; i < number_of_timers; i++) {
|
|
|
6493 total += timer(i)->seconds() - c;
|
|
|
6494 }
|
|
|
6495
|
|
|
6496 if (total >= 0.0005) {
|
|
|
6497 // print all information in one line for automatic processing
|
|
|
6498 tty->print("@"); allocator->compilation()->method()->print_name();
|
|
|
6499
|
|
|
6500 tty->print("@ %d ", allocator->compilation()->method()->code_size());
|
|
|
6501 tty->print("@ %d ", allocator->block_at(allocator->block_count() - 1)->last_lir_instruction_id() / 2);
|
|
|
6502 tty->print("@ %d ", allocator->block_count());
|
|
|
6503 tty->print("@ %d ", allocator->num_virtual_regs());
|
|
|
6504 tty->print("@ %d ", allocator->interval_count());
|
|
|
6505 tty->print("@ %d ", allocator->_num_calls);
|
|
|
6506 tty->print("@ %d ", allocator->num_loops());
|
|
|
6507
|
|
|
6508 tty->print("@ %6.6f ", total);
|
|
|
6509 for (int i = 1; i < number_of_timers; i++) {
|
|
|
6510 tty->print("@ %4.1f ", ((timer(i)->seconds() - c) / total) * 100);
|
|
|
6511 }
|
|
|
6512 tty->cr();
|
|
|
6513 }
|
|
|
6514 }
|
|
|
6515 }
|
|
|
6516
|
|
|
6517 void LinearScanTimers::print(double total_time) {
|
|
|
6518 if (TimeLinearScan) {
|
|
|
6519 // correction value: sum of dummy-timer that only measures the time that
|
|
|
6520 // is necesary to start and stop itself
|
|
|
6521 double c = timer(timer_do_nothing)->seconds();
|
|
|
6522
|
|
|
6523 for (int i = 0; i < number_of_timers; i++) {
|
|
|
6524 double t = timer(i)->seconds();
|
|
|
6525 tty->print_cr(" %25s: %6.3f s (%4.1f%%) corrected: %6.3f s (%4.1f%%)", timer_name(i), t, (t / total_time) * 100.0, t - c, (t - c) / (total_time - 2 * number_of_timers * c) * 100);
|
|
|
6526 }
|
|
|
6527 }
|
|
|
6528 }
|
|
|
6529
|
|
|
6530 #endif // #ifndef PRODUCT
|
