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1 /*
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2 * Copyright 2005-2006 Sun Microsystems, Inc. All Rights Reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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20 * CA 95054 USA or visit www.sun.com if you need additional information or
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21 * have any questions.
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22 *
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23 */
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24
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25 class DebugInfoCache;
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26 class FpuStackAllocator;
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27 class IRScopeDebugInfo;
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28 class Interval;
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29 class IntervalWalker;
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30 class LIRGenerator;
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31 class LinearScan;
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32 class MoveResolver;
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33 class Range;
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34
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35 define_array(IntervalArray, Interval*)
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36 define_stack(IntervalList, IntervalArray)
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37
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38 define_array(IntervalsArray, IntervalList*)
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39 define_stack(IntervalsList, IntervalsArray)
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40
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41 define_array(OopMapArray, OopMap*)
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42 define_stack(OopMapList, OopMapArray)
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43
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44 define_array(ScopeValueArray, ScopeValue*)
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45
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46 define_array(LIR_OpListArray, LIR_OpList*);
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47 define_stack(LIR_OpListStack, LIR_OpListArray);
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48
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49
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50 enum IntervalUseKind {
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51 // priority of use kinds must be ascending
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52 noUse = 0,
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53 loopEndMarker = 1,
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54 shouldHaveRegister = 2,
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55 mustHaveRegister = 3,
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56
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57 firstValidKind = 1,
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58 lastValidKind = 3
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59 };
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60 define_array(UseKindArray, IntervalUseKind)
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61 define_stack(UseKindStack, UseKindArray)
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62
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63
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64 enum IntervalKind {
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65 fixedKind = 0, // interval pre-colored by LIR_Generator
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66 anyKind = 1, // no register/memory allocated by LIR_Generator
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67 nofKinds,
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68 firstKind = fixedKind
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69 };
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70
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71
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72 // during linear scan an interval is in one of four states in
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73 enum IntervalState {
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74 unhandledState = 0, // unhandled state (not processed yet)
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75 activeState = 1, // life and is in a physical register
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76 inactiveState = 2, // in a life time hole and is in a physical register
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77 handledState = 3, // spilled or not life again
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78 invalidState = -1
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79 };
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80
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81
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82 enum IntervalSpillState {
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83 noDefinitionFound, // starting state of calculation: no definition found yet
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84 oneDefinitionFound, // one definition has already been found.
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85 // Note: two consecutive definitions are treated as one (e.g. consecutive move and add because of two-operand LIR form)
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86 // the position of this definition is stored in _definition_pos
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87 oneMoveInserted, // one spill move has already been inserted.
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88 storeAtDefinition, // the interval should be stored immediately after its definition because otherwise
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89 // there would be multiple redundant stores
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90 startInMemory, // the interval starts in memory (e.g. method parameter), so a store is never necessary
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91 noOptimization // the interval has more then one definition (e.g. resulting from phi moves), so stores to memory are not optimized
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92 };
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93
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94
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95 #define for_each_interval_kind(kind) \
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96 for (IntervalKind kind = firstKind; kind < nofKinds; kind = (IntervalKind)(kind + 1))
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97
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98 #define for_each_visitor_mode(mode) \
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99 for (LIR_OpVisitState::OprMode mode = LIR_OpVisitState::firstMode; mode < LIR_OpVisitState::numModes; mode = (LIR_OpVisitState::OprMode)(mode + 1))
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100
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101
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102 class LinearScan : public CompilationResourceObj {
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103 // declare classes used by LinearScan as friends because they
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104 // need a wide variety of functions declared here
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105 //
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106 // Only the small interface to the rest of the compiler is public
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107 friend class Interval;
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108 friend class IntervalWalker;
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109 friend class LinearScanWalker;
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110 friend class FpuStackAllocator;
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111 friend class MoveResolver;
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112 friend class LinearScanStatistic;
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113 friend class LinearScanTimers;
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114 friend class RegisterVerifier;
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115
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116 public:
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117 enum {
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118 any_reg = -1,
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119 nof_cpu_regs = pd_nof_cpu_regs_linearscan,
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120 nof_fpu_regs = pd_nof_fpu_regs_linearscan,
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121 nof_xmm_regs = pd_nof_xmm_regs_linearscan,
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122 nof_regs = nof_cpu_regs + nof_fpu_regs + nof_xmm_regs
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123 };
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124
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125 private:
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126 Compilation* _compilation;
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127 IR* _ir;
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128 LIRGenerator* _gen;
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129 FrameMap* _frame_map;
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130
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131 BlockList _cached_blocks; // cached list with all blocks in linear-scan order (only correct if original list keeps unchanged)
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132 int _num_virtual_regs; // number of virtual registers (without new registers introduced because of splitting intervals)
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133 bool _has_fpu_registers; // true if this method uses any floating point registers (and so fpu stack allocation is necessary)
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134 int _num_calls; // total number of calls in this method
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135 int _max_spills; // number of stack slots used for intervals allocated to memory
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136 int _unused_spill_slot; // unused spill slot for a single-word value because of alignment of a double-word value
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137
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138 IntervalList _intervals; // mapping from register number to interval
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139 IntervalList* _new_intervals_from_allocation; // list with all intervals created during allocation when an existing interval is split
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140 IntervalArray* _sorted_intervals; // intervals sorted by Interval::from()
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141
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142 LIR_OpArray _lir_ops; // mapping from LIR_Op id to LIR_Op node
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143 BlockBeginArray _block_of_op; // mapping from LIR_Op id to the BlockBegin containing this instruction
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144 BitMap _has_info; // bit set for each LIR_Op id that has a CodeEmitInfo
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145 BitMap _has_call; // bit set for each LIR_Op id that destroys all caller save registers
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146 BitMap2D _interval_in_loop; // bit set for each virtual register that is contained in each loop
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147
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148 // cached debug info to prevent multiple creation of same object
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149 // TODO: cached scope values for registers could be static
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150 ScopeValueArray _scope_value_cache;
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151
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152 static ConstantOopWriteValue _oop_null_scope_value;
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153 static ConstantIntValue _int_m1_scope_value;
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154 static ConstantIntValue _int_0_scope_value;
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155 static ConstantIntValue _int_1_scope_value;
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156 static ConstantIntValue _int_2_scope_value;
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157
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158 // accessors
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159 IR* ir() const { return _ir; }
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160 Compilation* compilation() const { return _compilation; }
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161 LIRGenerator* gen() const { return _gen; }
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162 FrameMap* frame_map() const { return _frame_map; }
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163
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164 // unified bailout support
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165 void bailout(const char* msg) const { compilation()->bailout(msg); }
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166 bool bailed_out() const { return compilation()->bailed_out(); }
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167
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168 // access to block list (sorted in linear scan order)
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169 int block_count() const { assert(_cached_blocks.length() == ir()->linear_scan_order()->length(), "invalid cached block list"); return _cached_blocks.length(); }
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170 BlockBegin* block_at(int idx) const { assert(_cached_blocks.at(idx) == ir()->linear_scan_order()->at(idx), "invalid cached block list"); return _cached_blocks.at(idx); }
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171
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172 int num_virtual_regs() const { return _num_virtual_regs; }
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173 // size of live_in and live_out sets of BasicBlocks (BitMap needs rounded size for iteration)
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174 int live_set_size() const { return round_to(_num_virtual_regs, BitsPerWord); }
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175 bool has_fpu_registers() const { return _has_fpu_registers; }
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176 int num_loops() const { return ir()->num_loops(); }
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177 bool is_interval_in_loop(int interval, int loop) const { return _interval_in_loop.at(interval, loop); }
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178
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179 // handling of fpu stack allocation (platform dependent, needed for debug information generation)
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180 #ifdef IA32
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181 FpuStackAllocator* _fpu_stack_allocator;
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182 bool use_fpu_stack_allocation() const { return UseSSE < 2 && has_fpu_registers(); }
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183 #else
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184 bool use_fpu_stack_allocation() const { return false; }
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185 #endif
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186
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187
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188 // access to interval list
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189 int interval_count() const { return _intervals.length(); }
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190 Interval* interval_at(int reg_num) const { return _intervals.at(reg_num); }
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191
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192 IntervalList* new_intervals_from_allocation() const { return _new_intervals_from_allocation; }
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193
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194 // access to LIR_Ops and Blocks indexed by op_id
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195 int max_lir_op_id() const { assert(_lir_ops.length() > 0, "no operations"); return (_lir_ops.length() - 1) << 1; }
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196 LIR_Op* lir_op_with_id(int op_id) const { assert(op_id >= 0 && op_id <= max_lir_op_id() && op_id % 2 == 0, "op_id out of range or not even"); return _lir_ops.at(op_id >> 1); }
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197 BlockBegin* block_of_op_with_id(int op_id) const { assert(_block_of_op.length() > 0 && op_id >= 0 && op_id <= max_lir_op_id() + 1, "op_id out of range"); return _block_of_op.at(op_id >> 1); }
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198
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199 bool is_block_begin(int op_id) { return op_id == 0 || block_of_op_with_id(op_id) != block_of_op_with_id(op_id - 1); }
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200 bool covers_block_begin(int op_id_1, int op_id_2) { return block_of_op_with_id(op_id_1) != block_of_op_with_id(op_id_2); }
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201
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202 bool has_call(int op_id) { assert(op_id % 2 == 0, "must be even"); return _has_call.at(op_id >> 1); }
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203 bool has_info(int op_id) { assert(op_id % 2 == 0, "must be even"); return _has_info.at(op_id >> 1); }
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204
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205
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206 // functions for converting LIR-Operands to register numbers
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207 static bool is_valid_reg_num(int reg_num) { return reg_num >= 0; }
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208 static int reg_num(LIR_Opr opr);
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209 static int reg_numHi(LIR_Opr opr);
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210
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211 // functions for classification of intervals
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212 static bool is_precolored_interval(const Interval* i);
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213 static bool is_virtual_interval(const Interval* i);
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214
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215 static bool is_precolored_cpu_interval(const Interval* i);
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216 static bool is_virtual_cpu_interval(const Interval* i);
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217 static bool is_precolored_fpu_interval(const Interval* i);
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218 static bool is_virtual_fpu_interval(const Interval* i);
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219
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220 static bool is_in_fpu_register(const Interval* i);
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221 static bool is_oop_interval(const Interval* i);
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222
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223
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224 // General helper functions
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225 int allocate_spill_slot(bool double_word);
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226 void assign_spill_slot(Interval* it);
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227 void propagate_spill_slots();
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228
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229 Interval* create_interval(int reg_num);
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230 void append_interval(Interval* it);
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231 void copy_register_flags(Interval* from, Interval* to);
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232
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233 // platform dependent functions
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234 static bool is_processed_reg_num(int reg_num);
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235 static int num_physical_regs(BasicType type);
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236 static bool requires_adjacent_regs(BasicType type);
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237 static bool is_caller_save(int assigned_reg);
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238
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239 // spill move optimization: eliminate moves from register to stack if
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240 // stack slot is known to be correct
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241 void change_spill_definition_pos(Interval* interval, int def_pos);
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242 void change_spill_state(Interval* interval, int spill_pos);
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243 static bool must_store_at_definition(const Interval* i);
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244 void eliminate_spill_moves();
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245
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246 // Phase 1: number all instructions in all blocks
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247 void number_instructions();
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248
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249 // Phase 2: compute local live sets separately for each block
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250 // (sets live_gen and live_kill for each block)
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251 //
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252 // helper methods used by compute_local_live_sets()
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253 void set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill);
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254
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255 void compute_local_live_sets();
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256
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257 // Phase 3: perform a backward dataflow analysis to compute global live sets
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258 // (sets live_in and live_out for each block)
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259 void compute_global_live_sets();
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260
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261
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262 // Phase 4: build intervals
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263 // (fills the list _intervals)
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264 //
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265 // helper methods used by build_intervals()
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266 void add_use (Value value, int from, int to, IntervalUseKind use_kind);
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267
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268 void add_def (LIR_Opr opr, int def_pos, IntervalUseKind use_kind);
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269 void add_use (LIR_Opr opr, int from, int to, IntervalUseKind use_kind);
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270 void add_temp(LIR_Opr opr, int temp_pos, IntervalUseKind use_kind);
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271
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272 void add_def (int reg_num, int def_pos, IntervalUseKind use_kind, BasicType type);
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273 void add_use (int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type);
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274 void add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type);
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275
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276 // Add platform dependent kills for particular LIR ops. Can be used
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277 // to add platform dependent behaviour for some operations.
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278 void pd_add_temps(LIR_Op* op);
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279
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280 IntervalUseKind use_kind_of_output_operand(LIR_Op* op, LIR_Opr opr);
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281 IntervalUseKind use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr);
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282 void handle_method_arguments(LIR_Op* op);
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283 void handle_doubleword_moves(LIR_Op* op);
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284 void add_register_hints(LIR_Op* op);
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285
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286 void build_intervals();
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287
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288
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289 // Phase 5: actual register allocation
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290 // (Uses LinearScanWalker)
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291 //
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292 // helper functions for building a sorted list of intervals
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293 NOT_PRODUCT(bool is_sorted(IntervalArray* intervals);)
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294 static int interval_cmp(Interval** a, Interval** b);
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295 void add_to_list(Interval** first, Interval** prev, Interval* interval);
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296 void create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i));
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297
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298 void sort_intervals_before_allocation();
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299 void sort_intervals_after_allocation();
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300 void allocate_registers();
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301
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302
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303 // Phase 6: resolve data flow
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304 // (insert moves at edges between blocks if intervals have been split)
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305 //
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306 // helper functions for resolve_data_flow()
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307 Interval* split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode);
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308 Interval* interval_at_block_begin(BlockBegin* block, int reg_num);
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309 Interval* interval_at_block_end(BlockBegin* block, int reg_num);
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310 Interval* interval_at_op_id(int reg_num, int op_id);
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311 void resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver);
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312 void resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver);
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313 void resolve_data_flow();
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314
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315 void resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver);
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316 void resolve_exception_entry(BlockBegin* block, MoveResolver &move_resolver);
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317 void resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver);
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318 void resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver);
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319 void resolve_exception_handlers();
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320
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321 // Phase 7: assign register numbers back to LIR
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322 // (includes computation of debug information and oop maps)
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323 //
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324 // helper functions for assign_reg_num()
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325 VMReg vm_reg_for_interval(Interval* interval);
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326 VMReg vm_reg_for_operand(LIR_Opr opr);
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327
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328 static LIR_Opr operand_for_interval(Interval* interval);
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329 static LIR_Opr calc_operand_for_interval(const Interval* interval);
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330 LIR_Opr canonical_spill_opr(Interval* interval);
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331
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332 LIR_Opr color_lir_opr(LIR_Opr opr, int id, LIR_OpVisitState::OprMode);
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333
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334 // methods used for oop map computation
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335 IntervalWalker* init_compute_oop_maps();
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336 OopMap* compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site);
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337 void compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op);
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338
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339 // methods used for debug information computation
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340 void init_compute_debug_info();
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341
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342 MonitorValue* location_for_monitor_index(int monitor_index);
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343 LocationValue* location_for_name(int name, Location::Type loc_type);
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344
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345 int append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values);
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346 int append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values);
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347 int append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values);
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348
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349 IRScopeDebugInfo* compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state, int cur_bci, int stack_end, int locks_end);
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350 void compute_debug_info(CodeEmitInfo* info, int op_id);
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351
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352 void assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw);
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353 void assign_reg_num();
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354
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355
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356 // Phase 8: fpu stack allocation
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357 // (Used only on x86 when fpu operands are present)
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358 void allocate_fpu_stack();
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359
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360
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361 // helper functions for printing state
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362 #ifndef PRODUCT
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363 static void print_bitmap(BitMap& bitmap);
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364 void print_intervals(const char* label);
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365 void print_lir(int level, const char* label, bool hir_valid = true);
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366 #endif
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367
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368 #ifdef ASSERT
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369 // verification functions for allocation
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370 // (check that all intervals have a correct register and that no registers are overwritten)
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371 void verify();
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372 void verify_intervals();
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373 void verify_no_oops_in_fixed_intervals();
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374 void verify_constants();
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375 void verify_registers();
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376 #endif
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377
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378 public:
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379 // creation
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380 LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map);
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381
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382 // main entry function: perform linear scan register allocation
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383 void do_linear_scan();
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384
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385 // accessors used by Compilation
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386 int max_spills() const { return _max_spills; }
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387 int num_calls() const { assert(_num_calls >= 0, "not set"); return _num_calls; }
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388
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389 // entry functions for printing
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390 #ifndef PRODUCT
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391 static void print_statistics();
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392 static void print_timers(double total);
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393 #endif
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394 };
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395
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396
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397 // Helper class for ordering moves that are inserted at the same position in the LIR
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398 // When moves between registers are inserted, it is important that the moves are
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|
399 // ordered such that no register is overwritten. So moves from register to stack
|
|
400 // are processed prior to moves from stack to register. When moves have circular
|
|
401 // dependencies, a temporary stack slot is used to break the circle.
|
|
402 // The same logic is used in the LinearScanWalker and in LinearScan during resolve_data_flow
|
|
403 // and therefore factored out in a separate class
|
|
404 class MoveResolver: public StackObj {
|
|
405 private:
|
|
406 LinearScan* _allocator;
|
|
407
|
|
408 LIR_List* _insert_list;
|
|
409 int _insert_idx;
|
|
410 LIR_InsertionBuffer _insertion_buffer; // buffer where moves are inserted
|
|
411
|
|
412 IntervalList _mapping_from;
|
|
413 LIR_OprList _mapping_from_opr;
|
|
414 IntervalList _mapping_to;
|
|
415 bool _multiple_reads_allowed;
|
|
416 int _register_blocked[LinearScan::nof_regs];
|
|
417
|
|
418 int register_blocked(int reg) { assert(reg >= 0 && reg < LinearScan::nof_regs, "out of bounds"); return _register_blocked[reg]; }
|
|
419 void set_register_blocked(int reg, int direction) { assert(reg >= 0 && reg < LinearScan::nof_regs, "out of bounds"); assert(direction == 1 || direction == -1, "out of bounds"); _register_blocked[reg] += direction; }
|
|
420
|
|
421 void block_registers(Interval* it);
|
|
422 void unblock_registers(Interval* it);
|
|
423 bool save_to_process_move(Interval* from, Interval* to);
|
|
424
|
|
425 void create_insertion_buffer(LIR_List* list);
|
|
426 void append_insertion_buffer();
|
|
427 void insert_move(Interval* from_interval, Interval* to_interval);
|
|
428 void insert_move(LIR_Opr from_opr, Interval* to_interval);
|
|
429
|
|
430 DEBUG_ONLY(void verify_before_resolve();)
|
|
431 void resolve_mappings();
|
|
432 public:
|
|
433 MoveResolver(LinearScan* allocator);
|
|
434
|
|
435 DEBUG_ONLY(void check_empty();)
|
|
436 void set_multiple_reads_allowed() { _multiple_reads_allowed = true; }
|
|
437 void set_insert_position(LIR_List* insert_list, int insert_idx);
|
|
438 void move_insert_position(LIR_List* insert_list, int insert_idx);
|
|
439 void add_mapping(Interval* from, Interval* to);
|
|
440 void add_mapping(LIR_Opr from, Interval* to);
|
|
441 void resolve_and_append_moves();
|
|
442
|
|
443 LinearScan* allocator() { return _allocator; }
|
|
444 bool has_mappings() { return _mapping_from.length() > 0; }
|
|
445 };
|
|
446
|
|
447
|
|
448 class Range : public CompilationResourceObj {
|
|
449 friend class Interval;
|
|
450
|
|
451 private:
|
|
452 static Range* _end; // sentinel (from == to == max_jint)
|
|
453
|
|
454 int _from; // from (inclusive)
|
|
455 int _to; // to (exclusive)
|
|
456 Range* _next; // linear list of Ranges
|
|
457
|
|
458 // used only by class Interval, so hide them
|
|
459 bool intersects(Range* r) const { return intersects_at(r) != -1; }
|
|
460 int intersects_at(Range* r) const;
|
|
461
|
|
462 public:
|
|
463 Range(int from, int to, Range* next);
|
|
464
|
|
465 static void initialize();
|
|
466 static Range* end() { return _end; }
|
|
467
|
|
468 int from() const { return _from; }
|
|
469 int to() const { return _to; }
|
|
470 Range* next() const { return _next; }
|
|
471 void set_from(int from) { _from = from; }
|
|
472 void set_to(int to) { _to = to; }
|
|
473 void set_next(Range* next) { _next = next; }
|
|
474
|
|
475 // for testing
|
|
476 void print(outputStream* out = tty) const PRODUCT_RETURN;
|
|
477 };
|
|
478
|
|
479
|
|
480 // Interval is an ordered list of disjoint ranges.
|
|
481
|
|
482 // For pre-colored double word LIR_Oprs, one interval is created for
|
|
483 // the low word register and one is created for the hi word register.
|
|
484 // On Intel for FPU double registers only one interval is created. At
|
|
485 // all times assigned_reg contains the reg. number of the physical
|
|
486 // register.
|
|
487
|
|
488 // For LIR_Opr in virtual registers a single interval can represent
|
|
489 // single and double word values. When a physical register is
|
|
490 // assigned to the interval, assigned_reg contains the
|
|
491 // phys. reg. number and for double word values assigned_regHi the
|
|
492 // phys. reg. number of the hi word if there is any. For spilled
|
|
493 // intervals assigned_reg contains the stack index. assigned_regHi is
|
|
494 // always -1.
|
|
495
|
|
496 class Interval : public CompilationResourceObj {
|
|
497 private:
|
|
498 static Interval* _end; // sentinel (interval with only range Range::end())
|
|
499
|
|
500 int _reg_num;
|
|
501 BasicType _type; // valid only for virtual registers
|
|
502 Range* _first; // sorted list of Ranges
|
|
503 intStack _use_pos_and_kinds; // sorted list of use-positions and their according use-kinds
|
|
504
|
|
505 Range* _current; // interval iteration: the current Range
|
|
506 Interval* _next; // interval iteration: sorted list of Intervals (ends with sentinel)
|
|
507 IntervalState _state; // interval iteration: to which set belongs this interval
|
|
508
|
|
509
|
|
510 int _assigned_reg;
|
|
511 int _assigned_regHi;
|
|
512
|
|
513 int _cached_to; // cached value: to of last range (-1: not cached)
|
|
514 LIR_Opr _cached_opr;
|
|
515 VMReg _cached_vm_reg;
|
|
516
|
|
517 Interval* _split_parent; // the original interval where this interval is derived from
|
|
518 IntervalList _split_children; // list of all intervals that are split off from this interval (only available for split parents)
|
|
519 Interval* _current_split_child; // the current split child that has been active or inactive last (always stored in split parents)
|
|
520
|
|
521 int _canonical_spill_slot; // the stack slot where all split parts of this interval are spilled to (always stored in split parents)
|
|
522 bool _insert_move_when_activated; // true if move is inserted between _current_split_child and this interval when interval gets active the first time
|
|
523 IntervalSpillState _spill_state; // for spill move optimization
|
|
524 int _spill_definition_pos; // position where the interval is defined (if defined only once)
|
|
525 Interval* _register_hint; // this interval should be in the same register as the hint interval
|
|
526
|
|
527 int calc_to();
|
|
528 Interval* new_split_child();
|
|
529 public:
|
|
530 Interval(int reg_num);
|
|
531
|
|
532 static void initialize();
|
|
533 static Interval* end() { return _end; }
|
|
534
|
|
535 // accessors
|
|
536 int reg_num() const { return _reg_num; }
|
|
537 void set_reg_num(int r) { assert(_reg_num == -1, "cannot change reg_num"); _reg_num = r; }
|
|
538 BasicType type() const { assert(_reg_num == -1 || _reg_num >= LIR_OprDesc::vreg_base, "cannot access type for fixed interval"); return _type; }
|
|
539 void set_type(BasicType type) { assert(_reg_num < LIR_OprDesc::vreg_base || _type == T_ILLEGAL || _type == type, "overwriting existing type"); _type = type; }
|
|
540
|
|
541 Range* first() const { return _first; }
|
|
542 int from() const { return _first->from(); }
|
|
543 int to() { if (_cached_to == -1) _cached_to = calc_to(); assert(_cached_to == calc_to(), "invalid cached value"); return _cached_to; }
|
|
544 int num_use_positions() const { return _use_pos_and_kinds.length() / 2; }
|
|
545
|
|
546 Interval* next() const { return _next; }
|
|
547 Interval** next_addr() { return &_next; }
|
|
548 void set_next(Interval* next) { _next = next; }
|
|
549
|
|
550 int assigned_reg() const { return _assigned_reg; }
|
|
551 int assigned_regHi() const { return _assigned_regHi; }
|
|
552 void assign_reg(int reg) { _assigned_reg = reg; _assigned_regHi = LinearScan::any_reg; }
|
|
553 void assign_reg(int reg,int regHi) { _assigned_reg = reg; _assigned_regHi = regHi; }
|
|
554
|
|
555 Interval* register_hint(bool search_split_child = true) const; // calculation needed
|
|
556 void set_register_hint(Interval* i) { _register_hint = i; }
|
|
557
|
|
558 int state() const { return _state; }
|
|
559 void set_state(IntervalState s) { _state = s; }
|
|
560
|
|
561 // access to split parent and split children
|
|
562 bool is_split_parent() const { return _split_parent == this; }
|
|
563 bool is_split_child() const { return _split_parent != this; }
|
|
564 Interval* split_parent() const { assert(_split_parent->is_split_parent(), "must be"); return _split_parent; }
|
|
565 Interval* split_child_at_op_id(int op_id, LIR_OpVisitState::OprMode mode);
|
|
566 Interval* split_child_before_op_id(int op_id);
|
|
567 bool split_child_covers(int op_id, LIR_OpVisitState::OprMode mode);
|
|
568 DEBUG_ONLY(void check_split_children();)
|
|
569
|
|
570 // information stored in split parent, but available for all children
|
|
571 int canonical_spill_slot() const { return split_parent()->_canonical_spill_slot; }
|
|
572 void set_canonical_spill_slot(int slot) { assert(split_parent()->_canonical_spill_slot == -1, "overwriting existing value"); split_parent()->_canonical_spill_slot = slot; }
|
|
573 Interval* current_split_child() const { return split_parent()->_current_split_child; }
|
|
574 void make_current_split_child() { split_parent()->_current_split_child = this; }
|
|
575
|
|
576 bool insert_move_when_activated() const { return _insert_move_when_activated; }
|
|
577 void set_insert_move_when_activated(bool b) { _insert_move_when_activated = b; }
|
|
578
|
|
579 // for spill optimization
|
|
580 IntervalSpillState spill_state() const { return split_parent()->_spill_state; }
|
|
581 int spill_definition_pos() const { return split_parent()->_spill_definition_pos; }
|
|
582 void set_spill_state(IntervalSpillState state) { assert(state >= spill_state(), "state cannot decrease"); split_parent()->_spill_state = state; }
|
|
583 void set_spill_definition_pos(int pos) { assert(spill_definition_pos() == -1, "cannot set the position twice"); split_parent()->_spill_definition_pos = pos; }
|
|
584 // returns true if this interval has a shadow copy on the stack that is always correct
|
|
585 bool always_in_memory() const { return split_parent()->_spill_state == storeAtDefinition || split_parent()->_spill_state == startInMemory; }
|
|
586
|
|
587 // caching of values that take time to compute and are used multiple times
|
|
588 LIR_Opr cached_opr() const { return _cached_opr; }
|
|
589 VMReg cached_vm_reg() const { return _cached_vm_reg; }
|
|
590 void set_cached_opr(LIR_Opr opr) { _cached_opr = opr; }
|
|
591 void set_cached_vm_reg(VMReg reg) { _cached_vm_reg = reg; }
|
|
592
|
|
593 // access to use positions
|
|
594 int first_usage(IntervalUseKind min_use_kind) const; // id of the first operation requiring this interval in a register
|
|
595 int next_usage(IntervalUseKind min_use_kind, int from) const; // id of next usage seen from the given position
|
|
596 int next_usage_exact(IntervalUseKind exact_use_kind, int from) const;
|
|
597 int previous_usage(IntervalUseKind min_use_kind, int from) const;
|
|
598
|
|
599 // manipulating intervals
|
|
600 void add_use_pos(int pos, IntervalUseKind use_kind);
|
|
601 void add_range(int from, int to);
|
|
602 Interval* split(int split_pos);
|
|
603 Interval* split_from_start(int split_pos);
|
|
604 void remove_first_use_pos() { _use_pos_and_kinds.truncate(_use_pos_and_kinds.length() - 2); }
|
|
605
|
|
606 // test intersection
|
|
607 bool covers(int op_id, LIR_OpVisitState::OprMode mode) const;
|
|
608 bool has_hole_between(int from, int to);
|
|
609 bool intersects(Interval* i) const { return _first->intersects(i->_first); }
|
|
610 int intersects_at(Interval* i) const { return _first->intersects_at(i->_first); }
|
|
611
|
|
612 // range iteration
|
|
613 void rewind_range() { _current = _first; }
|
|
614 void next_range() { assert(this != _end, "not allowed on sentinel"); _current = _current->next(); }
|
|
615 int current_from() const { return _current->from(); }
|
|
616 int current_to() const { return _current->to(); }
|
|
617 bool current_at_end() const { return _current == Range::end(); }
|
|
618 bool current_intersects(Interval* it) { return _current->intersects(it->_current); };
|
|
619 int current_intersects_at(Interval* it) { return _current->intersects_at(it->_current); };
|
|
620
|
|
621 // printing
|
|
622 void print(outputStream* out = tty) const PRODUCT_RETURN;
|
|
623 };
|
|
624
|
|
625
|
|
626 class IntervalWalker : public CompilationResourceObj {
|
|
627 protected:
|
|
628 Compilation* _compilation;
|
|
629 LinearScan* _allocator;
|
|
630
|
|
631 Interval* _unhandled_first[nofKinds]; // sorted list of intervals, not life before the current position
|
|
632 Interval* _active_first [nofKinds]; // sorted list of intervals, life at the current position
|
|
633 Interval* _inactive_first [nofKinds]; // sorted list of intervals, intervals in a life time hole at the current position
|
|
634
|
|
635 Interval* _current; // the current interval coming from unhandled list
|
|
636 int _current_position; // the current position (intercept point through the intervals)
|
|
637 IntervalKind _current_kind; // and whether it is fixed_kind or any_kind.
|
|
638
|
|
639
|
|
640 Compilation* compilation() const { return _compilation; }
|
|
641 LinearScan* allocator() const { return _allocator; }
|
|
642
|
|
643 // unified bailout support
|
|
644 void bailout(const char* msg) const { compilation()->bailout(msg); }
|
|
645 bool bailed_out() const { return compilation()->bailed_out(); }
|
|
646
|
|
647 void check_bounds(IntervalKind kind) { assert(kind >= fixedKind && kind <= anyKind, "invalid interval_kind"); }
|
|
648
|
|
649 Interval** unhandled_first_addr(IntervalKind kind) { check_bounds(kind); return &_unhandled_first[kind]; }
|
|
650 Interval** active_first_addr(IntervalKind kind) { check_bounds(kind); return &_active_first[kind]; }
|
|
651 Interval** inactive_first_addr(IntervalKind kind) { check_bounds(kind); return &_inactive_first[kind]; }
|
|
652
|
|
653 void append_unsorted(Interval** first, Interval* interval);
|
|
654 void append_sorted(Interval** first, Interval* interval);
|
|
655 void append_to_unhandled(Interval** list, Interval* interval);
|
|
656
|
|
657 bool remove_from_list(Interval** list, Interval* i);
|
|
658 void remove_from_list(Interval* i);
|
|
659
|
|
660 void next_interval();
|
|
661 Interval* current() const { return _current; }
|
|
662 IntervalKind current_kind() const { return _current_kind; }
|
|
663
|
|
664 void walk_to(IntervalState state, int from);
|
|
665
|
|
666 // activate_current() is called when an unhandled interval becomes active (in current(), current_kind()).
|
|
667 // Return false if current() should not be moved the the active interval list.
|
|
668 // It is safe to append current to any interval list but the unhandled list.
|
|
669 virtual bool activate_current() { return true; }
|
|
670
|
|
671 // interval_moved() is called whenever an interval moves from one interval list to another.
|
|
672 // In the implementation of this method it is prohibited to move the interval to any list.
|
|
673 virtual void interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to);
|
|
674
|
|
675 public:
|
|
676 IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first);
|
|
677
|
|
678 Interval* unhandled_first(IntervalKind kind) { check_bounds(kind); return _unhandled_first[kind]; }
|
|
679 Interval* active_first(IntervalKind kind) { check_bounds(kind); return _active_first[kind]; }
|
|
680 Interval* inactive_first(IntervalKind kind) { check_bounds(kind); return _inactive_first[kind]; }
|
|
681
|
|
682 // active contains the intervals that are live after the lir_op
|
|
683 void walk_to(int lir_op_id);
|
|
684 // active contains the intervals that are live before the lir_op
|
|
685 void walk_before(int lir_op_id) { walk_to(lir_op_id-1); }
|
|
686 // walk through all intervals
|
|
687 void walk() { walk_to(max_jint); }
|
|
688
|
|
689 int current_position() { return _current_position; }
|
|
690 };
|
|
691
|
|
692
|
|
693 // The actual linear scan register allocator
|
|
694 class LinearScanWalker : public IntervalWalker {
|
|
695 enum {
|
|
696 any_reg = LinearScan::any_reg
|
|
697 };
|
|
698
|
|
699 private:
|
|
700 int _first_reg; // the reg. number of the first phys. register
|
|
701 int _last_reg; // the reg. nmber of the last phys. register
|
|
702 int _num_phys_regs; // required by current interval
|
|
703 bool _adjacent_regs; // have lo/hi words of phys. regs be adjacent
|
|
704
|
|
705 int _use_pos[LinearScan::nof_regs];
|
|
706 int _block_pos[LinearScan::nof_regs];
|
|
707 IntervalList* _spill_intervals[LinearScan::nof_regs];
|
|
708
|
|
709 MoveResolver _move_resolver; // for ordering spill moves
|
|
710
|
|
711 // accessors mapped to same functions in class LinearScan
|
|
712 int block_count() const { return allocator()->block_count(); }
|
|
713 BlockBegin* block_at(int idx) const { return allocator()->block_at(idx); }
|
|
714 BlockBegin* block_of_op_with_id(int op_id) const { return allocator()->block_of_op_with_id(op_id); }
|
|
715
|
|
716 void init_use_lists(bool only_process_use_pos);
|
|
717 void exclude_from_use(int reg);
|
|
718 void exclude_from_use(Interval* i);
|
|
719 void set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos);
|
|
720 void set_use_pos(Interval* i, int use_pos, bool only_process_use_pos);
|
|
721 void set_block_pos(int reg, Interval* i, int block_pos);
|
|
722 void set_block_pos(Interval* i, int block_pos);
|
|
723
|
|
724 void free_exclude_active_fixed();
|
|
725 void free_exclude_active_any();
|
|
726 void free_collect_inactive_fixed(Interval* cur);
|
|
727 void free_collect_inactive_any(Interval* cur);
|
|
728 void free_collect_unhandled(IntervalKind kind, Interval* cur);
|
|
729 void spill_exclude_active_fixed();
|
|
730 void spill_block_unhandled_fixed(Interval* cur);
|
|
731 void spill_block_inactive_fixed(Interval* cur);
|
|
732 void spill_collect_active_any();
|
|
733 void spill_collect_inactive_any(Interval* cur);
|
|
734
|
|
735 void insert_move(int op_id, Interval* src_it, Interval* dst_it);
|
|
736 int find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos);
|
|
737 int find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization);
|
|
738 void split_before_usage(Interval* it, int min_split_pos, int max_split_pos);
|
|
739 void split_for_spilling(Interval* it);
|
|
740 void split_stack_interval(Interval* it);
|
|
741 void split_when_partial_register_available(Interval* it, int register_available_until);
|
|
742 void split_and_spill_interval(Interval* it);
|
|
743
|
|
744 int find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split);
|
|
745 int find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split);
|
|
746 bool alloc_free_reg(Interval* cur);
|
|
747
|
|
748 int find_locked_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split);
|
|
749 int find_locked_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split);
|
|
750 void split_and_spill_intersecting_intervals(int reg, int regHi);
|
|
751 void alloc_locked_reg(Interval* cur);
|
|
752
|
|
753 bool no_allocation_possible(Interval* cur);
|
|
754 void update_phys_reg_range(bool requires_cpu_register);
|
|
755 void init_vars_for_alloc(Interval* cur);
|
|
756 bool pd_init_regs_for_alloc(Interval* cur);
|
|
757
|
|
758 void combine_spilled_intervals(Interval* cur);
|
|
759 bool is_move(LIR_Op* op, Interval* from, Interval* to);
|
|
760
|
|
761 bool activate_current();
|
|
762
|
|
763 public:
|
|
764 LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first);
|
|
765
|
|
766 // must be called when all intervals are allocated
|
|
767 void finish_allocation() { _move_resolver.resolve_and_append_moves(); }
|
|
768 };
|
|
769
|
|
770
|
|
771
|
|
772 /*
|
|
773 When a block has more than one predecessor, and all predecessors end with
|
|
774 the same sequence of move-instructions, than this moves can be placed once
|
|
775 at the beginning of the block instead of multiple times in the predecessors.
|
|
776
|
|
777 Similarly, when a block has more than one successor, then equal sequences of
|
|
778 moves at the beginning of the successors can be placed once at the end of
|
|
779 the block. But because the moves must be inserted before all branch
|
|
780 instructions, this works only when there is exactly one conditional branch
|
|
781 at the end of the block (because the moves must be inserted before all
|
|
782 branches, but after all compares).
|
|
783
|
|
784 This optimization affects all kind of moves (reg->reg, reg->stack and
|
|
785 stack->reg). Because this optimization works best when a block contains only
|
|
786 few moves, it has a huge impact on the number of blocks that are totally
|
|
787 empty.
|
|
788 */
|
|
789 class EdgeMoveOptimizer : public StackObj {
|
|
790 private:
|
|
791 // the class maintains a list with all lir-instruction-list of the
|
|
792 // successors (predecessors) and the current index into the lir-lists
|
|
793 LIR_OpListStack _edge_instructions;
|
|
794 intStack _edge_instructions_idx;
|
|
795
|
|
796 void init_instructions();
|
|
797 void append_instructions(LIR_OpList* instructions, int instructions_idx);
|
|
798 LIR_Op* instruction_at(int edge);
|
|
799 void remove_cur_instruction(int edge, bool decrement_index);
|
|
800
|
|
801 bool operations_different(LIR_Op* op1, LIR_Op* op2);
|
|
802
|
|
803 void optimize_moves_at_block_end(BlockBegin* cur);
|
|
804 void optimize_moves_at_block_begin(BlockBegin* cur);
|
|
805
|
|
806 EdgeMoveOptimizer();
|
|
807
|
|
808 public:
|
|
809 static void optimize(BlockList* code);
|
|
810 };
|
|
811
|
|
812
|
|
813
|
|
814 class ControlFlowOptimizer : public StackObj {
|
|
815 private:
|
|
816 BlockList _original_preds;
|
|
817
|
|
818 enum {
|
|
819 ShortLoopSize = 5
|
|
820 };
|
|
821 void reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx);
|
|
822 void reorder_short_loops(BlockList* code);
|
|
823
|
|
824 bool can_delete_block(BlockBegin* cur);
|
|
825 void substitute_branch_target(BlockBegin* cur, BlockBegin* target_from, BlockBegin* target_to);
|
|
826 void delete_empty_blocks(BlockList* code);
|
|
827
|
|
828 void delete_unnecessary_jumps(BlockList* code);
|
|
829 void delete_jumps_to_return(BlockList* code);
|
|
830
|
|
831 DEBUG_ONLY(void verify(BlockList* code);)
|
|
832
|
|
833 ControlFlowOptimizer();
|
|
834 public:
|
|
835 static void optimize(BlockList* code);
|
|
836 };
|
|
837
|
|
838
|
|
839 #ifndef PRODUCT
|
|
840
|
|
841 // Helper class for collecting statistics of LinearScan
|
|
842 class LinearScanStatistic : public StackObj {
|
|
843 public:
|
|
844 enum Counter {
|
|
845 // general counters
|
|
846 counter_method,
|
|
847 counter_fpu_method,
|
|
848 counter_loop_method,
|
|
849 counter_exception_method,
|
|
850 counter_loop,
|
|
851 counter_block,
|
|
852 counter_loop_block,
|
|
853 counter_exception_block,
|
|
854 counter_interval,
|
|
855 counter_fixed_interval,
|
|
856 counter_range,
|
|
857 counter_fixed_range,
|
|
858 counter_use_pos,
|
|
859 counter_fixed_use_pos,
|
|
860 counter_spill_slots,
|
|
861 blank_line_1,
|
|
862
|
|
863 // counter for classes of lir instructions
|
|
864 counter_instruction,
|
|
865 counter_label,
|
|
866 counter_entry,
|
|
867 counter_return,
|
|
868 counter_call,
|
|
869 counter_move,
|
|
870 counter_cmp,
|
|
871 counter_cond_branch,
|
|
872 counter_uncond_branch,
|
|
873 counter_stub_branch,
|
|
874 counter_alu,
|
|
875 counter_alloc,
|
|
876 counter_sync,
|
|
877 counter_throw,
|
|
878 counter_unwind,
|
|
879 counter_typecheck,
|
|
880 counter_fpu_stack,
|
|
881 counter_misc_inst,
|
|
882 counter_other_inst,
|
|
883 blank_line_2,
|
|
884
|
|
885 // counter for different types of moves
|
|
886 counter_move_total,
|
|
887 counter_move_reg_reg,
|
|
888 counter_move_reg_stack,
|
|
889 counter_move_stack_reg,
|
|
890 counter_move_stack_stack,
|
|
891 counter_move_reg_mem,
|
|
892 counter_move_mem_reg,
|
|
893 counter_move_const_any,
|
|
894
|
|
895 number_of_counters,
|
|
896 invalid_counter = -1
|
|
897 };
|
|
898
|
|
899 private:
|
|
900 int _counters_sum[number_of_counters];
|
|
901 int _counters_max[number_of_counters];
|
|
902
|
|
903 void inc_counter(Counter idx, int value = 1) { _counters_sum[idx] += value; }
|
|
904
|
|
905 const char* counter_name(int counter_idx);
|
|
906 Counter base_counter(int counter_idx);
|
|
907
|
|
908 void sum_up(LinearScanStatistic &method_statistic);
|
|
909 void collect(LinearScan* allocator);
|
|
910
|
|
911 public:
|
|
912 LinearScanStatistic();
|
|
913 void print(const char* title);
|
|
914 static void compute(LinearScan* allocator, LinearScanStatistic &global_statistic);
|
|
915 };
|
|
916
|
|
917
|
|
918 // Helper class for collecting compilation time of LinearScan
|
|
919 class LinearScanTimers : public StackObj {
|
|
920 public:
|
|
921 enum Timer {
|
|
922 timer_do_nothing,
|
|
923 timer_number_instructions,
|
|
924 timer_compute_local_live_sets,
|
|
925 timer_compute_global_live_sets,
|
|
926 timer_build_intervals,
|
|
927 timer_sort_intervals_before,
|
|
928 timer_allocate_registers,
|
|
929 timer_resolve_data_flow,
|
|
930 timer_sort_intervals_after,
|
|
931 timer_eliminate_spill_moves,
|
|
932 timer_assign_reg_num,
|
|
933 timer_allocate_fpu_stack,
|
|
934 timer_optimize_lir,
|
|
935
|
|
936 number_of_timers
|
|
937 };
|
|
938
|
|
939 private:
|
|
940 elapsedTimer _timers[number_of_timers];
|
|
941 const char* timer_name(int idx);
|
|
942
|
|
943 public:
|
|
944 LinearScanTimers();
|
|
945
|
|
946 void begin_method(); // called for each method when register allocation starts
|
|
947 void end_method(LinearScan* allocator); // called for each method when register allocation completed
|
|
948 void print(double total_time); // called before termination of VM to print global summary
|
|
949
|
|
950 elapsedTimer* timer(int idx) { return &(_timers[idx]); }
|
|
951 };
|
|
952
|
|
953
|
|
954 #endif // ifndef PRODUCT
|
|
955
|
|
956
|
|
957 // Pick up platform-dependent implementation details
|
|
958 # include "incls/_c1_LinearScan_pd.hpp.incl"
|