Mercurial > hg > truffle
annotate src/share/vm/opto/matcher.hpp @ 253:b0fe4deeb9fb
6726999: nsk/stress/jck12a/jck12a010 assert(n != null,"Bad immediate dominator info.")
Summary: Escape Analysis fixes.
Reviewed-by: never, rasbold
| author | kvn |
|---|---|
| date | Mon, 28 Jul 2008 17:12:52 -0700 |
| parents | 9c2ecc2ffb12 |
| children | 36ccc817fca4 |
| rev | line source |
|---|---|
| 0 | 1 /* |
| 196 | 2 * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
| 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 20 * CA 95054 USA or visit www.sun.com if you need additional information or | |
| 21 * have any questions. | |
| 22 * | |
| 23 */ | |
| 24 | |
| 25 class Compile; | |
| 26 class Node; | |
| 27 class MachNode; | |
| 28 class MachTypeNode; | |
| 29 class MachOper; | |
| 30 | |
| 31 //---------------------------Matcher------------------------------------------- | |
| 32 class Matcher : public PhaseTransform { | |
| 33 friend class VMStructs; | |
| 34 // Private arena of State objects | |
| 35 ResourceArea _states_arena; | |
| 36 | |
| 37 VectorSet _visited; // Visit bits | |
| 38 | |
| 39 // Used to control the Label pass | |
| 40 VectorSet _shared; // Shared Ideal Node | |
| 41 VectorSet _dontcare; // Nothing the matcher cares about | |
| 42 | |
| 43 // Private methods which perform the actual matching and reduction | |
| 44 // Walks the label tree, generating machine nodes | |
| 45 MachNode *ReduceInst( State *s, int rule, Node *&mem); | |
| 46 void ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach); | |
| 47 uint ReduceInst_Interior(State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds); | |
| 48 void ReduceOper( State *s, int newrule, Node *&mem, MachNode *mach ); | |
| 49 | |
| 50 // If this node already matched using "rule", return the MachNode for it. | |
|
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51 MachNode* find_shared_node(Node* n, uint rule); |
| 0 | 52 |
| 53 // Convert a dense opcode number to an expanded rule number | |
| 54 const int *_reduceOp; | |
| 55 const int *_leftOp; | |
| 56 const int *_rightOp; | |
| 57 | |
| 58 // Map dense opcode number to info on when rule is swallowed constant. | |
| 59 const bool *_swallowed; | |
| 60 | |
| 61 // Map dense rule number to determine if this is an instruction chain rule | |
| 62 const uint _begin_inst_chain_rule; | |
| 63 const uint _end_inst_chain_rule; | |
| 64 | |
| 65 // We want to clone constants and possible CmpI-variants. | |
| 66 // If we do not clone CmpI, then we can have many instances of | |
| 67 // condition codes alive at once. This is OK on some chips and | |
| 68 // bad on others. Hence the machine-dependent table lookup. | |
| 69 const char *_must_clone; | |
| 70 | |
| 71 // Find shared Nodes, or Nodes that otherwise are Matcher roots | |
| 72 void find_shared( Node *n ); | |
| 73 | |
| 74 // Debug and profile information for nodes in old space: | |
| 75 GrowableArray<Node_Notes*>* _old_node_note_array; | |
| 76 | |
| 77 // Node labeling iterator for instruction selection | |
| 78 Node *Label_Root( const Node *n, State *svec, Node *control, const Node *mem ); | |
| 79 | |
| 80 Node *transform( Node *dummy ); | |
| 81 | |
| 82 Node_List &_proj_list; // For Machine nodes killing many values | |
| 83 | |
|
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84 Node_Array _shared_nodes; |
| 0 | 85 |
| 86 debug_only(Node_Array _old2new_map;) // Map roots of ideal-trees to machine-roots | |
| 222 | 87 debug_only(Node_Array _new2old_map;) // Maps machine nodes back to ideal |
| 0 | 88 |
| 89 // Accessors for the inherited field PhaseTransform::_nodes: | |
| 90 void grow_new_node_array(uint idx_limit) { | |
| 91 _nodes.map(idx_limit-1, NULL); | |
| 92 } | |
| 93 bool has_new_node(const Node* n) const { | |
| 94 return _nodes.at(n->_idx) != NULL; | |
| 95 } | |
| 96 Node* new_node(const Node* n) const { | |
| 97 assert(has_new_node(n), "set before get"); | |
| 98 return _nodes.at(n->_idx); | |
| 99 } | |
| 100 void set_new_node(const Node* n, Node *nn) { | |
| 101 assert(!has_new_node(n), "set only once"); | |
| 102 _nodes.map(n->_idx, nn); | |
| 103 } | |
| 104 | |
| 105 #ifdef ASSERT | |
| 106 // Make sure only new nodes are reachable from this node | |
| 107 void verify_new_nodes_only(Node* root); | |
|
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108 |
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109 Node* _mem_node; // Ideal memory node consumed by mach node |
| 0 | 110 #endif |
| 111 | |
| 112 public: | |
| 113 int LabelRootDepth; | |
| 114 static const int base2reg[]; // Map Types to machine register types | |
| 115 // Convert ideal machine register to a register mask for spill-loads | |
| 116 static const RegMask *idealreg2regmask[]; | |
| 117 RegMask *idealreg2spillmask[_last_machine_leaf]; | |
| 118 RegMask *idealreg2debugmask[_last_machine_leaf]; | |
| 119 void init_spill_mask( Node *ret ); | |
| 120 // Convert machine register number to register mask | |
| 121 static uint mreg2regmask_max; | |
| 122 static RegMask mreg2regmask[]; | |
| 123 static RegMask STACK_ONLY_mask; | |
| 124 | |
| 125 bool is_shared( Node *n ) { return _shared.test(n->_idx) != 0; } | |
| 126 void set_shared( Node *n ) { _shared.set(n->_idx); } | |
| 127 bool is_visited( Node *n ) { return _visited.test(n->_idx) != 0; } | |
| 128 void set_visited( Node *n ) { _visited.set(n->_idx); } | |
| 129 bool is_dontcare( Node *n ) { return _dontcare.test(n->_idx) != 0; } | |
| 130 void set_dontcare( Node *n ) { _dontcare.set(n->_idx); } | |
| 131 | |
| 132 // Mode bit to tell DFA and expand rules whether we are running after | |
| 133 // (or during) register selection. Usually, the matcher runs before, | |
| 134 // but it will also get called to generate post-allocation spill code. | |
| 135 // In this situation, it is a deadly error to attempt to allocate more | |
| 136 // temporary registers. | |
| 137 bool _allocation_started; | |
| 138 | |
| 139 // Machine register names | |
| 140 static const char *regName[]; | |
| 141 // Machine register encodings | |
| 142 static const unsigned char _regEncode[]; | |
| 143 // Machine Node names | |
| 144 const char **_ruleName; | |
| 145 // Rules that are cheaper to rematerialize than to spill | |
| 146 static const uint _begin_rematerialize; | |
| 147 static const uint _end_rematerialize; | |
| 148 | |
| 149 // An array of chars, from 0 to _last_Mach_Reg. | |
| 150 // No Save = 'N' (for register windows) | |
| 151 // Save on Entry = 'E' | |
| 152 // Save on Call = 'C' | |
| 153 // Always Save = 'A' (same as SOE + SOC) | |
| 154 const char *_register_save_policy; | |
| 155 const char *_c_reg_save_policy; | |
| 156 // Convert a machine register to a machine register type, so-as to | |
| 157 // properly match spill code. | |
| 158 const int *_register_save_type; | |
| 159 // Maps from machine register to boolean; true if machine register can | |
| 160 // be holding a call argument in some signature. | |
| 161 static bool can_be_java_arg( int reg ); | |
| 162 // Maps from machine register to boolean; true if machine register holds | |
| 163 // a spillable argument. | |
| 164 static bool is_spillable_arg( int reg ); | |
| 165 | |
| 166 // List of IfFalse or IfTrue Nodes that indicate a taken null test. | |
| 167 // List is valid in the post-matching space. | |
| 168 Node_List _null_check_tests; | |
| 169 void collect_null_checks( Node *proj ); | |
| 170 void validate_null_checks( ); | |
| 171 | |
| 172 Matcher( Node_List &proj_list ); | |
| 173 | |
| 174 // Select instructions for entire method | |
| 175 void match( ); | |
| 176 // Helper for match | |
| 177 OptoReg::Name warp_incoming_stk_arg( VMReg reg ); | |
| 178 | |
| 179 // Transform, then walk. Does implicit DCE while walking. | |
| 180 // Name changed from "transform" to avoid it being virtual. | |
| 181 Node *xform( Node *old_space_node, int Nodes ); | |
| 182 | |
| 183 // Match a single Ideal Node - turn it into a 1-Node tree; Label & Reduce. | |
| 184 MachNode *match_tree( const Node *n ); | |
| 185 MachNode *match_sfpt( SafePointNode *sfpt ); | |
| 186 // Helper for match_sfpt | |
| 187 OptoReg::Name warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ); | |
| 188 | |
| 189 // Initialize first stack mask and related masks. | |
| 190 void init_first_stack_mask(); | |
| 191 | |
| 192 // If we should save-on-entry this register | |
| 193 bool is_save_on_entry( int reg ); | |
| 194 | |
| 195 // Fixup the save-on-entry registers | |
| 196 void Fixup_Save_On_Entry( ); | |
| 197 | |
| 198 // --- Frame handling --- | |
| 199 | |
| 200 // Register number of the stack slot corresponding to the incoming SP. | |
| 201 // Per the Big Picture in the AD file, it is: | |
| 202 // SharedInfo::stack0 + locks + in_preserve_stack_slots + pad2. | |
| 203 OptoReg::Name _old_SP; | |
| 204 | |
| 205 // Register number of the stack slot corresponding to the highest incoming | |
| 206 // argument on the stack. Per the Big Picture in the AD file, it is: | |
| 207 // _old_SP + out_preserve_stack_slots + incoming argument size. | |
| 208 OptoReg::Name _in_arg_limit; | |
| 209 | |
| 210 // Register number of the stack slot corresponding to the new SP. | |
| 211 // Per the Big Picture in the AD file, it is: | |
| 212 // _in_arg_limit + pad0 | |
| 213 OptoReg::Name _new_SP; | |
| 214 | |
| 215 // Register number of the stack slot corresponding to the highest outgoing | |
| 216 // argument on the stack. Per the Big Picture in the AD file, it is: | |
| 217 // _new_SP + max outgoing arguments of all calls | |
| 218 OptoReg::Name _out_arg_limit; | |
| 219 | |
| 220 OptoRegPair *_parm_regs; // Array of machine registers per argument | |
| 221 RegMask *_calling_convention_mask; // Array of RegMasks per argument | |
| 222 | |
| 223 // Does matcher support this ideal node? | |
| 224 static const bool has_match_rule(int opcode); | |
| 225 static const bool _hasMatchRule[_last_opcode]; | |
| 226 | |
| 227 // Used to determine if we have fast l2f conversion | |
| 228 // USII has it, USIII doesn't | |
| 229 static const bool convL2FSupported(void); | |
| 230 | |
| 231 // Vector width in bytes | |
| 232 static const uint vector_width_in_bytes(void); | |
| 233 | |
| 234 // Vector ideal reg | |
| 235 static const uint vector_ideal_reg(void); | |
| 236 | |
| 237 // Used to determine a "low complexity" 64-bit constant. (Zero is simple.) | |
| 238 // The standard of comparison is one (StoreL ConL) vs. two (StoreI ConI). | |
| 239 // Depends on the details of 64-bit constant generation on the CPU. | |
| 240 static const bool isSimpleConstant64(jlong con); | |
| 241 | |
| 242 // These calls are all generated by the ADLC | |
| 243 | |
| 244 // TRUE - grows up, FALSE - grows down (Intel) | |
| 245 virtual bool stack_direction() const; | |
| 246 | |
| 247 // Java-Java calling convention | |
| 248 // (what you use when Java calls Java) | |
| 249 | |
| 250 // Alignment of stack in bytes, standard Intel word alignment is 4. | |
| 251 // Sparc probably wants at least double-word (8). | |
| 252 static uint stack_alignment_in_bytes(); | |
| 253 // Alignment of stack, measured in stack slots. | |
| 254 // The size of stack slots is defined by VMRegImpl::stack_slot_size. | |
| 255 static uint stack_alignment_in_slots() { | |
| 256 return stack_alignment_in_bytes() / (VMRegImpl::stack_slot_size); | |
| 257 } | |
| 258 | |
| 259 // Array mapping arguments to registers. Argument 0 is usually the 'this' | |
| 260 // pointer. Registers can include stack-slots and regular registers. | |
| 261 static void calling_convention( BasicType *, VMRegPair *, uint len, bool is_outgoing ); | |
| 262 | |
| 263 // Convert a sig into a calling convention register layout | |
| 264 // and find interesting things about it. | |
| 265 static OptoReg::Name find_receiver( bool is_outgoing ); | |
| 266 // Return address register. On Intel it is a stack-slot. On PowerPC | |
| 267 // it is the Link register. On Sparc it is r31? | |
| 268 virtual OptoReg::Name return_addr() const; | |
| 269 RegMask _return_addr_mask; | |
| 270 // Return value register. On Intel it is EAX. On Sparc i0/o0. | |
| 271 static OptoRegPair return_value(int ideal_reg, bool is_outgoing); | |
| 272 static OptoRegPair c_return_value(int ideal_reg, bool is_outgoing); | |
| 273 RegMask _return_value_mask; | |
| 274 // Inline Cache Register | |
| 275 static OptoReg::Name inline_cache_reg(); | |
| 276 static const RegMask &inline_cache_reg_mask(); | |
| 277 static int inline_cache_reg_encode(); | |
| 278 | |
| 279 // Register for DIVI projection of divmodI | |
| 280 static RegMask divI_proj_mask(); | |
| 281 // Register for MODI projection of divmodI | |
| 282 static RegMask modI_proj_mask(); | |
| 283 | |
| 284 // Register for DIVL projection of divmodL | |
| 285 static RegMask divL_proj_mask(); | |
| 286 // Register for MODL projection of divmodL | |
| 287 static RegMask modL_proj_mask(); | |
| 288 | |
| 289 // Java-Interpreter calling convention | |
| 290 // (what you use when calling between compiled-Java and Interpreted-Java | |
| 291 | |
| 292 // Number of callee-save + always-save registers | |
| 293 // Ignores frame pointer and "special" registers | |
| 294 static int number_of_saved_registers(); | |
| 295 | |
| 296 // The Method-klass-holder may be passed in the inline_cache_reg | |
| 297 // and then expanded into the inline_cache_reg and a method_oop register | |
| 298 | |
| 299 static OptoReg::Name interpreter_method_oop_reg(); | |
| 300 static const RegMask &interpreter_method_oop_reg_mask(); | |
| 301 static int interpreter_method_oop_reg_encode(); | |
| 302 | |
| 303 static OptoReg::Name compiler_method_oop_reg(); | |
| 304 static const RegMask &compiler_method_oop_reg_mask(); | |
| 305 static int compiler_method_oop_reg_encode(); | |
| 306 | |
| 307 // Interpreter's Frame Pointer Register | |
| 308 static OptoReg::Name interpreter_frame_pointer_reg(); | |
| 309 static const RegMask &interpreter_frame_pointer_reg_mask(); | |
| 310 | |
| 311 // Java-Native calling convention | |
| 312 // (what you use when intercalling between Java and C++ code) | |
| 313 | |
| 314 // Array mapping arguments to registers. Argument 0 is usually the 'this' | |
| 315 // pointer. Registers can include stack-slots and regular registers. | |
| 316 static void c_calling_convention( BasicType*, VMRegPair *, uint ); | |
| 317 // Frame pointer. The frame pointer is kept at the base of the stack | |
| 318 // and so is probably the stack pointer for most machines. On Intel | |
| 319 // it is ESP. On the PowerPC it is R1. On Sparc it is SP. | |
| 320 OptoReg::Name c_frame_pointer() const; | |
| 321 static RegMask c_frame_ptr_mask; | |
| 322 | |
| 323 // !!!!! Special stuff for building ScopeDescs | |
| 324 virtual int regnum_to_fpu_offset(int regnum); | |
| 325 | |
| 326 // Is this branch offset small enough to be addressed by a short branch? | |
| 327 bool is_short_branch_offset(int offset); | |
| 328 | |
| 329 // Optional scaling for the parameter to the ClearArray/CopyArray node. | |
| 330 static const bool init_array_count_is_in_bytes; | |
| 331 | |
| 332 // Threshold small size (in bytes) for a ClearArray/CopyArray node. | |
| 333 // Anything this size or smaller may get converted to discrete scalar stores. | |
| 334 static const int init_array_short_size; | |
| 335 | |
| 336 // Should the Matcher clone shifts on addressing modes, expecting them to | |
| 337 // be subsumed into complex addressing expressions or compute them into | |
| 338 // registers? True for Intel but false for most RISCs | |
| 339 static const bool clone_shift_expressions; | |
| 340 | |
| 341 // Is it better to copy float constants, or load them directly from memory? | |
| 342 // Intel can load a float constant from a direct address, requiring no | |
| 343 // extra registers. Most RISCs will have to materialize an address into a | |
| 344 // register first, so they may as well materialize the constant immediately. | |
| 345 static const bool rematerialize_float_constants; | |
| 346 | |
| 347 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
| 348 // needed. Else we split the double into 2 integer pieces and move it | |
| 349 // piece-by-piece. Only happens when passing doubles into C code or when | |
| 350 // calling i2c adapters as the Java calling convention forces doubles to be | |
| 351 // aligned. | |
| 352 static const bool misaligned_doubles_ok; | |
| 353 | |
| 354 // Perform a platform dependent implicit null fixup. This is needed | |
| 355 // on windows95 to take care of some unusual register constraints. | |
| 356 void pd_implicit_null_fixup(MachNode *load, uint idx); | |
| 357 | |
| 358 // Advertise here if the CPU requires explicit rounding operations | |
| 359 // to implement the UseStrictFP mode. | |
| 360 static const bool strict_fp_requires_explicit_rounding; | |
| 361 | |
| 362 // Do floats take an entire double register or just half? | |
| 363 static const bool float_in_double; | |
| 364 // Do ints take an entire long register or just half? | |
| 365 static const bool int_in_long; | |
| 366 | |
| 367 // This routine is run whenever a graph fails to match. | |
| 368 // If it returns, the compiler should bailout to interpreter without error. | |
| 369 // In non-product mode, SoftMatchFailure is false to detect non-canonical | |
| 370 // graphs. Print a message and exit. | |
| 371 static void soft_match_failure() { | |
| 372 if( SoftMatchFailure ) return; | |
| 373 else { fatal("SoftMatchFailure is not allowed except in product"); } | |
| 374 } | |
| 375 | |
| 376 // Used by the DFA in dfa_sparc.cpp. Check for a prior FastLock | |
| 377 // acting as an Acquire and thus we don't need an Acquire here. We | |
| 378 // retain the Node to act as a compiler ordering barrier. | |
| 379 static bool prior_fast_lock( const Node *acq ); | |
| 380 | |
| 381 // Used by the DFA in dfa_sparc.cpp. Check for a following | |
| 382 // FastUnLock acting as a Release and thus we don't need a Release | |
| 383 // here. We retain the Node to act as a compiler ordering barrier. | |
| 384 static bool post_fast_unlock( const Node *rel ); | |
| 385 | |
| 386 // Check for a following volatile memory barrier without an | |
| 387 // intervening load and thus we don't need a barrier here. We | |
| 388 // retain the Node to act as a compiler ordering barrier. | |
| 389 static bool post_store_load_barrier(const Node* mb); | |
| 390 | |
| 391 | |
| 392 #ifdef ASSERT | |
| 393 void dump_old2new_map(); // machine-independent to machine-dependent | |
| 222 | 394 |
| 395 Node* find_old_node(Node* new_node) { | |
| 396 return _new2old_map[new_node->_idx]; | |
| 397 } | |
| 0 | 398 #endif |
| 399 }; |