Mercurial > hg > truffle
annotate src/cpu/x86/vm/c1_FrameMap_x86.cpp @ 4582:b24386206122
Made all vm builds go into subdirectories, even product builds to simplify building the various types of VMs (server, client and graal).
Made HotSpot build jobs use the number of CPUs on the host machine.
| author | Doug Simon <doug.simon@oracle.com> |
|---|---|
| date | Mon, 13 Feb 2012 23:13:37 +0100 |
| parents | ac637b7220d1 |
| children | 8a02ca5e5576 |
| rev | line source |
|---|---|
| 0 | 1 /* |
| 1579 | 2 * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
|
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #include "precompiled.hpp" |
| 26 #include "c1/c1_FrameMap.hpp" | |
| 27 #include "c1/c1_LIR.hpp" | |
| 28 #include "runtime/sharedRuntime.hpp" | |
| 29 #include "vmreg_x86.inline.hpp" | |
| 0 | 30 |
| 31 const int FrameMap::pd_c_runtime_reserved_arg_size = 0; | |
| 32 | |
| 33 LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool) { | |
| 34 LIR_Opr opr = LIR_OprFact::illegalOpr; | |
| 35 VMReg r_1 = reg->first(); | |
| 36 VMReg r_2 = reg->second(); | |
| 37 if (r_1->is_stack()) { | |
| 38 // Convert stack slot to an SP offset | |
| 39 // The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value | |
| 40 // so we must add it in here. | |
| 41 int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; | |
| 42 opr = LIR_OprFact::address(new LIR_Address(rsp_opr, st_off, type)); | |
| 43 } else if (r_1->is_Register()) { | |
| 44 Register reg = r_1->as_Register(); | |
| 304 | 45 if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) { |
| 0 | 46 Register reg2 = r_2->as_Register(); |
| 304 | 47 #ifdef _LP64 |
| 48 assert(reg2 == reg, "must be same register"); | |
| 49 opr = as_long_opr(reg); | |
| 50 #else | |
| 0 | 51 opr = as_long_opr(reg2, reg); |
| 304 | 52 #endif // _LP64 |
| 53 } else if (type == T_OBJECT || type == T_ARRAY) { | |
| 0 | 54 opr = as_oop_opr(reg); |
| 55 } else { | |
| 56 opr = as_opr(reg); | |
| 57 } | |
| 58 } else if (r_1->is_FloatRegister()) { | |
| 59 assert(type == T_DOUBLE || type == T_FLOAT, "wrong type"); | |
| 60 int num = r_1->as_FloatRegister()->encoding(); | |
| 61 if (type == T_FLOAT) { | |
| 62 opr = LIR_OprFact::single_fpu(num); | |
| 63 } else { | |
| 64 opr = LIR_OprFact::double_fpu(num); | |
| 65 } | |
| 66 } else if (r_1->is_XMMRegister()) { | |
| 67 assert(type == T_DOUBLE || type == T_FLOAT, "wrong type"); | |
| 68 int num = r_1->as_XMMRegister()->encoding(); | |
| 69 if (type == T_FLOAT) { | |
| 70 opr = LIR_OprFact::single_xmm(num); | |
| 71 } else { | |
| 72 opr = LIR_OprFact::double_xmm(num); | |
| 73 } | |
| 74 } else { | |
| 75 ShouldNotReachHere(); | |
| 76 } | |
| 77 return opr; | |
| 78 } | |
| 79 | |
| 80 | |
| 81 LIR_Opr FrameMap::rsi_opr; | |
| 82 LIR_Opr FrameMap::rdi_opr; | |
| 83 LIR_Opr FrameMap::rbx_opr; | |
| 84 LIR_Opr FrameMap::rax_opr; | |
| 85 LIR_Opr FrameMap::rdx_opr; | |
| 86 LIR_Opr FrameMap::rcx_opr; | |
| 87 LIR_Opr FrameMap::rsp_opr; | |
| 88 LIR_Opr FrameMap::rbp_opr; | |
| 89 | |
| 90 LIR_Opr FrameMap::receiver_opr; | |
| 91 | |
| 92 LIR_Opr FrameMap::rsi_oop_opr; | |
| 93 LIR_Opr FrameMap::rdi_oop_opr; | |
| 94 LIR_Opr FrameMap::rbx_oop_opr; | |
| 95 LIR_Opr FrameMap::rax_oop_opr; | |
| 96 LIR_Opr FrameMap::rdx_oop_opr; | |
| 97 LIR_Opr FrameMap::rcx_oop_opr; | |
| 98 | |
| 304 | 99 LIR_Opr FrameMap::long0_opr; |
| 100 LIR_Opr FrameMap::long1_opr; | |
| 0 | 101 LIR_Opr FrameMap::fpu0_float_opr; |
| 102 LIR_Opr FrameMap::fpu0_double_opr; | |
| 103 LIR_Opr FrameMap::xmm0_float_opr; | |
| 104 LIR_Opr FrameMap::xmm0_double_opr; | |
| 105 | |
| 304 | 106 #ifdef _LP64 |
| 107 | |
| 108 LIR_Opr FrameMap::r8_opr; | |
| 109 LIR_Opr FrameMap::r9_opr; | |
| 110 LIR_Opr FrameMap::r10_opr; | |
| 111 LIR_Opr FrameMap::r11_opr; | |
| 112 LIR_Opr FrameMap::r12_opr; | |
| 113 LIR_Opr FrameMap::r13_opr; | |
| 114 LIR_Opr FrameMap::r14_opr; | |
| 115 LIR_Opr FrameMap::r15_opr; | |
| 116 | |
| 117 // r10 and r15 can never contain oops since they aren't available to | |
| 118 // the allocator | |
| 119 LIR_Opr FrameMap::r8_oop_opr; | |
| 120 LIR_Opr FrameMap::r9_oop_opr; | |
| 121 LIR_Opr FrameMap::r11_oop_opr; | |
| 122 LIR_Opr FrameMap::r12_oop_opr; | |
| 123 LIR_Opr FrameMap::r13_oop_opr; | |
| 124 LIR_Opr FrameMap::r14_oop_opr; | |
| 125 #endif // _LP64 | |
| 126 | |
| 0 | 127 LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, }; |
| 128 LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, }; | |
| 129 LIR_Opr FrameMap::_caller_save_xmm_regs[] = { 0, }; | |
| 130 | |
| 304 | 131 XMMRegister FrameMap::_xmm_regs [] = { 0, }; |
| 0 | 132 |
| 133 XMMRegister FrameMap::nr2xmmreg(int rnr) { | |
| 134 assert(_init_done, "tables not initialized"); | |
| 135 return _xmm_regs[rnr]; | |
| 136 } | |
| 137 | |
| 138 //-------------------------------------------------------- | |
| 139 // FrameMap | |
| 140 //-------------------------------------------------------- | |
| 141 | |
| 1584 | 142 void FrameMap::initialize() { |
| 143 assert(!_init_done, "once"); | |
| 0 | 144 |
| 304 | 145 assert(nof_cpu_regs == LP64_ONLY(16) NOT_LP64(8), "wrong number of CPU registers"); |
| 146 map_register(0, rsi); rsi_opr = LIR_OprFact::single_cpu(0); | |
| 147 map_register(1, rdi); rdi_opr = LIR_OprFact::single_cpu(1); | |
| 148 map_register(2, rbx); rbx_opr = LIR_OprFact::single_cpu(2); | |
| 149 map_register(3, rax); rax_opr = LIR_OprFact::single_cpu(3); | |
| 150 map_register(4, rdx); rdx_opr = LIR_OprFact::single_cpu(4); | |
| 151 map_register(5, rcx); rcx_opr = LIR_OprFact::single_cpu(5); | |
| 0 | 152 |
| 304 | 153 #ifndef _LP64 |
| 154 // The unallocatable registers are at the end | |
| 155 map_register(6, rsp); | |
| 156 map_register(7, rbp); | |
| 157 #else | |
| 158 map_register( 6, r8); r8_opr = LIR_OprFact::single_cpu(6); | |
| 159 map_register( 7, r9); r9_opr = LIR_OprFact::single_cpu(7); | |
| 160 map_register( 8, r11); r11_opr = LIR_OprFact::single_cpu(8); | |
| 2002 | 161 map_register( 9, r13); r13_opr = LIR_OprFact::single_cpu(9); |
| 162 map_register(10, r14); r14_opr = LIR_OprFact::single_cpu(10); | |
| 163 // r12 is allocated conditionally. With compressed oops it holds | |
| 164 // the heapbase value and is not visible to the allocator. | |
| 165 map_register(11, r12); r12_opr = LIR_OprFact::single_cpu(11); | |
| 304 | 166 // The unallocatable registers are at the end |
| 167 map_register(12, r10); r10_opr = LIR_OprFact::single_cpu(12); | |
| 168 map_register(13, r15); r15_opr = LIR_OprFact::single_cpu(13); | |
| 169 map_register(14, rsp); | |
| 170 map_register(15, rbp); | |
| 171 #endif // _LP64 | |
| 172 | |
| 173 #ifdef _LP64 | |
| 174 long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 3 /*eax*/); | |
| 175 long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 2 /*ebx*/); | |
| 176 #else | |
| 177 long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 4 /*edx*/); | |
| 178 long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 5 /*ecx*/); | |
| 179 #endif // _LP64 | |
| 0 | 180 fpu0_float_opr = LIR_OprFact::single_fpu(0); |
| 181 fpu0_double_opr = LIR_OprFact::double_fpu(0); | |
| 182 xmm0_float_opr = LIR_OprFact::single_xmm(0); | |
| 183 xmm0_double_opr = LIR_OprFact::double_xmm(0); | |
| 184 | |
| 185 _caller_save_cpu_regs[0] = rsi_opr; | |
| 186 _caller_save_cpu_regs[1] = rdi_opr; | |
| 187 _caller_save_cpu_regs[2] = rbx_opr; | |
| 188 _caller_save_cpu_regs[3] = rax_opr; | |
| 189 _caller_save_cpu_regs[4] = rdx_opr; | |
| 190 _caller_save_cpu_regs[5] = rcx_opr; | |
| 191 | |
| 304 | 192 #ifdef _LP64 |
| 193 _caller_save_cpu_regs[6] = r8_opr; | |
| 194 _caller_save_cpu_regs[7] = r9_opr; | |
| 195 _caller_save_cpu_regs[8] = r11_opr; | |
| 2002 | 196 _caller_save_cpu_regs[9] = r13_opr; |
| 197 _caller_save_cpu_regs[10] = r14_opr; | |
| 198 _caller_save_cpu_regs[11] = r12_opr; | |
| 304 | 199 #endif // _LP64 |
| 200 | |
| 0 | 201 |
| 202 _xmm_regs[0] = xmm0; | |
| 203 _xmm_regs[1] = xmm1; | |
| 204 _xmm_regs[2] = xmm2; | |
| 205 _xmm_regs[3] = xmm3; | |
| 206 _xmm_regs[4] = xmm4; | |
| 207 _xmm_regs[5] = xmm5; | |
| 208 _xmm_regs[6] = xmm6; | |
| 209 _xmm_regs[7] = xmm7; | |
| 210 | |
| 304 | 211 #ifdef _LP64 |
| 212 _xmm_regs[8] = xmm8; | |
| 213 _xmm_regs[9] = xmm9; | |
| 214 _xmm_regs[10] = xmm10; | |
| 215 _xmm_regs[11] = xmm11; | |
| 216 _xmm_regs[12] = xmm12; | |
| 217 _xmm_regs[13] = xmm13; | |
| 218 _xmm_regs[14] = xmm14; | |
| 219 _xmm_regs[15] = xmm15; | |
| 220 #endif // _LP64 | |
| 221 | |
| 0 | 222 for (int i = 0; i < 8; i++) { |
| 223 _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i); | |
| 304 | 224 } |
| 225 | |
| 226 for (int i = 0; i < nof_caller_save_xmm_regs ; i++) { | |
| 0 | 227 _caller_save_xmm_regs[i] = LIR_OprFact::single_xmm(i); |
| 228 } | |
| 229 | |
| 230 _init_done = true; | |
| 231 | |
| 304 | 232 rsi_oop_opr = as_oop_opr(rsi); |
| 233 rdi_oop_opr = as_oop_opr(rdi); | |
| 234 rbx_oop_opr = as_oop_opr(rbx); | |
| 235 rax_oop_opr = as_oop_opr(rax); | |
| 236 rdx_oop_opr = as_oop_opr(rdx); | |
| 237 rcx_oop_opr = as_oop_opr(rcx); | |
| 238 | |
| 239 rsp_opr = as_pointer_opr(rsp); | |
| 240 rbp_opr = as_pointer_opr(rbp); | |
| 241 | |
| 242 #ifdef _LP64 | |
| 243 r8_oop_opr = as_oop_opr(r8); | |
| 244 r9_oop_opr = as_oop_opr(r9); | |
| 245 r11_oop_opr = as_oop_opr(r11); | |
| 246 r12_oop_opr = as_oop_opr(r12); | |
| 247 r13_oop_opr = as_oop_opr(r13); | |
| 248 r14_oop_opr = as_oop_opr(r14); | |
| 249 #endif // _LP64 | |
| 250 | |
| 0 | 251 VMRegPair regs; |
| 252 BasicType sig_bt = T_OBJECT; | |
| 253 SharedRuntime::java_calling_convention(&sig_bt, ®s, 1, true); | |
| 254 receiver_opr = as_oop_opr(regs.first()->as_Register()); | |
| 304 | 255 |
| 0 | 256 } |
| 257 | |
| 258 | |
| 259 Address FrameMap::make_new_address(ByteSize sp_offset) const { | |
| 260 // for rbp, based address use this: | |
| 261 // return Address(rbp, in_bytes(sp_offset) - (framesize() - 2) * 4); | |
| 262 return Address(rsp, in_bytes(sp_offset)); | |
| 263 } | |
| 264 | |
| 265 | |
| 266 // ----------------mapping----------------------- | |
| 267 // all mapping is based on rbp, addressing, except for simple leaf methods where we access | |
| 268 // the locals rsp based (and no frame is built) | |
| 269 | |
| 270 | |
| 271 // Frame for simple leaf methods (quick entries) | |
| 272 // | |
| 273 // +----------+ | |
| 274 // | ret addr | <- TOS | |
| 275 // +----------+ | |
| 276 // | args | | |
| 277 // | ...... | | |
| 278 | |
| 279 // Frame for standard methods | |
| 280 // | |
| 281 // | .........| <- TOS | |
| 282 // | locals | | |
| 283 // +----------+ | |
| 284 // | old rbp, | <- EBP | |
| 285 // +----------+ | |
| 286 // | ret addr | | |
| 287 // +----------+ | |
| 288 // | args | | |
| 289 // | .........| | |
| 290 | |
| 291 | |
| 292 // For OopMaps, map a local variable or spill index to an VMRegImpl name. | |
| 293 // This is the offset from sp() in the frame of the slot for the index, | |
| 294 // skewed by VMRegImpl::stack0 to indicate a stack location (vs.a register.) | |
| 295 // | |
| 296 // framesize + | |
| 297 // stack0 stack0 0 <- VMReg | |
| 298 // | | <registers> | | |
| 299 // ...........|..............|.............| | |
| 300 // 0 1 2 3 x x 4 5 6 ... | <- local indices | |
| 301 // ^ ^ sp() ( x x indicate link | |
| 302 // | | and return addr) | |
| 303 // arguments non-argument locals | |
| 304 | |
| 305 | |
| 306 VMReg FrameMap::fpu_regname (int n) { | |
| 307 // Return the OptoReg name for the fpu stack slot "n" | |
| 308 // A spilled fpu stack slot comprises to two single-word OptoReg's. | |
| 309 return as_FloatRegister(n)->as_VMReg(); | |
| 310 } | |
| 311 | |
| 312 LIR_Opr FrameMap::stack_pointer() { | |
| 313 return FrameMap::rsp_opr; | |
| 314 } | |
| 315 | |
| 316 | |
| 1564 | 317 // JSR 292 |
| 318 LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() { | |
| 319 assert(rbp == rbp_mh_SP_save, "must be same register"); | |
| 320 return rbp_opr; | |
| 321 } | |
| 322 | |
| 323 | |
| 0 | 324 bool FrameMap::validate_frame() { |
| 325 return true; | |
| 326 } |