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annotate src/cpu/sparc/vm/assembler_sparc.hpp @ 3474:b9f76db5ac53
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author | Gilles Duboscq <gilles.duboscq@oracle.com> |
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date | Mon, 01 Aug 2011 13:56:56 +0200 |
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0 | 1 /* |
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2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_HPP |
26 #define CPU_SPARC_VM_ASSEMBLER_SPARC_HPP | |
27 | |
0 | 28 class BiasedLockingCounters; |
29 | |
30 // <sys/trap.h> promises that the system will not use traps 16-31 | |
31 #define ST_RESERVED_FOR_USER_0 0x10 | |
32 | |
33 /* Written: David Ungar 4/19/97 */ | |
34 | |
35 // Contains all the definitions needed for sparc assembly code generation. | |
36 | |
37 // Register aliases for parts of the system: | |
38 | |
39 // 64 bit values can be kept in g1-g5, o1-o5 and o7 and all 64 bits are safe | |
40 // across context switches in V8+ ABI. Of course, there are no 64 bit regs | |
41 // in V8 ABI. All 64 bits are preserved in V9 ABI for all registers. | |
42 | |
43 // g2-g4 are scratch registers called "application globals". Their | |
44 // meaning is reserved to the "compilation system"--which means us! | |
45 // They are are not supposed to be touched by ordinary C code, although | |
46 // highly-optimized C code might steal them for temps. They are safe | |
47 // across thread switches, and the ABI requires that they be safe | |
48 // across function calls. | |
49 // | |
50 // g1 and g3 are touched by more modules. V8 allows g1 to be clobbered | |
51 // across func calls, and V8+ also allows g5 to be clobbered across | |
52 // func calls. Also, g1 and g5 can get touched while doing shared | |
53 // library loading. | |
54 // | |
55 // We must not touch g7 (it is the thread-self register) and g6 is | |
56 // reserved for certain tools. g0, of course, is always zero. | |
57 // | |
58 // (Sources: SunSoft Compilers Group, thread library engineers.) | |
59 | |
60 // %%%% The interpreter should be revisited to reduce global scratch regs. | |
61 | |
62 // This global always holds the current JavaThread pointer: | |
63 | |
64 REGISTER_DECLARATION(Register, G2_thread , G2); | |
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65 REGISTER_DECLARATION(Register, G6_heapbase , G6); |
0 | 66 |
67 // The following globals are part of the Java calling convention: | |
68 | |
69 REGISTER_DECLARATION(Register, G5_method , G5); | |
70 REGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method); | |
71 REGISTER_DECLARATION(Register, G5_inline_cache_reg , G5_method); | |
72 | |
73 // The following globals are used for the new C1 & interpreter calling convention: | |
74 REGISTER_DECLARATION(Register, Gargs , G4); // pointing to the last argument | |
75 | |
76 // This local is used to preserve G2_thread in the interpreter and in stubs: | |
77 REGISTER_DECLARATION(Register, L7_thread_cache , L7); | |
78 | |
79 // These globals are used as scratch registers in the interpreter: | |
80 | |
81 REGISTER_DECLARATION(Register, Gframe_size , G1); // SAME REG as G1_scratch | |
82 REGISTER_DECLARATION(Register, G1_scratch , G1); // also SAME | |
83 REGISTER_DECLARATION(Register, G3_scratch , G3); | |
84 REGISTER_DECLARATION(Register, G4_scratch , G4); | |
85 | |
86 // These globals are used as short-lived scratch registers in the compiler: | |
87 | |
88 REGISTER_DECLARATION(Register, Gtemp , G5); | |
89 | |
710 | 90 // JSR 292 fixed register usages: |
91 REGISTER_DECLARATION(Register, G5_method_type , G5); | |
92 REGISTER_DECLARATION(Register, G3_method_handle , G3); | |
1564 | 93 REGISTER_DECLARATION(Register, L7_mh_SP_save , L7); |
710 | 94 |
0 | 95 // The compiler requires that G5_megamorphic_method is G5_inline_cache_klass, |
96 // because a single patchable "set" instruction (NativeMovConstReg, | |
97 // or NativeMovConstPatching for compiler1) instruction | |
98 // serves to set up either quantity, depending on whether the compiled | |
99 // call site is an inline cache or is megamorphic. See the function | |
100 // CompiledIC::set_to_megamorphic. | |
101 // | |
710 | 102 // If a inline cache targets an interpreted method, then the |
103 // G5 register will be used twice during the call. First, | |
104 // the call site will be patched to load a compiledICHolder | |
105 // into G5. (This is an ordered pair of ic_klass, method.) | |
106 // The c2i adapter will first check the ic_klass, then load | |
107 // G5_method with the method part of the pair just before | |
108 // jumping into the interpreter. | |
0 | 109 // |
110 // Note that G5_method is only the method-self for the interpreter, | |
111 // and is logically unrelated to G5_megamorphic_method. | |
112 // | |
113 // Invariants on G2_thread (the JavaThread pointer): | |
114 // - it should not be used for any other purpose anywhere | |
115 // - it must be re-initialized by StubRoutines::call_stub() | |
116 // - it must be preserved around every use of call_VM | |
117 | |
118 // We can consider using g2/g3/g4 to cache more values than the | |
119 // JavaThread, such as the card-marking base or perhaps pointers into | |
120 // Eden. It's something of a waste to use them as scratch temporaries, | |
121 // since they are not supposed to be volatile. (Of course, if we find | |
122 // that Java doesn't benefit from application globals, then we can just | |
123 // use them as ordinary temporaries.) | |
124 // | |
125 // Since g1 and g5 (and/or g6) are the volatile (caller-save) registers, | |
126 // it makes sense to use them routinely for procedure linkage, | |
127 // whenever the On registers are not applicable. Examples: G5_method, | |
128 // G5_inline_cache_klass, and a double handful of miscellaneous compiler | |
129 // stubs. This means that compiler stubs, etc., should be kept to a | |
130 // maximum of two or three G-register arguments. | |
131 | |
132 | |
133 // stub frames | |
134 | |
135 REGISTER_DECLARATION(Register, Lentry_args , L0); // pointer to args passed to callee (interpreter) not stub itself | |
136 | |
137 // Interpreter frames | |
138 | |
139 #ifdef CC_INTERP | |
140 REGISTER_DECLARATION(Register, Lstate , L0); // interpreter state object pointer | |
141 REGISTER_DECLARATION(Register, L1_scratch , L1); // scratch | |
142 REGISTER_DECLARATION(Register, Lmirror , L1); // mirror (for native methods only) | |
143 REGISTER_DECLARATION(Register, L2_scratch , L2); | |
144 REGISTER_DECLARATION(Register, L3_scratch , L3); | |
145 REGISTER_DECLARATION(Register, L4_scratch , L4); | |
146 REGISTER_DECLARATION(Register, Lscratch , L5); // C1 uses | |
147 REGISTER_DECLARATION(Register, Lscratch2 , L6); // C1 uses | |
148 REGISTER_DECLARATION(Register, L7_scratch , L7); // constant pool cache | |
149 REGISTER_DECLARATION(Register, O5_savedSP , O5); | |
150 REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply | |
151 // a copy SP, so in 64-bit it's a biased value. The bias | |
152 // is added and removed as needed in the frame code. | |
153 // Interface to signature handler | |
154 REGISTER_DECLARATION(Register, Llocals , L7); // pointer to locals for signature handler | |
155 REGISTER_DECLARATION(Register, Lmethod , L6); // methodOop when calling signature handler | |
156 | |
157 #else | |
158 REGISTER_DECLARATION(Register, Lesp , L0); // expression stack pointer | |
159 REGISTER_DECLARATION(Register, Lbcp , L1); // pointer to next bytecode | |
160 REGISTER_DECLARATION(Register, Lmethod , L2); | |
161 REGISTER_DECLARATION(Register, Llocals , L3); | |
162 REGISTER_DECLARATION(Register, Largs , L3); // pointer to locals for signature handler | |
163 // must match Llocals in asm interpreter | |
164 REGISTER_DECLARATION(Register, Lmonitors , L4); | |
165 REGISTER_DECLARATION(Register, Lbyte_code , L5); | |
166 // When calling out from the interpreter we record SP so that we can remove any extra stack | |
167 // space allocated during adapter transitions. This register is only live from the point | |
168 // of the call until we return. | |
169 REGISTER_DECLARATION(Register, Llast_SP , L5); | |
170 REGISTER_DECLARATION(Register, Lscratch , L5); | |
171 REGISTER_DECLARATION(Register, Lscratch2 , L6); | |
172 REGISTER_DECLARATION(Register, LcpoolCache , L6); // constant pool cache | |
173 | |
174 REGISTER_DECLARATION(Register, O5_savedSP , O5); | |
175 REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply | |
176 // a copy SP, so in 64-bit it's a biased value. The bias | |
177 // is added and removed as needed in the frame code. | |
178 REGISTER_DECLARATION(Register, IdispatchTables , I4); // Base address of the bytecode dispatch tables | |
179 REGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode | |
180 REGISTER_DECLARATION(Register, ImethodDataPtr , I2); // Pointer to the current method data | |
181 #endif /* CC_INTERP */ | |
182 | |
183 // NOTE: Lscratch2 and LcpoolCache point to the same registers in | |
184 // the interpreter code. If Lscratch2 needs to be used for some | |
185 // purpose than LcpoolCache should be restore after that for | |
186 // the interpreter to work right | |
187 // (These assignments must be compatible with L7_thread_cache; see above.) | |
188 | |
189 // Since Lbcp points into the middle of the method object, | |
190 // it is temporarily converted into a "bcx" during GC. | |
191 | |
192 // Exception processing | |
193 // These registers are passed into exception handlers. | |
194 // All exception handlers require the exception object being thrown. | |
195 // In addition, an nmethod's exception handler must be passed | |
196 // the address of the call site within the nmethod, to allow | |
197 // proper selection of the applicable catch block. | |
198 // (Interpreter frames use their own bcp() for this purpose.) | |
199 // | |
200 // The Oissuing_pc value is not always needed. When jumping to a | |
201 // handler that is known to be interpreted, the Oissuing_pc value can be | |
202 // omitted. An actual catch block in compiled code receives (from its | |
203 // nmethod's exception handler) the thrown exception in the Oexception, | |
204 // but it doesn't need the Oissuing_pc. | |
205 // | |
206 // If an exception handler (either interpreted or compiled) | |
207 // discovers there is no applicable catch block, it updates | |
208 // the Oissuing_pc to the continuation PC of its own caller, | |
209 // pops back to that caller's stack frame, and executes that | |
210 // caller's exception handler. Obviously, this process will | |
211 // iterate until the control stack is popped back to a method | |
212 // containing an applicable catch block. A key invariant is | |
213 // that the Oissuing_pc value is always a value local to | |
214 // the method whose exception handler is currently executing. | |
215 // | |
216 // Note: The issuing PC value is __not__ a raw return address (I7 value). | |
217 // It is a "return pc", the address __following__ the call. | |
218 // Raw return addresses are converted to issuing PCs by frame::pc(), | |
219 // or by stubs. Issuing PCs can be used directly with PC range tables. | |
220 // | |
221 REGISTER_DECLARATION(Register, Oexception , O0); // exception being thrown | |
222 REGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from | |
223 | |
224 | |
225 // These must occur after the declarations above | |
226 #ifndef DONT_USE_REGISTER_DEFINES | |
227 | |
228 #define Gthread AS_REGISTER(Register, Gthread) | |
229 #define Gmethod AS_REGISTER(Register, Gmethod) | |
230 #define Gmegamorphic_method AS_REGISTER(Register, Gmegamorphic_method) | |
231 #define Ginline_cache_reg AS_REGISTER(Register, Ginline_cache_reg) | |
232 #define Gargs AS_REGISTER(Register, Gargs) | |
233 #define Lthread_cache AS_REGISTER(Register, Lthread_cache) | |
234 #define Gframe_size AS_REGISTER(Register, Gframe_size) | |
235 #define Gtemp AS_REGISTER(Register, Gtemp) | |
236 | |
237 #ifdef CC_INTERP | |
238 #define Lstate AS_REGISTER(Register, Lstate) | |
239 #define Lesp AS_REGISTER(Register, Lesp) | |
240 #define L1_scratch AS_REGISTER(Register, L1_scratch) | |
241 #define Lmirror AS_REGISTER(Register, Lmirror) | |
242 #define L2_scratch AS_REGISTER(Register, L2_scratch) | |
243 #define L3_scratch AS_REGISTER(Register, L3_scratch) | |
244 #define L4_scratch AS_REGISTER(Register, L4_scratch) | |
245 #define Lscratch AS_REGISTER(Register, Lscratch) | |
246 #define Lscratch2 AS_REGISTER(Register, Lscratch2) | |
247 #define L7_scratch AS_REGISTER(Register, L7_scratch) | |
248 #define Ostate AS_REGISTER(Register, Ostate) | |
249 #else | |
250 #define Lesp AS_REGISTER(Register, Lesp) | |
251 #define Lbcp AS_REGISTER(Register, Lbcp) | |
252 #define Lmethod AS_REGISTER(Register, Lmethod) | |
253 #define Llocals AS_REGISTER(Register, Llocals) | |
254 #define Lmonitors AS_REGISTER(Register, Lmonitors) | |
255 #define Lbyte_code AS_REGISTER(Register, Lbyte_code) | |
256 #define Lscratch AS_REGISTER(Register, Lscratch) | |
257 #define Lscratch2 AS_REGISTER(Register, Lscratch2) | |
258 #define LcpoolCache AS_REGISTER(Register, LcpoolCache) | |
259 #endif /* ! CC_INTERP */ | |
260 | |
261 #define Lentry_args AS_REGISTER(Register, Lentry_args) | |
262 #define I5_savedSP AS_REGISTER(Register, I5_savedSP) | |
263 #define O5_savedSP AS_REGISTER(Register, O5_savedSP) | |
264 #define IdispatchAddress AS_REGISTER(Register, IdispatchAddress) | |
265 #define ImethodDataPtr AS_REGISTER(Register, ImethodDataPtr) | |
266 #define IdispatchTables AS_REGISTER(Register, IdispatchTables) | |
267 | |
268 #define Oexception AS_REGISTER(Register, Oexception) | |
269 #define Oissuing_pc AS_REGISTER(Register, Oissuing_pc) | |
270 | |
271 | |
272 #endif | |
273 | |
274 // Address is an abstraction used to represent a memory location. | |
275 // | |
276 // Note: A register location is represented via a Register, not | |
277 // via an address for efficiency & simplicity reasons. | |
278 | |
279 class Address VALUE_OBJ_CLASS_SPEC { | |
280 private: | |
727 | 281 Register _base; // Base register. |
282 RegisterOrConstant _index_or_disp; // Index register or constant displacement. | |
283 RelocationHolder _rspec; | |
284 | |
285 public: | |
286 Address() : _base(noreg), _index_or_disp(noreg) {} | |
287 | |
288 Address(Register base, RegisterOrConstant index_or_disp) | |
289 : _base(base), | |
290 _index_or_disp(index_or_disp) { | |
291 } | |
292 | |
293 Address(Register base, Register index) | |
294 : _base(base), | |
295 _index_or_disp(index) { | |
296 } | |
297 | |
298 Address(Register base, int disp) | |
299 : _base(base), | |
300 _index_or_disp(disp) { | |
301 } | |
302 | |
303 #ifdef ASSERT | |
304 // ByteSize is only a class when ASSERT is defined, otherwise it's an int. | |
305 Address(Register base, ByteSize disp) | |
306 : _base(base), | |
307 _index_or_disp(in_bytes(disp)) { | |
308 } | |
0 | 309 #endif |
727 | 310 |
311 // accessors | |
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312 Register base() const { return _base; } |
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313 Register index() const { return _index_or_disp.as_register(); } |
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314 int disp() const { return _index_or_disp.as_constant(); } |
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315 |
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316 bool has_index() const { return _index_or_disp.is_register(); } |
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317 bool has_disp() const { return _index_or_disp.is_constant(); } |
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318 |
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319 bool uses(Register reg) const { return base() == reg || (has_index() && index() == reg); } |
727 | 320 |
321 const relocInfo::relocType rtype() { return _rspec.type(); } | |
322 const RelocationHolder& rspec() { return _rspec; } | |
323 | |
324 RelocationHolder rspec(int offset) const { | |
325 return offset == 0 ? _rspec : _rspec.plus(offset); | |
326 } | |
327 | |
328 inline bool is_simm13(int offset = 0); // check disp+offset for overflow | |
329 | |
330 Address plus_disp(int plusdisp) const { // bump disp by a small amount | |
331 assert(_index_or_disp.is_constant(), "must have a displacement"); | |
332 Address a(base(), disp() + plusdisp); | |
333 return a; | |
334 } | |
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335 bool is_same_address(Address a) const { |
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336 // disregard _rspec |
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337 return base() == a.base() && (has_index() ? index() == a.index() : disp() == a.disp()); |
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338 } |
727 | 339 |
340 Address after_save() const { | |
341 Address a = (*this); | |
342 a._base = a._base->after_save(); | |
343 return a; | |
344 } | |
345 | |
346 Address after_restore() const { | |
347 Address a = (*this); | |
348 a._base = a._base->after_restore(); | |
349 return a; | |
350 } | |
351 | |
352 // Convert the raw encoding form into the form expected by the | |
353 // constructor for Address. | |
354 static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop); | |
355 | |
356 friend class Assembler; | |
357 }; | |
358 | |
359 | |
360 class AddressLiteral VALUE_OBJ_CLASS_SPEC { | |
361 private: | |
362 address _address; | |
363 RelocationHolder _rspec; | |
364 | |
365 RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) { | |
366 switch (rtype) { | |
0 | 367 case relocInfo::external_word_type: |
727 | 368 return external_word_Relocation::spec(addr); |
0 | 369 case relocInfo::internal_word_type: |
727 | 370 return internal_word_Relocation::spec(addr); |
0 | 371 #ifdef _LP64 |
372 case relocInfo::opt_virtual_call_type: | |
373 return opt_virtual_call_Relocation::spec(); | |
374 case relocInfo::static_call_type: | |
375 return static_call_Relocation::spec(); | |
376 case relocInfo::runtime_call_type: | |
377 return runtime_call_Relocation::spec(); | |
378 #endif | |
379 case relocInfo::none: | |
380 return RelocationHolder(); | |
381 default: | |
382 ShouldNotReachHere(); | |
383 return RelocationHolder(); | |
384 } | |
385 } | |
386 | |
727 | 387 protected: |
388 // creation | |
389 AddressLiteral() : _address(NULL), _rspec(NULL) {} | |
390 | |
0 | 391 public: |
727 | 392 AddressLiteral(address addr, RelocationHolder const& rspec) |
393 : _address(addr), | |
394 _rspec(rspec) {} | |
395 | |
396 // Some constructors to avoid casting at the call site. | |
397 AddressLiteral(jobject obj, RelocationHolder const& rspec) | |
398 : _address((address) obj), | |
399 _rspec(rspec) {} | |
400 | |
401 AddressLiteral(intptr_t value, RelocationHolder const& rspec) | |
402 : _address((address) value), | |
403 _rspec(rspec) {} | |
404 | |
405 AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none) | |
406 : _address((address) addr), | |
407 _rspec(rspec_from_rtype(rtype, (address) addr)) {} | |
408 | |
409 // Some constructors to avoid casting at the call site. | |
410 AddressLiteral(address* addr, relocInfo::relocType rtype = relocInfo::none) | |
411 : _address((address) addr), | |
412 _rspec(rspec_from_rtype(rtype, (address) addr)) {} | |
413 | |
414 AddressLiteral(bool* addr, relocInfo::relocType rtype = relocInfo::none) | |
415 : _address((address) addr), | |
416 _rspec(rspec_from_rtype(rtype, (address) addr)) {} | |
417 | |
418 AddressLiteral(const bool* addr, relocInfo::relocType rtype = relocInfo::none) | |
419 : _address((address) addr), | |
420 _rspec(rspec_from_rtype(rtype, (address) addr)) {} | |
421 | |
422 AddressLiteral(signed char* addr, relocInfo::relocType rtype = relocInfo::none) | |
423 : _address((address) addr), | |
424 _rspec(rspec_from_rtype(rtype, (address) addr)) {} | |
425 | |
426 AddressLiteral(int* addr, relocInfo::relocType rtype = relocInfo::none) | |
427 : _address((address) addr), | |
428 _rspec(rspec_from_rtype(rtype, (address) addr)) {} | |
429 | |
430 AddressLiteral(intptr_t addr, relocInfo::relocType rtype = relocInfo::none) | |
431 : _address((address) addr), | |
432 _rspec(rspec_from_rtype(rtype, (address) addr)) {} | |
433 | |
0 | 434 #ifdef _LP64 |
727 | 435 // 32-bit complains about a multiple declaration for int*. |
436 AddressLiteral(intptr_t* addr, relocInfo::relocType rtype = relocInfo::none) | |
437 : _address((address) addr), | |
438 _rspec(rspec_from_rtype(rtype, (address) addr)) {} | |
0 | 439 #endif |
727 | 440 |
441 AddressLiteral(oop addr, relocInfo::relocType rtype = relocInfo::none) | |
442 : _address((address) addr), | |
443 _rspec(rspec_from_rtype(rtype, (address) addr)) {} | |
444 | |
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445 AddressLiteral(oop* addr, relocInfo::relocType rtype = relocInfo::none) |
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446 : _address((address) addr), |
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447 _rspec(rspec_from_rtype(rtype, (address) addr)) {} |
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448 |
727 | 449 AddressLiteral(float* addr, relocInfo::relocType rtype = relocInfo::none) |
450 : _address((address) addr), | |
451 _rspec(rspec_from_rtype(rtype, (address) addr)) {} | |
452 | |
453 AddressLiteral(double* addr, relocInfo::relocType rtype = relocInfo::none) | |
454 : _address((address) addr), | |
455 _rspec(rspec_from_rtype(rtype, (address) addr)) {} | |
456 | |
457 intptr_t value() const { return (intptr_t) _address; } | |
458 int low10() const; | |
459 | |
460 const relocInfo::relocType rtype() const { return _rspec.type(); } | |
461 const RelocationHolder& rspec() const { return _rspec; } | |
462 | |
463 RelocationHolder rspec(int offset) const { | |
0 | 464 return offset == 0 ? _rspec : _rspec.plus(offset); |
465 } | |
466 }; | |
467 | |
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468 // Convenience classes |
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469 class ExternalAddress: public AddressLiteral { |
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470 private: |
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471 static relocInfo::relocType reloc_for_target(address target) { |
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472 // Sometimes ExternalAddress is used for values which aren't |
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473 // exactly addresses, like the card table base. |
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474 // external_word_type can't be used for values in the first page |
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475 // so just skip the reloc in that case. |
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476 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; |
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477 } |
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478 |
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479 public: |
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480 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target( target)) {} |
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481 ExternalAddress(oop* target) : AddressLiteral(target, reloc_for_target((address) target)) {} |
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482 }; |
0 | 483 |
484 inline Address RegisterImpl::address_in_saved_window() const { | |
727 | 485 return (Address(SP, (sp_offset_in_saved_window() * wordSize) + STACK_BIAS)); |
0 | 486 } |
487 | |
488 | |
489 | |
490 // Argument is an abstraction used to represent an outgoing | |
491 // actual argument or an incoming formal parameter, whether | |
492 // it resides in memory or in a register, in a manner consistent | |
493 // with the SPARC Application Binary Interface, or ABI. This is | |
494 // often referred to as the native or C calling convention. | |
495 | |
496 class Argument VALUE_OBJ_CLASS_SPEC { | |
497 private: | |
498 int _number; | |
499 bool _is_in; | |
500 | |
501 public: | |
502 #ifdef _LP64 | |
503 enum { | |
504 n_register_parameters = 6, // only 6 registers may contain integer parameters | |
505 n_float_register_parameters = 16 // Can have up to 16 floating registers | |
506 }; | |
507 #else | |
508 enum { | |
509 n_register_parameters = 6 // only 6 registers may contain integer parameters | |
510 }; | |
511 #endif | |
512 | |
513 // creation | |
514 Argument(int number, bool is_in) : _number(number), _is_in(is_in) {} | |
515 | |
516 int number() const { return _number; } | |
517 bool is_in() const { return _is_in; } | |
518 bool is_out() const { return !is_in(); } | |
519 | |
520 Argument successor() const { return Argument(number() + 1, is_in()); } | |
521 Argument as_in() const { return Argument(number(), true ); } | |
522 Argument as_out() const { return Argument(number(), false); } | |
523 | |
524 // locating register-based arguments: | |
525 bool is_register() const { return _number < n_register_parameters; } | |
526 | |
527 #ifdef _LP64 | |
528 // locating Floating Point register-based arguments: | |
529 bool is_float_register() const { return _number < n_float_register_parameters; } | |
530 | |
531 FloatRegister as_float_register() const { | |
532 assert(is_float_register(), "must be a register argument"); | |
533 return as_FloatRegister(( number() *2 ) + 1); | |
534 } | |
535 FloatRegister as_double_register() const { | |
536 assert(is_float_register(), "must be a register argument"); | |
537 return as_FloatRegister(( number() *2 )); | |
538 } | |
539 #endif | |
540 | |
541 Register as_register() const { | |
542 assert(is_register(), "must be a register argument"); | |
543 return is_in() ? as_iRegister(number()) : as_oRegister(number()); | |
544 } | |
545 | |
546 // locating memory-based arguments | |
547 Address as_address() const { | |
548 assert(!is_register(), "must be a memory argument"); | |
549 return address_in_frame(); | |
550 } | |
551 | |
552 // When applied to a register-based argument, give the corresponding address | |
553 // into the 6-word area "into which callee may store register arguments" | |
554 // (This is a different place than the corresponding register-save area location.) | |
727 | 555 Address address_in_frame() const; |
0 | 556 |
557 // debugging | |
558 const char* name() const; | |
559 | |
560 friend class Assembler; | |
561 }; | |
562 | |
563 | |
564 // The SPARC Assembler: Pure assembler doing NO optimizations on the instruction | |
565 // level; i.e., what you write | |
566 // is what you get. The Assembler is generating code into a CodeBuffer. | |
567 | |
568 class Assembler : public AbstractAssembler { | |
569 protected: | |
570 | |
571 static void print_instruction(int inst); | |
572 static int patched_branch(int dest_pos, int inst, int inst_pos); | |
573 static int branch_destination(int inst, int pos); | |
574 | |
575 | |
576 friend class AbstractAssembler; | |
727 | 577 friend class AddressLiteral; |
0 | 578 |
579 // code patchers need various routines like inv_wdisp() | |
580 friend class NativeInstruction; | |
581 friend class NativeGeneralJump; | |
582 friend class Relocation; | |
583 friend class Label; | |
584 | |
585 public: | |
586 // op carries format info; see page 62 & 267 | |
587 | |
588 enum ops { | |
589 call_op = 1, // fmt 1 | |
590 branch_op = 0, // also sethi (fmt2) | |
591 arith_op = 2, // fmt 3, arith & misc | |
592 ldst_op = 3 // fmt 3, load/store | |
593 }; | |
594 | |
595 enum op2s { | |
596 bpr_op2 = 3, | |
597 fb_op2 = 6, | |
598 fbp_op2 = 5, | |
599 br_op2 = 2, | |
600 bp_op2 = 1, | |
601 cb_op2 = 7, // V8 | |
602 sethi_op2 = 4 | |
603 }; | |
604 | |
605 enum op3s { | |
606 // selected op3s | |
607 add_op3 = 0x00, | |
608 and_op3 = 0x01, | |
609 or_op3 = 0x02, | |
610 xor_op3 = 0x03, | |
611 sub_op3 = 0x04, | |
612 andn_op3 = 0x05, | |
613 orn_op3 = 0x06, | |
614 xnor_op3 = 0x07, | |
615 addc_op3 = 0x08, | |
616 mulx_op3 = 0x09, | |
617 umul_op3 = 0x0a, | |
618 smul_op3 = 0x0b, | |
619 subc_op3 = 0x0c, | |
620 udivx_op3 = 0x0d, | |
621 udiv_op3 = 0x0e, | |
622 sdiv_op3 = 0x0f, | |
623 | |
624 addcc_op3 = 0x10, | |
625 andcc_op3 = 0x11, | |
626 orcc_op3 = 0x12, | |
627 xorcc_op3 = 0x13, | |
628 subcc_op3 = 0x14, | |
629 andncc_op3 = 0x15, | |
630 orncc_op3 = 0x16, | |
631 xnorcc_op3 = 0x17, | |
632 addccc_op3 = 0x18, | |
633 umulcc_op3 = 0x1a, | |
634 smulcc_op3 = 0x1b, | |
635 subccc_op3 = 0x1c, | |
636 udivcc_op3 = 0x1e, | |
637 sdivcc_op3 = 0x1f, | |
638 | |
639 taddcc_op3 = 0x20, | |
640 tsubcc_op3 = 0x21, | |
641 taddcctv_op3 = 0x22, | |
642 tsubcctv_op3 = 0x23, | |
643 mulscc_op3 = 0x24, | |
644 sll_op3 = 0x25, | |
645 sllx_op3 = 0x25, | |
646 srl_op3 = 0x26, | |
647 srlx_op3 = 0x26, | |
648 sra_op3 = 0x27, | |
649 srax_op3 = 0x27, | |
650 rdreg_op3 = 0x28, | |
651 membar_op3 = 0x28, | |
652 | |
653 flushw_op3 = 0x2b, | |
654 movcc_op3 = 0x2c, | |
655 sdivx_op3 = 0x2d, | |
656 popc_op3 = 0x2e, | |
657 movr_op3 = 0x2f, | |
658 | |
659 sir_op3 = 0x30, | |
660 wrreg_op3 = 0x30, | |
661 saved_op3 = 0x31, | |
662 | |
663 fpop1_op3 = 0x34, | |
664 fpop2_op3 = 0x35, | |
665 impdep1_op3 = 0x36, | |
666 impdep2_op3 = 0x37, | |
667 jmpl_op3 = 0x38, | |
668 rett_op3 = 0x39, | |
669 trap_op3 = 0x3a, | |
670 flush_op3 = 0x3b, | |
671 save_op3 = 0x3c, | |
672 restore_op3 = 0x3d, | |
673 done_op3 = 0x3e, | |
674 retry_op3 = 0x3e, | |
675 | |
676 lduw_op3 = 0x00, | |
677 ldub_op3 = 0x01, | |
678 lduh_op3 = 0x02, | |
679 ldd_op3 = 0x03, | |
680 stw_op3 = 0x04, | |
681 stb_op3 = 0x05, | |
682 sth_op3 = 0x06, | |
683 std_op3 = 0x07, | |
684 ldsw_op3 = 0x08, | |
685 ldsb_op3 = 0x09, | |
686 ldsh_op3 = 0x0a, | |
687 ldx_op3 = 0x0b, | |
688 | |
689 ldstub_op3 = 0x0d, | |
690 stx_op3 = 0x0e, | |
691 swap_op3 = 0x0f, | |
692 | |
693 stwa_op3 = 0x14, | |
694 stxa_op3 = 0x1e, | |
695 | |
696 ldf_op3 = 0x20, | |
697 ldfsr_op3 = 0x21, | |
698 ldqf_op3 = 0x22, | |
699 lddf_op3 = 0x23, | |
700 stf_op3 = 0x24, | |
701 stfsr_op3 = 0x25, | |
702 stqf_op3 = 0x26, | |
703 stdf_op3 = 0x27, | |
704 | |
705 prefetch_op3 = 0x2d, | |
706 | |
707 | |
708 ldc_op3 = 0x30, | |
709 ldcsr_op3 = 0x31, | |
710 lddc_op3 = 0x33, | |
711 stc_op3 = 0x34, | |
712 stcsr_op3 = 0x35, | |
713 stdcq_op3 = 0x36, | |
714 stdc_op3 = 0x37, | |
715 | |
716 casa_op3 = 0x3c, | |
717 casxa_op3 = 0x3e, | |
718 | |
719 alt_bit_op3 = 0x10, | |
720 cc_bit_op3 = 0x10 | |
721 }; | |
722 | |
723 enum opfs { | |
724 // selected opfs | |
725 fmovs_opf = 0x01, | |
726 fmovd_opf = 0x02, | |
727 | |
728 fnegs_opf = 0x05, | |
729 fnegd_opf = 0x06, | |
730 | |
731 fadds_opf = 0x41, | |
732 faddd_opf = 0x42, | |
733 fsubs_opf = 0x45, | |
734 fsubd_opf = 0x46, | |
735 | |
736 fmuls_opf = 0x49, | |
737 fmuld_opf = 0x4a, | |
738 fdivs_opf = 0x4d, | |
739 fdivd_opf = 0x4e, | |
740 | |
741 fcmps_opf = 0x51, | |
742 fcmpd_opf = 0x52, | |
743 | |
744 fstox_opf = 0x81, | |
745 fdtox_opf = 0x82, | |
746 fxtos_opf = 0x84, | |
747 fxtod_opf = 0x88, | |
748 fitos_opf = 0xc4, | |
749 fdtos_opf = 0xc6, | |
750 fitod_opf = 0xc8, | |
751 fstod_opf = 0xc9, | |
752 fstoi_opf = 0xd1, | |
753 fdtoi_opf = 0xd2 | |
754 }; | |
755 | |
756 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7 }; | |
757 | |
758 enum Condition { | |
759 // for FBfcc & FBPfcc instruction | |
760 f_never = 0, | |
761 f_notEqual = 1, | |
762 f_notZero = 1, | |
763 f_lessOrGreater = 2, | |
764 f_unorderedOrLess = 3, | |
765 f_less = 4, | |
766 f_unorderedOrGreater = 5, | |
767 f_greater = 6, | |
768 f_unordered = 7, | |
769 f_always = 8, | |
770 f_equal = 9, | |
771 f_zero = 9, | |
772 f_unorderedOrEqual = 10, | |
773 f_greaterOrEqual = 11, | |
774 f_unorderedOrGreaterOrEqual = 12, | |
775 f_lessOrEqual = 13, | |
776 f_unorderedOrLessOrEqual = 14, | |
777 f_ordered = 15, | |
778 | |
779 // V8 coproc, pp 123 v8 manual | |
780 | |
781 cp_always = 8, | |
782 cp_never = 0, | |
783 cp_3 = 7, | |
784 cp_2 = 6, | |
785 cp_2or3 = 5, | |
786 cp_1 = 4, | |
787 cp_1or3 = 3, | |
788 cp_1or2 = 2, | |
789 cp_1or2or3 = 1, | |
790 cp_0 = 9, | |
791 cp_0or3 = 10, | |
792 cp_0or2 = 11, | |
793 cp_0or2or3 = 12, | |
794 cp_0or1 = 13, | |
795 cp_0or1or3 = 14, | |
796 cp_0or1or2 = 15, | |
797 | |
798 | |
799 // for integers | |
800 | |
801 never = 0, | |
802 equal = 1, | |
803 zero = 1, | |
804 lessEqual = 2, | |
805 less = 3, | |
806 lessEqualUnsigned = 4, | |
807 lessUnsigned = 5, | |
808 carrySet = 5, | |
809 negative = 6, | |
810 overflowSet = 7, | |
811 always = 8, | |
812 notEqual = 9, | |
813 notZero = 9, | |
814 greater = 10, | |
815 greaterEqual = 11, | |
816 greaterUnsigned = 12, | |
817 greaterEqualUnsigned = 13, | |
818 carryClear = 13, | |
819 positive = 14, | |
820 overflowClear = 15 | |
821 }; | |
822 | |
823 enum CC { | |
824 icc = 0, xcc = 2, | |
825 // ptr_cc is the correct condition code for a pointer or intptr_t: | |
826 ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc), | |
827 fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3 | |
828 }; | |
829 | |
830 enum PrefetchFcn { | |
831 severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4 | |
832 }; | |
833 | |
834 public: | |
835 // Helper functions for groups of instructions | |
836 | |
837 enum Predict { pt = 1, pn = 0 }; // pt = predict taken | |
838 | |
839 enum Membar_mask_bits { // page 184, v9 | |
840 StoreStore = 1 << 3, | |
841 LoadStore = 1 << 2, | |
842 StoreLoad = 1 << 1, | |
843 LoadLoad = 1 << 0, | |
844 | |
845 Sync = 1 << 6, | |
846 MemIssue = 1 << 5, | |
847 Lookaside = 1 << 4 | |
848 }; | |
849 | |
850 // test if x is within signed immediate range for nbits | |
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851 static bool is_simm(intptr_t x, int nbits) { return -( intptr_t(1) << nbits-1 ) <= x && x < ( intptr_t(1) << nbits-1 ); } |
0 | 852 |
853 // test if -4096 <= x <= 4095 | |
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854 static bool is_simm13(intptr_t x) { return is_simm(x, 13); } |
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855 |
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856 static bool is_in_wdisp_range(address a, address b, int nbits) { |
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857 intptr_t d = intptr_t(b) - intptr_t(a); |
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858 return is_simm(d, nbits + 2); |
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859 } |
0 | 860 |
1848 | 861 // test if label is in simm16 range in words (wdisp16). |
862 bool is_in_wdisp16_range(Label& L) { | |
2121
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863 return is_in_wdisp_range(target(L), pc(), 16); |
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864 } |
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865 // test if the distance between two addresses fits in simm30 range in words |
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866 static bool is_in_wdisp30_range(address a, address b) { |
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867 return is_in_wdisp_range(a, b, 30); |
1848 | 868 } |
869 | |
0 | 870 enum ASIs { // page 72, v9 |
871 ASI_PRIMARY = 0x80, | |
872 ASI_PRIMARY_LITTLE = 0x88 | |
873 // add more from book as needed | |
874 }; | |
875 | |
876 protected: | |
877 // helpers | |
878 | |
879 // x is supposed to fit in a field "nbits" wide | |
880 // and be sign-extended. Check the range. | |
881 | |
882 static void assert_signed_range(intptr_t x, int nbits) { | |
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883 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < ( 1 << nbits-1)), |
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884 err_msg("value out of range: x=" INTPTR_FORMAT ", nbits=%d", x, nbits)); |
0 | 885 } |
886 | |
887 static void assert_signed_word_disp_range(intptr_t x, int nbits) { | |
888 assert( (x & 3) == 0, "not word aligned"); | |
889 assert_signed_range(x, nbits + 2); | |
890 } | |
891 | |
892 static void assert_unsigned_const(int x, int nbits) { | |
893 assert( juint(x) < juint(1 << nbits), "unsigned constant out of range"); | |
894 } | |
895 | |
896 // fields: note bits numbered from LSB = 0, | |
897 // fields known by inclusive bit range | |
898 | |
899 static int fmask(juint hi_bit, juint lo_bit) { | |
900 assert( hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits"); | |
901 return (1 << ( hi_bit-lo_bit + 1 )) - 1; | |
902 } | |
903 | |
904 // inverse of u_field | |
905 | |
906 static int inv_u_field(int x, int hi_bit, int lo_bit) { | |
907 juint r = juint(x) >> lo_bit; | |
908 r &= fmask( hi_bit, lo_bit); | |
909 return int(r); | |
910 } | |
911 | |
912 | |
913 // signed version: extract from field and sign-extend | |
914 | |
915 static int inv_s_field(int x, int hi_bit, int lo_bit) { | |
916 int sign_shift = 31 - hi_bit; | |
917 return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit); | |
918 } | |
919 | |
920 // given a field that ranges from hi_bit to lo_bit (inclusive, | |
921 // LSB = 0), and an unsigned value for the field, | |
922 // shift it into the field | |
923 | |
924 #ifdef ASSERT | |
925 static int u_field(int x, int hi_bit, int lo_bit) { | |
926 assert( ( x & ~fmask(hi_bit, lo_bit)) == 0, | |
927 "value out of range"); | |
928 int r = x << lo_bit; | |
929 assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking"); | |
930 return r; | |
931 } | |
932 #else | |
933 // make sure this is inlined as it will reduce code size significantly | |
934 #define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit)) | |
935 #endif | |
936 | |
937 static int inv_op( int x ) { return inv_u_field(x, 31, 30); } | |
938 static int inv_op2( int x ) { return inv_u_field(x, 24, 22); } | |
939 static int inv_op3( int x ) { return inv_u_field(x, 24, 19); } | |
940 static int inv_cond( int x ){ return inv_u_field(x, 28, 25); } | |
941 | |
942 static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; } | |
943 | |
944 static Register inv_rd( int x ) { return as_Register(inv_u_field(x, 29, 25)); } | |
945 static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); } | |
946 static Register inv_rs2( int x ) { return as_Register(inv_u_field(x, 4, 0)); } | |
947 | |
948 static int op( int x) { return u_field(x, 31, 30); } | |
949 static int rd( Register r) { return u_field(r->encoding(), 29, 25); } | |
950 static int fcn( int x) { return u_field(x, 29, 25); } | |
951 static int op3( int x) { return u_field(x, 24, 19); } | |
952 static int rs1( Register r) { return u_field(r->encoding(), 18, 14); } | |
953 static int rs2( Register r) { return u_field(r->encoding(), 4, 0); } | |
954 static int annul( bool a) { return u_field(a ? 1 : 0, 29, 29); } | |
955 static int cond( int x) { return u_field(x, 28, 25); } | |
956 static int cond_mov( int x) { return u_field(x, 17, 14); } | |
957 static int rcond( RCondition x) { return u_field(x, 12, 10); } | |
958 static int op2( int x) { return u_field(x, 24, 22); } | |
959 static int predict( bool p) { return u_field(p ? 1 : 0, 19, 19); } | |
960 static int branchcc( CC fcca) { return u_field(fcca, 21, 20); } | |
961 static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); } | |
962 static int imm_asi( int x) { return u_field(x, 12, 5); } | |
963 static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); } | |
964 static int opf_low6( int w) { return u_field(w, 10, 5); } | |
965 static int opf_low5( int w) { return u_field(w, 9, 5); } | |
966 static int trapcc( CC cc) { return u_field(cc, 12, 11); } | |
967 static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit | |
968 static int opf( int x) { return u_field(x, 13, 5); } | |
969 | |
970 static int opf_cc( CC c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); } | |
971 static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); } | |
972 | |
973 static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); }; | |
974 static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); }; | |
975 static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); }; | |
976 | |
977 // some float instructions use this encoding on the op3 field | |
978 static int alt_op3(int op, FloatRegisterImpl::Width w) { | |
979 int r; | |
980 switch(w) { | |
981 case FloatRegisterImpl::S: r = op + 0; break; | |
982 case FloatRegisterImpl::D: r = op + 3; break; | |
983 case FloatRegisterImpl::Q: r = op + 2; break; | |
984 default: ShouldNotReachHere(); break; | |
985 } | |
986 return op3(r); | |
987 } | |
988 | |
989 | |
990 // compute inverse of simm | |
991 static int inv_simm(int x, int nbits) { | |
992 return (int)(x << (32 - nbits)) >> (32 - nbits); | |
993 } | |
994 | |
995 static int inv_simm13( int x ) { return inv_simm(x, 13); } | |
996 | |
997 // signed immediate, in low bits, nbits long | |
998 static int simm(int x, int nbits) { | |
999 assert_signed_range(x, nbits); | |
1000 return x & (( 1 << nbits ) - 1); | |
1001 } | |
1002 | |
1003 // compute inverse of wdisp16 | |
1004 static intptr_t inv_wdisp16(int x, intptr_t pos) { | |
1005 int lo = x & (( 1 << 14 ) - 1); | |
1006 int hi = (x >> 20) & 3; | |
1007 if (hi >= 2) hi |= ~1; | |
1008 return (((hi << 14) | lo) << 2) + pos; | |
1009 } | |
1010 | |
1011 // word offset, 14 bits at LSend, 2 bits at B21, B20 | |
1012 static int wdisp16(intptr_t x, intptr_t off) { | |
1013 intptr_t xx = x - off; | |
1014 assert_signed_word_disp_range(xx, 16); | |
1015 int r = (xx >> 2) & ((1 << 14) - 1) | |
1016 | ( ( (xx>>(2+14)) & 3 ) << 20 ); | |
1017 assert( inv_wdisp16(r, off) == x, "inverse is not inverse"); | |
1018 return r; | |
1019 } | |
1020 | |
1021 | |
1022 // word displacement in low-order nbits bits | |
1023 | |
1024 static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) { | |
1025 int pre_sign_extend = x & (( 1 << nbits ) - 1); | |
1026 int r = pre_sign_extend >= ( 1 << (nbits-1) ) | |
1027 ? pre_sign_extend | ~(( 1 << nbits ) - 1) | |
1028 : pre_sign_extend; | |
1029 return (r << 2) + pos; | |
1030 } | |
1031 | |
1032 static int wdisp( intptr_t x, intptr_t off, int nbits ) { | |
1033 intptr_t xx = x - off; | |
1034 assert_signed_word_disp_range(xx, nbits); | |
1035 int r = (xx >> 2) & (( 1 << nbits ) - 1); | |
1036 assert( inv_wdisp( r, off, nbits ) == x, "inverse not inverse"); | |
1037 return r; | |
1038 } | |
1039 | |
1040 | |
1041 // Extract the top 32 bits in a 64 bit word | |
1042 static int32_t hi32( int64_t x ) { | |
1043 int32_t r = int32_t( (uint64_t)x >> 32 ); | |
1044 return r; | |
1045 } | |
1046 | |
1047 // given a sethi instruction, extract the constant, left-justified | |
1048 static int inv_hi22( int x ) { | |
1049 return x << 10; | |
1050 } | |
1051 | |
1052 // create an imm22 field, given a 32-bit left-justified constant | |
1053 static int hi22( int x ) { | |
1054 int r = int( juint(x) >> 10 ); | |
1055 assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'"); | |
1056 return r; | |
1057 } | |
1058 | |
1059 // create a low10 __value__ (not a field) for a given a 32-bit constant | |
1060 static int low10( int x ) { | |
1061 return x & ((1 << 10) - 1); | |
1062 } | |
1063 | |
1064 // instruction only in v9 | |
1065 static void v9_only() { assert( VM_Version::v9_instructions_work(), "This instruction only works on SPARC V9"); } | |
1066 | |
1067 // instruction only in v8 | |
1068 static void v8_only() { assert( VM_Version::v8_instructions_work(), "This instruction only works on SPARC V8"); } | |
1069 | |
1070 // instruction deprecated in v9 | |
1071 static void v9_dep() { } // do nothing for now | |
1072 | |
1073 // some float instructions only exist for single prec. on v8 | |
1074 static void v8_s_only(FloatRegisterImpl::Width w) { if (w != FloatRegisterImpl::S) v9_only(); } | |
1075 | |
1076 // v8 has no CC field | |
1077 static void v8_no_cc(CC cc) { if (cc) v9_only(); } | |
1078 | |
1079 protected: | |
1080 // Simple delay-slot scheme: | |
1081 // In order to check the programmer, the assembler keeps track of deley slots. | |
1082 // It forbids CTIs in delay slots (conservative, but should be OK). | |
1083 // Also, when putting an instruction into a delay slot, you must say | |
1084 // asm->delayed()->add(...), in order to check that you don't omit | |
1085 // delay-slot instructions. | |
1086 // To implement this, we use a simple FSA | |
1087 | |
1088 #ifdef ASSERT | |
1089 #define CHECK_DELAY | |
1090 #endif | |
1091 #ifdef CHECK_DELAY | |
1092 enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state; | |
1093 #endif | |
1094 | |
1095 public: | |
1096 // Tells assembler next instruction must NOT be in delay slot. | |
1097 // Use at start of multinstruction macros. | |
1098 void assert_not_delayed() { | |
1099 // This is a separate overloading to avoid creation of string constants | |
1100 // in non-asserted code--with some compilers this pollutes the object code. | |
1101 #ifdef CHECK_DELAY | |
1102 assert_not_delayed("next instruction should not be a delay slot"); | |
1103 #endif | |
1104 } | |
1105 void assert_not_delayed(const char* msg) { | |
1106 #ifdef CHECK_DELAY | |
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1107 assert(delay_state == no_delay, msg); |
0 | 1108 #endif |
1109 } | |
1110 | |
1111 protected: | |
1112 // Delay slot helpers | |
1113 // cti is called when emitting control-transfer instruction, | |
1114 // BEFORE doing the emitting. | |
1115 // Only effective when assertion-checking is enabled. | |
1116 void cti() { | |
1117 #ifdef CHECK_DELAY | |
1118 assert_not_delayed("cti should not be in delay slot"); | |
1119 #endif | |
1120 } | |
1121 | |
1122 // called when emitting cti with a delay slot, AFTER emitting | |
1123 void has_delay_slot() { | |
1124 #ifdef CHECK_DELAY | |
1125 assert_not_delayed("just checking"); | |
1126 delay_state = at_delay_slot; | |
1127 #endif | |
1128 } | |
1129 | |
1130 public: | |
1131 // Tells assembler you know that next instruction is delayed | |
1132 Assembler* delayed() { | |
1133 #ifdef CHECK_DELAY | |
1134 assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot"); | |
1135 delay_state = filling_delay_slot; | |
1136 #endif | |
1137 return this; | |
1138 } | |
1139 | |
1140 void flush() { | |
1141 #ifdef CHECK_DELAY | |
1142 assert ( delay_state == no_delay, "ending code with a delay slot"); | |
1143 #endif | |
1144 AbstractAssembler::flush(); | |
1145 } | |
1146 | |
1147 inline void emit_long(int); // shadows AbstractAssembler::emit_long | |
1148 inline void emit_data(int x) { emit_long(x); } | |
1149 inline void emit_data(int, RelocationHolder const&); | |
1150 inline void emit_data(int, relocInfo::relocType rtype); | |
1151 // helper for above fcns | |
1152 inline void check_delay(); | |
1153 | |
1154 | |
1155 public: | |
1156 // instructions, refer to page numbers in the SPARC Architecture Manual, V9 | |
1157 | |
1158 // pp 135 (addc was addx in v8) | |
1159 | |
727 | 1160 inline void add(Register s1, Register s2, Register d ); |
1161 inline void add(Register s1, int simm13a, Register d, relocInfo::relocType rtype = relocInfo::none); | |
1162 inline void add(Register s1, int simm13a, Register d, RelocationHolder const& rspec); | |
1163 inline void add(Register s1, RegisterOrConstant s2, Register d, int offset = 0); | |
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1164 inline void add(const Address& a, Register d, int offset = 0); |
0 | 1165 |
1166 void addcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1167 void addcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1168 void addc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | rs2(s2) ); } | |
1169 void addc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1170 void addccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1171 void addccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1172 | |
1173 // pp 136 | |
1174 | |
1175 inline void bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none ); | |
1176 inline void bpr( RCondition c, bool a, Predict p, Register s1, Label& L); | |
1177 | |
1178 protected: // use MacroAssembler::br instead | |
1179 | |
1180 // pp 138 | |
1181 | |
1182 inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none ); | |
1183 inline void fb( Condition c, bool a, Label& L ); | |
1184 | |
1185 // pp 141 | |
1186 | |
1187 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); | |
1188 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L ); | |
1189 | |
1190 public: | |
1191 | |
1192 // pp 144 | |
1193 | |
1194 inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none ); | |
1195 inline void br( Condition c, bool a, Label& L ); | |
1196 | |
1197 // pp 146 | |
1198 | |
1199 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); | |
1200 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L ); | |
1201 | |
1202 // pp 121 (V8) | |
1203 | |
1204 inline void cb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none ); | |
1205 inline void cb( Condition c, bool a, Label& L ); | |
1206 | |
1207 // pp 149 | |
1208 | |
1209 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type ); | |
1210 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type ); | |
1211 | |
1212 // pp 150 | |
1213 | |
1214 // These instructions compare the contents of s2 with the contents of | |
1215 // memory at address in s1. If the values are equal, the contents of memory | |
1216 // at address s1 is swapped with the data in d. If the values are not equal, | |
1217 // the the contents of memory at s1 is loaded into d, without the swap. | |
1218 | |
1219 void casa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); } | |
1220 void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); } | |
1221 | |
1222 // pp 152 | |
1223 | |
1224 void udiv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | rs2(s2)); } | |
1225 void udiv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1226 void sdiv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | rs2(s2)); } | |
1227 void sdiv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1228 void udivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); } | |
1229 void udivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1230 void sdivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); } | |
1231 void sdivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1232 | |
1233 // pp 155 | |
1234 | |
1235 void done() { v9_only(); cti(); emit_long( op(arith_op) | fcn(0) | op3(done_op3) ); } | |
1236 void retry() { v9_only(); cti(); emit_long( op(arith_op) | fcn(1) | op3(retry_op3) ); } | |
1237 | |
1238 // pp 156 | |
1239 | |
1240 void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); } | |
1241 void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); } | |
1242 | |
1243 // pp 157 | |
1244 | |
1245 void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc); emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); } | |
1246 void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc); emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); } | |
1247 | |
1248 // pp 159 | |
1249 | |
1250 void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); } | |
1251 void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); } | |
1252 | |
1253 // pp 160 | |
1254 | |
1255 void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); } | |
1256 | |
1257 // pp 161 | |
1258 | |
1259 void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, w)); } | |
1260 void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, w)); } | |
1261 | |
1262 // pp 162 | |
1263 | |
1264 void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); } | |
1265 | |
1266 void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); } | |
1267 | |
1268 // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fnegs is the only instruction available | |
1269 // on v8 to do negation of single, double and quad precision floats. | |
1270 | |
1271 void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(sd, w)); else emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x05) | fs2(sd, w)); } | |
1272 | |
1273 void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); } | |
1274 | |
1275 // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fabss is the only instruction available | |
1276 // on v8 to do abs operation on single/double/quad precision floats. | |
1277 | |
1278 void fabs( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(sd, w)); else emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x09) | fs2(sd, w)); } | |
1279 | |
1280 // pp 163 | |
1281 | |
1282 void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); } | |
1283 void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); } | |
1284 void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); } | |
1285 | |
1286 // pp 164 | |
1287 | |
1288 void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); } | |
1289 | |
1290 // pp 165 | |
1291 | |
1292 inline void flush( Register s1, Register s2 ); | |
1293 inline void flush( Register s1, int simm13a); | |
1294 | |
1295 // pp 167 | |
1296 | |
1297 void flushw() { v9_only(); emit_long( op(arith_op) | op3(flushw_op3) ); } | |
1298 | |
1299 // pp 168 | |
1300 | |
1301 void illtrap( int const22a) { if (const22a != 0) v9_only(); emit_long( op(branch_op) | u_field(const22a, 21, 0) ); } | |
1302 // v8 unimp == illtrap(0) | |
1303 | |
1304 // pp 169 | |
1305 | |
1306 void impdep1( int id1, int const19a ) { v9_only(); emit_long( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); } | |
1307 void impdep2( int id1, int const19a ) { v9_only(); emit_long( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); } | |
1308 | |
1309 // pp 149 (v8) | |
1310 | |
1311 void cpop1( int opc, int cr1, int cr2, int crd ) { v8_only(); emit_long( op(arith_op) | fcn(crd) | op3(impdep1_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); } | |
1312 void cpop2( int opc, int cr1, int cr2, int crd ) { v8_only(); emit_long( op(arith_op) | fcn(crd) | op3(impdep2_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); } | |
1313 | |
1314 // pp 170 | |
1315 | |
1316 void jmpl( Register s1, Register s2, Register d ); | |
1317 void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() ); | |
1318 | |
1319 // 171 | |
1320 | |
1006
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changeset
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1321 inline void ldf(FloatRegisterImpl::Width w, Register s1, RegisterOrConstant s2, FloatRegister d); |
727 | 1322 inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d); |
1323 inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder()); | |
1324 | |
1325 inline void ldf(FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset = 0); | |
0 | 1326 |
1327 | |
1328 inline void ldfsr( Register s1, Register s2 ); | |
1329 inline void ldfsr( Register s1, int simm13a); | |
1330 inline void ldxfsr( Register s1, Register s2 ); | |
1331 inline void ldxfsr( Register s1, int simm13a); | |
1332 | |
1333 // pp 94 (v8) | |
1334 | |
1335 inline void ldc( Register s1, Register s2, int crd ); | |
1336 inline void ldc( Register s1, int simm13a, int crd); | |
1337 inline void lddc( Register s1, Register s2, int crd ); | |
1338 inline void lddc( Register s1, int simm13a, int crd); | |
1339 inline void ldcsr( Register s1, Register s2, int crd ); | |
1340 inline void ldcsr( Register s1, int simm13a, int crd); | |
1341 | |
1342 | |
1343 // 173 | |
1344 | |
1345 void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1346 void ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1347 | |
1348 // pp 175, lduw is ld on v8 | |
1349 | |
1350 inline void ldsb( Register s1, Register s2, Register d ); | |
1351 inline void ldsb( Register s1, int simm13a, Register d); | |
1352 inline void ldsh( Register s1, Register s2, Register d ); | |
1353 inline void ldsh( Register s1, int simm13a, Register d); | |
1354 inline void ldsw( Register s1, Register s2, Register d ); | |
1355 inline void ldsw( Register s1, int simm13a, Register d); | |
1356 inline void ldub( Register s1, Register s2, Register d ); | |
1357 inline void ldub( Register s1, int simm13a, Register d); | |
1358 inline void lduh( Register s1, Register s2, Register d ); | |
1359 inline void lduh( Register s1, int simm13a, Register d); | |
1360 inline void lduw( Register s1, Register s2, Register d ); | |
1361 inline void lduw( Register s1, int simm13a, Register d); | |
1362 inline void ldx( Register s1, Register s2, Register d ); | |
1363 inline void ldx( Register s1, int simm13a, Register d); | |
1364 inline void ld( Register s1, Register s2, Register d ); | |
1365 inline void ld( Register s1, int simm13a, Register d); | |
1366 inline void ldd( Register s1, Register s2, Register d ); | |
1367 inline void ldd( Register s1, int simm13a, Register d); | |
1368 | |
727 | 1369 #ifdef ASSERT |
1370 // ByteSize is only a class when ASSERT is defined, otherwise it's an int. | |
1371 inline void ld( Register s1, ByteSize simm13a, Register d); | |
1372 #endif | |
1373 | |
1374 inline void ldsb(const Address& a, Register d, int offset = 0); | |
1375 inline void ldsh(const Address& a, Register d, int offset = 0); | |
1376 inline void ldsw(const Address& a, Register d, int offset = 0); | |
1377 inline void ldub(const Address& a, Register d, int offset = 0); | |
1378 inline void lduh(const Address& a, Register d, int offset = 0); | |
1379 inline void lduw(const Address& a, Register d, int offset = 0); | |
1380 inline void ldx( const Address& a, Register d, int offset = 0); | |
1381 inline void ld( const Address& a, Register d, int offset = 0); | |
1382 inline void ldd( const Address& a, Register d, int offset = 0); | |
0 | 1383 |
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1384 inline void ldub( Register s1, RegisterOrConstant s2, Register d ); |
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1385 inline void ldsb( Register s1, RegisterOrConstant s2, Register d ); |
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1386 inline void lduh( Register s1, RegisterOrConstant s2, Register d ); |
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1387 inline void ldsh( Register s1, RegisterOrConstant s2, Register d ); |
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1388 inline void lduw( Register s1, RegisterOrConstant s2, Register d ); |
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1389 inline void ldsw( Register s1, RegisterOrConstant s2, Register d ); |
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1390 inline void ldx( Register s1, RegisterOrConstant s2, Register d ); |
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1391 inline void ld( Register s1, RegisterOrConstant s2, Register d ); |
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1392 inline void ldd( Register s1, RegisterOrConstant s2, Register d ); |
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1393 |
0 | 1394 // pp 177 |
1395 | |
1396 void ldsba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1397 void ldsba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1398 void ldsha( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1399 void ldsha( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1400 void ldswa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1401 void ldswa( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1402 void lduba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1403 void lduba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1404 void lduha( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1405 void lduha( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1406 void lduwa( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1407 void lduwa( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1408 void ldxa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1409 void ldxa( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1410 void ldda( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1411 void ldda( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1412 | |
1413 // pp 179 | |
1414 | |
1415 inline void ldstub( Register s1, Register s2, Register d ); | |
1416 inline void ldstub( Register s1, int simm13a, Register d); | |
1417 | |
1418 // pp 180 | |
1419 | |
1420 void ldstuba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1421 void ldstuba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1422 | |
1423 // pp 181 | |
1424 | |
1503 | 1425 void and3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); } |
1426 void and3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
0 | 1427 void andcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } |
1428 void andcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1429 void andn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); } | |
1430 void andn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1503 | 1431 void andn( Register s1, RegisterOrConstant s2, Register d); |
0 | 1432 void andncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } |
1433 void andncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1503 | 1434 void or3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); } |
1435 void or3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
0 | 1436 void orcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } |
1437 void orcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1438 void orn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); } | |
1439 void orn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1440 void orncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1441 void orncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1503 | 1442 void xor3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); } |
1443 void xor3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
0 | 1444 void xorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } |
1445 void xorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1446 void xnor( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); } | |
1447 void xnor( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1448 void xnorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1449 void xnorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1450 | |
1451 // pp 183 | |
1452 | |
1453 void membar( Membar_mask_bits const7a ) { v9_only(); emit_long( op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field( int(const7a), 6, 0)); } | |
1454 | |
1455 // pp 185 | |
1456 | |
1457 void fmov( FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); } | |
1458 | |
1459 // pp 189 | |
1460 | |
1461 void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); } | |
1462 | |
1463 // pp 191 | |
1464 | |
1465 void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2) ); } | |
1466 void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11) ); } | |
1467 | |
1468 // pp 195 | |
1469 | |
1470 void movr( RCondition c, Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); } | |
1471 void movr( RCondition c, Register s1, int simm10a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); } | |
1472 | |
1473 // pp 196 | |
1474 | |
1475 void mulx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); } | |
1476 void mulx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1477 void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); } | |
1478 void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1479 void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); } | |
1480 void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1481 | |
1482 // pp 197 | |
1483 | |
1484 void umul( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | rs2(s2) ); } | |
1485 void umul( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1486 void smul( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | rs2(s2) ); } | |
1487 void smul( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1488 void umulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1489 void umulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1490 void smulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1491 void smulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1492 | |
1493 // pp 199 | |
1494 | |
1495 void mulscc( Register s1, Register s2, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | rs2(s2) ); } | |
1496 void mulscc( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1497 | |
1498 // pp 201 | |
1499 | |
1500 void nop() { emit_long( op(branch_op) | op2(sethi_op2) ); } | |
1501 | |
1502 | |
1503 // pp 202 | |
1504 | |
1505 void popc( Register s, Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); } | |
1506 void popc( int simm13a, Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); } | |
1507 | |
1508 // pp 203 | |
1509 | |
1510 void prefetch( Register s1, Register s2, PrefetchFcn f); | |
1511 void prefetch( Register s1, int simm13a, PrefetchFcn f); | |
1512 void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1513 void prefetcha( Register s1, int simm13a, PrefetchFcn f ) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1514 | |
1515 inline void prefetch(const Address& a, PrefetchFcn F, int offset = 0); | |
1516 | |
1517 // pp 208 | |
1518 | |
1519 // not implementing read privileged register | |
1520 | |
1521 inline void rdy( Register d) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); } | |
1522 inline void rdccr( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); } | |
1523 inline void rdasi( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); } | |
1524 inline void rdtick( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); } // Spoon! | |
1525 inline void rdpc( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); } | |
1526 inline void rdfprs( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); } | |
1527 | |
1528 // pp 213 | |
1529 | |
1530 inline void rett( Register s1, Register s2); | |
1531 inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none); | |
1532 | |
1533 // pp 214 | |
1534 | |
1535 void save( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2) ); } | |
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1536 void save( Register s1, int simm13a, Register d ) { |
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1537 // make sure frame is at least large enough for the register save area |
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1538 assert(-simm13a >= 16 * wordSize, "frame too small"); |
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1539 emit_long( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); |
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1540 } |
0 | 1541 |
1542 void restore( Register s1 = G0, Register s2 = G0, Register d = G0 ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2) ); } | |
1543 void restore( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1544 | |
1545 // pp 216 | |
1546 | |
1547 void saved() { v9_only(); emit_long( op(arith_op) | fcn(0) | op3(saved_op3)); } | |
1548 void restored() { v9_only(); emit_long( op(arith_op) | fcn(1) | op3(saved_op3)); } | |
1549 | |
1550 // pp 217 | |
1551 | |
1552 inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() ); | |
1553 // pp 218 | |
1554 | |
1555 void sll( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2) ); } | |
1556 void sll( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); } | |
1557 void srl( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2) ); } | |
1558 void srl( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); } | |
1559 void sra( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2) ); } | |
1560 void sra( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); } | |
1561 | |
1562 void sllx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2) ); } | |
1563 void sllx( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); } | |
1564 void srlx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2) ); } | |
1565 void srlx( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); } | |
1566 void srax( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2) ); } | |
1567 void srax( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); } | |
1568 | |
1569 // pp 220 | |
1570 | |
1571 void sir( int simm13a ) { emit_long( op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); } | |
1572 | |
1573 // pp 221 | |
1574 | |
1575 void stbar() { emit_long( op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); } | |
1576 | |
1577 // pp 222 | |
1578 | |
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1579 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, RegisterOrConstant s2); |
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1580 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2); |
0 | 1581 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a); |
1582 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset = 0); | |
1583 | |
1584 inline void stfsr( Register s1, Register s2 ); | |
1585 inline void stfsr( Register s1, int simm13a); | |
1586 inline void stxfsr( Register s1, Register s2 ); | |
1587 inline void stxfsr( Register s1, int simm13a); | |
1588 | |
1589 // pp 224 | |
1590 | |
1591 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1592 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1593 | |
1594 // p 226 | |
1595 | |
1596 inline void stb( Register d, Register s1, Register s2 ); | |
1597 inline void stb( Register d, Register s1, int simm13a); | |
1598 inline void sth( Register d, Register s1, Register s2 ); | |
1599 inline void sth( Register d, Register s1, int simm13a); | |
1600 inline void stw( Register d, Register s1, Register s2 ); | |
1601 inline void stw( Register d, Register s1, int simm13a); | |
1602 inline void st( Register d, Register s1, Register s2 ); | |
1603 inline void st( Register d, Register s1, int simm13a); | |
1604 inline void stx( Register d, Register s1, Register s2 ); | |
1605 inline void stx( Register d, Register s1, int simm13a); | |
1606 inline void std( Register d, Register s1, Register s2 ); | |
1607 inline void std( Register d, Register s1, int simm13a); | |
1608 | |
727 | 1609 #ifdef ASSERT |
1610 // ByteSize is only a class when ASSERT is defined, otherwise it's an int. | |
1611 inline void st( Register d, Register s1, ByteSize simm13a); | |
1612 #endif | |
1613 | |
0 | 1614 inline void stb( Register d, const Address& a, int offset = 0 ); |
1615 inline void sth( Register d, const Address& a, int offset = 0 ); | |
1616 inline void stw( Register d, const Address& a, int offset = 0 ); | |
1617 inline void stx( Register d, const Address& a, int offset = 0 ); | |
1618 inline void st( Register d, const Address& a, int offset = 0 ); | |
1619 inline void std( Register d, const Address& a, int offset = 0 ); | |
1620 | |
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1621 inline void stb( Register d, Register s1, RegisterOrConstant s2 ); |
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1622 inline void sth( Register d, Register s1, RegisterOrConstant s2 ); |
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1623 inline void stw( Register d, Register s1, RegisterOrConstant s2 ); |
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1624 inline void stx( Register d, Register s1, RegisterOrConstant s2 ); |
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1625 inline void std( Register d, Register s1, RegisterOrConstant s2 ); |
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1626 inline void st( Register d, Register s1, RegisterOrConstant s2 ); |
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1627 |
0 | 1628 // pp 177 |
1629 | |
1630 void stba( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1631 void stba( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1632 void stha( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1633 void stha( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1634 void stwa( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1635 void stwa( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1636 void stxa( Register d, Register s1, Register s2, int ia ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1637 void stxa( Register d, Register s1, int simm13a ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1638 void stda( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1639 void stda( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1640 | |
1641 // pp 97 (v8) | |
1642 | |
1643 inline void stc( int crd, Register s1, Register s2 ); | |
1644 inline void stc( int crd, Register s1, int simm13a); | |
1645 inline void stdc( int crd, Register s1, Register s2 ); | |
1646 inline void stdc( int crd, Register s1, int simm13a); | |
1647 inline void stcsr( int crd, Register s1, Register s2 ); | |
1648 inline void stcsr( int crd, Register s1, int simm13a); | |
1649 inline void stdcq( int crd, Register s1, Register s2 ); | |
1650 inline void stdcq( int crd, Register s1, int simm13a); | |
1651 | |
1652 // pp 230 | |
1653 | |
1654 void sub( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | rs2(s2) ); } | |
1655 void sub( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
2008 | 1656 |
1657 // Note: offset is added to s2. | |
1658 inline void sub(Register s1, RegisterOrConstant s2, Register d, int offset = 0); | |
1659 | |
0 | 1660 void subcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); } |
1661 void subcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1662 void subc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | rs2(s2) ); } | |
1663 void subc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1664 void subccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1665 void subccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1666 | |
1667 // pp 231 | |
1668 | |
1669 inline void swap( Register s1, Register s2, Register d ); | |
1670 inline void swap( Register s1, int simm13a, Register d); | |
1671 inline void swap( Address& a, Register d, int offset = 0 ); | |
1672 | |
1673 // pp 232 | |
1674 | |
1675 void swapa( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1676 void swapa( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1677 | |
1678 // pp 234, note op in book is wrong, see pp 268 | |
1679 | |
1680 void taddcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | rs2(s2) ); } | |
1681 void taddcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1682 void taddcctv( Register s1, Register s2, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | rs2(s2) ); } | |
1683 void taddcctv( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1684 | |
1685 // pp 235 | |
1686 | |
1687 void tsubcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | rs2(s2) ); } | |
1688 void tsubcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1689 void tsubcctv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | rs2(s2) ); } | |
1690 void tsubcctv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1691 | |
1692 // pp 237 | |
1693 | |
1694 void trap( Condition c, CC cc, Register s1, Register s2 ) { v8_no_cc(cc); emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); } | |
1695 void trap( Condition c, CC cc, Register s1, int trapa ) { v8_no_cc(cc); emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); } | |
1696 // simple uncond. trap | |
1697 void trap( int trapa ) { trap( always, icc, G0, trapa ); } | |
1698 | |
1699 // pp 239 omit write priv register for now | |
1700 | |
1701 inline void wry( Register d) { v9_dep(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); } | |
1702 inline void wrccr(Register s) { v9_only(); emit_long( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); } | |
1703 inline void wrccr(Register s, int simm13a) { v9_only(); emit_long( op(arith_op) | | |
1704 rs1(s) | | |
1705 op3(wrreg_op3) | | |
1706 u_field(2, 29, 25) | | |
1707 u_field(1, 13, 13) | | |
1708 simm(simm13a, 13)); } | |
1709 inline void wrasi( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); } | |
1710 inline void wrfprs( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); } | |
1711 | |
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1712 // For a given register condition, return the appropriate condition code |
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1713 // Condition (the one you would use to get the same effect after "tst" on |
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1714 // the target register.) |
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1715 Assembler::Condition reg_cond_to_cc_cond(RCondition in); |
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1716 |
0 | 1717 |
1718 // Creation | |
1719 Assembler(CodeBuffer* code) : AbstractAssembler(code) { | |
1720 #ifdef CHECK_DELAY | |
1721 delay_state = no_delay; | |
1722 #endif | |
1723 } | |
1724 | |
1725 // Testing | |
1726 #ifndef PRODUCT | |
1727 void test_v9(); | |
1728 void test_v8_onlys(); | |
1729 #endif | |
1730 }; | |
1731 | |
1732 | |
1733 class RegistersForDebugging : public StackObj { | |
1734 public: | |
1735 intptr_t i[8], l[8], o[8], g[8]; | |
1736 float f[32]; | |
1737 double d[32]; | |
1738 | |
1739 void print(outputStream* s); | |
1740 | |
1741 static int i_offset(int j) { return offset_of(RegistersForDebugging, i[j]); } | |
1742 static int l_offset(int j) { return offset_of(RegistersForDebugging, l[j]); } | |
1743 static int o_offset(int j) { return offset_of(RegistersForDebugging, o[j]); } | |
1744 static int g_offset(int j) { return offset_of(RegistersForDebugging, g[j]); } | |
1745 static int f_offset(int j) { return offset_of(RegistersForDebugging, f[j]); } | |
1746 static int d_offset(int j) { return offset_of(RegistersForDebugging, d[j / 2]); } | |
1747 | |
1748 // gen asm code to save regs | |
1749 static void save_registers(MacroAssembler* a); | |
1750 | |
1751 // restore global registers in case C code disturbed them | |
1752 static void restore_registers(MacroAssembler* a, Register r); | |
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1753 |
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1754 |
0 | 1755 }; |
1756 | |
1757 | |
1758 // MacroAssembler extends Assembler by a few frequently used macros. | |
1759 // | |
1760 // Most of the standard SPARC synthetic ops are defined here. | |
1761 // Instructions for which a 'better' code sequence exists depending | |
1762 // on arguments should also go in here. | |
1763 | |
1764 #define JMP2(r1, r2) jmp(r1, r2, __FILE__, __LINE__) | |
1765 #define JMP(r1, off) jmp(r1, off, __FILE__, __LINE__) | |
727 | 1766 #define JUMP(a, temp, off) jump(a, temp, off, __FILE__, __LINE__) |
1767 #define JUMPL(a, temp, d, off) jumpl(a, temp, d, off, __FILE__, __LINE__) | |
0 | 1768 |
1769 | |
1770 class MacroAssembler: public Assembler { | |
1771 protected: | |
1772 // Support for VM calls | |
1773 // This is the base routine called by the different versions of call_VM_leaf. The interpreter | |
1774 // may customize this version by overriding it for its purposes (e.g., to save/restore | |
1775 // additional registers when doing a VM call). | |
1776 #ifdef CC_INTERP | |
1777 #define VIRTUAL | |
1778 #else | |
1779 #define VIRTUAL virtual | |
1780 #endif | |
1781 | |
1782 VIRTUAL void call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments); | |
1783 | |
1784 // | |
1785 // It is imperative that all calls into the VM are handled via the call_VM macros. | |
1786 // They make sure that the stack linkage is setup correctly. call_VM's correspond | |
1787 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. | |
1788 // | |
1789 // This is the base routine called by the different versions of call_VM. The interpreter | |
1790 // may customize this version by overriding it for its purposes (e.g., to save/restore | |
1791 // additional registers when doing a VM call). | |
1792 // | |
1793 // A non-volatile java_thread_cache register should be specified so | |
1794 // that the G2_thread value can be preserved across the call. | |
1795 // (If java_thread_cache is noreg, then a slow get_thread call | |
1796 // will re-initialize the G2_thread.) call_VM_base returns the register that contains the | |
1797 // thread. | |
1798 // | |
1799 // If no last_java_sp is specified (noreg) than SP will be used instead. | |
1800 | |
1801 virtual void call_VM_base( | |
1802 Register oop_result, // where an oop-result ends up if any; use noreg otherwise | |
1803 Register java_thread_cache, // the thread if computed before ; use noreg otherwise | |
1804 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise | |
1805 address entry_point, // the entry point | |
1806 int number_of_arguments, // the number of arguments (w/o thread) to pop after call | |
1807 bool check_exception=true // flag which indicates if exception should be checked | |
1808 ); | |
1809 | |
1810 // This routine should emit JVMTI PopFrame and ForceEarlyReturn handling code. | |
1811 // The implementation is only non-empty for the InterpreterMacroAssembler, | |
1812 // as only the interpreter handles and ForceEarlyReturn PopFrame requests. | |
1813 virtual void check_and_handle_popframe(Register scratch_reg); | |
1814 virtual void check_and_handle_earlyret(Register scratch_reg); | |
1815 | |
1816 public: | |
1817 MacroAssembler(CodeBuffer* code) : Assembler(code) {} | |
1818 | |
1819 // Support for NULL-checks | |
1820 // | |
1821 // Generates code that causes a NULL OS exception if the content of reg is NULL. | |
1822 // If the accessed location is M[reg + offset] and the offset is known, provide the | |
1823 // offset. No explicit code generation is needed if the offset is within a certain | |
1824 // range (0 <= offset <= page_size). | |
1825 // | |
1826 // %%%%%% Currently not done for SPARC | |
1827 | |
1828 void null_check(Register reg, int offset = -1); | |
1829 static bool needs_explicit_null_check(intptr_t offset); | |
1830 | |
1831 // support for delayed instructions | |
1832 MacroAssembler* delayed() { Assembler::delayed(); return this; } | |
1833 | |
1834 // branches that use right instruction for v8 vs. v9 | |
1835 inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); | |
1836 inline void br( Condition c, bool a, Predict p, Label& L ); | |
2002 | 1837 |
0 | 1838 inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); |
1839 inline void fb( Condition c, bool a, Predict p, Label& L ); | |
1840 | |
1841 // compares register with zero and branches (V9 and V8 instructions) | |
1842 void br_zero( Condition c, bool a, Predict p, Register s1, Label& L); | |
1843 // Compares a pointer register with zero and branches on (not)null. | |
1844 // Does a test & branch on 32-bit systems and a register-branch on 64-bit. | |
1845 void br_null ( Register s1, bool a, Predict p, Label& L ); | |
1846 void br_notnull( Register s1, bool a, Predict p, Label& L ); | |
1847 | |
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1848 // These versions will do the most efficient thing on v8 and v9. Perhaps |
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1849 // this is what the routine above was meant to do, but it didn't (and |
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1850 // didn't cover both target address kinds.) |
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1851 void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none ); |
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1852 void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, Label& L); |
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1853 |
0 | 1854 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); |
1855 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L ); | |
1856 | |
1857 // Branch that tests xcc in LP64 and icc in !LP64 | |
1858 inline void brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); | |
1859 inline void brx( Condition c, bool a, Predict p, Label& L ); | |
1860 | |
1861 // unconditional short branch | |
1862 inline void ba( bool a, Label& L ); | |
1863 | |
1864 // Branch that tests fp condition codes | |
1865 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); | |
1866 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L ); | |
1867 | |
1868 // get PC the best way | |
1869 inline int get_pc( Register d ); | |
1870 | |
1871 // Sparc shorthands(pp 85, V8 manual, pp 289 V9 manual) | |
1872 inline void cmp( Register s1, Register s2 ) { subcc( s1, s2, G0 ); } | |
1873 inline void cmp( Register s1, int simm13a ) { subcc( s1, simm13a, G0 ); } | |
1874 | |
1875 inline void jmp( Register s1, Register s2 ); | |
1876 inline void jmp( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() ); | |
1877 | |
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1878 // Check if the call target is out of wdisp30 range (relative to the code cache) |
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1879 static inline bool is_far_target(address d); |
0 | 1880 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type ); |
1881 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type ); | |
1882 inline void callr( Register s1, Register s2 ); | |
1883 inline void callr( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() ); | |
1884 | |
1885 // Emits nothing on V8 | |
1886 inline void iprefetch( address d, relocInfo::relocType rt = relocInfo::none ); | |
1887 inline void iprefetch( Label& L); | |
1888 | |
1889 inline void tst( Register s ) { orcc( G0, s, G0 ); } | |
1890 | |
1891 #ifdef PRODUCT | |
1892 inline void ret( bool trace = TraceJumps ) { if (trace) { | |
1893 mov(I7, O7); // traceable register | |
1894 JMP(O7, 2 * BytesPerInstWord); | |
1895 } else { | |
1896 jmpl( I7, 2 * BytesPerInstWord, G0 ); | |
1897 } | |
1898 } | |
1899 | |
1900 inline void retl( bool trace = TraceJumps ) { if (trace) JMP(O7, 2 * BytesPerInstWord); | |
1901 else jmpl( O7, 2 * BytesPerInstWord, G0 ); } | |
1902 #else | |
1903 void ret( bool trace = TraceJumps ); | |
1904 void retl( bool trace = TraceJumps ); | |
1905 #endif /* PRODUCT */ | |
1906 | |
1907 // Required platform-specific helpers for Label::patch_instructions. | |
1908 // They _shadow_ the declarations in AbstractAssembler, which are undefined. | |
1909 void pd_patch_instruction(address branch, address target); | |
1910 #ifndef PRODUCT | |
1911 static void pd_print_patched_instruction(address branch); | |
1912 #endif | |
1913 | |
1914 // sethi Macro handles optimizations and relocations | |
727 | 1915 private: |
1916 void internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable); | |
1917 public: | |
1918 void sethi(const AddressLiteral& addrlit, Register d); | |
1919 void patchable_sethi(const AddressLiteral& addrlit, Register d); | |
0 | 1920 |
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1921 // compute the number of instructions for a sethi/set |
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1922 static int insts_for_sethi( address a, bool worst_case = false ); |
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1923 static int worst_case_insts_for_set(); |
0 | 1924 |
1925 // set may be either setsw or setuw (high 32 bits may be zero or sign) | |
727 | 1926 private: |
1927 void internal_set(const AddressLiteral& al, Register d, bool ForceRelocatable); | |
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1928 static int insts_for_internal_set(intptr_t value); |
727 | 1929 public: |
1930 void set(const AddressLiteral& addrlit, Register d); | |
1931 void set(intptr_t value, Register d); | |
1932 void set(address addr, Register d, RelocationHolder const& rspec); | |
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1933 static int insts_for_set(intptr_t value) { return insts_for_internal_set(value); } |
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1934 |
727 | 1935 void patchable_set(const AddressLiteral& addrlit, Register d); |
1936 void patchable_set(intptr_t value, Register d); | |
1937 void set64(jlong value, Register d, Register tmp); | |
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1938 static int insts_for_set64(jlong value); |
2008 | 1939 |
0 | 1940 // sign-extend 32 to 64 |
1941 inline void signx( Register s, Register d ) { sra( s, G0, d); } | |
1942 inline void signx( Register d ) { sra( d, G0, d); } | |
1943 | |
1944 inline void not1( Register s, Register d ) { xnor( s, G0, d ); } | |
1945 inline void not1( Register d ) { xnor( d, G0, d ); } | |
1946 | |
1947 inline void neg( Register s, Register d ) { sub( G0, s, d ); } | |
1948 inline void neg( Register d ) { sub( G0, d, d ); } | |
1949 | |
1950 inline void cas( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY); } | |
1951 inline void casx( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY); } | |
1952 // Functions for isolating 64 bit atomic swaps for LP64 | |
1953 // cas_ptr will perform cas for 32 bit VM's and casx for 64 bit VM's | |
1954 inline void cas_ptr( Register s1, Register s2, Register d) { | |
1955 #ifdef _LP64 | |
1956 casx( s1, s2, d ); | |
1957 #else | |
1958 cas( s1, s2, d ); | |
1959 #endif | |
1960 } | |
1961 | |
1962 // Functions for isolating 64 bit shifts for LP64 | |
1963 inline void sll_ptr( Register s1, Register s2, Register d ); | |
1964 inline void sll_ptr( Register s1, int imm6a, Register d ); | |
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1965 inline void sll_ptr( Register s1, RegisterOrConstant s2, Register d ); |
0 | 1966 inline void srl_ptr( Register s1, Register s2, Register d ); |
1967 inline void srl_ptr( Register s1, int imm6a, Register d ); | |
1968 | |
1969 // little-endian | |
1970 inline void casl( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY_LITTLE); } | |
1971 inline void casxl( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY_LITTLE); } | |
1972 | |
1973 inline void inc( Register d, int const13 = 1 ) { add( d, const13, d); } | |
1974 inline void inccc( Register d, int const13 = 1 ) { addcc( d, const13, d); } | |
1975 | |
1976 inline void dec( Register d, int const13 = 1 ) { sub( d, const13, d); } | |
1977 inline void deccc( Register d, int const13 = 1 ) { subcc( d, const13, d); } | |
1978 | |
1979 inline void btst( Register s1, Register s2 ) { andcc( s1, s2, G0 ); } | |
1980 inline void btst( int simm13a, Register s ) { andcc( s, simm13a, G0 ); } | |
1981 | |
1982 inline void bset( Register s1, Register s2 ) { or3( s1, s2, s2 ); } | |
1983 inline void bset( int simm13a, Register s ) { or3( s, simm13a, s ); } | |
1984 | |
1985 inline void bclr( Register s1, Register s2 ) { andn( s1, s2, s2 ); } | |
1986 inline void bclr( int simm13a, Register s ) { andn( s, simm13a, s ); } | |
1987 | |
1988 inline void btog( Register s1, Register s2 ) { xor3( s1, s2, s2 ); } | |
1989 inline void btog( int simm13a, Register s ) { xor3( s, simm13a, s ); } | |
1990 | |
1991 inline void clr( Register d ) { or3( G0, G0, d ); } | |
1992 | |
1993 inline void clrb( Register s1, Register s2); | |
1994 inline void clrh( Register s1, Register s2); | |
1995 inline void clr( Register s1, Register s2); | |
1996 inline void clrx( Register s1, Register s2); | |
1997 | |
1998 inline void clrb( Register s1, int simm13a); | |
1999 inline void clrh( Register s1, int simm13a); | |
2000 inline void clr( Register s1, int simm13a); | |
2001 inline void clrx( Register s1, int simm13a); | |
2002 | |
2003 // copy & clear upper word | |
2004 inline void clruw( Register s, Register d ) { srl( s, G0, d); } | |
2005 // clear upper word | |
2006 inline void clruwu( Register d ) { srl( d, G0, d); } | |
2007 | |
2008 // membar psuedo instruction. takes into account target memory model. | |
2009 inline void membar( Assembler::Membar_mask_bits const7a ); | |
2010 | |
2011 // returns if membar generates anything. | |
2012 inline bool membar_has_effect( Assembler::Membar_mask_bits const7a ); | |
2013 | |
2014 // mov pseudo instructions | |
2015 inline void mov( Register s, Register d) { | |
2016 if ( s != d ) or3( G0, s, d); | |
2017 else assert_not_delayed(); // Put something useful in the delay slot! | |
2018 } | |
2019 | |
2020 inline void mov_or_nop( Register s, Register d) { | |
2021 if ( s != d ) or3( G0, s, d); | |
2022 else nop(); | |
2023 } | |
2024 | |
2025 inline void mov( int simm13a, Register d) { or3( G0, simm13a, d); } | |
2026 | |
2027 // address pseudos: make these names unlike instruction names to avoid confusion | |
2028 inline intptr_t load_pc_address( Register reg, int bytes_to_skip ); | |
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2029 inline void load_contents(const AddressLiteral& addrlit, Register d, int offset = 0); |
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2030 inline void load_ptr_contents(const AddressLiteral& addrlit, Register d, int offset = 0); |
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2031 inline void store_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0); |
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2032 inline void store_ptr_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0); |
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2033 inline void jumpl_to(const AddressLiteral& addrlit, Register temp, Register d, int offset = 0); |
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2034 inline void jump_to(const AddressLiteral& addrlit, Register temp, int offset = 0); |
727 | 2035 inline void jump_indirect_to(Address& a, Register temp, int ld_offset = 0, int jmp_offset = 0); |
0 | 2036 |
2037 // ring buffer traceable jumps | |
2038 | |
2039 void jmp2( Register r1, Register r2, const char* file, int line ); | |
2040 void jmp ( Register r1, int offset, const char* file, int line ); | |
2041 | |
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2042 void jumpl(const AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line); |
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2043 void jump (const AddressLiteral& addrlit, Register temp, int offset, const char* file, int line); |
0 | 2044 |
2045 | |
2046 // argument pseudos: | |
2047 | |
2048 inline void load_argument( Argument& a, Register d ); | |
2049 inline void store_argument( Register s, Argument& a ); | |
2050 inline void store_ptr_argument( Register s, Argument& a ); | |
2051 inline void store_float_argument( FloatRegister s, Argument& a ); | |
2052 inline void store_double_argument( FloatRegister s, Argument& a ); | |
2053 inline void store_long_argument( Register s, Argument& a ); | |
2054 | |
2055 // handy macros: | |
2056 | |
2057 inline void round_to( Register r, int modulus ) { | |
2058 assert_not_delayed(); | |
2059 inc( r, modulus - 1 ); | |
2060 and3( r, -modulus, r ); | |
2061 } | |
2062 | |
2063 // -------------------------------------------------- | |
2064 | |
2065 // Functions for isolating 64 bit loads for LP64 | |
2066 // ld_ptr will perform ld for 32 bit VM's and ldx for 64 bit VM's | |
2067 // st_ptr will perform st for 32 bit VM's and stx for 64 bit VM's | |
727 | 2068 inline void ld_ptr(Register s1, Register s2, Register d); |
2069 inline void ld_ptr(Register s1, int simm13a, Register d); | |
2070 inline void ld_ptr(Register s1, RegisterOrConstant s2, Register d); | |
2071 inline void ld_ptr(const Address& a, Register d, int offset = 0); | |
2072 inline void st_ptr(Register d, Register s1, Register s2); | |
2073 inline void st_ptr(Register d, Register s1, int simm13a); | |
2074 inline void st_ptr(Register d, Register s1, RegisterOrConstant s2); | |
2075 inline void st_ptr(Register d, const Address& a, int offset = 0); | |
2076 | |
2077 #ifdef ASSERT | |
2078 // ByteSize is only a class when ASSERT is defined, otherwise it's an int. | |
2079 inline void ld_ptr(Register s1, ByteSize simm13a, Register d); | |
2080 inline void st_ptr(Register d, Register s1, ByteSize simm13a); | |
2081 #endif | |
0 | 2082 |
1503 | 2083 // ld_long will perform ldd for 32 bit VM's and ldx for 64 bit VM's |
2084 // st_long will perform std for 32 bit VM's and stx for 64 bit VM's | |
727 | 2085 inline void ld_long(Register s1, Register s2, Register d); |
2086 inline void ld_long(Register s1, int simm13a, Register d); | |
2087 inline void ld_long(Register s1, RegisterOrConstant s2, Register d); | |
2088 inline void ld_long(const Address& a, Register d, int offset = 0); | |
2089 inline void st_long(Register d, Register s1, Register s2); | |
2090 inline void st_long(Register d, Register s1, int simm13a); | |
2091 inline void st_long(Register d, Register s1, RegisterOrConstant s2); | |
2092 inline void st_long(Register d, const Address& a, int offset = 0); | |
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2093 |
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2094 // Helpers for address formation. |
1503 | 2095 // - They emit only a move if s2 is a constant zero. |
2096 // - If dest is a constant and either s1 or s2 is a register, the temp argument is required and becomes the result. | |
2097 // - If dest is a register and either s1 or s2 is a non-simm13 constant, the temp argument is required and used to materialize the constant. | |
2098 RegisterOrConstant regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg); | |
2099 RegisterOrConstant regcon_inc_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg); | |
2100 RegisterOrConstant regcon_sll_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg); | |
2101 | |
2102 RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant src, Register temp) { | |
2103 if (is_simm13(src.constant_or_zero())) | |
2104 return src; // register or short constant | |
2105 guarantee(temp != noreg, "constant offset overflow"); | |
2106 set(src.as_constant(), temp); | |
2107 return temp; | |
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2108 } |
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2109 |
0 | 2110 // -------------------------------------------------- |
2111 | |
2112 public: | |
2113 // traps as per trap.h (SPARC ABI?) | |
2114 | |
2115 void breakpoint_trap(); | |
2116 void breakpoint_trap(Condition c, CC cc = icc); | |
2117 void flush_windows_trap(); | |
2118 void clean_windows_trap(); | |
2119 void get_psr_trap(); | |
2120 void set_psr_trap(); | |
2121 | |
2122 // V8/V9 flush_windows | |
2123 void flush_windows(); | |
2124 | |
2125 // Support for serializing memory accesses between threads | |
2126 void serialize_memory(Register thread, Register tmp1, Register tmp2); | |
2127 | |
2128 // Stack frame creation/removal | |
2129 void enter(); | |
2130 void leave(); | |
2131 | |
2132 // V8/V9 integer multiply | |
2133 void mult(Register s1, Register s2, Register d); | |
2134 void mult(Register s1, int simm13a, Register d); | |
2135 | |
2136 // V8/V9 read and write of condition codes. | |
2137 void read_ccr(Register d); | |
2138 void write_ccr(Register s); | |
2139 | |
2140 // Manipulation of C++ bools | |
2141 // These are idioms to flag the need for care with accessing bools but on | |
2142 // this platform we assume byte size | |
2143 | |
727 | 2144 inline void stbool(Register d, const Address& a) { stb(d, a); } |
2145 inline void ldbool(const Address& a, Register d) { ldsb(a, d); } | |
0 | 2146 inline void tstbool( Register s ) { tst(s); } |
2147 inline void movbool( bool boolconst, Register d) { mov( (int) boolconst, d); } | |
2148 | |
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2149 // klass oop manipulations if compressed |
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2150 void load_klass(Register src_oop, Register klass); |
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2151 void store_klass(Register klass, Register dst_oop); |
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2152 void store_klass_gap(Register s, Register dst_oop); |
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2153 |
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2154 // oop manipulations |
727 | 2155 void load_heap_oop(const Address& s, Register d); |
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2156 void load_heap_oop(Register s1, Register s2, Register d); |
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2157 void load_heap_oop(Register s1, int simm13a, Register d); |
1846 | 2158 void load_heap_oop(Register s1, RegisterOrConstant s2, Register d); |
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2159 void store_heap_oop(Register d, Register s1, Register s2); |
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2160 void store_heap_oop(Register d, Register s1, int simm13a); |
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2161 void store_heap_oop(Register d, const Address& a, int offset = 0); |
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2162 |
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2163 void encode_heap_oop(Register src, Register dst); |
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2164 void encode_heap_oop(Register r) { |
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2165 encode_heap_oop(r, r); |
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2166 } |
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2167 void decode_heap_oop(Register src, Register dst); |
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2168 void decode_heap_oop(Register r) { |
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2169 decode_heap_oop(r, r); |
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2170 } |
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2171 void encode_heap_oop_not_null(Register r); |
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2172 void decode_heap_oop_not_null(Register r); |
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2173 void encode_heap_oop_not_null(Register src, Register dst); |
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2174 void decode_heap_oop_not_null(Register src, Register dst); |
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2175 |
0 | 2176 // Support for managing the JavaThread pointer (i.e.; the reference to |
2177 // thread-local information). | |
2178 void get_thread(); // load G2_thread | |
2179 void verify_thread(); // verify G2_thread contents | |
2180 void save_thread (const Register threache); // save to cache | |
2181 void restore_thread(const Register thread_cache); // restore from cache | |
2182 | |
2183 // Support for last Java frame (but use call_VM instead where possible) | |
2184 void set_last_Java_frame(Register last_java_sp, Register last_Java_pc); | |
2185 void reset_last_Java_frame(void); | |
2186 | |
2187 // Call into the VM. | |
2188 // Passes the thread pointer (in O0) as a prepended argument. | |
2189 // Makes sure oop return values are visible to the GC. | |
2190 void call_VM(Register oop_result, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); | |
2191 void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true); | |
2192 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); | |
2193 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); | |
2194 | |
2195 // these overloadings are not presently used on SPARC: | |
2196 void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); | |
2197 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); | |
2198 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); | |
2199 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); | |
2200 | |
2201 void call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments = 0); | |
2202 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1); | |
2203 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2); | |
2204 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3); | |
2205 | |
2206 void get_vm_result (Register oop_result); | |
2207 void get_vm_result_2(Register oop_result); | |
2208 | |
2209 // vm result is currently getting hijacked to for oop preservation | |
2210 void set_vm_result(Register oop_result); | |
2211 | |
2212 // if call_VM_base was called with check_exceptions=false, then call | |
2213 // check_and_forward_exception to handle exceptions when it is safe | |
2214 void check_and_forward_exception(Register scratch_reg); | |
2215 | |
2216 private: | |
2217 // For V8 | |
2218 void read_ccr_trap(Register ccr_save); | |
2219 void write_ccr_trap(Register ccr_save1, Register scratch1, Register scratch2); | |
2220 | |
2221 #ifdef ASSERT | |
2222 // For V8 debugging. Uses V8 instruction sequence and checks | |
2223 // result with V9 insturctions rdccr and wrccr. | |
2224 // Uses Gscatch and Gscatch2 | |
2225 void read_ccr_v8_assert(Register ccr_save); | |
2226 void write_ccr_v8_assert(Register ccr_save); | |
2227 #endif // ASSERT | |
2228 | |
2229 public: | |
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2230 |
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2231 // Write to card table for - register is destroyed afterwards. |
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2232 void card_table_write(jbyte* byte_map_base, Register tmp, Register obj); |
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2233 |
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2234 void card_write_barrier_post(Register store_addr, Register new_val, Register tmp); |
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2235 |
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2236 #ifndef SERIALGC |
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2237 // General G1 pre-barrier generator. |
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2238 void g1_write_barrier_pre(Register obj, Register index, int offset, Register pre_val, Register tmp, bool preserve_o_regs); |
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2239 |
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2240 // General G1 post-barrier generator |
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2241 void g1_write_barrier_post(Register store_addr, Register new_val, Register tmp); |
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2242 #endif // SERIALGC |
0 | 2243 |
2244 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack | |
2245 void push_fTOS(); | |
2246 | |
2247 // pops double TOS element from CPU stack and pushes on FPU stack | |
2248 void pop_fTOS(); | |
2249 | |
2250 void empty_FPU_stack(); | |
2251 | |
2252 void push_IU_state(); | |
2253 void pop_IU_state(); | |
2254 | |
2255 void push_FPU_state(); | |
2256 void pop_FPU_state(); | |
2257 | |
2258 void push_CPU_state(); | |
2259 void pop_CPU_state(); | |
2260 | |
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2261 // if heap base register is used - reinit it with the correct value |
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2262 void reinit_heapbase(); |
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2263 |
0 | 2264 // Debugging |
2265 void _verify_oop(Register reg, const char * msg, const char * file, int line); | |
2266 void _verify_oop_addr(Address addr, const char * msg, const char * file, int line); | |
2267 | |
2268 #define verify_oop(reg) _verify_oop(reg, "broken oop " #reg, __FILE__, __LINE__) | |
2269 #define verify_oop_addr(addr) _verify_oop_addr(addr, "broken oop addr ", __FILE__, __LINE__) | |
2270 | |
2271 // only if +VerifyOops | |
2272 void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); | |
2273 // only if +VerifyFPU | |
2274 void stop(const char* msg); // prints msg, dumps registers and stops execution | |
2275 void warn(const char* msg); // prints msg, but don't stop | |
2276 void untested(const char* what = ""); | |
1846 | 2277 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); } |
0 | 2278 void should_not_reach_here() { stop("should not reach here"); } |
2279 void print_CPU_state(); | |
2280 | |
2281 // oops in code | |
727 | 2282 AddressLiteral allocate_oop_address(jobject obj); // allocate_index |
2283 AddressLiteral constant_oop_address(jobject obj); // find_index | |
2284 inline void set_oop (jobject obj, Register d); // uses allocate_oop_address | |
2285 inline void set_oop_constant (jobject obj, Register d); // uses constant_oop_address | |
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2286 inline void set_oop (const AddressLiteral& obj_addr, Register d); // same as load_address |
0 | 2287 |
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2288 void set_narrow_oop( jobject obj, Register d ); |
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2289 |
0 | 2290 // nop padding |
2291 void align(int modulus); | |
2292 | |
2293 // declare a safepoint | |
2294 void safepoint(); | |
2295 | |
2296 // factor out part of stop into subroutine to save space | |
2297 void stop_subroutine(); | |
2298 // factor out part of verify_oop into subroutine to save space | |
2299 void verify_oop_subroutine(); | |
2300 | |
2301 // side-door communication with signalHandler in os_solaris.cpp | |
2302 static address _verify_oop_implicit_branch[3]; | |
2303 | |
2304 #ifndef PRODUCT | |
2305 static void test(); | |
2306 #endif | |
2307 | |
2308 // convert an incoming arglist to varargs format; put the pointer in d | |
2309 void set_varargs( Argument a, Register d ); | |
2310 | |
2311 int total_frame_size_in_bytes(int extraWords); | |
2312 | |
2313 // used when extraWords known statically | |
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2314 void save_frame(int extraWords = 0); |
0 | 2315 void save_frame_c1(int size_in_bytes); |
2316 // make a frame, and simultaneously pass up one or two register value | |
2317 // into the new register window | |
2318 void save_frame_and_mov(int extraWords, Register s1, Register d1, Register s2 = Register(), Register d2 = Register()); | |
2319 | |
2320 // give no. (outgoing) params, calc # of words will need on frame | |
2321 void calc_mem_param_words(Register Rparam_words, Register Rresult); | |
2322 | |
2323 // used to calculate frame size dynamically | |
2324 // result is in bytes and must be negated for save inst | |
2325 void calc_frame_size(Register extraWords, Register resultReg); | |
2326 | |
2327 // calc and also save | |
2328 void calc_frame_size_and_save(Register extraWords, Register resultReg); | |
2329 | |
2330 static void debug(char* msg, RegistersForDebugging* outWindow); | |
2331 | |
2332 // implementations of bytecodes used by both interpreter and compiler | |
2333 | |
2334 void lcmp( Register Ra_hi, Register Ra_low, | |
2335 Register Rb_hi, Register Rb_low, | |
2336 Register Rresult); | |
2337 | |
2338 void lneg( Register Rhi, Register Rlow ); | |
2339 | |
2340 void lshl( Register Rin_high, Register Rin_low, Register Rcount, | |
2341 Register Rout_high, Register Rout_low, Register Rtemp ); | |
2342 | |
2343 void lshr( Register Rin_high, Register Rin_low, Register Rcount, | |
2344 Register Rout_high, Register Rout_low, Register Rtemp ); | |
2345 | |
2346 void lushr( Register Rin_high, Register Rin_low, Register Rcount, | |
2347 Register Rout_high, Register Rout_low, Register Rtemp ); | |
2348 | |
2349 #ifdef _LP64 | |
2350 void lcmp( Register Ra, Register Rb, Register Rresult); | |
2351 #endif | |
2352 | |
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2353 // Load and store values by size and signed-ness |
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2354 void load_sized_value( Address src, Register dst, size_t size_in_bytes, bool is_signed); |
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2355 void store_sized_value(Register src, Address dst, size_t size_in_bytes); |
1503 | 2356 |
0 | 2357 void float_cmp( bool is_float, int unordered_result, |
2358 FloatRegister Fa, FloatRegister Fb, | |
2359 Register Rresult); | |
2360 | |
2361 void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); | |
2362 void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { Assembler::fneg(w, sd); } | |
2363 void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); | |
2364 void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); | |
2365 | |
2366 void save_all_globals_into_locals(); | |
2367 void restore_globals_from_locals(); | |
2368 | |
2369 void casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, | |
2370 address lock_addr=0, bool use_call_vm=false); | |
2371 void cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, | |
2372 address lock_addr=0, bool use_call_vm=false); | |
2373 void casn (Register addr_reg, Register cmp_reg, Register set_reg) ; | |
2374 | |
2375 // These set the icc condition code to equal if the lock succeeded | |
2376 // and notEqual if it failed and requires a slow case | |
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2377 void compiler_lock_object(Register Roop, Register Rmark, Register Rbox, |
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2378 Register Rscratch, |
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2379 BiasedLockingCounters* counters = NULL, |
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2380 bool try_bias = UseBiasedLocking); |
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2381 void compiler_unlock_object(Register Roop, Register Rmark, Register Rbox, |
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2382 Register Rscratch, |
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2383 bool try_bias = UseBiasedLocking); |
0 | 2384 |
2385 // Biased locking support | |
2386 // Upon entry, lock_reg must point to the lock record on the stack, | |
2387 // obj_reg must contain the target object, and mark_reg must contain | |
2388 // the target object's header. | |
2389 // Destroys mark_reg if an attempt is made to bias an anonymously | |
2390 // biased lock. In this case a failure will go either to the slow | |
2391 // case or fall through with the notEqual condition code set with | |
2392 // the expectation that the slow case in the runtime will be called. | |
2393 // In the fall-through case where the CAS-based lock is done, | |
2394 // mark_reg is not destroyed. | |
2395 void biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg, | |
2396 Label& done, Label* slow_case = NULL, | |
2397 BiasedLockingCounters* counters = NULL); | |
2398 // Upon entry, the base register of mark_addr must contain the oop. | |
2399 // Destroys temp_reg. | |
2400 | |
2401 // If allow_delay_slot_filling is set to true, the next instruction | |
2402 // emitted after this one will go in an annulled delay slot if the | |
2403 // biased locking exit case failed. | |
2404 void biased_locking_exit(Address mark_addr, Register temp_reg, Label& done, bool allow_delay_slot_filling = false); | |
2405 | |
2406 // allocation | |
2407 void eden_allocate( | |
2408 Register obj, // result: pointer to object after successful allocation | |
2409 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise | |
2410 int con_size_in_bytes, // object size in bytes if known at compile time | |
2411 Register t1, // temp register | |
2412 Register t2, // temp register | |
2413 Label& slow_case // continuation point if fast allocation fails | |
2414 ); | |
2415 void tlab_allocate( | |
2416 Register obj, // result: pointer to object after successful allocation | |
2417 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise | |
2418 int con_size_in_bytes, // object size in bytes if known at compile time | |
2419 Register t1, // temp register | |
2420 Label& slow_case // continuation point if fast allocation fails | |
2421 ); | |
2422 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); | |
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2423 void incr_allocated_bytes(RegisterOrConstant size_in_bytes, |
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2424 Register t1, Register t2); |
0 | 2425 |
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2426 // interface method calling |
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2427 void lookup_interface_method(Register recv_klass, |
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2428 Register intf_klass, |
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2429 RegisterOrConstant itable_index, |
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2430 Register method_result, |
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2431 Register temp_reg, Register temp2_reg, |
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2432 Label& no_such_interface); |
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2433 |
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2434 // Test sub_klass against super_klass, with fast and slow paths. |
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2435 |
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2436 // The fast path produces a tri-state answer: yes / no / maybe-slow. |
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2437 // One of the three labels can be NULL, meaning take the fall-through. |
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2438 // If super_check_offset is -1, the value is loaded up from super_klass. |
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2439 // No registers are killed, except temp_reg and temp2_reg. |
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2440 // If super_check_offset is not -1, temp2_reg is not used and can be noreg. |
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2441 void check_klass_subtype_fast_path(Register sub_klass, |
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2442 Register super_klass, |
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2443 Register temp_reg, |
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2444 Register temp2_reg, |
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2445 Label* L_success, |
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2446 Label* L_failure, |
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2447 Label* L_slow_path, |
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2448 RegisterOrConstant super_check_offset = RegisterOrConstant(-1), |
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2449 Register instanceof_hack = noreg); |
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2450 |
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2451 // The rest of the type check; must be wired to a corresponding fast path. |
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2452 // It does not repeat the fast path logic, so don't use it standalone. |
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2453 // The temp_reg can be noreg, if no temps are available. |
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2454 // It can also be sub_klass or super_klass, meaning it's OK to kill that one. |
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2455 // Updates the sub's secondary super cache as necessary. |
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2456 void check_klass_subtype_slow_path(Register sub_klass, |
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2457 Register super_klass, |
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2458 Register temp_reg, |
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2459 Register temp2_reg, |
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2460 Register temp3_reg, |
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2461 Register temp4_reg, |
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2462 Label* L_success, |
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2463 Label* L_failure); |
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2464 |
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2465 // Simplified, combined version, good for typical uses. |
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2466 // Falls through on failure. |
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2467 void check_klass_subtype(Register sub_klass, |
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2468 Register super_klass, |
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2469 Register temp_reg, |
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2470 Register temp2_reg, |
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2471 Label& L_success); |
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2472 |
710 | 2473 // method handles (JSR 292) |
2474 void check_method_handle_type(Register mtype_reg, Register mh_reg, | |
2475 Register temp_reg, | |
2476 Label& wrong_method_type); | |
1503 | 2477 void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg, |
2478 Register temp_reg); | |
2479 void jump_to_method_handle_entry(Register mh_reg, Register temp_reg, bool emit_delayed_nop = true); | |
710 | 2480 // offset relative to Gargs of argument at tos[arg_slot]. |
2481 // (arg_slot == 0 means the last argument, not the first). | |
2482 RegisterOrConstant argument_offset(RegisterOrConstant arg_slot, | |
3442
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2483 Register temp_reg, |
710 | 2484 int extra_slot_offset = 0); |
1503 | 2485 // Address of Gargs and argument_offset. |
2486 Address argument_address(RegisterOrConstant arg_slot, | |
3442
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2487 Register temp_reg, |
1503 | 2488 int extra_slot_offset = 0); |
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2489 |
0 | 2490 // Stack overflow checking |
2491 | |
2492 // Note: this clobbers G3_scratch | |
2493 void bang_stack_with_offset(int offset) { | |
2494 // stack grows down, caller passes positive offset | |
2495 assert(offset > 0, "must bang with negative offset"); | |
2496 set((-offset)+STACK_BIAS, G3_scratch); | |
2497 st(G0, SP, G3_scratch); | |
2498 } | |
2499 | |
2500 // Writes to stack successive pages until offset reached to check for | |
2501 // stack overflow + shadow pages. Clobbers tsp and scratch registers. | |
2502 void bang_stack_size(Register Rsize, Register Rtsp, Register Rscratch); | |
2503 | |
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2504 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, Register tmp, int offset); |
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2505 |
0 | 2506 void verify_tlab(); |
2507 | |
2508 Condition negate_condition(Condition cond); | |
2509 | |
2510 // Helper functions for statistics gathering. | |
2511 // Conditionally (non-atomically) increments passed counter address, preserving condition codes. | |
2512 void cond_inc(Condition cond, address counter_addr, Register Rtemp1, Register Rtemp2); | |
2513 // Unconditional increment. | |
727 | 2514 void inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2); |
2515 void inc_counter(int* counter_addr, Register Rtmp1, Register Rtmp2); | |
0 | 2516 |
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2517 // Compare char[] arrays aligned to 4 bytes. |
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2518 void char_arrays_equals(Register ary1, Register ary2, |
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2519 Register limit, Register result, |
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2520 Register chr1, Register chr2, Label& Ldone); |
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2521 |
0 | 2522 #undef VIRTUAL |
2523 | |
2524 }; | |
2525 | |
2526 /** | |
2527 * class SkipIfEqual: | |
2528 * | |
2529 * Instantiating this class will result in assembly code being output that will | |
2530 * jump around any code emitted between the creation of the instance and it's | |
2531 * automatic destruction at the end of a scope block, depending on the value of | |
2532 * the flag passed to the constructor, which will be checked at run-time. | |
2533 */ | |
2534 class SkipIfEqual : public StackObj { | |
2535 private: | |
2536 MacroAssembler* _masm; | |
2537 Label _label; | |
2538 | |
2539 public: | |
2540 // 'temp' is a temp register that this object can use (and trash) | |
2541 SkipIfEqual(MacroAssembler*, Register temp, | |
2542 const bool* flag_addr, Assembler::Condition condition); | |
2543 ~SkipIfEqual(); | |
2544 }; | |
2545 | |
2546 #ifdef ASSERT | |
2547 // On RISC, there's no benefit to verifying instruction boundaries. | |
2548 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; } | |
2549 #endif | |
1972 | 2550 |
2551 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP |