annotate src/cpu/sparc/vm/c1_LIRAssembler_sparc.hpp @ 113:ba764ed4b6f2

6420645: Create a vm that uses compressed oops for up to 32gb heapsizes Summary: Compressed oops in instances, arrays, and headers. Code contributors are coleenp, phh, never, swamyv Reviewed-by: jmasa, kamg, acorn, tbell, kvn, rasbold
author coleenp
date Sun, 13 Apr 2008 17:43:42 -0400
parents a61af66fc99e
children c18cbe5936b8
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1 /*
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2 * Copyright 2000-2006 Sun Microsystems, Inc. All Rights Reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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20 * CA 95054 USA or visit www.sun.com if you need additional information or
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21 * have any questions.
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22 *
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23 */
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24
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25 private:
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26
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27 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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28 //
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29 // Sparc load/store emission
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30 //
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31 // The sparc ld/st instructions cannot accomodate displacements > 13 bits long.
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32 // The following "pseudo" sparc instructions (load/store) make it easier to use the indexed addressing mode
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33 // by allowing 32 bit displacements:
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34 //
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35 // When disp <= 13 bits long, a single load or store instruction is emitted with (disp + [d]).
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36 // When disp > 13 bits long, code is emitted to set the displacement into the O7 register,
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37 // and then a load or store is emitted with ([O7] + [d]).
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38 //
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39
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40 // some load/store variants return the code_offset for proper positioning of debug info for null checks
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41
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42 // load/store with 32 bit displacement
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43 int load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo* info = NULL);
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44 void store(Register value, Register base, int offset, BasicType type, CodeEmitInfo *info = NULL);
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45
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46 // loadf/storef with 32 bit displacement
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47 void load(Register s, int disp, FloatRegister d, BasicType ld_type, CodeEmitInfo* info = NULL);
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48 void store(FloatRegister d, Register s1, int disp, BasicType st_type, CodeEmitInfo* info = NULL);
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49
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50 // convienence methods for calling load/store with an Address
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51 void load(const Address& a, Register d, BasicType ld_type, CodeEmitInfo* info = NULL, int offset = 0);
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52 void store(Register d, const Address& a, BasicType st_type, CodeEmitInfo* info = NULL, int offset = 0);
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53 void load(const Address& a, FloatRegister d, BasicType ld_type, CodeEmitInfo* info = NULL, int offset = 0);
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54 void store(FloatRegister d, const Address& a, BasicType st_type, CodeEmitInfo* info = NULL, int offset = 0);
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55
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56 // convienence methods for calling load/store with an LIR_Address
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57 void load(LIR_Address* a, Register d, BasicType ld_type, CodeEmitInfo* info = NULL);
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58 void store(Register d, LIR_Address* a, BasicType st_type, CodeEmitInfo* info = NULL);
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59 void load(LIR_Address* a, FloatRegister d, BasicType ld_type, CodeEmitInfo* info = NULL);
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60 void store(FloatRegister d, LIR_Address* a, BasicType st_type, CodeEmitInfo* info = NULL);
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61
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62 int store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool unaligned = false);
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63 int store(LIR_Opr from_reg, Register base, Register disp, BasicType type);
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64
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65 int load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool unaligned = false);
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66 int load(Register base, Register disp, LIR_Opr to_reg, BasicType type);
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67
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68 void monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no);
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69
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70 int shift_amount(BasicType t);
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71
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72 static bool is_single_instruction(LIR_Op* op);
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73
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74 public:
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75 void pack64( Register rs, Register rd );
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76 void unpack64( Register rd );
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77
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78 enum {
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79 #ifdef _LP64
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80 call_stub_size = 68,
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81 #else
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82 call_stub_size = 20,
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83 #endif // _LP64
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84 exception_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(10*4),
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85 deopt_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(10*4) };