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1 /*
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2 * Copyright 1997-2007 Sun Microsystems, Inc. All Rights Reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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20 * CA 95054 USA or visit www.sun.com if you need additional information or
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21 * have any questions.
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22 *
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23 */
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24
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25 // We have interface for the following instructions:
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26 // - NativeInstruction
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27 // - - NativeCall
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28 // - - NativeFarCall
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29 // - - NativeMovConstReg
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30 // - - NativeMovConstRegPatching
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31 // - - NativeMovRegMem
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32 // - - NativeMovRegMemPatching
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33 // - - NativeJump
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34 // - - NativeGeneralJump
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35 // - - NativeIllegalInstruction
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36 // The base class for different kinds of native instruction abstractions.
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37 // Provides the primitive operations to manipulate code relative to this.
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38 class NativeInstruction VALUE_OBJ_CLASS_SPEC {
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39 friend class Relocation;
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40
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41 public:
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42 enum Sparc_specific_constants {
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43 nop_instruction_size = 4
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44 };
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45
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46 bool is_nop() { return long_at(0) == nop_instruction(); }
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47 bool is_call() { return is_op(long_at(0), Assembler::call_op); }
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48 bool is_sethi() { return (is_op2(long_at(0), Assembler::sethi_op2)
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49 && inv_rd(long_at(0)) != G0); }
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50
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51 bool sets_cc() {
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52 // conservative (returns true for some instructions that do not set the
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53 // the condition code, such as, "save".
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54 // Does not return true for the deprecated tagged instructions, such as, TADDcc
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55 int x = long_at(0);
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56 return (is_op(x, Assembler::arith_op) &&
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57 (inv_op3(x) & Assembler::cc_bit_op3) == Assembler::cc_bit_op3);
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58 }
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59 bool is_illegal();
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60 bool is_zombie() {
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61 int x = long_at(0);
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62 return is_op3(x,
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63 VM_Version::v9_instructions_work() ?
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64 Assembler::ldsw_op3 : Assembler::lduw_op3,
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65 Assembler::ldst_op)
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66 && Assembler::inv_rs1(x) == G0
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67 && Assembler::inv_rd(x) == O7;
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68 }
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69 bool is_ic_miss_trap(); // Inline-cache uses a trap to detect a miss
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70 bool is_return() {
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71 // is it the output of MacroAssembler::ret or MacroAssembler::retl?
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72 int x = long_at(0);
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73 const int pc_return_offset = 8; // see frame_sparc.hpp
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74 return is_op3(x, Assembler::jmpl_op3, Assembler::arith_op)
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75 && (inv_rs1(x) == I7 || inv_rs1(x) == O7)
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76 && inv_immed(x) && inv_simm(x, 13) == pc_return_offset
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77 && inv_rd(x) == G0;
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78 }
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79 bool is_int_jump() {
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80 // is it the output of MacroAssembler::b?
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81 int x = long_at(0);
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82 return is_op2(x, Assembler::bp_op2) || is_op2(x, Assembler::br_op2);
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83 }
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84 bool is_float_jump() {
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85 // is it the output of MacroAssembler::fb?
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86 int x = long_at(0);
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87 return is_op2(x, Assembler::fbp_op2) || is_op2(x, Assembler::fb_op2);
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88 }
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89 bool is_jump() {
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90 return is_int_jump() || is_float_jump();
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91 }
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92 bool is_cond_jump() {
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93 int x = long_at(0);
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94 return (is_int_jump() && Assembler::inv_cond(x) != Assembler::always) ||
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95 (is_float_jump() && Assembler::inv_cond(x) != Assembler::f_always);
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96 }
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97
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98 bool is_stack_bang() {
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99 int x = long_at(0);
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100 return is_op3(x, Assembler::stw_op3, Assembler::ldst_op) &&
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101 (inv_rd(x) == G0) && (inv_rs1(x) == SP) && (inv_rs2(x) == G3_scratch);
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102 }
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103
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104 bool is_prefetch() {
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105 int x = long_at(0);
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106 return is_op3(x, Assembler::prefetch_op3, Assembler::ldst_op);
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107 }
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108
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109 bool is_membar() {
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110 int x = long_at(0);
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111 return is_op3(x, Assembler::membar_op3, Assembler::arith_op) &&
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112 (inv_rd(x) == G0) && (inv_rs1(x) == O7);
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113 }
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114
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115 bool is_safepoint_poll() {
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116 int x = long_at(0);
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117 #ifdef _LP64
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118 return is_op3(x, Assembler::ldx_op3, Assembler::ldst_op) &&
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119 #else
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120 return is_op3(x, Assembler::lduw_op3, Assembler::ldst_op) &&
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121 #endif
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122 (inv_rd(x) == G0) && (inv_immed(x) ? Assembler::inv_simm13(x) == 0 : inv_rs2(x) == G0);
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123 }
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124
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125 bool is_zero_test(Register ®);
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126 bool is_load_store_with_small_offset(Register reg);
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127
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128 public:
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129 #ifdef ASSERT
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130 static int rdpc_instruction() { return Assembler::op(Assembler::arith_op ) | Assembler::op3(Assembler::rdreg_op3) | Assembler::u_field(5, 18, 14) | Assembler::rd(O7); }
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131 #else
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132 // Temporary fix: in optimized mode, u_field is a macro for efficiency reasons (see Assembler::u_field) - needs to be fixed
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133 static int rdpc_instruction() { return Assembler::op(Assembler::arith_op ) | Assembler::op3(Assembler::rdreg_op3) | u_field(5, 18, 14) | Assembler::rd(O7); }
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134 #endif
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135 static int nop_instruction() { return Assembler::op(Assembler::branch_op) | Assembler::op2(Assembler::sethi_op2); }
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136 static int illegal_instruction(); // the output of __ breakpoint_trap()
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137 static int call_instruction(address destination, address pc) { return Assembler::op(Assembler::call_op) | Assembler::wdisp((intptr_t)destination, (intptr_t)pc, 30); }
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138
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139 static int branch_instruction(Assembler::op2s op2val, Assembler::Condition c, bool a) {
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140 return Assembler::op(Assembler::branch_op) | Assembler::op2(op2val) | Assembler::annul(a) | Assembler::cond(c);
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141 }
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142
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143 static int op3_instruction(Assembler::ops opval, Register rd, Assembler::op3s op3val, Register rs1, int simm13a) {
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144 return Assembler::op(opval) | Assembler::rd(rd) | Assembler::op3(op3val) | Assembler::rs1(rs1) | Assembler::immed(true) | Assembler::simm(simm13a, 13);
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145 }
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146
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147 static int sethi_instruction(Register rd, int imm22a) {
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148 return Assembler::op(Assembler::branch_op) | Assembler::rd(rd) | Assembler::op2(Assembler::sethi_op2) | Assembler::hi22(imm22a);
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149 }
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150
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151 protected:
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152 address addr_at(int offset) const { return address(this) + offset; }
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153 int long_at(int offset) const { return *(int*)addr_at(offset); }
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154 void set_long_at(int offset, int i); /* deals with I-cache */
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155 void set_jlong_at(int offset, jlong i); /* deals with I-cache */
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156 void set_addr_at(int offset, address x); /* deals with I-cache */
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157
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158 address instruction_address() const { return addr_at(0); }
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159 address next_instruction_address() const { return addr_at(BytesPerInstWord); }
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160
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161 static bool is_op( int x, Assembler::ops opval) {
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162 return Assembler::inv_op(x) == opval;
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163 }
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164 static bool is_op2(int x, Assembler::op2s op2val) {
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165 return Assembler::inv_op(x) == Assembler::branch_op && Assembler::inv_op2(x) == op2val;
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166 }
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167 static bool is_op3(int x, Assembler::op3s op3val, Assembler::ops opval) {
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168 return Assembler::inv_op(x) == opval && Assembler::inv_op3(x) == op3val;
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169 }
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170
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171 // utilities to help subclasses decode:
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172 static Register inv_rd( int x ) { return Assembler::inv_rd( x); }
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173 static Register inv_rs1( int x ) { return Assembler::inv_rs1(x); }
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174 static Register inv_rs2( int x ) { return Assembler::inv_rs2(x); }
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175
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176 static bool inv_immed( int x ) { return Assembler::inv_immed(x); }
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177 static bool inv_annul( int x ) { return (Assembler::annul(true) & x) != 0; }
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178 static int inv_cond( int x ) { return Assembler::inv_cond(x); }
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179
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180 static int inv_op( int x ) { return Assembler::inv_op( x); }
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181 static int inv_op2( int x ) { return Assembler::inv_op2(x); }
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182 static int inv_op3( int x ) { return Assembler::inv_op3(x); }
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183
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184 static int inv_simm( int x, int nbits ) { return Assembler::inv_simm(x, nbits); }
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185 static intptr_t inv_wdisp( int x, int nbits ) { return Assembler::inv_wdisp( x, 0, nbits); }
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186 static intptr_t inv_wdisp16( int x ) { return Assembler::inv_wdisp16(x, 0); }
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187 static int branch_destination_offset(int x) { return Assembler::branch_destination(x, 0); }
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188 static int patch_branch_destination_offset(int dest_offset, int x) {
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189 return Assembler::patched_branch(dest_offset, x, 0);
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190 }
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191 void set_annul_bit() { set_long_at(0, long_at(0) | Assembler::annul(true)); }
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192
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193 // utility for checking if x is either of 2 small constants
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194 static bool is_either(int x, int k1, int k2) {
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195 // return x == k1 || x == k2;
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196 return (1 << x) & (1 << k1 | 1 << k2);
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197 }
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198
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199 // utility for checking overflow of signed instruction fields
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200 static bool fits_in_simm(int x, int nbits) {
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201 // cf. Assembler::assert_signed_range()
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202 // return -(1 << nbits-1) <= x && x < ( 1 << nbits-1),
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203 return (unsigned)(x + (1 << nbits-1)) < (unsigned)(1 << nbits);
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204 }
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205
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206 // set a signed immediate field
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207 static int set_simm(int insn, int imm, int nbits) {
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208 return (insn &~ Assembler::simm(-1, nbits)) | Assembler::simm(imm, nbits);
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209 }
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210
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211 // set a wdisp field (disp should be the difference of two addresses)
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212 static int set_wdisp(int insn, intptr_t disp, int nbits) {
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213 return (insn &~ Assembler::wdisp((intptr_t)-4, (intptr_t)0, nbits)) | Assembler::wdisp(disp, 0, nbits);
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214 }
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215
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216 static int set_wdisp16(int insn, intptr_t disp) {
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217 return (insn &~ Assembler::wdisp16((intptr_t)-4, 0)) | Assembler::wdisp16(disp, 0);
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218 }
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219
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220 // get a simm13 field from an arithmetic or memory instruction
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221 static int get_simm13(int insn) {
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222 assert(is_either(Assembler::inv_op(insn),
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223 Assembler::arith_op, Assembler::ldst_op) &&
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224 (insn & Assembler::immed(true)), "must have a simm13 field");
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225 return Assembler::inv_simm(insn, 13);
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226 }
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227
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228 // set the simm13 field of an arithmetic or memory instruction
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229 static bool set_simm13(int insn, int imm) {
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230 get_simm13(insn); // tickle the assertion check
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231 return set_simm(insn, imm, 13);
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232 }
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233
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234 // combine the fields of a sethi stream (7 instructions ) and an add, jmp or ld/st
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235 static intptr_t data64( address pc, int arith_insn ) {
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236 assert(is_op2(*(unsigned int *)pc, Assembler::sethi_op2), "must be sethi");
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237 intptr_t hi = (intptr_t)gethi( (unsigned int *)pc );
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238 intptr_t lo = (intptr_t)get_simm13(arith_insn);
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239 assert((unsigned)lo < (1 << 10), "offset field of set_oop must be 10 bits");
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240 return hi | lo;
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241 }
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242
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243 // Regenerate the instruction sequence that performs the 64 bit
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244 // sethi. This only does the sethi. The disp field (bottom 10 bits)
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245 // must be handled seperately.
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246 static void set_data64_sethi(address instaddr, intptr_t x);
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247
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248 // combine the fields of a sethi/simm13 pair (simm13 = or, add, jmpl, ld/st)
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249 static int data32(int sethi_insn, int arith_insn) {
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250 assert(is_op2(sethi_insn, Assembler::sethi_op2), "must be sethi");
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251 int hi = Assembler::inv_hi22(sethi_insn);
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252 int lo = get_simm13(arith_insn);
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253 assert((unsigned)lo < (1 << 10), "offset field of set_oop must be 10 bits");
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254 return hi | lo;
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255 }
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256
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257 static int set_data32_sethi(int sethi_insn, int imm) {
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258 // note that Assembler::hi22 clips the low 10 bits for us
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259 assert(is_op2(sethi_insn, Assembler::sethi_op2), "must be sethi");
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260 return (sethi_insn &~ Assembler::hi22(-1)) | Assembler::hi22(imm);
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261 }
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262
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263 static int set_data32_simm13(int arith_insn, int imm) {
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264 get_simm13(arith_insn); // tickle the assertion check
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265 int imm10 = Assembler::low10(imm);
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266 return (arith_insn &~ Assembler::simm(-1, 13)) | Assembler::simm(imm10, 13);
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267 }
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268
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269 static int low10(int imm) {
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270 return Assembler::low10(imm);
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271 }
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272
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273 // Perform the inverse of the LP64 Macroassembler::sethi
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274 // routine. Extracts the 54 bits of address from the instruction
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275 // stream. This routine must agree with the sethi routine in
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276 // assembler_inline_sparc.hpp
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277 static address gethi( unsigned int *pc ) {
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278 int i = 0;
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279 uintptr_t adr;
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280 // We first start out with the real sethi instruction
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281 assert(is_op2(*pc, Assembler::sethi_op2), "in gethi - must be sethi");
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282 adr = (unsigned int)Assembler::inv_hi22( *(pc++) );
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283 i++;
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284 while ( i < 7 ) {
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285 // We're done if we hit a nop
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286 if ( (int)*pc == nop_instruction() ) break;
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287 assert ( Assembler::inv_op(*pc) == Assembler::arith_op, "in gethi - must be arith_op" );
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288 switch ( Assembler::inv_op3(*pc) ) {
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289 case Assembler::xor_op3:
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290 adr ^= (intptr_t)get_simm13( *pc );
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291 return ( (address)adr );
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292 break;
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293 case Assembler::sll_op3:
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294 adr <<= ( *pc & 0x3f );
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295 break;
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296 case Assembler::or_op3:
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297 adr |= (intptr_t)get_simm13( *pc );
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298 break;
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299 default:
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300 assert ( 0, "in gethi - Should not reach here" );
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301 break;
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302 }
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303 pc++;
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304 i++;
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305 }
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306 return ( (address)adr );
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307 }
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308
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309 public:
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310 void verify();
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311 void print();
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312
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313 // unit test stuff
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314 static void test() {} // override for testing
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315
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316 inline friend NativeInstruction* nativeInstruction_at(address address);
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317 };
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318
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319 inline NativeInstruction* nativeInstruction_at(address address) {
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320 NativeInstruction* inst = (NativeInstruction*)address;
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321 #ifdef ASSERT
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322 inst->verify();
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323 #endif
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324 return inst;
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325 }
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326
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327
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328
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329 //-----------------------------------------------------------------------------
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330
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331 // The NativeCall is an abstraction for accessing/manipulating native call imm32 instructions.
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332 // (used to manipulate inline caches, primitive & dll calls, etc.)
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333 inline NativeCall* nativeCall_at(address instr);
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334 inline NativeCall* nativeCall_overwriting_at(address instr,
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335 address destination);
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336 inline NativeCall* nativeCall_before(address return_address);
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337 class NativeCall: public NativeInstruction {
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338 public:
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339 enum Sparc_specific_constants {
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340 instruction_size = 8,
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341 return_address_offset = 8,
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342 call_displacement_width = 30,
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343 displacement_offset = 0,
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344 instruction_offset = 0
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345 };
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346 address instruction_address() const { return addr_at(0); }
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347 address next_instruction_address() const { return addr_at(instruction_size); }
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348 address return_address() const { return addr_at(return_address_offset); }
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349
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350 address destination() const { return inv_wdisp(long_at(0), call_displacement_width) + instruction_address(); }
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351 address displacement_address() const { return addr_at(displacement_offset); }
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352 void set_destination(address dest) { set_long_at(0, set_wdisp(long_at(0), dest - instruction_address(), call_displacement_width)); }
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353 void set_destination_mt_safe(address dest);
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354
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355 void verify_alignment() {} // do nothing on sparc
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356 void verify();
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357 void print();
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358
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359 // unit test stuff
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360 static void test();
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361
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362 // Creation
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363 friend inline NativeCall* nativeCall_at(address instr);
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364 friend NativeCall* nativeCall_overwriting_at(address instr, address destination = NULL) {
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365 // insert a "blank" call:
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366 NativeCall* call = (NativeCall*)instr;
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367 call->set_long_at(0 * BytesPerInstWord, call_instruction(destination, instr));
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368 call->set_long_at(1 * BytesPerInstWord, nop_instruction());
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369 assert(call->addr_at(2 * BytesPerInstWord) - instr == instruction_size, "instruction size");
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370 // check its structure now:
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371 assert(nativeCall_at(instr)->destination() == destination, "correct call destination");
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372 return call;
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373 }
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374
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375 friend inline NativeCall* nativeCall_before(address return_address) {
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376 NativeCall* call = (NativeCall*)(return_address - return_address_offset);
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377 #ifdef ASSERT
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378 call->verify();
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379 #endif
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380 return call;
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381 }
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382
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383 static bool is_call_at(address instr) {
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384 return nativeInstruction_at(instr)->is_call();
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385 }
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386
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387 static bool is_call_before(address instr) {
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388 return nativeInstruction_at(instr - return_address_offset)->is_call();
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389 }
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390
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391 static bool is_call_to(address instr, address target) {
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392 return nativeInstruction_at(instr)->is_call() &&
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393 nativeCall_at(instr)->destination() == target;
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394 }
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395
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396 // MT-safe patching of a call instruction.
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397 static void insert(address code_pos, address entry) {
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398 (void)nativeCall_overwriting_at(code_pos, entry);
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399 }
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400
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401 static void replace_mt_safe(address instr_addr, address code_buffer);
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402 };
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403 inline NativeCall* nativeCall_at(address instr) {
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404 NativeCall* call = (NativeCall*)instr;
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405 #ifdef ASSERT
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406 call->verify();
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|
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407 #endif
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408 return call;
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|
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409 }
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410
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411 // The NativeFarCall is an abstraction for accessing/manipulating native call-anywhere
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412 // instructions in the sparcv9 vm. Used to call native methods which may be loaded
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413 // anywhere in the address space, possibly out of reach of a call instruction.
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414
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|
|
415 #ifndef _LP64
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416
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417 // On 32-bit systems, a far call is the same as a near one.
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418 class NativeFarCall;
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419 inline NativeFarCall* nativeFarCall_at(address instr);
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420 class NativeFarCall : public NativeCall {
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421 public:
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422 friend inline NativeFarCall* nativeFarCall_at(address instr) { return (NativeFarCall*)nativeCall_at(instr); }
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423 friend NativeFarCall* nativeFarCall_overwriting_at(address instr, address destination = NULL)
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424 { return (NativeFarCall*)nativeCall_overwriting_at(instr, destination); }
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|
425 friend NativeFarCall* nativeFarCall_before(address return_address)
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426 { return (NativeFarCall*)nativeCall_before(return_address); }
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|
427 };
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|
|
428
|
|
|
429 #else
|
|
|
430
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|
|
431 // The format of this extended-range call is:
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|
|
432 // jumpl_to addr, lreg
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|
|
433 // == sethi %hi54(addr), O7 ; jumpl O7, %lo10(addr), O7 ; <delay>
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|
434 // That is, it is essentially the same as a NativeJump.
|
|
|
435 class NativeFarCall;
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|
|
436 inline NativeFarCall* nativeFarCall_overwriting_at(address instr, address destination);
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|
|
437 inline NativeFarCall* nativeFarCall_at(address instr);
|
|
|
438 class NativeFarCall: public NativeInstruction {
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|
439 public:
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|
|
440 enum Sparc_specific_constants {
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|
|
441 // instruction_size includes the delay slot instruction.
|
|
|
442 instruction_size = 9 * BytesPerInstWord,
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|
|
443 return_address_offset = 9 * BytesPerInstWord,
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|
|
444 jmpl_offset = 7 * BytesPerInstWord,
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|
|
445 displacement_offset = 0,
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|
|
446 instruction_offset = 0
|
|
|
447 };
|
|
|
448 address instruction_address() const { return addr_at(0); }
|
|
|
449 address next_instruction_address() const { return addr_at(instruction_size); }
|
|
|
450 address return_address() const { return addr_at(return_address_offset); }
|
|
|
451
|
|
|
452 address destination() const {
|
|
|
453 return (address) data64(addr_at(0), long_at(jmpl_offset));
|
|
|
454 }
|
|
|
455 address displacement_address() const { return addr_at(displacement_offset); }
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|
|
456 void set_destination(address dest);
|
|
|
457
|
|
|
458 bool destination_is_compiled_verified_entry_point();
|
|
|
459
|
|
|
460 void verify();
|
|
|
461 void print();
|
|
|
462
|
|
|
463 // unit test stuff
|
|
|
464 static void test();
|
|
|
465
|
|
|
466 // Creation
|
|
|
467 friend inline NativeFarCall* nativeFarCall_at(address instr) {
|
|
|
468 NativeFarCall* call = (NativeFarCall*)instr;
|
|
|
469 #ifdef ASSERT
|
|
|
470 call->verify();
|
|
|
471 #endif
|
|
|
472 return call;
|
|
|
473 }
|
|
|
474
|
|
|
475 friend inline NativeFarCall* nativeFarCall_overwriting_at(address instr, address destination = NULL) {
|
|
|
476 Unimplemented();
|
|
|
477 NativeFarCall* call = (NativeFarCall*)instr;
|
|
|
478 return call;
|
|
|
479 }
|
|
|
480
|
|
|
481 friend NativeFarCall* nativeFarCall_before(address return_address) {
|
|
|
482 NativeFarCall* call = (NativeFarCall*)(return_address - return_address_offset);
|
|
|
483 #ifdef ASSERT
|
|
|
484 call->verify();
|
|
|
485 #endif
|
|
|
486 return call;
|
|
|
487 }
|
|
|
488
|
|
|
489 static bool is_call_at(address instr);
|
|
|
490
|
|
|
491 // MT-safe patching of a call instruction.
|
|
|
492 static void insert(address code_pos, address entry) {
|
|
|
493 (void)nativeFarCall_overwriting_at(code_pos, entry);
|
|
|
494 }
|
|
|
495 static void replace_mt_safe(address instr_addr, address code_buffer);
|
|
|
496 };
|
|
|
497
|
|
|
498 #endif // _LP64
|
|
|
499
|
|
|
500 // An interface for accessing/manipulating native set_oop imm, reg instructions.
|
|
|
501 // (used to manipulate inlined data references, etc.)
|
|
|
502 // set_oop imm, reg
|
|
|
503 // == sethi %hi22(imm), reg ; add reg, %lo10(imm), reg
|
|
|
504 class NativeMovConstReg;
|
|
|
505 inline NativeMovConstReg* nativeMovConstReg_at(address address);
|
|
|
506 class NativeMovConstReg: public NativeInstruction {
|
|
|
507 public:
|
|
|
508 enum Sparc_specific_constants {
|
|
|
509 sethi_offset = 0,
|
|
|
510 #ifdef _LP64
|
|
|
511 add_offset = 7 * BytesPerInstWord,
|
|
|
512 instruction_size = 8 * BytesPerInstWord
|
|
|
513 #else
|
|
|
514 add_offset = 4,
|
|
|
515 instruction_size = 8
|
|
|
516 #endif
|
|
|
517 };
|
|
|
518
|
|
|
519 address instruction_address() const { return addr_at(0); }
|
|
|
520 address next_instruction_address() const { return addr_at(instruction_size); }
|
|
|
521
|
|
|
522 // (The [set_]data accessor respects oop_type relocs also.)
|
|
|
523 intptr_t data() const;
|
|
|
524 void set_data(intptr_t x);
|
|
|
525
|
|
|
526 // report the destination register
|
|
|
527 Register destination() { return inv_rd(long_at(sethi_offset)); }
|
|
|
528
|
|
|
529 void verify();
|
|
|
530 void print();
|
|
|
531
|
|
|
532 // unit test stuff
|
|
|
533 static void test();
|
|
|
534
|
|
|
535 // Creation
|
|
|
536 friend inline NativeMovConstReg* nativeMovConstReg_at(address address) {
|
|
|
537 NativeMovConstReg* test = (NativeMovConstReg*)address;
|
|
|
538 #ifdef ASSERT
|
|
|
539 test->verify();
|
|
|
540 #endif
|
|
|
541 return test;
|
|
|
542 }
|
|
|
543
|
|
|
544
|
|
|
545 friend NativeMovConstReg* nativeMovConstReg_before(address address) {
|
|
|
546 NativeMovConstReg* test = (NativeMovConstReg*)(address - instruction_size);
|
|
|
547 #ifdef ASSERT
|
|
|
548 test->verify();
|
|
|
549 #endif
|
|
|
550 return test;
|
|
|
551 }
|
|
|
552
|
|
|
553 };
|
|
|
554
|
|
|
555
|
|
|
556 // An interface for accessing/manipulating native set_oop imm, reg instructions.
|
|
|
557 // (used to manipulate inlined data references, etc.)
|
|
|
558 // set_oop imm, reg
|
|
|
559 // == sethi %hi22(imm), reg; nop; add reg, %lo10(imm), reg
|
|
|
560 //
|
|
|
561 // Note that it is identical to NativeMovConstReg with the exception of a nop between the
|
|
|
562 // sethi and the add. The nop is required to be in the delay slot of the call instruction
|
|
|
563 // which overwrites the sethi during patching.
|
|
|
564 class NativeMovConstRegPatching;
|
|
|
565 inline NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address);class NativeMovConstRegPatching: public NativeInstruction {
|
|
|
566 public:
|
|
|
567 enum Sparc_specific_constants {
|
|
|
568 sethi_offset = 0,
|
|
|
569 #ifdef _LP64
|
|
|
570 nop_offset = 7 * BytesPerInstWord,
|
|
|
571 #else
|
|
|
572 nop_offset = sethi_offset + BytesPerInstWord,
|
|
|
573 #endif
|
|
|
574 add_offset = nop_offset + BytesPerInstWord,
|
|
|
575 instruction_size = add_offset + BytesPerInstWord
|
|
|
576 };
|
|
|
577
|
|
|
578 address instruction_address() const { return addr_at(0); }
|
|
|
579 address next_instruction_address() const { return addr_at(instruction_size); }
|
|
|
580
|
|
|
581 // (The [set_]data accessor respects oop_type relocs also.)
|
|
|
582 int data() const;
|
|
|
583 void set_data(int x);
|
|
|
584
|
|
|
585 // report the destination register
|
|
|
586 Register destination() { return inv_rd(long_at(sethi_offset)); }
|
|
|
587
|
|
|
588 void verify();
|
|
|
589 void print();
|
|
|
590
|
|
|
591 // unit test stuff
|
|
|
592 static void test();
|
|
|
593
|
|
|
594 // Creation
|
|
|
595 friend inline NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) {
|
|
|
596 NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)address;
|
|
|
597 #ifdef ASSERT
|
|
|
598 test->verify();
|
|
|
599 #endif
|
|
|
600 return test;
|
|
|
601 }
|
|
|
602
|
|
|
603
|
|
|
604 friend NativeMovConstRegPatching* nativeMovConstRegPatching_before(address address) {
|
|
|
605 NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_size);
|
|
|
606 #ifdef ASSERT
|
|
|
607 test->verify();
|
|
|
608 #endif
|
|
|
609 return test;
|
|
|
610 }
|
|
|
611
|
|
|
612 };
|
|
|
613
|
|
|
614
|
|
|
615 // An interface for accessing/manipulating native memory ops
|
|
|
616 // ld* [reg + offset], reg
|
|
|
617 // st* reg, [reg + offset]
|
|
|
618 // sethi %hi(imm), reg; add reg, %lo(imm), reg; ld* [reg1 + reg], reg2
|
|
|
619 // sethi %hi(imm), reg; add reg, %lo(imm), reg; st* reg2, [reg1 + reg]
|
|
|
620 // Ops covered: {lds,ldu,st}{w,b,h}, {ld,st}{d,x}
|
|
|
621 //
|
|
|
622 class NativeMovRegMem;
|
|
|
623 inline NativeMovRegMem* nativeMovRegMem_at (address address);
|
|
|
624 class NativeMovRegMem: public NativeInstruction {
|
|
|
625 public:
|
|
|
626 enum Sparc_specific_constants {
|
|
|
627 op3_mask_ld = 1 << Assembler::lduw_op3 |
|
|
|
628 1 << Assembler::ldub_op3 |
|
|
|
629 1 << Assembler::lduh_op3 |
|
|
|
630 1 << Assembler::ldd_op3 |
|
|
|
631 1 << Assembler::ldsw_op3 |
|
|
|
632 1 << Assembler::ldsb_op3 |
|
|
|
633 1 << Assembler::ldsh_op3 |
|
|
|
634 1 << Assembler::ldx_op3,
|
|
|
635 op3_mask_st = 1 << Assembler::stw_op3 |
|
|
|
636 1 << Assembler::stb_op3 |
|
|
|
637 1 << Assembler::sth_op3 |
|
|
|
638 1 << Assembler::std_op3 |
|
|
|
639 1 << Assembler::stx_op3,
|
|
|
640 op3_ldst_int_limit = Assembler::ldf_op3,
|
|
|
641 op3_mask_ldf = 1 << (Assembler::ldf_op3 - op3_ldst_int_limit) |
|
|
|
642 1 << (Assembler::lddf_op3 - op3_ldst_int_limit),
|
|
|
643 op3_mask_stf = 1 << (Assembler::stf_op3 - op3_ldst_int_limit) |
|
|
|
644 1 << (Assembler::stdf_op3 - op3_ldst_int_limit),
|
|
|
645
|
|
|
646 offset_width = 13,
|
|
|
647 sethi_offset = 0,
|
|
|
648 #ifdef _LP64
|
|
|
649 add_offset = 7 * BytesPerInstWord,
|
|
|
650 #else
|
|
|
651 add_offset = 4,
|
|
|
652 #endif
|
|
|
653 ldst_offset = add_offset + BytesPerInstWord
|
|
|
654 };
|
|
|
655 bool is_immediate() const {
|
|
|
656 // check if instruction is ld* [reg + offset], reg or st* reg, [reg + offset]
|
|
|
657 int i0 = long_at(0);
|
|
|
658 return (is_op(i0, Assembler::ldst_op));
|
|
|
659 }
|
|
|
660
|
|
|
661 address instruction_address() const { return addr_at(0); }
|
|
|
662 address next_instruction_address() const {
|
|
|
663 #ifdef _LP64
|
|
|
664 return addr_at(is_immediate() ? 4 : (7 * BytesPerInstWord));
|
|
|
665 #else
|
|
|
666 return addr_at(is_immediate() ? 4 : 12);
|
|
|
667 #endif
|
|
|
668 }
|
|
|
669 intptr_t offset() const {
|
|
|
670 return is_immediate()? inv_simm(long_at(0), offset_width) :
|
|
|
671 nativeMovConstReg_at(addr_at(0))->data();
|
|
|
672 }
|
|
|
673 void set_offset(intptr_t x) {
|
|
|
674 if (is_immediate()) {
|
|
|
675 guarantee(fits_in_simm(x, offset_width), "data block offset overflow");
|
|
|
676 set_long_at(0, set_simm(long_at(0), x, offset_width));
|
|
|
677 } else
|
|
|
678 nativeMovConstReg_at(addr_at(0))->set_data(x);
|
|
|
679 }
|
|
|
680
|
|
|
681 void add_offset_in_bytes(intptr_t radd_offset) {
|
|
|
682 set_offset (offset() + radd_offset);
|
|
|
683 }
|
|
|
684
|
|
|
685 void copy_instruction_to(address new_instruction_address);
|
|
|
686
|
|
|
687 void verify();
|
|
|
688 void print ();
|
|
|
689
|
|
|
690 // unit test stuff
|
|
|
691 static void test();
|
|
|
692
|
|
|
693 private:
|
|
|
694 friend inline NativeMovRegMem* nativeMovRegMem_at (address address) {
|
|
|
695 NativeMovRegMem* test = (NativeMovRegMem*)address;
|
|
|
696 #ifdef ASSERT
|
|
|
697 test->verify();
|
|
|
698 #endif
|
|
|
699 return test;
|
|
|
700 }
|
|
|
701 };
|
|
|
702
|
|
|
703
|
|
|
704 // An interface for accessing/manipulating native memory ops
|
|
|
705 // ld* [reg + offset], reg
|
|
|
706 // st* reg, [reg + offset]
|
|
|
707 // sethi %hi(imm), reg; nop; add reg, %lo(imm), reg; ld* [reg1 + reg], reg2
|
|
|
708 // sethi %hi(imm), reg; nop; add reg, %lo(imm), reg; st* reg2, [reg1 + reg]
|
|
|
709 // Ops covered: {lds,ldu,st}{w,b,h}, {ld,st}{d,x}
|
|
|
710 //
|
|
|
711 // Note that it is identical to NativeMovRegMem with the exception of a nop between the
|
|
|
712 // sethi and the add. The nop is required to be in the delay slot of the call instruction
|
|
|
713 // which overwrites the sethi during patching.
|
|
|
714 class NativeMovRegMemPatching;
|
|
|
715 inline NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address);
|
|
|
716 class NativeMovRegMemPatching: public NativeInstruction {
|
|
|
717 public:
|
|
|
718 enum Sparc_specific_constants {
|
|
|
719 op3_mask_ld = 1 << Assembler::lduw_op3 |
|
|
|
720 1 << Assembler::ldub_op3 |
|
|
|
721 1 << Assembler::lduh_op3 |
|
|
|
722 1 << Assembler::ldd_op3 |
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|
|
723 1 << Assembler::ldsw_op3 |
|
|
|
724 1 << Assembler::ldsb_op3 |
|
|
|
725 1 << Assembler::ldsh_op3 |
|
|
|
726 1 << Assembler::ldx_op3,
|
|
|
727 op3_mask_st = 1 << Assembler::stw_op3 |
|
|
|
728 1 << Assembler::stb_op3 |
|
|
|
729 1 << Assembler::sth_op3 |
|
|
|
730 1 << Assembler::std_op3 |
|
|
|
731 1 << Assembler::stx_op3,
|
|
|
732 op3_ldst_int_limit = Assembler::ldf_op3,
|
|
|
733 op3_mask_ldf = 1 << (Assembler::ldf_op3 - op3_ldst_int_limit) |
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|
|
734 1 << (Assembler::lddf_op3 - op3_ldst_int_limit),
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|
|
735 op3_mask_stf = 1 << (Assembler::stf_op3 - op3_ldst_int_limit) |
|
|
|
736 1 << (Assembler::stdf_op3 - op3_ldst_int_limit),
|
|
|
737
|
|
|
738 offset_width = 13,
|
|
|
739 sethi_offset = 0,
|
|
|
740 #ifdef _LP64
|
|
|
741 nop_offset = 7 * BytesPerInstWord,
|
|
|
742 #else
|
|
|
743 nop_offset = 4,
|
|
|
744 #endif
|
|
|
745 add_offset = nop_offset + BytesPerInstWord,
|
|
|
746 ldst_offset = add_offset + BytesPerInstWord
|
|
|
747 };
|
|
|
748 bool is_immediate() const {
|
|
|
749 // check if instruction is ld* [reg + offset], reg or st* reg, [reg + offset]
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|
|
750 int i0 = long_at(0);
|
|
|
751 return (is_op(i0, Assembler::ldst_op));
|
|
|
752 }
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|
|
753
|
|
|
754 address instruction_address() const { return addr_at(0); }
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|
|
755 address next_instruction_address() const {
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|
|
756 return addr_at(is_immediate()? 4 : 16);
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|
|
757 }
|
|
|
758 int offset() const {
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|
|
759 return is_immediate()? inv_simm(long_at(0), offset_width) :
|
|
|
760 nativeMovConstRegPatching_at(addr_at(0))->data();
|
|
|
761 }
|
|
|
762 void set_offset(int x) {
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|
|
763 if (is_immediate()) {
|
|
|
764 guarantee(fits_in_simm(x, offset_width), "data block offset overflow");
|
|
|
765 set_long_at(0, set_simm(long_at(0), x, offset_width));
|
|
|
766 }
|
|
|
767 else
|
|
|
768 nativeMovConstRegPatching_at(addr_at(0))->set_data(x);
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|
|
769 }
|
|
|
770
|
|
|
771 void add_offset_in_bytes(intptr_t radd_offset) {
|
|
|
772 set_offset (offset() + radd_offset);
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|
|
773 }
|
|
|
774
|
|
|
775 void copy_instruction_to(address new_instruction_address);
|
|
|
776
|
|
|
777 void verify();
|
|
|
778 void print ();
|
|
|
779
|
|
|
780 // unit test stuff
|
|
|
781 static void test();
|
|
|
782
|
|
|
783 private:
|
|
|
784 friend inline NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address) {
|
|
|
785 NativeMovRegMemPatching* test = (NativeMovRegMemPatching*)address;
|
|
|
786 #ifdef ASSERT
|
|
|
787 test->verify();
|
|
|
788 #endif
|
|
|
789 return test;
|
|
|
790 }
|
|
|
791 };
|
|
|
792
|
|
|
793
|
|
|
794 // An interface for accessing/manipulating native jumps
|
|
|
795 // jump_to addr
|
|
|
796 // == sethi %hi22(addr), temp ; jumpl reg, %lo10(addr), G0 ; <delay>
|
|
|
797 // jumpl_to addr, lreg
|
|
|
798 // == sethi %hi22(addr), temp ; jumpl reg, %lo10(addr), lreg ; <delay>
|
|
|
799 class NativeJump;
|
|
|
800 inline NativeJump* nativeJump_at(address address);
|
|
|
801 class NativeJump: public NativeInstruction {
|
|
|
802 private:
|
|
|
803 void guarantee_displacement(int disp, int width) {
|
|
|
804 guarantee(fits_in_simm(disp, width + 2), "branch displacement overflow");
|
|
|
805 }
|
|
|
806
|
|
|
807 public:
|
|
|
808 enum Sparc_specific_constants {
|
|
|
809 sethi_offset = 0,
|
|
|
810 #ifdef _LP64
|
|
|
811 jmpl_offset = 7 * BytesPerInstWord,
|
|
|
812 instruction_size = 9 * BytesPerInstWord // includes delay slot
|
|
|
813 #else
|
|
|
814 jmpl_offset = 1 * BytesPerInstWord,
|
|
|
815 instruction_size = 3 * BytesPerInstWord // includes delay slot
|
|
|
816 #endif
|
|
|
817 };
|
|
|
818
|
|
|
819 address instruction_address() const { return addr_at(0); }
|
|
|
820 address next_instruction_address() const { return addr_at(instruction_size); }
|
|
|
821
|
|
|
822 #ifdef _LP64
|
|
|
823 address jump_destination() const {
|
|
|
824 return (address) data64(instruction_address(), long_at(jmpl_offset));
|
|
|
825 }
|
|
|
826 void set_jump_destination(address dest) {
|
|
|
827 set_data64_sethi( instruction_address(), (intptr_t)dest);
|
|
|
828 set_long_at(jmpl_offset, set_data32_simm13( long_at(jmpl_offset), (intptr_t)dest));
|
|
|
829 }
|
|
|
830 #else
|
|
|
831 address jump_destination() const {
|
|
|
832 return (address) data32(long_at(sethi_offset), long_at(jmpl_offset));
|
|
|
833 }
|
|
|
834 void set_jump_destination(address dest) {
|
|
|
835 set_long_at(sethi_offset, set_data32_sethi( long_at(sethi_offset), (intptr_t)dest));
|
|
|
836 set_long_at(jmpl_offset, set_data32_simm13( long_at(jmpl_offset), (intptr_t)dest));
|
|
|
837 }
|
|
|
838 #endif
|
|
|
839
|
|
|
840 // Creation
|
|
|
841 friend inline NativeJump* nativeJump_at(address address) {
|
|
|
842 NativeJump* jump = (NativeJump*)address;
|
|
|
843 #ifdef ASSERT
|
|
|
844 jump->verify();
|
|
|
845 #endif
|
|
|
846 return jump;
|
|
|
847 }
|
|
|
848
|
|
|
849 void verify();
|
|
|
850 void print();
|
|
|
851
|
|
|
852 // Unit testing stuff
|
|
|
853 static void test();
|
|
|
854
|
|
|
855 // Insertion of native jump instruction
|
|
|
856 static void insert(address code_pos, address entry);
|
|
|
857 // MT-safe insertion of native jump at verified method entry
|
|
|
858 static void check_verified_entry_alignment(address entry, address verified_entry) {
|
|
|
859 // nothing to do for sparc.
|
|
|
860 }
|
|
|
861 static void patch_verified_entry(address entry, address verified_entry, address dest);
|
|
|
862 };
|
|
|
863
|
|
|
864
|
|
|
865
|
|
|
866 // Despite the name, handles only simple branches.
|
|
|
867 class NativeGeneralJump;
|
|
|
868 inline NativeGeneralJump* nativeGeneralJump_at(address address);
|
|
|
869 class NativeGeneralJump: public NativeInstruction {
|
|
|
870 public:
|
|
|
871 enum Sparc_specific_constants {
|
|
|
872 instruction_size = 8
|
|
|
873 };
|
|
|
874
|
|
|
875 address instruction_address() const { return addr_at(0); }
|
|
|
876 address jump_destination() const { return addr_at(0) + branch_destination_offset(long_at(0)); }
|
|
|
877 void set_jump_destination(address dest) {
|
|
|
878 int patched_instr = patch_branch_destination_offset(dest - addr_at(0), long_at(0));
|
|
|
879 set_long_at(0, patched_instr);
|
|
|
880 }
|
|
|
881 void set_annul() { set_annul_bit(); }
|
|
|
882 NativeInstruction *delay_slot_instr() { return nativeInstruction_at(addr_at(4));}
|
|
|
883 void fill_delay_slot(int instr) { set_long_at(4, instr);}
|
|
|
884 Assembler::Condition condition() {
|
|
|
885 int x = long_at(0);
|
|
|
886 return (Assembler::Condition) Assembler::inv_cond(x);
|
|
|
887 }
|
|
|
888
|
|
|
889 // Creation
|
|
|
890 friend inline NativeGeneralJump* nativeGeneralJump_at(address address) {
|
|
|
891 NativeGeneralJump* jump = (NativeGeneralJump*)(address);
|
|
|
892 #ifdef ASSERT
|
|
|
893 jump->verify();
|
|
|
894 #endif
|
|
|
895 return jump;
|
|
|
896 }
|
|
|
897
|
|
|
898 // Insertion of native general jump instruction
|
|
|
899 static void insert_unconditional(address code_pos, address entry);
|
|
|
900 static void replace_mt_safe(address instr_addr, address code_buffer);
|
|
|
901
|
|
|
902 void verify();
|
|
|
903 };
|
|
|
904
|
|
|
905
|
|
|
906 class NativeIllegalInstruction: public NativeInstruction {
|
|
|
907 public:
|
|
|
908 enum Sparc_specific_constants {
|
|
|
909 instruction_size = 4
|
|
|
910 };
|
|
|
911
|
|
|
912 // Insert illegal opcode as specific address
|
|
|
913 static void insert(address code_pos);
|
|
|
914 };
|
