Mercurial > hg > truffle
annotate src/share/vm/opto/regmask.cpp @ 9126:bc26f978b0ce
HotSpotResolvedObjectType: implement hasFinalizeSubclass() correctly
don't use the (wrong) cached value, but ask the runtime on each request.
Fixes regression on xml.* benchmarks @ specjvm2008. The problem was:
After the constructor of Object was deoptimized due to an assumption violation,
it was recompiled again after some time. However, on recompilation, the value
of hasFinalizeSubclass for the class was not updated and it was compiled again
with a, now wrong, assumption, which then triggers deoptimization again.
This was repeated until it hit the recompilation limit (defined by
PerMethodRecompilationCutoff), and therefore only executed by the interpreter
from now on, causing the performance regression.
author | Bernhard Urban <bernhard.urban@jku.at> |
---|---|
date | Mon, 15 Apr 2013 19:54:58 +0200 |
parents | 2c673161698a |
children | d2907f74462e |
rev | line source |
---|---|
0 | 1 /* |
8044
2c673161698a
8007402: Code cleanup to remove Parfait false positive
drchase
parents:
7636
diff
changeset
|
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
0
diff
changeset
|
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
0
diff
changeset
|
20 * or visit www.oracle.com if you need additional information or have any |
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
0
diff
changeset
|
21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
26 #include "opto/compile.hpp" | |
27 #include "opto/regmask.hpp" | |
28 #ifdef TARGET_ARCH_MODEL_x86_32 | |
29 # include "adfiles/ad_x86_32.hpp" | |
30 #endif | |
31 #ifdef TARGET_ARCH_MODEL_x86_64 | |
32 # include "adfiles/ad_x86_64.hpp" | |
33 #endif | |
34 #ifdef TARGET_ARCH_MODEL_sparc | |
35 # include "adfiles/ad_sparc.hpp" | |
36 #endif | |
37 #ifdef TARGET_ARCH_MODEL_zero | |
38 # include "adfiles/ad_zero.hpp" | |
39 #endif | |
2192
b92c45f2bc75
7016023: Enable building ARM and PPC from src/closed repository
bobv
parents:
1972
diff
changeset
|
40 #ifdef TARGET_ARCH_MODEL_arm |
b92c45f2bc75
7016023: Enable building ARM and PPC from src/closed repository
bobv
parents:
1972
diff
changeset
|
41 # include "adfiles/ad_arm.hpp" |
b92c45f2bc75
7016023: Enable building ARM and PPC from src/closed repository
bobv
parents:
1972
diff
changeset
|
42 #endif |
b92c45f2bc75
7016023: Enable building ARM and PPC from src/closed repository
bobv
parents:
1972
diff
changeset
|
43 #ifdef TARGET_ARCH_MODEL_ppc |
b92c45f2bc75
7016023: Enable building ARM and PPC from src/closed repository
bobv
parents:
1972
diff
changeset
|
44 # include "adfiles/ad_ppc.hpp" |
b92c45f2bc75
7016023: Enable building ARM and PPC from src/closed repository
bobv
parents:
1972
diff
changeset
|
45 #endif |
0 | 46 |
47 #define RM_SIZE _RM_SIZE /* a constant private to the class RegMask */ | |
48 | |
49 //-------------Non-zero bit search methods used by RegMask--------------------- | |
50 // Find lowest 1, or return 32 if empty | |
51 int find_lowest_bit( uint32 mask ) { | |
52 int n = 0; | |
53 if( (mask & 0xffff) == 0 ) { | |
54 mask >>= 16; | |
55 n += 16; | |
56 } | |
57 if( (mask & 0xff) == 0 ) { | |
58 mask >>= 8; | |
59 n += 8; | |
60 } | |
61 if( (mask & 0xf) == 0 ) { | |
62 mask >>= 4; | |
63 n += 4; | |
64 } | |
65 if( (mask & 0x3) == 0 ) { | |
66 mask >>= 2; | |
67 n += 2; | |
68 } | |
69 if( (mask & 0x1) == 0 ) { | |
70 mask >>= 1; | |
71 n += 1; | |
72 } | |
73 if( mask == 0 ) { | |
74 n = 32; | |
75 } | |
76 return n; | |
77 } | |
78 | |
79 // Find highest 1, or return 32 if empty | |
80 int find_hihghest_bit( uint32 mask ) { | |
81 int n = 0; | |
82 if( mask > 0xffff ) { | |
83 mask >>= 16; | |
84 n += 16; | |
85 } | |
86 if( mask > 0xff ) { | |
87 mask >>= 8; | |
88 n += 8; | |
89 } | |
90 if( mask > 0xf ) { | |
91 mask >>= 4; | |
92 n += 4; | |
93 } | |
94 if( mask > 0x3 ) { | |
95 mask >>= 2; | |
96 n += 2; | |
97 } | |
98 if( mask > 0x1 ) { | |
99 mask >>= 1; | |
100 n += 1; | |
101 } | |
102 if( mask == 0 ) { | |
103 n = 32; | |
104 } | |
105 return n; | |
106 } | |
107 | |
108 //------------------------------dump------------------------------------------- | |
109 | |
110 #ifndef PRODUCT | |
7636
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
111 void OptoReg::dump(int r, outputStream *st) { |
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
112 switch (r) { |
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
113 case Special: st->print("r---"); break; |
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
114 case Bad: st->print("rBAD"); break; |
0 | 115 default: |
7636
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
116 if (r < _last_Mach_Reg) st->print(Matcher::regName[r]); |
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
117 else st->print("rS%d",r); |
0 | 118 break; |
119 } | |
120 } | |
121 #endif | |
122 | |
123 | |
124 //============================================================================= | |
125 const RegMask RegMask::Empty( | |
126 # define BODY(I) 0, | |
127 FORALL_BODY | |
128 # undef BODY | |
129 0 | |
130 ); | |
131 | |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
132 //============================================================================= |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
133 bool RegMask::is_vector(uint ireg) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
134 return (ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
135 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
136 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
137 int RegMask::num_registers(uint ireg) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
138 switch(ireg) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
139 case Op_VecY: |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
140 return 8; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
141 case Op_VecX: |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
142 return 4; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
143 case Op_VecD: |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
144 case Op_RegD: |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
145 case Op_RegL: |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
146 #ifdef _LP64 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
147 case Op_RegP: |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
148 #endif |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
149 return 2; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
150 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
151 // Op_VecS and the rest ideal registers. |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
152 return 1; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
153 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
154 |
0 | 155 //------------------------------find_first_pair-------------------------------- |
156 // Find the lowest-numbered register pair in the mask. Return the | |
157 // HIGHEST register number in the pair, or BAD if no pairs. | |
158 OptoReg::Name RegMask::find_first_pair() const { | |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
159 verify_pairs(); |
0 | 160 for( int i = 0; i < RM_SIZE; i++ ) { |
161 if( _A[i] ) { // Found some bits | |
162 int bit = _A[i] & -_A[i]; // Extract low bit | |
163 // Convert to bit number, return hi bit in pair | |
164 return OptoReg::Name((i<<_LogWordBits)+find_lowest_bit(bit)+1); | |
165 } | |
166 } | |
167 return OptoReg::Bad; | |
168 } | |
169 | |
170 //------------------------------ClearToPairs----------------------------------- | |
171 // Clear out partial bits; leave only bit pairs | |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
172 void RegMask::clear_to_pairs() { |
0 | 173 for( int i = 0; i < RM_SIZE; i++ ) { |
174 int bits = _A[i]; | |
175 bits &= ((bits & 0x55555555)<<1); // 1 hi-bit set for each pair | |
176 bits |= (bits>>1); // Smear 1 hi-bit into a pair | |
177 _A[i] = bits; | |
178 } | |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
179 verify_pairs(); |
0 | 180 } |
181 | |
182 //------------------------------SmearToPairs----------------------------------- | |
183 // Smear out partial bits; leave only bit pairs | |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
184 void RegMask::smear_to_pairs() { |
0 | 185 for( int i = 0; i < RM_SIZE; i++ ) { |
186 int bits = _A[i]; | |
187 bits |= ((bits & 0x55555555)<<1); // Smear lo bit hi per pair | |
188 bits |= ((bits & 0xAAAAAAAA)>>1); // Smear hi bit lo per pair | |
189 _A[i] = bits; | |
190 } | |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
191 verify_pairs(); |
0 | 192 } |
193 | |
194 //------------------------------is_aligned_pairs------------------------------- | |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
195 bool RegMask::is_aligned_pairs() const { |
0 | 196 // Assert that the register mask contains only bit pairs. |
197 for( int i = 0; i < RM_SIZE; i++ ) { | |
198 int bits = _A[i]; | |
199 while( bits ) { // Check bits for pairing | |
200 int bit = bits & -bits; // Extract low bit | |
201 // Low bit is not odd means its mis-aligned. | |
202 if( (bit & 0x55555555) == 0 ) return false; | |
203 bits -= bit; // Remove bit from mask | |
204 // Check for aligned adjacent bit | |
205 if( (bits & (bit<<1)) == 0 ) return false; | |
206 bits -= (bit<<1); // Remove other halve of pair | |
207 } | |
208 } | |
209 return true; | |
210 } | |
211 | |
212 //------------------------------is_bound1-------------------------------------- | |
213 // Return TRUE if the mask contains a single bit | |
214 int RegMask::is_bound1() const { | |
215 if( is_AllStack() ) return false; | |
216 int bit = -1; // Set to hold the one bit allowed | |
217 for( int i = 0; i < RM_SIZE; i++ ) { | |
218 if( _A[i] ) { // Found some bits | |
219 if( bit != -1 ) return false; // Already had bits, so fail | |
220 bit = _A[i] & -_A[i]; // Extract 1 bit from mask | |
221 if( bit != _A[i] ) return false; // Found many bits, so fail | |
222 } | |
223 } | |
224 // True for both the empty mask and for a single bit | |
225 return true; | |
226 } | |
227 | |
228 //------------------------------is_bound2-------------------------------------- | |
229 // Return TRUE if the mask contains an adjacent pair of bits and no other bits. | |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
230 int RegMask::is_bound_pair() const { |
0 | 231 if( is_AllStack() ) return false; |
232 | |
233 int bit = -1; // Set to hold the one bit allowed | |
234 for( int i = 0; i < RM_SIZE; i++ ) { | |
235 if( _A[i] ) { // Found some bits | |
236 if( bit != -1 ) return false; // Already had bits, so fail | |
237 bit = _A[i] & -(_A[i]); // Extract 1 bit from mask | |
238 if( (bit << 1) != 0 ) { // Bit pair stays in same word? | |
239 if( (bit | (bit<<1)) != _A[i] ) | |
240 return false; // Require adjacent bit pair and no more bits | |
241 } else { // Else its a split-pair case | |
242 if( bit != _A[i] ) return false; // Found many bits, so fail | |
243 i++; // Skip iteration forward | |
8044
2c673161698a
8007402: Code cleanup to remove Parfait false positive
drchase
parents:
7636
diff
changeset
|
244 if( i >= RM_SIZE || _A[i] != 1 ) |
2c673161698a
8007402: Code cleanup to remove Parfait false positive
drchase
parents:
7636
diff
changeset
|
245 return false; // Require 1 lo bit in next word |
0 | 246 } |
247 } | |
248 } | |
249 // True for both the empty mask and for a bit pair | |
250 return true; | |
251 } | |
252 | |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
253 static int low_bits[3] = { 0x55555555, 0x11111111, 0x01010101 }; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
254 //------------------------------find_first_set--------------------------------- |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
255 // Find the lowest-numbered register set in the mask. Return the |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
256 // HIGHEST register number in the set, or BAD if no sets. |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
257 // Works also for size 1. |
8044
2c673161698a
8007402: Code cleanup to remove Parfait false positive
drchase
parents:
7636
diff
changeset
|
258 OptoReg::Name RegMask::find_first_set(const int size) const { |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
259 verify_sets(size); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
260 for (int i = 0; i < RM_SIZE; i++) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
261 if (_A[i]) { // Found some bits |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
262 int bit = _A[i] & -_A[i]; // Extract low bit |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
263 // Convert to bit number, return hi bit in pair |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
264 return OptoReg::Name((i<<_LogWordBits)+find_lowest_bit(bit)+(size-1)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
265 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
266 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
267 return OptoReg::Bad; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
268 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
269 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
270 //------------------------------clear_to_sets---------------------------------- |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
271 // Clear out partial bits; leave only aligned adjacent bit pairs |
8044
2c673161698a
8007402: Code cleanup to remove Parfait false positive
drchase
parents:
7636
diff
changeset
|
272 void RegMask::clear_to_sets(const int size) { |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
273 if (size == 1) return; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
274 assert(2 <= size && size <= 8, "update low bits table"); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
275 assert(is_power_of_2(size), "sanity"); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
276 int low_bits_mask = low_bits[size>>2]; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
277 for (int i = 0; i < RM_SIZE; i++) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
278 int bits = _A[i]; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
279 int sets = (bits & low_bits_mask); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
280 for (int j = 1; j < size; j++) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
281 sets = (bits & (sets<<1)); // filter bits which produce whole sets |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
282 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
283 sets |= (sets>>1); // Smear 1 hi-bit into a set |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
284 if (size > 2) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
285 sets |= (sets>>2); // Smear 2 hi-bits into a set |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
286 if (size > 4) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
287 sets |= (sets>>4); // Smear 4 hi-bits into a set |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
288 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
289 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
290 _A[i] = sets; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
291 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
292 verify_sets(size); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
293 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
294 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
295 //------------------------------smear_to_sets---------------------------------- |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
296 // Smear out partial bits to aligned adjacent bit sets |
8044
2c673161698a
8007402: Code cleanup to remove Parfait false positive
drchase
parents:
7636
diff
changeset
|
297 void RegMask::smear_to_sets(const int size) { |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
298 if (size == 1) return; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
299 assert(2 <= size && size <= 8, "update low bits table"); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
300 assert(is_power_of_2(size), "sanity"); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
301 int low_bits_mask = low_bits[size>>2]; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
302 for (int i = 0; i < RM_SIZE; i++) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
303 int bits = _A[i]; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
304 int sets = 0; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
305 for (int j = 0; j < size; j++) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
306 sets |= (bits & low_bits_mask); // collect partial bits |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
307 bits = bits>>1; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
308 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
309 sets |= (sets<<1); // Smear 1 lo-bit into a set |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
310 if (size > 2) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
311 sets |= (sets<<2); // Smear 2 lo-bits into a set |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
312 if (size > 4) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
313 sets |= (sets<<4); // Smear 4 lo-bits into a set |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
314 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
315 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
316 _A[i] = sets; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
317 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
318 verify_sets(size); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
319 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
320 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
321 //------------------------------is_aligned_set-------------------------------- |
8044
2c673161698a
8007402: Code cleanup to remove Parfait false positive
drchase
parents:
7636
diff
changeset
|
322 bool RegMask::is_aligned_sets(const int size) const { |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
323 if (size == 1) return true; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
324 assert(2 <= size && size <= 8, "update low bits table"); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
325 assert(is_power_of_2(size), "sanity"); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
326 int low_bits_mask = low_bits[size>>2]; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
327 // Assert that the register mask contains only bit sets. |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
328 for (int i = 0; i < RM_SIZE; i++) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
329 int bits = _A[i]; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
330 while (bits) { // Check bits for pairing |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
331 int bit = bits & -bits; // Extract low bit |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
332 // Low bit is not odd means its mis-aligned. |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
333 if ((bit & low_bits_mask) == 0) return false; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
334 // Do extra work since (bit << size) may overflow. |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
335 int hi_bit = bit << (size-1); // high bit |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
336 int set = hi_bit + ((hi_bit-1) & ~(bit-1)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
337 // Check for aligned adjacent bits in this set |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
338 if ((bits & set) != set) return false; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
339 bits -= set; // Remove this set |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
340 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
341 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
342 return true; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
343 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
344 |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
345 //------------------------------is_bound_set----------------------------------- |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
346 // Return TRUE if the mask contains one adjacent set of bits and no other bits. |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
347 // Works also for size 1. |
8044
2c673161698a
8007402: Code cleanup to remove Parfait false positive
drchase
parents:
7636
diff
changeset
|
348 int RegMask::is_bound_set(const int size) const { |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
349 if( is_AllStack() ) return false; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
350 assert(1 <= size && size <= 8, "update low bits table"); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
351 int bit = -1; // Set to hold the one bit allowed |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
352 for (int i = 0; i < RM_SIZE; i++) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
353 if (_A[i] ) { // Found some bits |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
354 if (bit != -1) |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
355 return false; // Already had bits, so fail |
8044
2c673161698a
8007402: Code cleanup to remove Parfait false positive
drchase
parents:
7636
diff
changeset
|
356 bit = _A[i] & -_A[i]; // Extract low bit from mask |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
357 int hi_bit = bit << (size-1); // high bit |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
358 if (hi_bit != 0) { // Bit set stays in same word? |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
359 int set = hi_bit + ((hi_bit-1) & ~(bit-1)); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
360 if (set != _A[i]) |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
361 return false; // Require adjacent bit set and no more bits |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
362 } else { // Else its a split-set case |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
363 if (((-1) & ~(bit-1)) != _A[i]) |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
364 return false; // Found many bits, so fail |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
365 i++; // Skip iteration forward and check high part |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
366 // The lower 24 bits should be 0 since it is split case and size <= 8. |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
367 int set = bit>>24; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
368 set = set & -set; // Remove sign extension. |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
369 set = (((set << size) - 1) >> 8); |
8044
2c673161698a
8007402: Code cleanup to remove Parfait false positive
drchase
parents:
7636
diff
changeset
|
370 if (i >= RM_SIZE || _A[i] != set) |
2c673161698a
8007402: Code cleanup to remove Parfait false positive
drchase
parents:
7636
diff
changeset
|
371 return false; // Require expected low bits in next word |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
372 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
373 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
374 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
375 // True for both the empty mask and for a bit set |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
376 return true; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
377 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
2426
diff
changeset
|
378 |
0 | 379 //------------------------------is_UP------------------------------------------ |
380 // UP means register only, Register plus stack, or stack only is DOWN | |
381 bool RegMask::is_UP() const { | |
382 // Quick common case check for DOWN (any stack slot is legal) | |
383 if( is_AllStack() ) | |
384 return false; | |
385 // Slower check for any stack bits set (also DOWN) | |
386 if( overlap(Matcher::STACK_ONLY_mask) ) | |
387 return false; | |
388 // Not DOWN, so must be UP | |
389 return true; | |
390 } | |
391 | |
392 //------------------------------Size------------------------------------------- | |
393 // Compute size of register mask in bits | |
394 uint RegMask::Size() const { | |
395 extern uint8 bitsInByte[256]; | |
396 uint sum = 0; | |
397 for( int i = 0; i < RM_SIZE; i++ ) | |
398 sum += | |
399 bitsInByte[(_A[i]>>24) & 0xff] + | |
400 bitsInByte[(_A[i]>>16) & 0xff] + | |
401 bitsInByte[(_A[i]>> 8) & 0xff] + | |
402 bitsInByte[ _A[i] & 0xff]; | |
403 return sum; | |
404 } | |
405 | |
406 #ifndef PRODUCT | |
407 //------------------------------print------------------------------------------ | |
7636
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
408 void RegMask::dump(outputStream *st) const { |
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
409 st->print("["); |
0 | 410 RegMask rm = *this; // Structure copy into local temp |
411 | |
412 OptoReg::Name start = rm.find_first_elem(); // Get a register | |
7636
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
413 if (OptoReg::is_valid(start)) { // Check for empty mask |
0 | 414 rm.Remove(start); // Yank from mask |
7636
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
415 OptoReg::dump(start, st); // Print register |
0 | 416 OptoReg::Name last = start; |
417 | |
418 // Now I have printed an initial register. | |
419 // Print adjacent registers as "rX-rZ" instead of "rX,rY,rZ". | |
420 // Begin looping over the remaining registers. | |
7636
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
421 while (1) { // |
0 | 422 OptoReg::Name reg = rm.find_first_elem(); // Get a register |
7636
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
423 if (!OptoReg::is_valid(reg)) |
0 | 424 break; // Empty mask, end loop |
425 rm.Remove(reg); // Yank from mask | |
426 | |
7636
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
427 if (last+1 == reg) { // See if they are adjacent |
0 | 428 // Adjacent registers just collect into long runs, no printing. |
429 last = reg; | |
430 } else { // Ending some kind of run | |
7636
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
431 if (start == last) { // 1-register run; no special printing |
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
432 } else if (start+1 == last) { |
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
433 st->print(","); // 2-register run; print as "rX,rY" |
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
434 OptoReg::dump(last, st); |
0 | 435 } else { // Multi-register run; print as "rX-rZ" |
7636
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
436 st->print("-"); |
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
437 OptoReg::dump(last, st); |
0 | 438 } |
7636
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
439 st->print(","); // Seperate start of new run |
0 | 440 start = last = reg; // Start a new register run |
7636
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
441 OptoReg::dump(start, st); // Print register |
0 | 442 } // End of if ending a register run or not |
443 } // End of while regmask not empty | |
444 | |
7636
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
445 if (start == last) { // 1-register run; no special printing |
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
446 } else if (start+1 == last) { |
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
447 st->print(","); // 2-register run; print as "rX,rY" |
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
448 OptoReg::dump(last, st); |
0 | 449 } else { // Multi-register run; print as "rX-rZ" |
7636
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
450 st->print("-"); |
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
451 OptoReg::dump(last, st); |
0 | 452 } |
7636
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
453 if (rm.is_AllStack()) st->print("..."); |
0 | 454 } |
7636
a7114d3d712e
8005055: pass outputStream to more opto debug routines
kvn
parents:
6179
diff
changeset
|
455 st->print("]"); |
0 | 456 } |
457 #endif |