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1 /*
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2 * Copyright 2002 Sun Microsystems, Inc. All Rights Reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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20 * CA 95054 USA or visit www.sun.com if you need additional information or
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21 * have any questions.
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22 *
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23 */
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24
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25 package sun.jvm.hotspot.asm.sparc;
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26
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27 import sun.jvm.hotspot.asm.*;
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28
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29 // Please refer to "The SPARC Architecture Manual - Version 9"
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30
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31 public interface SPARCV9Opcodes extends SPARCOpcodes {
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32 // format 2, v9 specific "op2" values.
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33
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34 // branch on integer condition codes with prediction
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35 public static final int OP_2_BPcc = 1;
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36
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37 // branch on integer register contents with prediction
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38 public static final int OP_2_BPr = 3;
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39
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40 // branch on float condition codes with prediction
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41 public static final int OP_2_FBPfcc = 5;
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42
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43 // "rcond" - branch on register condition
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44 public static final int BRANCH_RCOND_START_BIT = 25;
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45
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46 // rcond is 3 bits length
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47 public static final int BRANCH_RCOND_MASK = 7 << BRANCH_RCOND_START_BIT;
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48
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49 // "rcond" - as used in conditional moves
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50 public static final int CMOVE_RCOND_START_BIT = 10;
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51 public static final int CMOVE_RCOND_MASK = 7 << CMOVE_RCOND_START_BIT;
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52
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53 public static final int IMPDEP1 = CPop1;
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54 public static final int IMPDEP2 = CPop2;
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55
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56 // various rcond values - used in BPr, MOVr and FMOVr
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57
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58 // reserved register condition
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59 public static final int BRANCH_RCOND_RESERVED1 = 0; // 000
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60
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61 public static final int BRZ = 1;
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62 public static final int MOVRZ = BRZ;
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63 public static final int FMOVZ = BRZ;
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64
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65 public static final int BRLEZ = 2;
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66 public static final int MOVRLEZ = BRLEZ;
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67 public static final int FMOVLEZ = BRLEZ;
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68
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69 public static final int BRLZ = 3;
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70 public static final int MOVRLZ = BRLZ;
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71 public static final int FMOVLZ = BRLZ;
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72
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73 // reserved register condition
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74 public static final int BRANCH_RCOND_RESERVED2 = 4; // 100
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75
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76 public static final int BRNZ = 5;
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77 public static final int MOVRNZ = BRNZ;
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78 public static final int FMOVNZ = BRNZ;
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79
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80 public static final int BRGZ = 6;
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81 public static final int MOVGZ = BRGZ;
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82 public static final int FMOVGZ = BRGZ;
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83
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84 public static final int BRGEZ = 7;
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85 public static final int MOVRGEZ = BRGEZ;
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86 public static final int FMOVGEZ = BRGEZ;
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87
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88 // "p" - prediction bit - predict branch taken or not taken
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89 public static final int PREDICTION_START_BIT = 19;
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90 public static final int PREDICTION_MASK = 1 << PREDICTION_START_BIT;
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91
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92 // branch pc relative displacement - hi 2 bits of disp16.
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93 public static final int DISP_16_HI_START_BIT = 20;
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94
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95 // disp 16 hi is 2 bits length
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96 public static final int DISP_16_HI_MASK = 3 << DISP_16_HI_START_BIT;
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97
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98 // disp 16 low 14 bits
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99 public static final int DISP_16_LO_START_BIT = 0; // just for completion.
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100 public static final int DISP_16_LO_MASK = 0x3FFF;
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101 public static final int DISP_16_LO_NUMBITS = 14;
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102
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103 // disp 19 - integer branch with prediction - displacement
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104 public static final int DISP_19_MASK = 0x7FFFF;
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105
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106 /*
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107 * condition code selected for integer branches - cc1 & cc0.
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108 * condition code selected for float branches - cc1 & cc0.
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109 * opf_cc field - floating conditional moves - 3 bits.
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110 * convert 2 bit codes as 3 bit codes always and use following codes
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111 * uniformly.
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112 */
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113
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114 // opf_cc - 3 bits
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115 public static final int OPF_CC_START_BIT = 11;
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116 public static final int OPF_CC_MASK = 7 << OPF_CC_START_BIT;
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117
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118 public static final int fcc0 = 0; // 000
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119 public static final int fcc1 = 1; // 001
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120 public static final int fcc2 = 2; // 010
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121 public static final int fcc3 = 3; // 011
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122 public static final int icc = 4; // 100
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123 public static final int CFLAG_RESERVED1 = 5; // 101
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124 public static final int xcc = 6; // 110
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125 public static final int CFLAG_RESERVED2 = 7; // 111
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126
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127 // cc0, cc1 as in integer, float predicted branches
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128 public static final int BPcc_CC_START_BIT = 20;
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129 public static final int BPcc_CC_MASK = 3 << BPcc_CC_START_BIT;
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130 public static final int FBPfcc_CC_START_BIT = BPcc_CC_START_BIT;
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131 public static final int FBPfcc_CC_MASK = BPcc_CC_MASK;
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132
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133 // condition codes for integer branches with prediction - BPcc
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134 public static final int CONDITION_BPN = CONDITION_BN;
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135 public static final int CONDITION_BPE = CONDITION_BE;
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136 public static final int CONDITION_BPLE = CONDITION_BLE;
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137 public static final int CONDITION_BPL = CONDITION_BL;
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138 public static final int CONDITION_BPLEU = CONDITION_BLEU;
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139 public static final int CONDITION_BPCS = CONDITION_BCS;
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140 public static final int CONDITION_BPNEG = CONDITION_BNEG;
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141 public static final int CONDITION_BPVS = CONDITION_BVS;
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142 public static final int CONDITION_BPA = CONDITION_BA;
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143 public static final int CONDITION_BPNE = CONDITION_BNE;
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144 public static final int CONDITION_BPG = CONDITION_BG;
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145 public static final int CONDITION_BPGE = CONDITION_BGE;
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146 public static final int CONDITION_BPGU = CONDITION_BGU;
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147 public static final int CONDITION_BPCC = CONDITION_BCC;
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148 public static final int CONDITION_BPPOS = CONDITION_BPOS;
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149 public static final int CONDITION_BPVC = CONDITION_BVC;
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150
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151 // condition codes for float branches with prediction
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152 public static final int CONDITION_FBPN = CONDITION_BN;
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153 public static final int CONDITION_FBPNE = CONDITION_BE;
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154 public static final int CONDITION_FBPLG = CONDITION_BLE;
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155 public static final int CONDITION_FBPUL = CONDITION_BL;
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156 public static final int CONDITION_FBPL = CONDITION_BLEU;
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157 public static final int CONDITION_FBPUG = CONDITION_BCS;
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158 public static final int CONDITION_FBPG = CONDITION_BNEG;
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159 public static final int CONDITION_FBPU = CONDITION_BVS;
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160 public static final int CONDITION_FBPA = CONDITION_BA;
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161 public static final int CONDITION_FBPE = CONDITION_BNE;
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162 public static final int CONDITION_FBPUE = CONDITION_BG;
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163 public static final int CONDITION_FBPGE = CONDITION_BGE;
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164 public static final int CONDITION_FBPUGE= CONDITION_BGU;
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165 public static final int CONDITION_FBPLE = CONDITION_BCC;
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166 public static final int CONDITION_FBPULE= CONDITION_BPOS;
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167 public static final int CONDITION_FBPO = CONDITION_BVC;
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168
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169 // "cmask" - 3 bit mask used in membar for completion constraints
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170 public static final int CMASK_START_BIT = 4;
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171 public static final int CMASK_MASK = 7 << CMASK_START_BIT;
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172
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173 // "mmask" - 4 bit mask used in member for ordering instruction classes.
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174 public static final int MMASK_START_BIT = 0;
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175 public static final int MMASK_MASK = 0xF; // no need to shift
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176
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177 // v9 specific load/store instruction opcodes
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178 // load/store instructions - op3 values - used with op=3 (FORMAT_3)
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179
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180 public static final int LDUW = LD;
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181 public static final int LDUWA = LDA;
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182
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183 public static final int LDXFSR = LDFSR;
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184
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185 public static final int LDFA = LDC;
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186 public static final int LDQF = (2 << 4) | 2;
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187 public static final int LDQFA = (3 << 4) | 2;
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188 public static final int LDDFA = LDDC;
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189
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190 public static final int STW = ST;
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191 public static final int STWA = STA;
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192 public static final int STFA = STC;
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193
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194 public static final int STXFSR = STFSR;
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195
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196 public static final int STQF = STDFQ;
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197 public static final int STQFA = STDCQ;
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198 public static final int STDFA = STDC;
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199
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200 public static final int LDSW = 8;
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201 public static final int LDSWA = (1 << 4) | 8;
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202
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203 public static final int LDX = 0xB;
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204 public static final int LDXA = (1 << 4) | 0xB;
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205
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206 public static final int PREFETCH = (2 << 4) | 0xD;
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207 public static final int PREFETCHA = (3 << 4) | 0xD;
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208
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209 public static final int CASA = (3 << 4) | 0xC;
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210
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211 public static final int STX = 0xE;
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212 public static final int STXA = (1 << 4) | 0xE;
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213 public static final int CASXA = (3 << 4) | 0xE;
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214
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215 // 6 bit immediate shift count mask
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216 public static final int SHIFT_COUNT_6_MASK = 0x3F;
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217
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218 // X bit mask - used to differentiate b/w 32 bit and 64 bit shifts
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219 public static final int X_MASK = 1 << 12;
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220
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221 // E Opcode maps - Page 274 - Table 32 - op3 (op=2) table
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222 // v9 specific items
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223 public static final int ADDC = ADDX;
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224 public static final int ADDCcc = ADDXcc;
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225
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226 public static final int SUBC = SUBX;
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227 public static final int SUBCcc = SUBXcc;
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228
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229 public static final int MULX = 9;
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230 public static final int UDIVX = 0xD;
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231
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232 public static final int SLLX = SLL;
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233 public static final int SRLX = SRL;
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234 public static final int SRAX = SRA;
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235
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236 // special register reads
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237 public static final int RDCCR = RDY;
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238 public static final int RDASI = RDY;
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239 public static final int RDTICK = RDY;
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240 public static final int RDPC = RDY;
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241 public static final int RDFPRS = RDY;
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242 public static final int MEMBAR = RDY;
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243 public static final int STMBAR = RDY;
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244
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245 public static final int RDPR = (2 << 4) | 0xA;
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246
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247 public static final int FLUSHW = (2 << 4) | 0xB;
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248
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249 public static final int MOVcc = (2 << 4) | 0xC;
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250
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251 public static final int SDIVX = (2 << 4) | 0xD;
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252
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253 public static final int POPC = (2 << 4) | 0xE;
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254
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255 public static final int MOVr = (2 << 4) | 0xF;
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256
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257 // special regitser writes
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258 public static final int WRCCR = WRY;
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259 public static final int WRASI = WRY;
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260 public static final int WRFPRS = WRY;
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261 public static final int SIR = WRY;
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262
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263 public static final int SAVED = (3 << 4) | 0x1;
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264 public static final int RESTORED = SAVED;
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265
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266 public static final int WRPR = (3 << 4) | 0x2;
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267
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268 public static final int RETURN = RETT;
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269
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270 public static final int DONE = (3 << 4) | 0xE;
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271 public static final int RETRY = DONE;
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272
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273 // various integer condition code move instructions
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274 public static final int CONDITION_MOVN = CONDITION_BN;
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275 public static final int CONDITION_MOVE = CONDITION_BE;
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276 public static final int CONDITION_MOVLE = CONDITION_BLE;
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277 public static final int CONDITION_MOVL = CONDITION_BL;
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278 public static final int CONDITION_MOVLEU = CONDITION_BLEU;
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279 public static final int CONDITION_MOVCS = CONDITION_BCS;
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280 public static final int CONDITION_MOVNEG = CONDITION_BNEG;
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281 public static final int CONDITION_MOVVS = CONDITION_BVS;
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282 public static final int CONDITION_MOVA = CONDITION_BA;
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283 public static final int CONDITION_MOVNE = CONDITION_BNE;
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284 public static final int CONDITION_MOVG = CONDITION_BG;
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285 public static final int CONDITION_MOVGE = CONDITION_BGE;
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286 public static final int CONDITION_MOVGU = CONDITION_BGU;
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287 public static final int CONDITION_MOVCC = CONDITION_BCC;
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288 public static final int CONDITION_MOVPOS = CONDITION_BPOS;
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289 public static final int CONDITION_MOVVC = CONDITION_BVC;
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290
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291 // cc0, cc1 & cc2 in conditional moves
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292 public static final int CMOVE_CC_START_BIT = 11;
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293 public static final int CMOVE_CC0_CC1_MASK = 3 << CMOVE_CC_START_BIT;
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294 public static final int CMOVE_CC2_START_BIT = 18;
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295 public static final int CMOVE_CC2_MASK = 1 << CMOVE_CC2_START_BIT;
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296
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297 public static final int CMOVE_COND_START_BIT = 14;
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298 // condition code is 4 bits
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299 public static final int CMOVE_COND_MASK = 0xF << CMOVE_COND_START_BIT;
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300
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301 // opf[8:0] (op=2,op3=0x34=FPop1) - Table 34 - Page 276 - E Opcode Maps
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302 // v9 specific opcodes only - remaining are in SPARCOpcodes.
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303
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304 public static final int FMOVd = 0x2;
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305 public static final int FMOVq = 0x3;
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306 public static final int FNEGd = 0x6;
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307 public static final int FNEGq = 0x7;
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308 public static final int FABSd = 0xA;
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309 public static final int FABSq = 0xB;
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310 public static final int FsTOx = (0x8 << 4) | 0x1;
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311 public static final int FdTOx = (0x8 << 4) | 0x2;
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312 public static final int FqTOx = (0x8 << 4) | 0x3;
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313 public static final int FxTOs = (0x8 << 4) | 0x4;
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314 public static final int FxTOd = (0x8 << 4) | 0x8;
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315 public static final int FxTOq = (0x8 << 4) | 0xC;
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316
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317 // opf[8:0] (op=2, op3=0x35= FPop2) - Table 35 - Page 277 - E.2 Tables
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318 // v9 specific opcodes only 0 remanining are in SPARCOpcodes.
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319
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320 // fp condition moves
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321
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322 public static final int FMOVs_fcc0 = 1;
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323 public static final int FMOVs_fcc1 = 1 | (0x4 << 4);
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324 public static final int FMOVs_fcc2 = 1 | (0x8 << 4);
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325 public static final int FMOVs_fcc3 = 1 | (0xC << 4);
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326 public static final int FMOVs_icc = 1 | (0x10 << 4);
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327 public static final int FMOVs_xcc = 1 | (0x18 << 4);
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328
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329 public static final int FMOVd_fcc0 = 2;
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330 public static final int FMOVd_fcc1 = 2 | (0x4 << 4);
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331 public static final int FMOVd_fcc2 = 2 | (0x8 << 4);
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332 public static final int FMOVd_fcc3 = 2 | (0xC << 4);
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333 public static final int FMOVd_icc = 2 | (0x10 << 4);
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334 public static final int FMOVd_xcc = 2 | (0x18 << 4);
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335
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336 public static final int FMOVq_fcc0 = 3;
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337 public static final int FMOVq_fcc1 = 3 | (0x4 << 4);
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338 public static final int FMOVq_fcc2 = 3 | (0x8 << 4);
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339 public static final int FMOVq_fcc3 = 3 | (0xC << 4);
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340 public static final int FMOVq_icc = 3 | (0x10 << 4);
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341 public static final int FMOVq_xcc = 3 | (0x18 << 4);
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342
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343 // fp register condition moves
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344
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345 public static final int FMOVRsZ = 5 | (0x2 << 4);
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346 public static final int FMOVRsLEZ = 5 | (0x4 << 4);
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347 public static final int FMOVRsLZ = 5 | (0x6 << 4);
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348 public static final int FMOVRsNZ = 5 | (0xA << 4);
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349 public static final int FMOVRsGZ = 5 | (0xC << 4);
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350 public static final int FMOVRsGEZ = 5 | (0xE << 4);
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351
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352 public static final int FMOVRdZ = 6 | (0x2 << 4);
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353 public static final int FMOVRdLEZ = 6 | (0x4 << 4);
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354 public static final int FMOVRdLZ = 6 | (0x6 << 4);
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355 public static final int FMOVRdNZ = 6 | (0xA << 4);
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356 public static final int FMOVRdGZ = 6 | (0xC << 4);
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357 public static final int FMOVRdGEZ = 6 | (0xE << 4);
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358
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359 public static final int FMOVRqZ = 7 | (0x2 << 4);
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360 public static final int FMOVRqLEZ = 7 | (0x4 << 4);
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361 public static final int FMOVRqLZ = 7 | (0x6 << 4);
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362 public static final int FMOVRqNZ = 7 | (0xA << 4);
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363 public static final int FMOVRqGZ = 7 | (0xC << 4);
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364 public static final int FMOVRqGEZ = 7 | (0xE << 4);
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365 }
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