annotate src/share/vm/opto/coalesce.cpp @ 17716:cdb71841f4bc

6498581: ThreadInterruptTest3 produces wrong output on Windows Summary: There is race condition between os::interrupt and os::is_interrupted on Windows. In JVM_Sleep(Thread.sleep), check if thread gets interrupted, it may see interrupted but not really interrupted so cause spurious waking up (early return from sleep). Fix by checking if interrupt event really gets set thus prevent false return. For intrinsic of _isInterrupted, on Windows, go fastpath only on bit not set. Reviewed-by: acorn, kvn Contributed-by: david.holmes@oracle.com, yumin.qi@oracle.com
author minqi
date Wed, 26 Feb 2014 15:20:41 -0800
parents 4b078f877b56
children 04e7587c97dc b8e2e616c1e9
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1 /*
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2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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20 * or visit www.oracle.com if you need additional information or have any
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21 * questions.
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22 *
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23 */
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24
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25 #include "precompiled.hpp"
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26 #include "memory/allocation.inline.hpp"
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27 #include "opto/block.hpp"
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28 #include "opto/cfgnode.hpp"
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29 #include "opto/chaitin.hpp"
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30 #include "opto/coalesce.hpp"
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31 #include "opto/connode.hpp"
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32 #include "opto/indexSet.hpp"
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33 #include "opto/machnode.hpp"
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34 #include "opto/matcher.hpp"
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35 #include "opto/regmask.hpp"
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36
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37 #ifndef PRODUCT
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38 void PhaseCoalesce::dump(Node *n) const {
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39 // Being a const function means I cannot use 'Find'
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40 uint r = _phc._lrg_map.find(n);
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41 tty->print("L%d/N%d ",r,n->_idx);
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42 }
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43
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44 void PhaseCoalesce::dump() const {
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45 // I know I have a block layout now, so I can print blocks in a loop
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46 for( uint i=0; i<_phc._cfg.number_of_blocks(); i++ ) {
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47 uint j;
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48 Block* b = _phc._cfg.get_block(i);
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49 // Print a nice block header
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50 tty->print("B%d: ",b->_pre_order);
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51 for( j=1; j<b->num_preds(); j++ )
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52 tty->print("B%d ", _phc._cfg.get_block_for_node(b->pred(j))->_pre_order);
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53 tty->print("-> ");
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54 for( j=0; j<b->_num_succs; j++ )
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55 tty->print("B%d ",b->_succs[j]->_pre_order);
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56 tty->print(" IDom: B%d/#%d\n", b->_idom ? b->_idom->_pre_order : 0, b->_dom_depth);
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57 uint cnt = b->number_of_nodes();
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58 for( j=0; j<cnt; j++ ) {
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59 Node *n = b->get_node(j);
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60 dump( n );
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61 tty->print("\t%s\t",n->Name());
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62
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63 // Dump the inputs
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64 uint k; // Exit value of loop
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65 for( k=0; k<n->req(); k++ ) // For all required inputs
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66 if( n->in(k) ) dump( n->in(k) );
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67 else tty->print("_ ");
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68 int any_prec = 0;
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69 for( ; k<n->len(); k++ ) // For all precedence inputs
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70 if( n->in(k) ) {
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71 if( !any_prec++ ) tty->print(" |");
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72 dump( n->in(k) );
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73 }
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74
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75 // Dump node-specific info
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76 n->dump_spec(tty);
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77 tty->print("\n");
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78
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79 }
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80 tty->print("\n");
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81 }
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82 }
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83 #endif
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84
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85 // Combine the live ranges def'd by these 2 Nodes. N2 is an input to N1.
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86 void PhaseCoalesce::combine_these_two(Node *n1, Node *n2) {
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87 uint lr1 = _phc._lrg_map.find(n1);
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88 uint lr2 = _phc._lrg_map.find(n2);
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89 if( lr1 != lr2 && // Different live ranges already AND
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90 !_phc._ifg->test_edge_sq( lr1, lr2 ) ) { // Do not interfere
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91 LRG *lrg1 = &_phc.lrgs(lr1);
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92 LRG *lrg2 = &_phc.lrgs(lr2);
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93 // Not an oop->int cast; oop->oop, int->int, AND int->oop are OK.
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94
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95 // Now, why is int->oop OK? We end up declaring a raw-pointer as an oop
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96 // and in general that's a bad thing. However, int->oop conversions only
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97 // happen at GC points, so the lifetime of the misclassified raw-pointer
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98 // is from the CheckCastPP (that converts it to an oop) backwards up
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99 // through a merge point and into the slow-path call, and around the
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100 // diamond up to the heap-top check and back down into the slow-path call.
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101 // The misclassified raw pointer is NOT live across the slow-path call,
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102 // and so does not appear in any GC info, so the fact that it is
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103 // misclassified is OK.
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104
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105 if( (lrg1->_is_oop || !lrg2->_is_oop) && // not an oop->int cast AND
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106 // Compatible final mask
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107 lrg1->mask().overlap( lrg2->mask() ) ) {
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108 // Merge larger into smaller.
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109 if( lr1 > lr2 ) {
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110 uint tmp = lr1; lr1 = lr2; lr2 = tmp;
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111 Node *n = n1; n1 = n2; n2 = n;
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112 LRG *ltmp = lrg1; lrg1 = lrg2; lrg2 = ltmp;
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113 }
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114 // Union lr2 into lr1
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115 _phc.Union( n1, n2 );
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116 if (lrg1->_maxfreq < lrg2->_maxfreq)
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117 lrg1->_maxfreq = lrg2->_maxfreq;
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118 // Merge in the IFG
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119 _phc._ifg->Union( lr1, lr2 );
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120 // Combine register restrictions
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121 lrg1->AND(lrg2->mask());
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122 }
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123 }
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124 }
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125
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126 // Copy coalescing
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127 void PhaseCoalesce::coalesce_driver() {
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128 verify();
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129 // Coalesce from high frequency to low
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130 for (uint i = 0; i < _phc._cfg.number_of_blocks(); i++) {
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131 coalesce(_phc._blks[i]);
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132 }
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133 }
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134
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135 // I am inserting copies to come out of SSA form. In the general case, I am
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136 // doing a parallel renaming. I'm in the Named world now, so I can't do a
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137 // general parallel renaming. All the copies now use "names" (live-ranges)
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138 // to carry values instead of the explicit use-def chains. Suppose I need to
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139 // insert 2 copies into the same block. They copy L161->L128 and L128->L132.
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140 // If I insert them in the wrong order then L128 will get clobbered before it
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141 // can get used by the second copy. This cannot happen in the SSA model;
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142 // direct use-def chains get me the right value. It DOES happen in the named
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143 // model so I have to handle the reordering of copies.
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144 //
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145 // In general, I need to topo-sort the placed copies to avoid conflicts.
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146 // Its possible to have a closed cycle of copies (e.g., recirculating the same
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147 // values around a loop). In this case I need a temp to break the cycle.
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148 void PhaseAggressiveCoalesce::insert_copy_with_overlap( Block *b, Node *copy, uint dst_name, uint src_name ) {
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149
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150 // Scan backwards for the locations of the last use of the dst_name.
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151 // I am about to clobber the dst_name, so the copy must be inserted
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152 // after the last use. Last use is really first-use on a backwards scan.
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153 uint i = b->end_idx()-1;
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154 while(1) {
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155 Node *n = b->get_node(i);
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156 // Check for end of virtual copies; this is also the end of the
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157 // parallel renaming effort.
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158 if (n->_idx < _unique) {
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159 break;
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160 }
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161 uint idx = n->is_Copy();
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162 assert( idx || n->is_Con() || n->is_MachProj(), "Only copies during parallel renaming" );
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163 if (idx && _phc._lrg_map.find(n->in(idx)) == dst_name) {
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164 break;
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165 }
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166 i--;
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167 }
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168 uint last_use_idx = i;
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169
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170 // Also search for any kill of src_name that exits the block.
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171 // Since the copy uses src_name, I have to come before any kill.
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172 uint kill_src_idx = b->end_idx();
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173 // There can be only 1 kill that exits any block and that is
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174 // the last kill. Thus it is the first kill on a backwards scan.
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175 i = b->end_idx()-1;
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176 while (1) {
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177 Node *n = b->get_node(i);
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178 // Check for end of virtual copies; this is also the end of the
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179 // parallel renaming effort.
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180 if (n->_idx < _unique) {
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181 break;
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182 }
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183 assert( n->is_Copy() || n->is_Con() || n->is_MachProj(), "Only copies during parallel renaming" );
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184 if (_phc._lrg_map.find(n) == src_name) {
0
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185 kill_src_idx = i;
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186 break;
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diff changeset
187 }
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188 i--;
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189 }
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parents:
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190 // Need a temp? Last use of dst comes after the kill of src?
10111
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parents: 3842
diff changeset
191 if (last_use_idx >= kill_src_idx) {
0
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parents:
diff changeset
192 // Need to break a cycle with a temp
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parents:
diff changeset
193 uint idx = copy->is_Copy();
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diff changeset
194 Node *tmp = copy->clone();
10111
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parents: 3842
diff changeset
195 uint max_lrg_id = _phc._lrg_map.max_lrg_id();
8373c19be854 8011621: live_ranges_in_separate_class.patch
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parents: 3842
diff changeset
196 _phc.new_lrg(tmp, max_lrg_id);
8373c19be854 8011621: live_ranges_in_separate_class.patch
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diff changeset
197 _phc._lrg_map.set_max_lrg_id(max_lrg_id + 1);
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diff changeset
198
0
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parents:
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199 // Insert new temp between copy and source
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diff changeset
200 tmp ->set_req(idx,copy->in(idx));
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diff changeset
201 copy->set_req(idx,tmp);
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parents:
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202 // Save source in temp early, before source is killed
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diff changeset
203 b->insert_node(tmp, kill_src_idx);
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d1034bd8cefc 8022284: Hide internal data structure in PhaseCFG
adlertz
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diff changeset
204 _phc._cfg.map_node_to_block(tmp, b);
0
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205 last_use_idx++;
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206 }
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207
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208 // Insert just after last use
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diff changeset
209 b->insert_node(copy, last_use_idx + 1);
0
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210 }
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211
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212 void PhaseAggressiveCoalesce::insert_copies( Matcher &matcher ) {
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213 // We do LRGs compressing and fix a liveout data only here since the other
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214 // place in Split() is guarded by the assert which we never hit.
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diff changeset
215 _phc._lrg_map.compress_uf_map_for_nodes();
0
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216 // Fix block's liveout data for compressed live ranges.
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diff changeset
217 for (uint lrg = 1; lrg < _phc._lrg_map.max_lrg_id(); lrg++) {
8373c19be854 8011621: live_ranges_in_separate_class.patch
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diff changeset
218 uint compressed_lrg = _phc._lrg_map.find(lrg);
8373c19be854 8011621: live_ranges_in_separate_class.patch
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diff changeset
219 if (lrg != compressed_lrg) {
12071
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
220 for (uint bidx = 0; bidx < _phc._cfg.number_of_blocks(); bidx++) {
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
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diff changeset
221 IndexSet *liveout = _phc._live->live(_phc._cfg.get_block(bidx));
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diff changeset
222 if (liveout->member(lrg)) {
0
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223 liveout->remove(lrg);
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224 liveout->insert(compressed_lrg);
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225 }
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226 }
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227 }
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228 }
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229
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230 // All new nodes added are actual copies to replace virtual copies.
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231 // Nodes with index less than '_unique' are original, non-virtual Nodes.
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232 _unique = C->unique();
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233
12071
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adlertz
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diff changeset
234 for (uint i = 0; i < _phc._cfg.number_of_blocks(); i++) {
10999
693e4d04fd09 8014959: assert(Compile::current()->live_nodes() < (uint)MaxNodeLimit) failed: Live Node limit exceeded limit
drchase
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diff changeset
235 C->check_node_count(NodeLimitFudgeFactor, "out of nodes in coalesce");
693e4d04fd09 8014959: assert(Compile::current()->live_nodes() < (uint)MaxNodeLimit) failed: Live Node limit exceeded limit
drchase
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diff changeset
236 if (C->failing()) return;
12071
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adlertz
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diff changeset
237 Block *b = _phc._cfg.get_block(i);
0
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238 uint cnt = b->num_preds(); // Number of inputs to the Phi
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239
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650868c062a9 8023691: Create interface for nodes in class Block
adlertz
parents: 12075
diff changeset
240 for( uint l = 1; l<b->number_of_nodes(); l++ ) {
650868c062a9 8023691: Create interface for nodes in class Block
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diff changeset
241 Node *n = b->get_node(l);
0
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242
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diff changeset
243 // Do not use removed-copies, use copied value instead
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244 uint ncnt = n->req();
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245 for( uint k = 1; k<ncnt; k++ ) {
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246 Node *copy = n->in(k);
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247 uint cidx = copy->is_Copy();
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248 if( cidx ) {
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249 Node *def = copy->in(cidx);
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
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diff changeset
250 if (_phc._lrg_map.find(copy) == _phc._lrg_map.find(def)) {
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
251 n->set_req(k, def);
8373c19be854 8011621: live_ranges_in_separate_class.patch
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diff changeset
252 }
0
a61af66fc99e Initial load
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253 }
a61af66fc99e Initial load
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254 }
a61af66fc99e Initial load
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255
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parents:
diff changeset
256 // Remove any explicit copies that get coalesced.
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parents:
diff changeset
257 uint cidx = n->is_Copy();
a61af66fc99e Initial load
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parents:
diff changeset
258 if( cidx ) {
a61af66fc99e Initial load
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parents:
diff changeset
259 Node *def = n->in(cidx);
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
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parents: 3842
diff changeset
260 if (_phc._lrg_map.find(n) == _phc._lrg_map.find(def)) {
0
a61af66fc99e Initial load
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parents:
diff changeset
261 n->replace_by(def);
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diff changeset
262 n->set_req(cidx,NULL);
12167
650868c062a9 8023691: Create interface for nodes in class Block
adlertz
parents: 12075
diff changeset
263 b->remove_node(l);
0
a61af66fc99e Initial load
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parents:
diff changeset
264 l--;
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parents:
diff changeset
265 continue;
a61af66fc99e Initial load
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266 }
a61af66fc99e Initial load
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diff changeset
267 }
a61af66fc99e Initial load
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268
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
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parents: 3842
diff changeset
269 if (n->is_Phi()) {
0
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parents:
diff changeset
270 // Get the chosen name for the Phi
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
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diff changeset
271 uint phi_name = _phc._lrg_map.find(n);
0
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parents:
diff changeset
272 // Ignore the pre-allocated specials
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
273 if (!phi_name) {
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
274 continue;
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
275 }
0
a61af66fc99e Initial load
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parents:
diff changeset
276 // Check for mismatch inputs to Phi
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
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parents: 3842
diff changeset
277 for (uint j = 1; j < cnt; j++) {
0
a61af66fc99e Initial load
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parents:
diff changeset
278 Node *m = n->in(j);
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
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parents: 3842
diff changeset
279 uint src_name = _phc._lrg_map.find(m);
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
280 if (src_name != phi_name) {
12023
d1034bd8cefc 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 10999
diff changeset
281 Block *pred = _phc._cfg.get_block_for_node(b->pred(j));
0
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parents:
diff changeset
282 Node *copy;
a61af66fc99e Initial load
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parents:
diff changeset
283 assert(!m->is_Con() || m->is_Mach(), "all Con must be Mach");
a61af66fc99e Initial load
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parents:
diff changeset
284 // Rematerialize constants instead of copying them
a61af66fc99e Initial load
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parents:
diff changeset
285 if( m->is_Mach() && m->as_Mach()->is_Con() &&
a61af66fc99e Initial load
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parents:
diff changeset
286 m->as_Mach()->rematerialize() ) {
a61af66fc99e Initial load
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parents:
diff changeset
287 copy = m->clone();
a61af66fc99e Initial load
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parents:
diff changeset
288 // Insert the copy in the predecessor basic block
a61af66fc99e Initial load
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parents:
diff changeset
289 pred->add_inst(copy);
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parents:
diff changeset
290 // Copy any flags as well
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
291 _phc.clone_projs(pred, pred->end_idx(), m, copy, _phc._lrg_map);
0
a61af66fc99e Initial load
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parents:
diff changeset
292 } else {
a61af66fc99e Initial load
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parents:
diff changeset
293 const RegMask *rm = C->matcher()->idealreg2spillmask[m->ideal_reg()];
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
294 copy = new (C) MachSpillCopyNode(m, *rm, *rm);
0
a61af66fc99e Initial load
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parents:
diff changeset
295 // Find a good place to insert. Kinda tricky, use a subroutine
a61af66fc99e Initial load
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parents:
diff changeset
296 insert_copy_with_overlap(pred,copy,phi_name,src_name);
a61af66fc99e Initial load
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parents:
diff changeset
297 }
a61af66fc99e Initial load
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parents:
diff changeset
298 // Insert the copy in the use-def chain
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
299 n->set_req(j, copy);
12023
d1034bd8cefc 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 10999
diff changeset
300 _phc._cfg.map_node_to_block(copy, pred);
0
a61af66fc99e Initial load
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parents:
diff changeset
301 // Extend ("register allocate") the names array for the copy.
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
302 _phc._lrg_map.extend(copy->_idx, phi_name);
0
a61af66fc99e Initial load
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parents:
diff changeset
303 } // End of if Phi names do not match
a61af66fc99e Initial load
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parents:
diff changeset
304 } // End of for all inputs to Phi
a61af66fc99e Initial load
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parents:
diff changeset
305 } else { // End of if Phi
a61af66fc99e Initial load
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parents:
diff changeset
306
a61af66fc99e Initial load
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parents:
diff changeset
307 // Now check for 2-address instructions
a61af66fc99e Initial load
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parents:
diff changeset
308 uint idx;
a61af66fc99e Initial load
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parents:
diff changeset
309 if( n->is_Mach() && (idx=n->as_Mach()->two_adr()) ) {
a61af66fc99e Initial load
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parents:
diff changeset
310 // Get the chosen name for the Node
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
311 uint name = _phc._lrg_map.find(n);
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
312 assert (name, "no 2-address specials");
0
a61af66fc99e Initial load
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parents:
diff changeset
313 // Check for name mis-match on the 2-address input
a61af66fc99e Initial load
duke
parents:
diff changeset
314 Node *m = n->in(idx);
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
315 if (_phc._lrg_map.find(m) != name) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
316 Node *copy;
a61af66fc99e Initial load
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parents:
diff changeset
317 assert(!m->is_Con() || m->is_Mach(), "all Con must be Mach");
a61af66fc99e Initial load
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parents:
diff changeset
318 // At this point it is unsafe to extend live ranges (6550579).
a61af66fc99e Initial load
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parents:
diff changeset
319 // Rematerialize only constants as we do for Phi above.
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
320 if(m->is_Mach() && m->as_Mach()->is_Con() &&
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
321 m->as_Mach()->rematerialize()) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
322 copy = m->clone();
a61af66fc99e Initial load
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parents:
diff changeset
323 // Insert the copy in the basic block, just before us
12167
650868c062a9 8023691: Create interface for nodes in class Block
adlertz
parents: 12075
diff changeset
324 b->insert_node(copy, l++);
12075
4b2838704fd5 8021898: Broken JIT compiler optimization for loop unswitching
kvn
parents: 12071
diff changeset
325 l += _phc.clone_projs(b, l, m, copy, _phc._lrg_map);
0
a61af66fc99e Initial load
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parents:
diff changeset
326 } else {
a61af66fc99e Initial load
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parents:
diff changeset
327 const RegMask *rm = C->matcher()->idealreg2spillmask[m->ideal_reg()];
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
328 copy = new (C) MachSpillCopyNode(m, *rm, *rm);
0
a61af66fc99e Initial load
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parents:
diff changeset
329 // Insert the copy in the basic block, just before us
12167
650868c062a9 8023691: Create interface for nodes in class Block
adlertz
parents: 12075
diff changeset
330 b->insert_node(copy, l++);
0
a61af66fc99e Initial load
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parents:
diff changeset
331 }
a61af66fc99e Initial load
duke
parents:
diff changeset
332 // Insert the copy in the use-def chain
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
333 n->set_req(idx, copy);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
334 // Extend ("register allocate") the names array for the copy.
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
335 _phc._lrg_map.extend(copy->_idx, name);
12023
d1034bd8cefc 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 10999
diff changeset
336 _phc._cfg.map_node_to_block(copy, b);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
337 }
a61af66fc99e Initial load
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parents:
diff changeset
338
a61af66fc99e Initial load
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parents:
diff changeset
339 } // End of is two-adr
a61af66fc99e Initial load
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parents:
diff changeset
340
a61af66fc99e Initial load
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parents:
diff changeset
341 // Insert a copy at a debug use for a lrg which has high frequency
12171
4b078f877b56 8023988: Move local scheduling of nodes to the CFG creation and code motion phase (PhaseCFG)
adlertz
parents: 12167
diff changeset
342 if (b->_freq < OPTO_DEBUG_SPLIT_FREQ || _phc._cfg.is_uncommon(b)) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
343 // Walk the debug inputs to the node and check for lrg freq
a61af66fc99e Initial load
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parents:
diff changeset
344 JVMState* jvms = n->jvms();
a61af66fc99e Initial load
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parents:
diff changeset
345 uint debug_start = jvms ? jvms->debug_start() : 999999;
a61af66fc99e Initial load
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parents:
diff changeset
346 uint debug_end = jvms ? jvms->debug_end() : 999999;
a61af66fc99e Initial load
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parents:
diff changeset
347 for(uint inpidx = debug_start; inpidx < debug_end; inpidx++) {
a61af66fc99e Initial load
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parents:
diff changeset
348 // Do not split monitors; they are only needed for debug table
a61af66fc99e Initial load
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parents:
diff changeset
349 // entries and need no code.
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
350 if (jvms->is_monitor_use(inpidx)) {
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
351 continue;
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
352 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
353 Node *inp = n->in(inpidx);
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
354 uint nidx = _phc._lrg_map.live_range_id(inp);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
355 LRG &lrg = lrgs(nidx);
a61af66fc99e Initial load
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parents:
diff changeset
356
a61af66fc99e Initial load
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parents:
diff changeset
357 // If this lrg has a high frequency use/def
673
fbc12e71c476 6810845: Performance regression in mpegaudio on x64
kvn
parents: 605
diff changeset
358 if( lrg._maxfreq >= _phc.high_frequency_lrg() ) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
359 // If the live range is also live out of this block (like it
a61af66fc99e Initial load
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parents:
diff changeset
360 // would be for a fast/slow idiom), the normal spill mechanism
a61af66fc99e Initial load
duke
parents:
diff changeset
361 // does an excellent job. If it is not live out of this block
a61af66fc99e Initial load
duke
parents:
diff changeset
362 // (like it would be for debug info to uncommon trap) splitting
a61af66fc99e Initial load
duke
parents:
diff changeset
363 // the live range now allows a better allocation in the high
a61af66fc99e Initial load
duke
parents:
diff changeset
364 // frequency blocks.
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365 // Build_IFG_virtual has converted the live sets to
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366 // live-IN info, not live-OUT info.
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367 uint k;
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368 for( k=0; k < b->_num_succs; k++ )
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369 if( _phc._live->live(b->_succs[k])->member( nidx ) )
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370 break; // Live in to some successor block?
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371 if( k < b->_num_succs )
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372 continue; // Live out; do not pre-split
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373 // Split the lrg at this use
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374 const RegMask *rm = C->matcher()->idealreg2spillmask[inp->ideal_reg()];
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375 Node *copy = new (C) MachSpillCopyNode( inp, *rm, *rm );
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376 // Insert the copy in the use-def chain
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377 n->set_req(inpidx, copy );
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378 // Insert the copy in the basic block, just before us
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379 b->insert_node(copy, l++);
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380 // Extend ("register allocate") the names array for the copy.
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381 uint max_lrg_id = _phc._lrg_map.max_lrg_id();
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382 _phc.new_lrg(copy, max_lrg_id);
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383 _phc._lrg_map.set_max_lrg_id(max_lrg_id + 1);
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384 _phc._cfg.map_node_to_block(copy, b);
0
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385 //tty->print_cr("Split a debug use in Aggressive Coalesce");
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386 } // End of if high frequency use/def
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387 } // End of for all debug inputs
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388 } // End of if low frequency safepoint
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389
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390 } // End of if Phi
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391
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392 } // End of for all instructions
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393 } // End of for all blocks
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394 }
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395
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396
0
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397 // Aggressive (but pessimistic) copy coalescing of a single block
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398
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399 // The following coalesce pass represents a single round of aggressive
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400 // pessimistic coalesce. "Aggressive" means no attempt to preserve
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401 // colorability when coalescing. This occasionally means more spills, but
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402 // it also means fewer rounds of coalescing for better code - and that means
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403 // faster compiles.
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404
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405 // "Pessimistic" means we do not hit the fixed point in one pass (and we are
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406 // reaching for the least fixed point to boot). This is typically solved
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407 // with a few more rounds of coalescing, but the compiler must run fast. We
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408 // could optimistically coalescing everything touching PhiNodes together
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409 // into one big live range, then check for self-interference. Everywhere
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410 // the live range interferes with self it would have to be split. Finding
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411 // the right split points can be done with some heuristics (based on
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412 // expected frequency of edges in the live range). In short, it's a real
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413 // research problem and the timeline is too short to allow such research.
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414 // Further thoughts: (1) build the LR in a pass, (2) find self-interference
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415 // in another pass, (3) per each self-conflict, split, (4) split by finding
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416 // the low-cost cut (min-cut) of the LR, (5) edges in the LR are weighted
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417 // according to the GCM algorithm (or just exec freq on CFG edges).
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418
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419 void PhaseAggressiveCoalesce::coalesce( Block *b ) {
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420 // Copies are still "virtual" - meaning we have not made them explicitly
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421 // copies. Instead, Phi functions of successor blocks have mis-matched
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422 // live-ranges. If I fail to coalesce, I'll have to insert a copy to line
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423 // up the live-ranges. Check for Phis in successor blocks.
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424 uint i;
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425 for( i=0; i<b->_num_succs; i++ ) {
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426 Block *bs = b->_succs[i];
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parents:
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427 // Find index of 'b' in 'bs' predecessors
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428 uint j=1;
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d1034bd8cefc 8022284: Hide internal data structure in PhaseCFG
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429 while (_phc._cfg.get_block_for_node(bs->pred(j)) != b) {
d1034bd8cefc 8022284: Hide internal data structure in PhaseCFG
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diff changeset
430 j++;
d1034bd8cefc 8022284: Hide internal data structure in PhaseCFG
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431 }
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432
0
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diff changeset
433 // Visit all the Phis in successor block
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434 for( uint k = 1; k<bs->number_of_nodes(); k++ ) {
650868c062a9 8023691: Create interface for nodes in class Block
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435 Node *n = bs->get_node(k);
0
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436 if( !n->is_Phi() ) break;
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437 combine_these_two( n, n->in(j) );
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438 }
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439 } // End of for all successor blocks
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440
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441
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442 // Check _this_ block for 2-address instructions and copies.
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443 uint cnt = b->end_idx();
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444 for( i = 1; i<cnt; i++ ) {
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diff changeset
445 Node *n = b->get_node(i);
0
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446 uint idx;
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447 // 2-address instructions have a virtual Copy matching their input
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448 // to their output
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449 if (n->is_Mach() && (idx = n->as_Mach()->two_adr())) {
0
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450 MachNode *mach = n->as_Mach();
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451 combine_these_two(mach, mach->in(idx));
0
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452 }
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453 } // End of for all instructions in block
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454 }
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455
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456 PhaseConservativeCoalesce::PhaseConservativeCoalesce(PhaseChaitin &chaitin) : PhaseCoalesce(chaitin) {
8373c19be854 8011621: live_ranges_in_separate_class.patch
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457 _ulr.initialize(_phc._lrg_map.max_lrg_id());
0
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458 }
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459
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460 void PhaseConservativeCoalesce::verify() {
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461 #ifdef ASSERT
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462 _phc.set_was_low();
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463 #endif
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464 }
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465
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466 void PhaseConservativeCoalesce::union_helper( Node *lr1_node, Node *lr2_node, uint lr1, uint lr2, Node *src_def, Node *dst_copy, Node *src_copy, Block *b, uint bindex ) {
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467 // Join live ranges. Merge larger into smaller. Union lr2 into lr1 in the
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468 // union-find tree
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469 _phc.Union( lr1_node, lr2_node );
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470
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471 // Single-def live range ONLY if both live ranges are single-def.
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472 // If both are single def, then src_def powers one live range
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473 // and def_copy powers the other. After merging, src_def powers
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474 // the combined live range.
295
ea18057223c4 6732194: Data corruption dependent on -server/-client/-Xbatch
never
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475 lrgs(lr1)._def = (lrgs(lr1).is_multidef() ||
ea18057223c4 6732194: Data corruption dependent on -server/-client/-Xbatch
never
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diff changeset
476 lrgs(lr2).is_multidef() )
0
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477 ? NodeSentinel : src_def;
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diff changeset
478 lrgs(lr2)._def = NULL; // No def for lrg 2
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479 lrgs(lr2).Clear(); // Force empty mask for LRG 2
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480 //lrgs(lr2)._size = 0; // Live-range 2 goes dead
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481 lrgs(lr1)._is_oop |= lrgs(lr2)._is_oop;
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482 lrgs(lr2)._is_oop = 0; // In particular, not an oop for GC info
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483
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484 if (lrgs(lr1)._maxfreq < lrgs(lr2)._maxfreq)
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485 lrgs(lr1)._maxfreq = lrgs(lr2)._maxfreq;
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486
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487 // Copy original value instead. Intermediate copies go dead, and
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488 // the dst_copy becomes useless.
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diff changeset
489 int didx = dst_copy->is_Copy();
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490 dst_copy->set_req( didx, src_def );
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491 // Add copy to free list
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492 // _phc.free_spillcopy(b->_nodes[bindex]);
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diff changeset
493 assert( b->get_node(bindex) == dst_copy, "" );
0
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494 dst_copy->replace_by( dst_copy->in(didx) );
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495 dst_copy->set_req( didx, NULL);
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650868c062a9 8023691: Create interface for nodes in class Block
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diff changeset
496 b->remove_node(bindex);
0
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diff changeset
497 if( bindex < b->_ihrp_index ) b->_ihrp_index--;
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diff changeset
498 if( bindex < b->_fhrp_index ) b->_fhrp_index--;
a61af66fc99e Initial load
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499
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diff changeset
500 // Stretched lr1; add it to liveness of intermediate blocks
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diff changeset
501 Block *b2 = _phc._cfg.get_block_for_node(src_copy);
0
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parents:
diff changeset
502 while( b != b2 ) {
12023
d1034bd8cefc 8022284: Hide internal data structure in PhaseCFG
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diff changeset
503 b = _phc._cfg.get_block_for_node(b->pred(1));
0
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504 _phc._live->live(b)->insert(lr1);
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505 }
a61af66fc99e Initial load
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diff changeset
506 }
a61af66fc99e Initial load
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507
a61af66fc99e Initial load
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diff changeset
508 // Factored code from copy_copy that computes extra interferences from
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509 // lengthening a live range by double-coalescing.
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510 uint PhaseConservativeCoalesce::compute_separating_interferences(Node *dst_copy, Node *src_copy, Block *b, uint bindex, RegMask &rm, uint reg_degree, uint rm_size, uint lr1, uint lr2 ) {
a61af66fc99e Initial load
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parents:
diff changeset
511
a61af66fc99e Initial load
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parents:
diff changeset
512 assert(!lrgs(lr1)._fat_proj, "cannot coalesce fat_proj");
a61af66fc99e Initial load
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parents:
diff changeset
513 assert(!lrgs(lr2)._fat_proj, "cannot coalesce fat_proj");
a61af66fc99e Initial load
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diff changeset
514 Node *prev_copy = dst_copy->in(dst_copy->is_Copy());
a61af66fc99e Initial load
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515 Block *b2 = b;
a61af66fc99e Initial load
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diff changeset
516 uint bindex2 = bindex;
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517 while( 1 ) {
a61af66fc99e Initial load
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parents:
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518 // Find previous instruction
a61af66fc99e Initial load
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parents:
diff changeset
519 bindex2--; // Chain backwards 1 instruction
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diff changeset
520 while( bindex2 == 0 ) { // At block start, find prior block
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521 assert( b2->num_preds() == 2, "cannot double coalesce across c-flow" );
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diff changeset
522 b2 = _phc._cfg.get_block_for_node(b2->pred(1));
0
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parents:
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523 bindex2 = b2->end_idx()-1;
a61af66fc99e Initial load
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parents:
diff changeset
524 }
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diff changeset
525 // Get prior instruction
12167
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parents: 12075
diff changeset
526 assert(bindex2 < b2->number_of_nodes(), "index out of bounds");
650868c062a9 8023691: Create interface for nodes in class Block
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parents: 12075
diff changeset
527 Node *x = b2->get_node(bindex2);
0
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parents:
diff changeset
528 if( x == prev_copy ) { // Previous copy in copy chain?
a61af66fc99e Initial load
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diff changeset
529 if( prev_copy == src_copy)// Found end of chain and all interferences
a61af66fc99e Initial load
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parents:
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530 break; // So break out of loop
a61af66fc99e Initial load
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parents:
diff changeset
531 // Else work back one in copy chain
a61af66fc99e Initial load
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diff changeset
532 prev_copy = prev_copy->in(prev_copy->is_Copy());
a61af66fc99e Initial load
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diff changeset
533 } else { // Else collect interferences
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
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diff changeset
534 uint lidx = _phc._lrg_map.find(x);
0
a61af66fc99e Initial load
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parents:
diff changeset
535 // Found another def of live-range being stretched?
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
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parents: 3842
diff changeset
536 if(lidx == lr1) {
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
537 return max_juint;
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
538 }
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
539 if(lidx == lr2) {
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
540 return max_juint;
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
541 }
0
a61af66fc99e Initial load
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parents:
diff changeset
542
a61af66fc99e Initial load
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parents:
diff changeset
543 // If we attempt to coalesce across a bound def
a61af66fc99e Initial load
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parents:
diff changeset
544 if( lrgs(lidx).is_bound() ) {
a61af66fc99e Initial load
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parents:
diff changeset
545 // Do not let the coalesced LRG expect to get the bound color
a61af66fc99e Initial load
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parents:
diff changeset
546 rm.SUBTRACT( lrgs(lidx).mask() );
a61af66fc99e Initial load
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parents:
diff changeset
547 // Recompute rm_size
a61af66fc99e Initial load
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parents:
diff changeset
548 rm_size = rm.Size();
a61af66fc99e Initial load
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parents:
diff changeset
549 //if( rm._flags ) rm_size += 1000000;
a61af66fc99e Initial load
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parents:
diff changeset
550 if( reg_degree >= rm_size ) return max_juint;
a61af66fc99e Initial load
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parents:
diff changeset
551 }
a61af66fc99e Initial load
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parents:
diff changeset
552 if( rm.overlap(lrgs(lidx).mask()) ) {
a61af66fc99e Initial load
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parents:
diff changeset
553 // Insert lidx into union LRG; returns TRUE if actually inserted
a61af66fc99e Initial load
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parents:
diff changeset
554 if( _ulr.insert(lidx) ) {
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parents:
diff changeset
555 // Infinite-stack neighbors do not alter colorability, as they
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parents:
diff changeset
556 // can always color to some other color.
a61af66fc99e Initial load
duke
parents:
diff changeset
557 if( !lrgs(lidx).mask().is_AllStack() ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
558 // If this coalesce will make any new neighbor uncolorable,
a61af66fc99e Initial load
duke
parents:
diff changeset
559 // do not coalesce.
a61af66fc99e Initial load
duke
parents:
diff changeset
560 if( lrgs(lidx).just_lo_degree() )
a61af66fc99e Initial load
duke
parents:
diff changeset
561 return max_juint;
a61af66fc99e Initial load
duke
parents:
diff changeset
562 // Bump our degree
a61af66fc99e Initial load
duke
parents:
diff changeset
563 if( ++reg_degree >= rm_size )
a61af66fc99e Initial load
duke
parents:
diff changeset
564 return max_juint;
a61af66fc99e Initial load
duke
parents:
diff changeset
565 } // End of if not infinite-stack neighbor
a61af66fc99e Initial load
duke
parents:
diff changeset
566 } // End of if actually inserted
a61af66fc99e Initial load
duke
parents:
diff changeset
567 } // End of if live range overlaps
605
98cb887364d3 6810672: Comment typos
twisti
parents: 337
diff changeset
568 } // End of else collect interferences for 1 node
98cb887364d3 6810672: Comment typos
twisti
parents: 337
diff changeset
569 } // End of while forever, scan back for interferences
0
a61af66fc99e Initial load
duke
parents:
diff changeset
570 return reg_degree;
a61af66fc99e Initial load
duke
parents:
diff changeset
571 }
a61af66fc99e Initial load
duke
parents:
diff changeset
572
a61af66fc99e Initial load
duke
parents:
diff changeset
573 void PhaseConservativeCoalesce::update_ifg(uint lr1, uint lr2, IndexSet *n_lr1, IndexSet *n_lr2) {
a61af66fc99e Initial load
duke
parents:
diff changeset
574 // Some original neighbors of lr1 might have gone away
a61af66fc99e Initial load
duke
parents:
diff changeset
575 // because the constrained register mask prevented them.
a61af66fc99e Initial load
duke
parents:
diff changeset
576 // Remove lr1 from such neighbors.
a61af66fc99e Initial load
duke
parents:
diff changeset
577 IndexSetIterator one(n_lr1);
a61af66fc99e Initial load
duke
parents:
diff changeset
578 uint neighbor;
a61af66fc99e Initial load
duke
parents:
diff changeset
579 LRG &lrg1 = lrgs(lr1);
a61af66fc99e Initial load
duke
parents:
diff changeset
580 while ((neighbor = one.next()) != 0)
a61af66fc99e Initial load
duke
parents:
diff changeset
581 if( !_ulr.member(neighbor) )
a61af66fc99e Initial load
duke
parents:
diff changeset
582 if( _phc._ifg->neighbors(neighbor)->remove(lr1) )
a61af66fc99e Initial load
duke
parents:
diff changeset
583 lrgs(neighbor).inc_degree( -lrg1.compute_degree(lrgs(neighbor)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
584
a61af66fc99e Initial load
duke
parents:
diff changeset
585
a61af66fc99e Initial load
duke
parents:
diff changeset
586 // lr2 is now called (coalesced into) lr1.
a61af66fc99e Initial load
duke
parents:
diff changeset
587 // Remove lr2 from the IFG.
a61af66fc99e Initial load
duke
parents:
diff changeset
588 IndexSetIterator two(n_lr2);
a61af66fc99e Initial load
duke
parents:
diff changeset
589 LRG &lrg2 = lrgs(lr2);
a61af66fc99e Initial load
duke
parents:
diff changeset
590 while ((neighbor = two.next()) != 0)
a61af66fc99e Initial load
duke
parents:
diff changeset
591 if( _phc._ifg->neighbors(neighbor)->remove(lr2) )
a61af66fc99e Initial load
duke
parents:
diff changeset
592 lrgs(neighbor).inc_degree( -lrg2.compute_degree(lrgs(neighbor)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
593
a61af66fc99e Initial load
duke
parents:
diff changeset
594 // Some neighbors of intermediate copies now interfere with the
a61af66fc99e Initial load
duke
parents:
diff changeset
595 // combined live range.
a61af66fc99e Initial load
duke
parents:
diff changeset
596 IndexSetIterator three(&_ulr);
a61af66fc99e Initial load
duke
parents:
diff changeset
597 while ((neighbor = three.next()) != 0)
a61af66fc99e Initial load
duke
parents:
diff changeset
598 if( _phc._ifg->neighbors(neighbor)->insert(lr1) )
a61af66fc99e Initial load
duke
parents:
diff changeset
599 lrgs(neighbor).inc_degree( lrg1.compute_degree(lrgs(neighbor)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
600 }
a61af66fc99e Initial load
duke
parents:
diff changeset
601
a61af66fc99e Initial load
duke
parents:
diff changeset
602 static void record_bias( const PhaseIFG *ifg, int lr1, int lr2 ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
603 // Tag copy bias here
a61af66fc99e Initial load
duke
parents:
diff changeset
604 if( !ifg->lrgs(lr1)._copy_bias )
a61af66fc99e Initial load
duke
parents:
diff changeset
605 ifg->lrgs(lr1)._copy_bias = lr2;
a61af66fc99e Initial load
duke
parents:
diff changeset
606 if( !ifg->lrgs(lr2)._copy_bias )
a61af66fc99e Initial load
duke
parents:
diff changeset
607 ifg->lrgs(lr2)._copy_bias = lr1;
a61af66fc99e Initial load
duke
parents:
diff changeset
608 }
a61af66fc99e Initial load
duke
parents:
diff changeset
609
a61af66fc99e Initial load
duke
parents:
diff changeset
610 // See if I can coalesce a series of multiple copies together. I need the
a61af66fc99e Initial load
duke
parents:
diff changeset
611 // final dest copy and the original src copy. They can be the same Node.
a61af66fc99e Initial load
duke
parents:
diff changeset
612 // Compute the compatible register masks.
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
613 bool PhaseConservativeCoalesce::copy_copy(Node *dst_copy, Node *src_copy, Block *b, uint bindex) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
614
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
615 if (!dst_copy->is_SpillCopy()) {
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
616 return false;
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
617 }
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
618 if (!src_copy->is_SpillCopy()) {
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
619 return false;
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
620 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
621 Node *src_def = src_copy->in(src_copy->is_Copy());
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
622 uint lr1 = _phc._lrg_map.find(dst_copy);
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
623 uint lr2 = _phc._lrg_map.find(src_def);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
624
a61af66fc99e Initial load
duke
parents:
diff changeset
625 // Same live ranges already?
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
626 if (lr1 == lr2) {
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
627 return false;
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
628 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
629
a61af66fc99e Initial load
duke
parents:
diff changeset
630 // Interfere?
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
631 if (_phc._ifg->test_edge_sq(lr1, lr2)) {
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
632 return false;
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
633 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
634
a61af66fc99e Initial load
duke
parents:
diff changeset
635 // Not an oop->int cast; oop->oop, int->int, AND int->oop are OK.
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
636 if (!lrgs(lr1)._is_oop && lrgs(lr2)._is_oop) { // not an oop->int cast
0
a61af66fc99e Initial load
duke
parents:
diff changeset
637 return false;
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
638 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
639
a61af66fc99e Initial load
duke
parents:
diff changeset
640 // Coalescing between an aligned live range and a mis-aligned live range?
a61af66fc99e Initial load
duke
parents:
diff changeset
641 // No, no! Alignment changes how we count degree.
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
642 if (lrgs(lr1)._fat_proj != lrgs(lr2)._fat_proj) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
643 return false;
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
644 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
645
a61af66fc99e Initial load
duke
parents:
diff changeset
646 // Sort; use smaller live-range number
a61af66fc99e Initial load
duke
parents:
diff changeset
647 Node *lr1_node = dst_copy;
a61af66fc99e Initial load
duke
parents:
diff changeset
648 Node *lr2_node = src_def;
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
649 if (lr1 > lr2) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
650 uint tmp = lr1; lr1 = lr2; lr2 = tmp;
a61af66fc99e Initial load
duke
parents:
diff changeset
651 lr1_node = src_def; lr2_node = dst_copy;
a61af66fc99e Initial load
duke
parents:
diff changeset
652 }
a61af66fc99e Initial load
duke
parents:
diff changeset
653
a61af66fc99e Initial load
duke
parents:
diff changeset
654 // Check for compatibility of the 2 live ranges by
a61af66fc99e Initial load
duke
parents:
diff changeset
655 // intersecting their allowed register sets.
a61af66fc99e Initial load
duke
parents:
diff changeset
656 RegMask rm = lrgs(lr1).mask();
a61af66fc99e Initial load
duke
parents:
diff changeset
657 rm.AND(lrgs(lr2).mask());
a61af66fc99e Initial load
duke
parents:
diff changeset
658 // Number of bits free
a61af66fc99e Initial load
duke
parents:
diff changeset
659 uint rm_size = rm.Size();
a61af66fc99e Initial load
duke
parents:
diff changeset
660
1730
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 1552
diff changeset
661 if (UseFPUForSpilling && rm.is_AllStack() ) {
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 1552
diff changeset
662 // Don't coalesce when frequency difference is large
12023
d1034bd8cefc 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 10999
diff changeset
663 Block *dst_b = _phc._cfg.get_block_for_node(dst_copy);
d1034bd8cefc 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 10999
diff changeset
664 Block *src_def_b = _phc._cfg.get_block_for_node(src_def);
1730
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 1552
diff changeset
665 if (src_def_b->_freq > 10*dst_b->_freq )
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 1552
diff changeset
666 return false;
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 1552
diff changeset
667 }
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 1552
diff changeset
668
0
a61af66fc99e Initial load
duke
parents:
diff changeset
669 // If we can use any stack slot, then effective size is infinite
a61af66fc99e Initial load
duke
parents:
diff changeset
670 if( rm.is_AllStack() ) rm_size += 1000000;
a61af66fc99e Initial load
duke
parents:
diff changeset
671 // Incompatible masks, no way to coalesce
a61af66fc99e Initial load
duke
parents:
diff changeset
672 if( rm_size == 0 ) return false;
a61af66fc99e Initial load
duke
parents:
diff changeset
673
a61af66fc99e Initial load
duke
parents:
diff changeset
674 // Another early bail-out test is when we are double-coalescing and the
605
98cb887364d3 6810672: Comment typos
twisti
parents: 337
diff changeset
675 // 2 copies are separated by some control flow.
0
a61af66fc99e Initial load
duke
parents:
diff changeset
676 if( dst_copy != src_copy ) {
12023
d1034bd8cefc 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 10999
diff changeset
677 Block *src_b = _phc._cfg.get_block_for_node(src_copy);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
678 Block *b2 = b;
a61af66fc99e Initial load
duke
parents:
diff changeset
679 while( b2 != src_b ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
680 if( b2->num_preds() > 2 ){// Found merge-point
a61af66fc99e Initial load
duke
parents:
diff changeset
681 _phc._lost_opp_cflow_coalesce++;
a61af66fc99e Initial load
duke
parents:
diff changeset
682 // extra record_bias commented out because Chris believes it is not
a61af66fc99e Initial load
duke
parents:
diff changeset
683 // productive. Since we can record only 1 bias, we want to choose one
a61af66fc99e Initial load
duke
parents:
diff changeset
684 // that stands a chance of working and this one probably does not.
a61af66fc99e Initial load
duke
parents:
diff changeset
685 //record_bias( _phc._lrgs, lr1, lr2 );
a61af66fc99e Initial load
duke
parents:
diff changeset
686 return false; // To hard to find all interferences
a61af66fc99e Initial load
duke
parents:
diff changeset
687 }
12023
d1034bd8cefc 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 10999
diff changeset
688 b2 = _phc._cfg.get_block_for_node(b2->pred(1));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
689 }
a61af66fc99e Initial load
duke
parents:
diff changeset
690 }
a61af66fc99e Initial load
duke
parents:
diff changeset
691
a61af66fc99e Initial load
duke
parents:
diff changeset
692 // Union the two interference sets together into '_ulr'
a61af66fc99e Initial load
duke
parents:
diff changeset
693 uint reg_degree = _ulr.lrg_union( lr1, lr2, rm_size, _phc._ifg, rm );
a61af66fc99e Initial load
duke
parents:
diff changeset
694
a61af66fc99e Initial load
duke
parents:
diff changeset
695 if( reg_degree >= rm_size ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
696 record_bias( _phc._ifg, lr1, lr2 );
a61af66fc99e Initial load
duke
parents:
diff changeset
697 return false;
a61af66fc99e Initial load
duke
parents:
diff changeset
698 }
a61af66fc99e Initial load
duke
parents:
diff changeset
699
a61af66fc99e Initial load
duke
parents:
diff changeset
700 // Now I need to compute all the interferences between dst_copy and
a61af66fc99e Initial load
duke
parents:
diff changeset
701 // src_copy. I'm not willing visit the entire interference graph, so
a61af66fc99e Initial load
duke
parents:
diff changeset
702 // I limit my search to things in dst_copy's block or in a straight
a61af66fc99e Initial load
duke
parents:
diff changeset
703 // line of previous blocks. I give up at merge points or when I get
a61af66fc99e Initial load
duke
parents:
diff changeset
704 // more interferences than my degree. I can stop when I find src_copy.
a61af66fc99e Initial load
duke
parents:
diff changeset
705 if( dst_copy != src_copy ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
706 reg_degree = compute_separating_interferences(dst_copy, src_copy, b, bindex, rm, rm_size, reg_degree, lr1, lr2 );
a61af66fc99e Initial load
duke
parents:
diff changeset
707 if( reg_degree == max_juint ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
708 record_bias( _phc._ifg, lr1, lr2 );
a61af66fc99e Initial load
duke
parents:
diff changeset
709 return false;
a61af66fc99e Initial load
duke
parents:
diff changeset
710 }
a61af66fc99e Initial load
duke
parents:
diff changeset
711 } // End of if dst_copy & src_copy are different
a61af66fc99e Initial load
duke
parents:
diff changeset
712
a61af66fc99e Initial load
duke
parents:
diff changeset
713
a61af66fc99e Initial load
duke
parents:
diff changeset
714 // ---- THE COMBINED LRG IS COLORABLE ----
a61af66fc99e Initial load
duke
parents:
diff changeset
715
a61af66fc99e Initial load
duke
parents:
diff changeset
716 // YEAH - Now coalesce this copy away
a61af66fc99e Initial load
duke
parents:
diff changeset
717 assert( lrgs(lr1).num_regs() == lrgs(lr2).num_regs(), "" );
a61af66fc99e Initial load
duke
parents:
diff changeset
718
a61af66fc99e Initial load
duke
parents:
diff changeset
719 IndexSet *n_lr1 = _phc._ifg->neighbors(lr1);
a61af66fc99e Initial load
duke
parents:
diff changeset
720 IndexSet *n_lr2 = _phc._ifg->neighbors(lr2);
a61af66fc99e Initial load
duke
parents:
diff changeset
721
a61af66fc99e Initial load
duke
parents:
diff changeset
722 // Update the interference graph
a61af66fc99e Initial load
duke
parents:
diff changeset
723 update_ifg(lr1, lr2, n_lr1, n_lr2);
a61af66fc99e Initial load
duke
parents:
diff changeset
724
a61af66fc99e Initial load
duke
parents:
diff changeset
725 _ulr.remove(lr1);
a61af66fc99e Initial load
duke
parents:
diff changeset
726
a61af66fc99e Initial load
duke
parents:
diff changeset
727 // Uncomment the following code to trace Coalescing in great detail.
a61af66fc99e Initial load
duke
parents:
diff changeset
728 //
a61af66fc99e Initial load
duke
parents:
diff changeset
729 //if (false) {
a61af66fc99e Initial load
duke
parents:
diff changeset
730 // tty->cr();
a61af66fc99e Initial load
duke
parents:
diff changeset
731 // tty->print_cr("#######################################");
a61af66fc99e Initial load
duke
parents:
diff changeset
732 // tty->print_cr("union %d and %d", lr1, lr2);
a61af66fc99e Initial load
duke
parents:
diff changeset
733 // n_lr1->dump();
a61af66fc99e Initial load
duke
parents:
diff changeset
734 // n_lr2->dump();
a61af66fc99e Initial load
duke
parents:
diff changeset
735 // tty->print_cr("resulting set is");
a61af66fc99e Initial load
duke
parents:
diff changeset
736 // _ulr.dump();
a61af66fc99e Initial load
duke
parents:
diff changeset
737 //}
a61af66fc99e Initial load
duke
parents:
diff changeset
738
a61af66fc99e Initial load
duke
parents:
diff changeset
739 // Replace n_lr1 with the new combined live range. _ulr will use
a61af66fc99e Initial load
duke
parents:
diff changeset
740 // n_lr1's old memory on the next iteration. n_lr2 is cleared to
a61af66fc99e Initial load
duke
parents:
diff changeset
741 // send its internal memory to the free list.
a61af66fc99e Initial load
duke
parents:
diff changeset
742 _ulr.swap(n_lr1);
a61af66fc99e Initial load
duke
parents:
diff changeset
743 _ulr.clear();
a61af66fc99e Initial load
duke
parents:
diff changeset
744 n_lr2->clear();
a61af66fc99e Initial load
duke
parents:
diff changeset
745
a61af66fc99e Initial load
duke
parents:
diff changeset
746 lrgs(lr1).set_degree( _phc._ifg->effective_degree(lr1) );
a61af66fc99e Initial load
duke
parents:
diff changeset
747 lrgs(lr2).set_degree( 0 );
a61af66fc99e Initial load
duke
parents:
diff changeset
748
a61af66fc99e Initial load
duke
parents:
diff changeset
749 // Join live ranges. Merge larger into smaller. Union lr2 into lr1 in the
a61af66fc99e Initial load
duke
parents:
diff changeset
750 // union-find tree
a61af66fc99e Initial load
duke
parents:
diff changeset
751 union_helper( lr1_node, lr2_node, lr1, lr2, src_def, dst_copy, src_copy, b, bindex );
a61af66fc99e Initial load
duke
parents:
diff changeset
752 // Combine register restrictions
a61af66fc99e Initial load
duke
parents:
diff changeset
753 lrgs(lr1).set_mask(rm);
a61af66fc99e Initial load
duke
parents:
diff changeset
754 lrgs(lr1).compute_set_mask_size();
a61af66fc99e Initial load
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parents:
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755 lrgs(lr1)._cost += lrgs(lr2)._cost;
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parents:
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756 lrgs(lr1)._area += lrgs(lr2)._area;
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parents:
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757
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parents:
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758 // While its uncommon to successfully coalesce live ranges that started out
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parents:
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759 // being not-lo-degree, it can happen. In any case the combined coalesced
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parents:
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760 // live range better Simplify nicely.
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761 lrgs(lr1)._was_lo = 1;
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parents:
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762
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parents:
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763 // kinda expensive to do all the time
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parents:
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764 //tty->print_cr("warning: slow verify happening");
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parents:
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765 //_phc._ifg->verify( &_phc );
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766 return true;
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parents:
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767 }
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parents:
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768
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parents:
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769 // Conservative (but pessimistic) copy coalescing of a single block
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parents:
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770 void PhaseConservativeCoalesce::coalesce( Block *b ) {
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parents:
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771 // Bail out on infrequent blocks
12171
4b078f877b56 8023988: Move local scheduling of nodes to the CFG creation and code motion phase (PhaseCFG)
adlertz
parents: 12167
diff changeset
772 if (_phc._cfg.is_uncommon(b)) {
0
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parents:
diff changeset
773 return;
12023
d1034bd8cefc 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 10999
diff changeset
774 }
0
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parents:
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775 // Check this block for copies.
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parents:
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776 for( uint i = 1; i<b->end_idx(); i++ ) {
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parents:
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777 // Check for actual copies on inputs. Coalesce a copy into its
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parents:
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778 // input if use and copy's input are compatible.
12167
650868c062a9 8023691: Create interface for nodes in class Block
adlertz
parents: 12075
diff changeset
779 Node *copy1 = b->get_node(i);
0
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parents:
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780 uint idx1 = copy1->is_Copy();
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781 if( !idx1 ) continue; // Not a copy
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parents:
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782
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parents:
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783 if( copy_copy(copy1,copy1,b,i) ) {
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parents:
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784 i--; // Retry, same location in block
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parents:
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785 PhaseChaitin::_conserv_coalesce++; // Collect stats on success
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parents:
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786 continue;
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parents:
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787 }
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parents:
diff changeset
788 }
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parents:
diff changeset
789 }