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1 /*
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2 * Copyright 1997-2006 Sun Microsystems, Inc. All Rights Reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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20 * CA 95054 USA or visit www.sun.com if you need additional information or
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21 * have any questions.
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22 *
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23 */
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24
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25 inline void MacroAssembler::pd_patch_instruction(address branch, address target) {
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26 jint& stub_inst = *(jint*) branch;
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27 stub_inst = patched_branch(target - branch, stub_inst, 0);
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28 }
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29
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30 #ifndef PRODUCT
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31 inline void MacroAssembler::pd_print_patched_instruction(address branch) {
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32 jint stub_inst = *(jint*) branch;
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33 print_instruction(stub_inst);
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34 ::tty->print("%s", " (unresolved)");
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35 }
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36 #endif // PRODUCT
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37
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38 inline bool Address::is_simm13(int offset) { return Assembler::is_simm13(disp() + offset); }
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39
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40
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41 // inlines for SPARC assembler -- dmu 5/97
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42
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43 inline void Assembler::check_delay() {
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44 # ifdef CHECK_DELAY
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45 guarantee( delay_state != at_delay_slot, "must say delayed() when filling delay slot");
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46 delay_state = no_delay;
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47 # endif
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48 }
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49
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50 inline void Assembler::emit_long(int x) {
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51 check_delay();
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52 AbstractAssembler::emit_long(x);
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53 }
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54
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55 inline void Assembler::emit_data(int x, relocInfo::relocType rtype) {
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56 relocate(rtype);
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57 emit_long(x);
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58 }
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59
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60 inline void Assembler::emit_data(int x, RelocationHolder const& rspec) {
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61 relocate(rspec);
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62 emit_long(x);
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63 }
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64
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65
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66 inline void Assembler::add( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | rs2(s2) ); }
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67 inline void Assembler::add( Register s1, int simm13a, Register d, relocInfo::relocType rtype ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rtype ); }
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68 inline void Assembler::add( Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec ); }
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69 inline void Assembler::add( const Address& a, Register d, int offset) { add( a.base(), a.disp() + offset, d, a.rspec(offset)); }
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70
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71 inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt ) { v9_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(bpr_op2) | wdisp16(intptr_t(d), intptr_t(pc())) | predict(p) | rs1(s1), rt); has_delay_slot(); }
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72 inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, Label& L) { bpr( c, a, p, s1, target(L)); }
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73
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74 inline void Assembler::fb( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(fb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); }
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75 inline void Assembler::fb( Condition c, bool a, Label& L ) { fb(c, a, target(L)); }
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76
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77 inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(fbp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); has_delay_slot(); }
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78 inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) { fbp(c, a, cc, p, target(L)); }
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79
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80 inline void Assembler::cb( Condition c, bool a, address d, relocInfo::relocType rt ) { v8_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(cb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); }
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81 inline void Assembler::cb( Condition c, bool a, Label& L ) { cb(c, a, target(L)); }
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82
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83 inline void Assembler::br( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(br_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); }
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84 inline void Assembler::br( Condition c, bool a, Label& L ) { br(c, a, target(L)); }
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85
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86 inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(bp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); has_delay_slot(); }
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87 inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) { bp(c, a, cc, p, target(L)); }
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88
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89 inline void Assembler::call( address d, relocInfo::relocType rt ) { emit_data( op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rt); has_delay_slot(); assert(rt != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec"); }
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90 inline void Assembler::call( Label& L, relocInfo::relocType rt ) { call( target(L), rt); }
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91
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92 inline void Assembler::flush( Register s1, Register s2) { emit_long( op(arith_op) | op3(flush_op3) | rs1(s1) | rs2(s2)); }
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93 inline void Assembler::flush( Register s1, int simm13a) { emit_data( op(arith_op) | op3(flush_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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94
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95 inline void Assembler::jmpl( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | rs2(s2)); has_delay_slot(); }
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96 inline void Assembler::jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); has_delay_slot(); }
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97
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98 inline void Assembler::jmpl( Address& a, Register d, int offset) { jmpl( a.base(), a.disp() + offset, d, a.rspec(offset)); }
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99
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100
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101 inline void Assembler::ldf( FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | rs2(s2) ); }
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102 inline void Assembler::ldf( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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103
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104 inline void Assembler::ldf( FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset) { relocate(a.rspec(offset)); ldf( w, a.base(), a.disp() + offset, d); }
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105
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106 inline void Assembler::ldfsr( Register s1, Register s2) { v9_dep(); emit_long( op(ldst_op) | op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); }
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107 inline void Assembler::ldfsr( Register s1, int simm13a) { v9_dep(); emit_data( op(ldst_op) | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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108 inline void Assembler::ldxfsr( Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); }
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109 inline void Assembler::ldxfsr( Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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110
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111 inline void Assembler::ldc( Register s1, Register s2, int crd) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(ldc_op3 ) | rs1(s1) | rs2(s2) ); }
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112 inline void Assembler::ldc( Register s1, int simm13a, int crd) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(ldc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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113 inline void Assembler::lddc( Register s1, Register s2, int crd) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(lddc_op3 ) | rs1(s1) | rs2(s2) ); }
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114 inline void Assembler::lddc( Register s1, int simm13a, int crd) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(lddc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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115 inline void Assembler::ldcsr( Register s1, Register s2, int crd) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(ldcsr_op3) | rs1(s1) | rs2(s2) ); }
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116 inline void Assembler::ldcsr( Register s1, int simm13a, int crd) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(ldcsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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117
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118 inline void Assembler::ldsb( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | rs2(s2) ); }
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119 inline void Assembler::ldsb( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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120
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121 inline void Assembler::ldsh( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | rs2(s2) ); }
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122 inline void Assembler::ldsh( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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123 inline void Assembler::ldsw( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | rs2(s2) ); }
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124 inline void Assembler::ldsw( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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125 inline void Assembler::ldub( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | rs2(s2) ); }
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126 inline void Assembler::ldub( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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127 inline void Assembler::lduh( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | rs2(s2) ); }
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128 inline void Assembler::lduh( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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129 inline void Assembler::lduw( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | rs2(s2) ); }
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130 inline void Assembler::lduw( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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131
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132 inline void Assembler::ldx( Register s1, Register s2, Register d) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | rs2(s2) ); }
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133 inline void Assembler::ldx( Register s1, int simm13a, Register d) { v9_only(); emit_data( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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134 inline void Assembler::ldd( Register s1, Register s2, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | rs2(s2) ); }
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135 inline void Assembler::ldd( Register s1, int simm13a, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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136
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137 #ifdef _LP64
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138 // Make all 32 bit loads signed so 64 bit registers maintain proper sign
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139 inline void Assembler::ld( Register s1, Register s2, Register d) { ldsw( s1, s2, d); }
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140 inline void Assembler::ld( Register s1, int simm13a, Register d) { ldsw( s1, simm13a, d); }
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141 #else
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142 inline void Assembler::ld( Register s1, Register s2, Register d) { lduw( s1, s2, d); }
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143 inline void Assembler::ld( Register s1, int simm13a, Register d) { lduw( s1, simm13a, d); }
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144 #endif
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145
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146
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147 inline void Assembler::ld( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ld( a.base(), a.disp() + offset, d ); }
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148 inline void Assembler::ldsb( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldsb( a.base(), a.disp() + offset, d ); }
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149 inline void Assembler::ldsh( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldsh( a.base(), a.disp() + offset, d ); }
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150 inline void Assembler::ldsw( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldsw( a.base(), a.disp() + offset, d ); }
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151 inline void Assembler::ldub( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldub( a.base(), a.disp() + offset, d ); }
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152 inline void Assembler::lduh( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); lduh( a.base(), a.disp() + offset, d ); }
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153 inline void Assembler::lduw( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); lduw( a.base(), a.disp() + offset, d ); }
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154 inline void Assembler::ldd( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldd( a.base(), a.disp() + offset, d ); }
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155 inline void Assembler::ldx( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldx( a.base(), a.disp() + offset, d ); }
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156
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157
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158 inline void Assembler::ldstub( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3) | rs1(s1) | rs2(s2) ); }
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159 inline void Assembler::ldstub( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldstub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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160
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161
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162 inline void Assembler::prefetch(Register s1, Register s2, PrefetchFcn f) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); }
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163 inline void Assembler::prefetch(Register s1, int simm13a, PrefetchFcn f) { v9_only(); emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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164
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165 inline void Assembler::prefetch(const Address& a, PrefetchFcn f, int offset) { v9_only(); relocate(a.rspec(offset)); prefetch(a.base(), a.disp() + offset, f); }
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166
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167
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168 inline void Assembler::rett( Register s1, Register s2 ) { emit_long( op(arith_op) | op3(rett_op3) | rs1(s1) | rs2(s2)); has_delay_slot(); }
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169 inline void Assembler::rett( Register s1, int simm13a, relocInfo::relocType rt) { emit_data( op(arith_op) | op3(rett_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rt); has_delay_slot(); }
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170
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171 inline void Assembler::sethi( int imm22a, Register d, RelocationHolder const& rspec ) { emit_data( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(imm22a), rspec); }
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172
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173 // pp 222
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174
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175 inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | rs2(s2) ); }
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176 inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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177
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178 inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset) { relocate(a.rspec(offset)); stf(w, d, a.base(), a.disp() + offset); }
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179
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180 inline void Assembler::stfsr( Register s1, Register s2) { v9_dep(); emit_long( op(ldst_op) | op3(stfsr_op3) | rs1(s1) | rs2(s2) ); }
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181 inline void Assembler::stfsr( Register s1, int simm13a) { v9_dep(); emit_data( op(ldst_op) | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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182 inline void Assembler::stxfsr( Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | rs2(s2) ); }
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183 inline void Assembler::stxfsr( Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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184
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185 // p 226
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186
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187 inline void Assembler::stb( Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | rs2(s2) ); }
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188 inline void Assembler::stb( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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189 inline void Assembler::sth( Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | rs2(s2) ); }
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190 inline void Assembler::sth( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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191 inline void Assembler::stw( Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | rs2(s2) ); }
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192 inline void Assembler::stw( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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193
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194
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195 inline void Assembler::stx( Register d, Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | rs2(s2) ); }
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196 inline void Assembler::stx( Register d, Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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197 inline void Assembler::std( Register d, Register s1, Register s2) { v9_dep(); assert(d->is_even(), "not even"); emit_long( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | rs2(s2) ); }
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198 inline void Assembler::std( Register d, Register s1, int simm13a) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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199
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200 inline void Assembler::st( Register d, Register s1, Register s2) { stw(d, s1, s2); }
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201 inline void Assembler::st( Register d, Register s1, int simm13a) { stw(d, s1, simm13a); }
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202
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203 inline void Assembler::stb( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); stb( d, a.base(), a.disp() + offset); }
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204 inline void Assembler::sth( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); sth( d, a.base(), a.disp() + offset); }
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205 inline void Assembler::stw( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); stw( d, a.base(), a.disp() + offset); }
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206 inline void Assembler::st( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); st( d, a.base(), a.disp() + offset); }
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207 inline void Assembler::std( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); std( d, a.base(), a.disp() + offset); }
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208 inline void Assembler::stx( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); stx( d, a.base(), a.disp() + offset); }
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209
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210 // v8 p 99
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211
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212 inline void Assembler::stc( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stc_op3 ) | rs1(s1) | rs2(s2) ); }
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213 inline void Assembler::stc( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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214 inline void Assembler::stdc( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stdc_op3) | rs1(s1) | rs2(s2) ); }
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215 inline void Assembler::stdc( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stdc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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216 inline void Assembler::stcsr( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stcsr_op3) | rs1(s1) | rs2(s2) ); }
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217 inline void Assembler::stcsr( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stcsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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218 inline void Assembler::stdcq( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stdcq_op3) | rs1(s1) | rs2(s2) ); }
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219 inline void Assembler::stdcq( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stdcq_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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220
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221
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222 // pp 231
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223
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224 inline void Assembler::swap( Register s1, Register s2, Register d) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | rs2(s2) ); }
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225 inline void Assembler::swap( Register s1, int simm13a, Register d) { v9_dep(); emit_data( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
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226
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227 inline void Assembler::swap( Address& a, Register d, int offset ) { relocate(a.rspec(offset)); swap( a.base(), a.disp() + offset, d ); }
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228
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229
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230 // Use the right loads/stores for the platform
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231 inline void MacroAssembler::ld_ptr( Register s1, Register s2, Register d ) {
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232 #ifdef _LP64
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233 Assembler::ldx( s1, s2, d);
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234 #else
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235 Assembler::ld( s1, s2, d);
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236 #endif
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237 }
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238
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239 inline void MacroAssembler::ld_ptr( Register s1, int simm13a, Register d ) {
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240 #ifdef _LP64
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241 Assembler::ldx( s1, simm13a, d);
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242 #else
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243 Assembler::ld( s1, simm13a, d);
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244 #endif
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245 }
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246
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247 inline void MacroAssembler::ld_ptr( const Address& a, Register d, int offset ) {
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248 #ifdef _LP64
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249 Assembler::ldx( a, d, offset );
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250 #else
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251 Assembler::ld( a, d, offset );
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252 #endif
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253 }
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254
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255 inline void MacroAssembler::st_ptr( Register d, Register s1, Register s2 ) {
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256 #ifdef _LP64
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257 Assembler::stx( d, s1, s2);
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258 #else
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259 Assembler::st( d, s1, s2);
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260 #endif
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261 }
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262
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263 inline void MacroAssembler::st_ptr( Register d, Register s1, int simm13a ) {
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264 #ifdef _LP64
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265 Assembler::stx( d, s1, simm13a);
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266 #else
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267 Assembler::st( d, s1, simm13a);
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268 #endif
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269 }
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270
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271 inline void MacroAssembler::st_ptr( Register d, const Address& a, int offset) {
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272 #ifdef _LP64
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273 Assembler::stx( d, a, offset);
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274 #else
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275 Assembler::st( d, a, offset);
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276 #endif
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277 }
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278
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279 // Use the right loads/stores for the platform
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280 inline void MacroAssembler::ld_long( Register s1, Register s2, Register d ) {
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281 #ifdef _LP64
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282 Assembler::ldx(s1, s2, d);
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283 #else
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284 Assembler::ldd(s1, s2, d);
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285 #endif
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286 }
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287
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288 inline void MacroAssembler::ld_long( Register s1, int simm13a, Register d ) {
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289 #ifdef _LP64
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290 Assembler::ldx(s1, simm13a, d);
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291 #else
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292 Assembler::ldd(s1, simm13a, d);
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293 #endif
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294 }
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295
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296 inline void MacroAssembler::ld_long( const Address& a, Register d, int offset ) {
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297 #ifdef _LP64
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298 Assembler::ldx(a, d, offset );
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299 #else
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300 Assembler::ldd(a, d, offset );
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301 #endif
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302 }
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303
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304 inline void MacroAssembler::st_long( Register d, Register s1, Register s2 ) {
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305 #ifdef _LP64
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306 Assembler::stx(d, s1, s2);
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307 #else
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308 Assembler::std(d, s1, s2);
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309 #endif
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310 }
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311
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312 inline void MacroAssembler::st_long( Register d, Register s1, int simm13a ) {
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313 #ifdef _LP64
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314 Assembler::stx(d, s1, simm13a);
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315 #else
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316 Assembler::std(d, s1, simm13a);
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317 #endif
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318 }
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319
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320 inline void MacroAssembler::st_long( Register d, const Address& a, int offset ) {
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321 #ifdef _LP64
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322 Assembler::stx(d, a, offset);
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323 #else
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324 Assembler::std(d, a, offset);
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325 #endif
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326 }
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327
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328 // Functions for isolating 64 bit shifts for LP64
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329
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330 inline void MacroAssembler::sll_ptr( Register s1, Register s2, Register d ) {
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331 #ifdef _LP64
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332 Assembler::sllx(s1, s2, d);
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333 #else
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334 Assembler::sll(s1, s2, d);
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335 #endif
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336 }
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337
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338 inline void MacroAssembler::sll_ptr( Register s1, int imm6a, Register d ) {
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339 #ifdef _LP64
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340 Assembler::sllx(s1, imm6a, d);
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341 #else
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342 Assembler::sll(s1, imm6a, d);
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343 #endif
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344 }
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345
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346 inline void MacroAssembler::srl_ptr( Register s1, Register s2, Register d ) {
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347 #ifdef _LP64
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348 Assembler::srlx(s1, s2, d);
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349 #else
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350 Assembler::srl(s1, s2, d);
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351 #endif
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352 }
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353
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354 inline void MacroAssembler::srl_ptr( Register s1, int imm6a, Register d ) {
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355 #ifdef _LP64
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356 Assembler::srlx(s1, imm6a, d);
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357 #else
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358 Assembler::srl(s1, imm6a, d);
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359 #endif
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360 }
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361
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362 // Use the right branch for the platform
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363
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364 inline void MacroAssembler::br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
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365 if (VM_Version::v9_instructions_work())
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366 Assembler::bp(c, a, icc, p, d, rt);
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367 else
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368 Assembler::br(c, a, d, rt);
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369 }
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370
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371 inline void MacroAssembler::br( Condition c, bool a, Predict p, Label& L ) {
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372 br(c, a, p, target(L));
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373 }
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374
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375
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376 // Branch that tests either xcc or icc depending on the
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377 // architecture compiled (LP64 or not)
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378 inline void MacroAssembler::brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
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379 #ifdef _LP64
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380 Assembler::bp(c, a, xcc, p, d, rt);
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381 #else
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382 MacroAssembler::br(c, a, p, d, rt);
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383 #endif
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384 }
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385
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386 inline void MacroAssembler::brx( Condition c, bool a, Predict p, Label& L ) {
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387 brx(c, a, p, target(L));
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388 }
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389
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390 inline void MacroAssembler::ba( bool a, Label& L ) {
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391 br(always, a, pt, L);
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392 }
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393
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394 // Warning: V9 only functions
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395 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {
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396 Assembler::bp(c, a, cc, p, d, rt);
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397 }
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398
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399 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) {
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400 Assembler::bp(c, a, cc, p, L);
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401 }
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402
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403 inline void MacroAssembler::fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
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404 if (VM_Version::v9_instructions_work())
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405 fbp(c, a, fcc0, p, d, rt);
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406 else
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407 Assembler::fb(c, a, d, rt);
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408 }
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409
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410 inline void MacroAssembler::fb( Condition c, bool a, Predict p, Label& L ) {
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411 fb(c, a, p, target(L));
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412 }
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413
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414 inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {
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415 Assembler::fbp(c, a, cc, p, d, rt);
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416 }
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417
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418 inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) {
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419 Assembler::fbp(c, a, cc, p, L);
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420 }
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421
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422 inline void MacroAssembler::jmp( Register s1, Register s2 ) { jmpl( s1, s2, G0 ); }
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423 inline void MacroAssembler::jmp( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, G0, rspec); }
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424
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425 // Call with a check to see if we need to deal with the added
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|
426 // expense of relocation and if we overflow the displacement
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427 // of the quick call instruction./
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428 // Check to see if we have to deal with relocations
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429 inline void MacroAssembler::call( address d, relocInfo::relocType rt ) {
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430 #ifdef _LP64
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|
431 intptr_t disp;
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|
432 // NULL is ok because it will be relocated later.
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|
433 // Must change NULL to a reachable address in order to
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|
434 // pass asserts here and in wdisp.
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435 if ( d == NULL )
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436 d = pc();
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437
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|
438 // Is this address within range of the call instruction?
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|
439 // If not, use the expensive instruction sequence
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440 disp = (intptr_t)d - (intptr_t)pc();
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441 if ( disp != (intptr_t)(int32_t)disp ) {
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|
442 relocate(rt);
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|
443 Address dest(O7, (address)d);
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|
444 sethi(dest, /*ForceRelocatable=*/ true);
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|
445 jmpl(dest, O7);
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446 }
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|
447 else {
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|
|
448 Assembler::call( d, rt );
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449 }
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|
450 #else
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|
|
451 Assembler::call( d, rt );
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|
452 #endif
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|
453 }
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454
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455 inline void MacroAssembler::call( Label& L, relocInfo::relocType rt ) {
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456 MacroAssembler::call( target(L), rt);
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457 }
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458
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459
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460
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461 inline void MacroAssembler::callr( Register s1, Register s2 ) { jmpl( s1, s2, O7 ); }
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462 inline void MacroAssembler::callr( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, O7, rspec); }
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463
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464 // prefetch instruction
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465 inline void MacroAssembler::iprefetch( address d, relocInfo::relocType rt ) {
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|
|
466 if (VM_Version::v9_instructions_work())
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467 Assembler::bp( never, true, xcc, pt, d, rt );
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|
|
468 }
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|
|
469 inline void MacroAssembler::iprefetch( Label& L) { iprefetch( target(L) ); }
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470
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|
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471
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|
472 // clobbers o7 on V8!!
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|
473 // returns delta from gotten pc to addr after
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|
474 inline int MacroAssembler::get_pc( Register d ) {
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|
475 int x = offset();
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|
|
476 if (VM_Version::v9_instructions_work())
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|
|
477 rdpc(d);
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|
|
478 else {
|
|
|
479 Label lbl;
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|
|
480 Assembler::call(lbl, relocInfo::none); // No relocation as this is call to pc+0x8
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|
|
481 if (d == O7) delayed()->nop();
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|
|
482 else delayed()->mov(O7, d);
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|
|
483 bind(lbl);
|
|
|
484 }
|
|
|
485 return offset() - x;
|
|
|
486 }
|
|
|
487
|
|
|
488
|
|
|
489 // Note: All MacroAssembler::set_foo functions are defined out-of-line.
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|
|
490
|
|
|
491
|
|
|
492 // Loads the current PC of the following instruction as an immediate value in
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|
|
493 // 2 instructions. All PCs in the CodeCache are within 2 Gig of each other.
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|
|
494 inline intptr_t MacroAssembler::load_pc_address( Register reg, int bytes_to_skip ) {
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|
|
495 intptr_t thepc = (intptr_t)pc() + 2*BytesPerInstWord + bytes_to_skip;
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|
|
496 #ifdef _LP64
|
|
|
497 Unimplemented();
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|
|
498 #else
|
|
|
499 Assembler::sethi( thepc & ~0x3ff, reg, internal_word_Relocation::spec((address)thepc));
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|
|
500 Assembler::add(reg,thepc & 0x3ff, reg, internal_word_Relocation::spec((address)thepc));
|
|
|
501 #endif
|
|
|
502 return thepc;
|
|
|
503 }
|
|
|
504
|
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505 inline void MacroAssembler::load_address( Address& a, int offset ) {
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506 assert_not_delayed();
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507 #ifdef _LP64
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508 sethi(a);
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509 add(a, a.base(), offset);
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510 #else
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511 if (a.hi() == 0 && a.rtype() == relocInfo::none) {
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512 set(a.disp() + offset, a.base());
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513 }
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514 else {
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515 sethi(a);
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516 add(a, a.base(), offset);
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517 }
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518 #endif
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519 }
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520
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521
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522 inline void MacroAssembler::split_disp( Address& a, Register temp ) {
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523 assert_not_delayed();
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524 a = a.split_disp();
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525 Assembler::sethi(a.hi(), temp, a.rspec());
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526 add(a.base(), temp, a.base());
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527 }
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528
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529
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530 inline void MacroAssembler::load_contents( Address& a, Register d, int offset ) {
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531 assert_not_delayed();
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532 sethi(a);
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533 ld(a, d, offset);
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534 }
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535
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536
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537 inline void MacroAssembler::load_ptr_contents( Address& a, Register d, int offset ) {
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538 assert_not_delayed();
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539 sethi(a);
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540 ld_ptr(a, d, offset);
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541 }
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542
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543
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544 inline void MacroAssembler::store_contents( Register s, Address& a, int offset ) {
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545 assert_not_delayed();
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546 sethi(a);
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547 st(s, a, offset);
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548 }
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549
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550
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551 inline void MacroAssembler::store_ptr_contents( Register s, Address& a, int offset ) {
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552 assert_not_delayed();
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553 sethi(a);
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554 st_ptr(s, a, offset);
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555 }
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556
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557
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558 // This code sequence is relocatable to any address, even on LP64.
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559 inline void MacroAssembler::jumpl_to( Address& a, Register d, int offset ) {
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560 assert_not_delayed();
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561 // Force fixed length sethi because NativeJump and NativeFarCall don't handle
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562 // variable length instruction streams.
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563 sethi(a, /*ForceRelocatable=*/ true);
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564 jmpl(a, d, offset);
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565 }
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566
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567
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568 inline void MacroAssembler::jump_to( Address& a, int offset ) {
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569 jumpl_to( a, G0, offset );
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570 }
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571
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572
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573 inline void MacroAssembler::set_oop( jobject obj, Register d ) {
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574 set_oop(allocate_oop_address(obj, d));
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575 }
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576
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577
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578 inline void MacroAssembler::set_oop_constant( jobject obj, Register d ) {
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579 set_oop(constant_oop_address(obj, d));
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580 }
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581
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582
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583 inline void MacroAssembler::set_oop( Address obj_addr ) {
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584 assert(obj_addr.rspec().type()==relocInfo::oop_type, "must be an oop reloc");
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585 load_address(obj_addr);
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586 }
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587
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588
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589 inline void MacroAssembler::load_argument( Argument& a, Register d ) {
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590 if (a.is_register())
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591 mov(a.as_register(), d);
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592 else
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593 ld (a.as_address(), d);
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594 }
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595
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596 inline void MacroAssembler::store_argument( Register s, Argument& a ) {
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597 if (a.is_register())
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598 mov(s, a.as_register());
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599 else
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600 st_ptr (s, a.as_address()); // ABI says everything is right justified.
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601 }
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602
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603 inline void MacroAssembler::store_ptr_argument( Register s, Argument& a ) {
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604 if (a.is_register())
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605 mov(s, a.as_register());
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606 else
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607 st_ptr (s, a.as_address());
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608 }
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609
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610
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611 #ifdef _LP64
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612 inline void MacroAssembler::store_float_argument( FloatRegister s, Argument& a ) {
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613 if (a.is_float_register())
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614 // V9 ABI has F1, F3, F5 are used to pass instead of O0, O1, O2
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615 fmov(FloatRegisterImpl::S, s, a.as_float_register() );
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616 else
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617 // Floats are stored in the high half of the stack entry
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618 // The low half is undefined per the ABI.
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619 stf(FloatRegisterImpl::S, s, a.as_address(), sizeof(jfloat));
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620 }
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621
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622 inline void MacroAssembler::store_double_argument( FloatRegister s, Argument& a ) {
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623 if (a.is_float_register())
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624 // V9 ABI has D0, D2, D4 are used to pass instead of O0, O1, O2
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625 fmov(FloatRegisterImpl::D, s, a.as_double_register() );
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626 else
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627 stf(FloatRegisterImpl::D, s, a.as_address());
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628 }
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629
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630 inline void MacroAssembler::store_long_argument( Register s, Argument& a ) {
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631 if (a.is_register())
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632 mov(s, a.as_register());
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633 else
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634 stx(s, a.as_address());
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635 }
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636 #endif
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637
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638 inline void MacroAssembler::clrb( Register s1, Register s2) { stb( G0, s1, s2 ); }
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639 inline void MacroAssembler::clrh( Register s1, Register s2) { sth( G0, s1, s2 ); }
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640 inline void MacroAssembler::clr( Register s1, Register s2) { stw( G0, s1, s2 ); }
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641 inline void MacroAssembler::clrx( Register s1, Register s2) { stx( G0, s1, s2 ); }
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642
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643 inline void MacroAssembler::clrb( Register s1, int simm13a) { stb( G0, s1, simm13a); }
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644 inline void MacroAssembler::clrh( Register s1, int simm13a) { sth( G0, s1, simm13a); }
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645 inline void MacroAssembler::clr( Register s1, int simm13a) { stw( G0, s1, simm13a); }
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646 inline void MacroAssembler::clrx( Register s1, int simm13a) { stx( G0, s1, simm13a); }
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647
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648 // returns if membar generates anything, obviously this code should mirror
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649 // membar below.
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650 inline bool MacroAssembler::membar_has_effect( Membar_mask_bits const7a ) {
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651 if( !os::is_MP() ) return false; // Not needed on single CPU
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652 if( VM_Version::v9_instructions_work() ) {
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653 const Membar_mask_bits effective_mask =
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654 Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore));
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655 return (effective_mask != 0);
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656 } else {
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657 return true;
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658 }
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659 }
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660
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661 inline void MacroAssembler::membar( Membar_mask_bits const7a ) {
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662 // Uniprocessors do not need memory barriers
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663 if (!os::is_MP()) return;
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664 // Weakened for current Sparcs and TSO. See the v9 manual, sections 8.4.3,
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665 // 8.4.4.3, a.31 and a.50.
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666 if( VM_Version::v9_instructions_work() ) {
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667 // Under TSO, setting bit 3, 2, or 0 is redundant, so the only value
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668 // of the mmask subfield of const7a that does anything that isn't done
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669 // implicitly is StoreLoad.
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670 const Membar_mask_bits effective_mask =
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671 Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore));
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672 if ( effective_mask != 0 ) {
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673 Assembler::membar( effective_mask );
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674 }
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675 } else {
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676 // stbar is the closest there is on v8. Equivalent to membar(StoreStore). We
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677 // do not issue the stbar because to my knowledge all v8 machines implement TSO,
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678 // which guarantees that all stores behave as if an stbar were issued just after
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679 // each one of them. On these machines, stbar ought to be a nop. There doesn't
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680 // appear to be an equivalent of membar(StoreLoad) on v8: TSO doesn't require it,
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681 // it can't be specified by stbar, nor have I come up with a way to simulate it.
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682 //
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683 // Addendum. Dave says that ldstub guarantees a write buffer flush to coherent
|
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684 // space. Put one here to be on the safe side.
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685 Assembler::ldstub(SP, 0, G0);
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686 }
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687 }
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