annotate src/share/vm/opto/coalesce.cpp @ 196:d1605aabd0a1 jdk7-b30

6719955: Update copyright year Summary: Update copyright year for files that have been modified in 2008 Reviewed-by: ohair, tbell
author xdono
date Wed, 02 Jul 2008 12:55:16 -0700
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1 /*
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2 * Copyright 1997-2006 Sun Microsystems, Inc. All Rights Reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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20 * CA 95054 USA or visit www.sun.com if you need additional information or
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21 * have any questions.
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22 *
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23 */
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24
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25 #include "incls/_precompiled.incl"
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26 #include "incls/_coalesce.cpp.incl"
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27
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28 //=============================================================================
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29 //------------------------------reset_uf_map-----------------------------------
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30 void PhaseChaitin::reset_uf_map( uint maxlrg ) {
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31 _maxlrg = maxlrg;
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32 // Force the Union-Find mapping to be at least this large
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33 _uf_map.extend(_maxlrg,0);
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34 // Initialize it to be the ID mapping.
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35 for( uint i=0; i<_maxlrg; i++ )
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36 _uf_map.map(i,i);
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37 }
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38
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39 //------------------------------compress_uf_map--------------------------------
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40 // Make all Nodes map directly to their final live range; no need for
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41 // the Union-Find mapping after this call.
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42 void PhaseChaitin::compress_uf_map_for_nodes( ) {
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43 // For all Nodes, compress mapping
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44 uint unique = _names.Size();
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45 for( uint i=0; i<unique; i++ ) {
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46 uint lrg = _names[i];
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47 uint compressed_lrg = Find(lrg);
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48 if( lrg != compressed_lrg )
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49 _names.map(i,compressed_lrg);
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50 }
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51 }
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52
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53 //------------------------------Find-------------------------------------------
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54 // Straight out of Tarjan's union-find algorithm
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55 uint PhaseChaitin::Find_compress( uint lrg ) {
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56 uint cur = lrg;
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57 uint next = _uf_map[cur];
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58 while( next != cur ) { // Scan chain of equivalences
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59 assert( next < cur, "always union smaller" );
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60 cur = next; // until find a fixed-point
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61 next = _uf_map[cur];
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62 }
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63 // Core of union-find algorithm: update chain of
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64 // equivalences to be equal to the root.
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65 while( lrg != next ) {
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66 uint tmp = _uf_map[lrg];
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67 _uf_map.map(lrg, next);
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68 lrg = tmp;
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69 }
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70 return lrg;
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71 }
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72
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73 //------------------------------Find-------------------------------------------
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74 // Straight out of Tarjan's union-find algorithm
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75 uint PhaseChaitin::Find_compress( const Node *n ) {
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76 uint lrg = Find_compress(_names[n->_idx]);
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77 _names.map(n->_idx,lrg);
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78 return lrg;
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79 }
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80
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81 //------------------------------Find_const-------------------------------------
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82 // Like Find above, but no path compress, so bad asymptotic behavior
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83 uint PhaseChaitin::Find_const( uint lrg ) const {
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84 if( !lrg ) return lrg; // Ignore the zero LRG
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85 // Off the end? This happens during debugging dumps when you got
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86 // brand new live ranges but have not told the allocator yet.
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87 if( lrg >= _maxlrg ) return lrg;
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88 uint next = _uf_map[lrg];
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89 while( next != lrg ) { // Scan chain of equivalences
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90 assert( next < lrg, "always union smaller" );
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91 lrg = next; // until find a fixed-point
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92 next = _uf_map[lrg];
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93 }
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94 return next;
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95 }
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96
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97 //------------------------------Find-------------------------------------------
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98 // Like Find above, but no path compress, so bad asymptotic behavior
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99 uint PhaseChaitin::Find_const( const Node *n ) const {
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100 if( n->_idx >= _names.Size() ) return 0; // not mapped, usual for debug dump
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101 return Find_const( _names[n->_idx] );
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102 }
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103
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104 //------------------------------Union------------------------------------------
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105 // union 2 sets together.
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106 void PhaseChaitin::Union( const Node *src_n, const Node *dst_n ) {
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107 uint src = Find(src_n);
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108 uint dst = Find(dst_n);
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109 assert( src, "" );
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110 assert( dst, "" );
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111 assert( src < _maxlrg, "oob" );
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112 assert( dst < _maxlrg, "oob" );
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113 assert( src < dst, "always union smaller" );
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114 _uf_map.map(dst,src);
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115 }
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116
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117 //------------------------------new_lrg----------------------------------------
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118 void PhaseChaitin::new_lrg( const Node *x, uint lrg ) {
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119 // Make the Node->LRG mapping
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120 _names.extend(x->_idx,lrg);
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121 // Make the Union-Find mapping an identity function
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122 _uf_map.extend(lrg,lrg);
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123 }
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124
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125 //------------------------------clone_projs------------------------------------
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126 // After cloning some rematierialized instruction, clone any MachProj's that
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127 // follow it. Example: Intel zero is XOR, kills flags. Sparc FP constants
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128 // use G3 as an address temp.
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129 int PhaseChaitin::clone_projs( Block *b, uint idx, Node *con, Node *copy, uint &maxlrg ) {
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130 Block *bcon = _cfg._bbs[con->_idx];
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131 uint cindex = bcon->find_node(con);
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132 Node *con_next = bcon->_nodes[cindex+1];
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133 if( con_next->in(0) != con || con_next->Opcode() != Op_MachProj )
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134 return false; // No MachProj's follow
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135
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136 // Copy kills after the cloned constant
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137 Node *kills = con_next->clone();
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138 kills->set_req( 0, copy );
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139 b->_nodes.insert( idx, kills );
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140 _cfg._bbs.map( kills->_idx, b );
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141 new_lrg( kills, maxlrg++ );
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142 return true;
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143 }
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144
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145 //------------------------------compact----------------------------------------
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146 // Renumber the live ranges to compact them. Makes the IFG smaller.
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147 void PhaseChaitin::compact() {
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148 // Current the _uf_map contains a series of short chains which are headed
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149 // by a self-cycle. All the chains run from big numbers to little numbers.
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150 // The Find() call chases the chains & shortens them for the next Find call.
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151 // We are going to change this structure slightly. Numbers above a moving
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152 // wave 'i' are unchanged. Numbers below 'j' point directly to their
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153 // compacted live range with no further chaining. There are no chains or
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154 // cycles below 'i', so the Find call no longer works.
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155 uint j=1;
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156 uint i;
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157 for( i=1; i < _maxlrg; i++ ) {
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158 uint lr = _uf_map[i];
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159 // Ignore unallocated live ranges
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160 if( !lr ) continue;
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161 assert( lr <= i, "" );
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162 _uf_map.map(i, ( lr == i ) ? j++ : _uf_map[lr]);
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163 }
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164 if( false ) // PrintOptoCompactLiveRanges
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165 printf("Compacted %d LRs from %d\n",i-j,i);
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166 // Now change the Node->LR mapping to reflect the compacted names
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167 uint unique = _names.Size();
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168 for( i=0; i<unique; i++ )
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169 _names.map(i,_uf_map[_names[i]]);
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170
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171 // Reset the Union-Find mapping
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172 reset_uf_map(j);
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173
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174 }
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175
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176 //=============================================================================
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177 //------------------------------Dump-------------------------------------------
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178 #ifndef PRODUCT
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179 void PhaseCoalesce::dump( Node *n ) const {
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180 // Being a const function means I cannot use 'Find'
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181 uint r = _phc.Find(n);
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182 tty->print("L%d/N%d ",r,n->_idx);
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183 }
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184
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185 //------------------------------dump-------------------------------------------
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186 void PhaseCoalesce::dump() const {
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187 // I know I have a block layout now, so I can print blocks in a loop
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188 for( uint i=0; i<_phc._cfg._num_blocks; i++ ) {
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189 uint j;
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190 Block *b = _phc._cfg._blocks[i];
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191 // Print a nice block header
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192 tty->print("B%d: ",b->_pre_order);
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193 for( j=1; j<b->num_preds(); j++ )
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194 tty->print("B%d ", _phc._cfg._bbs[b->pred(j)->_idx]->_pre_order);
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195 tty->print("-> ");
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196 for( j=0; j<b->_num_succs; j++ )
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197 tty->print("B%d ",b->_succs[j]->_pre_order);
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198 tty->print(" IDom: B%d/#%d\n", b->_idom ? b->_idom->_pre_order : 0, b->_dom_depth);
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199 uint cnt = b->_nodes.size();
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200 for( j=0; j<cnt; j++ ) {
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201 Node *n = b->_nodes[j];
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202 dump( n );
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203 tty->print("\t%s\t",n->Name());
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204
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205 // Dump the inputs
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206 uint k; // Exit value of loop
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207 for( k=0; k<n->req(); k++ ) // For all required inputs
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208 if( n->in(k) ) dump( n->in(k) );
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209 else tty->print("_ ");
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210 int any_prec = 0;
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211 for( ; k<n->len(); k++ ) // For all precedence inputs
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212 if( n->in(k) ) {
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213 if( !any_prec++ ) tty->print(" |");
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214 dump( n->in(k) );
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215 }
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216
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217 // Dump node-specific info
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218 n->dump_spec(tty);
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219 tty->print("\n");
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220
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221 }
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222 tty->print("\n");
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223 }
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224 }
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225 #endif
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226
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227 //------------------------------combine_these_two------------------------------
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228 // Combine the live ranges def'd by these 2 Nodes. N2 is an input to N1.
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229 void PhaseCoalesce::combine_these_two( Node *n1, Node *n2 ) {
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230 uint lr1 = _phc.Find(n1);
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231 uint lr2 = _phc.Find(n2);
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232 if( lr1 != lr2 && // Different live ranges already AND
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233 !_phc._ifg->test_edge_sq( lr1, lr2 ) ) { // Do not interfere
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234 LRG *lrg1 = &_phc.lrgs(lr1);
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235 LRG *lrg2 = &_phc.lrgs(lr2);
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236 // Not an oop->int cast; oop->oop, int->int, AND int->oop are OK.
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237
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238 // Now, why is int->oop OK? We end up declaring a raw-pointer as an oop
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239 // and in general that's a bad thing. However, int->oop conversions only
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240 // happen at GC points, so the lifetime of the misclassified raw-pointer
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241 // is from the CheckCastPP (that converts it to an oop) backwards up
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242 // through a merge point and into the slow-path call, and around the
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243 // diamond up to the heap-top check and back down into the slow-path call.
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244 // The misclassified raw pointer is NOT live across the slow-path call,
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245 // and so does not appear in any GC info, so the fact that it is
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246 // misclassified is OK.
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247
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248 if( (lrg1->_is_oop || !lrg2->_is_oop) && // not an oop->int cast AND
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249 // Compatible final mask
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250 lrg1->mask().overlap( lrg2->mask() ) ) {
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251 // Merge larger into smaller.
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252 if( lr1 > lr2 ) {
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253 uint tmp = lr1; lr1 = lr2; lr2 = tmp;
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254 Node *n = n1; n1 = n2; n2 = n;
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255 LRG *ltmp = lrg1; lrg1 = lrg2; lrg2 = ltmp;
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256 }
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257 // Union lr2 into lr1
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258 _phc.Union( n1, n2 );
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259 if (lrg1->_maxfreq < lrg2->_maxfreq)
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260 lrg1->_maxfreq = lrg2->_maxfreq;
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261 // Merge in the IFG
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262 _phc._ifg->Union( lr1, lr2 );
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263 // Combine register restrictions
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264 lrg1->AND(lrg2->mask());
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265 }
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266 }
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267 }
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268
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269 //------------------------------coalesce_driver--------------------------------
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270 // Copy coalescing
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271 void PhaseCoalesce::coalesce_driver( ) {
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272
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273 verify();
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274 // Coalesce from high frequency to low
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275 for( uint i=0; i<_phc._cfg._num_blocks; i++ )
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276 coalesce( _phc._blks[i] );
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277
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278 }
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279
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280 //------------------------------insert_copy_with_overlap-----------------------
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281 // I am inserting copies to come out of SSA form. In the general case, I am
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282 // doing a parallel renaming. I'm in the Named world now, so I can't do a
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283 // general parallel renaming. All the copies now use "names" (live-ranges)
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284 // to carry values instead of the explicit use-def chains. Suppose I need to
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285 // insert 2 copies into the same block. They copy L161->L128 and L128->L132.
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286 // If I insert them in the wrong order then L128 will get clobbered before it
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287 // can get used by the second copy. This cannot happen in the SSA model;
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288 // direct use-def chains get me the right value. It DOES happen in the named
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289 // model so I have to handle the reordering of copies.
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290 //
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291 // In general, I need to topo-sort the placed copies to avoid conflicts.
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292 // Its possible to have a closed cycle of copies (e.g., recirculating the same
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293 // values around a loop). In this case I need a temp to break the cycle.
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294 void PhaseAggressiveCoalesce::insert_copy_with_overlap( Block *b, Node *copy, uint dst_name, uint src_name ) {
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295
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296 // Scan backwards for the locations of the last use of the dst_name.
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297 // I am about to clobber the dst_name, so the copy must be inserted
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298 // after the last use. Last use is really first-use on a backwards scan.
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299 uint i = b->end_idx()-1;
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300 while( 1 ) {
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301 Node *n = b->_nodes[i];
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302 // Check for end of virtual copies; this is also the end of the
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303 // parallel renaming effort.
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304 if( n->_idx < _unique ) break;
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305 uint idx = n->is_Copy();
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306 assert( idx || n->is_Con() || n->Opcode() == Op_MachProj, "Only copies during parallel renaming" );
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307 if( idx && _phc.Find(n->in(idx)) == dst_name ) break;
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308 i--;
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309 }
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310 uint last_use_idx = i;
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311
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312 // Also search for any kill of src_name that exits the block.
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313 // Since the copy uses src_name, I have to come before any kill.
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314 uint kill_src_idx = b->end_idx();
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315 // There can be only 1 kill that exits any block and that is
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316 // the last kill. Thus it is the first kill on a backwards scan.
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317 i = b->end_idx()-1;
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318 while( 1 ) {
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319 Node *n = b->_nodes[i];
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320 // Check for end of virtual copies; this is also the end of the
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321 // parallel renaming effort.
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322 if( n->_idx < _unique ) break;
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323 assert( n->is_Copy() || n->is_Con() || n->Opcode() == Op_MachProj, "Only copies during parallel renaming" );
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324 if( _phc.Find(n) == src_name ) {
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325 kill_src_idx = i;
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326 break;
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327 }
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328 i--;
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329 }
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330 // Need a temp? Last use of dst comes after the kill of src?
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331 if( last_use_idx >= kill_src_idx ) {
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332 // Need to break a cycle with a temp
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333 uint idx = copy->is_Copy();
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334 Node *tmp = copy->clone();
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335 _phc.new_lrg(tmp,_phc._maxlrg++);
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336 // Insert new temp between copy and source
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337 tmp ->set_req(idx,copy->in(idx));
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338 copy->set_req(idx,tmp);
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339 // Save source in temp early, before source is killed
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340 b->_nodes.insert(kill_src_idx,tmp);
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341 _phc._cfg._bbs.map( tmp->_idx, b );
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342 last_use_idx++;
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343 }
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344
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345 // Insert just after last use
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346 b->_nodes.insert(last_use_idx+1,copy);
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347 }
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348
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349 //------------------------------insert_copies----------------------------------
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350 void PhaseAggressiveCoalesce::insert_copies( Matcher &matcher ) {
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351 // We do LRGs compressing and fix a liveout data only here since the other
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352 // place in Split() is guarded by the assert which we never hit.
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353 _phc.compress_uf_map_for_nodes();
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354 // Fix block's liveout data for compressed live ranges.
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355 for(uint lrg = 1; lrg < _phc._maxlrg; lrg++ ) {
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356 uint compressed_lrg = _phc.Find(lrg);
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357 if( lrg != compressed_lrg ) {
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358 for( uint bidx = 0; bidx < _phc._cfg._num_blocks; bidx++ ) {
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359 IndexSet *liveout = _phc._live->live(_phc._cfg._blocks[bidx]);
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360 if( liveout->member(lrg) ) {
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361 liveout->remove(lrg);
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362 liveout->insert(compressed_lrg);
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363 }
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364 }
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365 }
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366 }
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367
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368 // All new nodes added are actual copies to replace virtual copies.
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369 // Nodes with index less than '_unique' are original, non-virtual Nodes.
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370 _unique = C->unique();
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371
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372 for( uint i=0; i<_phc._cfg._num_blocks; i++ ) {
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373 Block *b = _phc._cfg._blocks[i];
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374 uint cnt = b->num_preds(); // Number of inputs to the Phi
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375
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376 for( uint l = 1; l<b->_nodes.size(); l++ ) {
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377 Node *n = b->_nodes[l];
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378
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379 // Do not use removed-copies, use copied value instead
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380 uint ncnt = n->req();
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381 for( uint k = 1; k<ncnt; k++ ) {
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382 Node *copy = n->in(k);
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383 uint cidx = copy->is_Copy();
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384 if( cidx ) {
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385 Node *def = copy->in(cidx);
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386 if( _phc.Find(copy) == _phc.Find(def) )
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387 n->set_req(k,def);
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388 }
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389 }
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390
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391 // Remove any explicit copies that get coalesced.
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392 uint cidx = n->is_Copy();
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393 if( cidx ) {
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394 Node *def = n->in(cidx);
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395 if( _phc.Find(n) == _phc.Find(def) ) {
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396 n->replace_by(def);
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397 n->set_req(cidx,NULL);
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398 b->_nodes.remove(l);
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399 l--;
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400 continue;
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401 }
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402 }
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403
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404 if( n->is_Phi() ) {
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405 // Get the chosen name for the Phi
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406 uint phi_name = _phc.Find( n );
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407 // Ignore the pre-allocated specials
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408 if( !phi_name ) continue;
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409 // Check for mismatch inputs to Phi
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410 for( uint j = 1; j<cnt; j++ ) {
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411 Node *m = n->in(j);
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412 uint src_name = _phc.Find(m);
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413 if( src_name != phi_name ) {
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414 Block *pred = _phc._cfg._bbs[b->pred(j)->_idx];
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415 Node *copy;
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416 assert(!m->is_Con() || m->is_Mach(), "all Con must be Mach");
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417 // Rematerialize constants instead of copying them
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418 if( m->is_Mach() && m->as_Mach()->is_Con() &&
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419 m->as_Mach()->rematerialize() ) {
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420 copy = m->clone();
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421 // Insert the copy in the predecessor basic block
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422 pred->add_inst(copy);
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423 // Copy any flags as well
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424 _phc.clone_projs( pred, pred->end_idx(), m, copy, _phc._maxlrg );
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425 } else {
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426 const RegMask *rm = C->matcher()->idealreg2spillmask[m->ideal_reg()];
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427 copy = new (C) MachSpillCopyNode(m,*rm,*rm);
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428 // Find a good place to insert. Kinda tricky, use a subroutine
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429 insert_copy_with_overlap(pred,copy,phi_name,src_name);
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430 }
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431 // Insert the copy in the use-def chain
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diff changeset
432 n->set_req( j, copy );
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parents:
diff changeset
433 _phc._cfg._bbs.map( copy->_idx, pred );
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parents:
diff changeset
434 // Extend ("register allocate") the names array for the copy.
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parents:
diff changeset
435 _phc._names.extend( copy->_idx, phi_name );
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parents:
diff changeset
436 } // End of if Phi names do not match
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parents:
diff changeset
437 } // End of for all inputs to Phi
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parents:
diff changeset
438 } else { // End of if Phi
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parents:
diff changeset
439
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parents:
diff changeset
440 // Now check for 2-address instructions
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parents:
diff changeset
441 uint idx;
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parents:
diff changeset
442 if( n->is_Mach() && (idx=n->as_Mach()->two_adr()) ) {
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parents:
diff changeset
443 // Get the chosen name for the Node
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parents:
diff changeset
444 uint name = _phc.Find( n );
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parents:
diff changeset
445 assert( name, "no 2-address specials" );
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duke
parents:
diff changeset
446 // Check for name mis-match on the 2-address input
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parents:
diff changeset
447 Node *m = n->in(idx);
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parents:
diff changeset
448 if( _phc.Find(m) != name ) {
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parents:
diff changeset
449 Node *copy;
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parents:
diff changeset
450 assert(!m->is_Con() || m->is_Mach(), "all Con must be Mach");
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parents:
diff changeset
451 // At this point it is unsafe to extend live ranges (6550579).
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duke
parents:
diff changeset
452 // Rematerialize only constants as we do for Phi above.
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parents:
diff changeset
453 if( m->is_Mach() && m->as_Mach()->is_Con() &&
a61af66fc99e Initial load
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parents:
diff changeset
454 m->as_Mach()->rematerialize() ) {
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parents:
diff changeset
455 copy = m->clone();
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duke
parents:
diff changeset
456 // Insert the copy in the basic block, just before us
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parents:
diff changeset
457 b->_nodes.insert( l++, copy );
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parents:
diff changeset
458 if( _phc.clone_projs( b, l, m, copy, _phc._maxlrg ) )
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parents:
diff changeset
459 l++;
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parents:
diff changeset
460 } else {
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parents:
diff changeset
461 const RegMask *rm = C->matcher()->idealreg2spillmask[m->ideal_reg()];
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parents:
diff changeset
462 copy = new (C) MachSpillCopyNode( m, *rm, *rm );
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parents:
diff changeset
463 // Insert the copy in the basic block, just before us
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parents:
diff changeset
464 b->_nodes.insert( l++, copy );
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parents:
diff changeset
465 }
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parents:
diff changeset
466 // Insert the copy in the use-def chain
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parents:
diff changeset
467 n->set_req(idx, copy );
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parents:
diff changeset
468 // Extend ("register allocate") the names array for the copy.
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parents:
diff changeset
469 _phc._names.extend( copy->_idx, name );
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parents:
diff changeset
470 _phc._cfg._bbs.map( copy->_idx, b );
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parents:
diff changeset
471 }
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parents:
diff changeset
472
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parents:
diff changeset
473 } // End of is two-adr
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parents:
diff changeset
474
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parents:
diff changeset
475 // Insert a copy at a debug use for a lrg which has high frequency
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parents:
diff changeset
476 if( (b->_freq < OPTO_DEBUG_SPLIT_FREQ) && n->is_MachSafePoint() ) {
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parents:
diff changeset
477 // Walk the debug inputs to the node and check for lrg freq
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parents:
diff changeset
478 JVMState* jvms = n->jvms();
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parents:
diff changeset
479 uint debug_start = jvms ? jvms->debug_start() : 999999;
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parents:
diff changeset
480 uint debug_end = jvms ? jvms->debug_end() : 999999;
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parents:
diff changeset
481 for(uint inpidx = debug_start; inpidx < debug_end; inpidx++) {
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parents:
diff changeset
482 // Do not split monitors; they are only needed for debug table
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parents:
diff changeset
483 // entries and need no code.
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parents:
diff changeset
484 if( jvms->is_monitor_use(inpidx) ) continue;
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parents:
diff changeset
485 Node *inp = n->in(inpidx);
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duke
parents:
diff changeset
486 uint nidx = _phc.n2lidx(inp);
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duke
parents:
diff changeset
487 LRG &lrg = lrgs(nidx);
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parents:
diff changeset
488
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duke
parents:
diff changeset
489 // If this lrg has a high frequency use/def
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parents:
diff changeset
490 if( lrg._maxfreq >= OPTO_LRG_HIGH_FREQ ) {
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parents:
diff changeset
491 // If the live range is also live out of this block (like it
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parents:
diff changeset
492 // would be for a fast/slow idiom), the normal spill mechanism
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duke
parents:
diff changeset
493 // does an excellent job. If it is not live out of this block
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parents:
diff changeset
494 // (like it would be for debug info to uncommon trap) splitting
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parents:
diff changeset
495 // the live range now allows a better allocation in the high
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duke
parents:
diff changeset
496 // frequency blocks.
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parents:
diff changeset
497 // Build_IFG_virtual has converted the live sets to
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parents:
diff changeset
498 // live-IN info, not live-OUT info.
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duke
parents:
diff changeset
499 uint k;
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parents:
diff changeset
500 for( k=0; k < b->_num_succs; k++ )
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parents:
diff changeset
501 if( _phc._live->live(b->_succs[k])->member( nidx ) )
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parents:
diff changeset
502 break; // Live in to some successor block?
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parents:
diff changeset
503 if( k < b->_num_succs )
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parents:
diff changeset
504 continue; // Live out; do not pre-split
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duke
parents:
diff changeset
505 // Split the lrg at this use
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parents:
diff changeset
506 const RegMask *rm = C->matcher()->idealreg2spillmask[inp->ideal_reg()];
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parents:
diff changeset
507 Node *copy = new (C) MachSpillCopyNode( inp, *rm, *rm );
a61af66fc99e Initial load
duke
parents:
diff changeset
508 // Insert the copy in the use-def chain
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duke
parents:
diff changeset
509 n->set_req(inpidx, copy );
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parents:
diff changeset
510 // Insert the copy in the basic block, just before us
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parents:
diff changeset
511 b->_nodes.insert( l++, copy );
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duke
parents:
diff changeset
512 // Extend ("register allocate") the names array for the copy.
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parents:
diff changeset
513 _phc.new_lrg( copy, _phc._maxlrg++ );
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parents:
diff changeset
514 _phc._cfg._bbs.map( copy->_idx, b );
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parents:
diff changeset
515 //tty->print_cr("Split a debug use in Aggressive Coalesce");
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parents:
diff changeset
516 } // End of if high frequency use/def
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parents:
diff changeset
517 } // End of for all debug inputs
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duke
parents:
diff changeset
518 } // End of if low frequency safepoint
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parents:
diff changeset
519
a61af66fc99e Initial load
duke
parents:
diff changeset
520 } // End of if Phi
a61af66fc99e Initial load
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parents:
diff changeset
521
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duke
parents:
diff changeset
522 } // End of for all instructions
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parents:
diff changeset
523 } // End of for all blocks
a61af66fc99e Initial load
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parents:
diff changeset
524 }
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parents:
diff changeset
525
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duke
parents:
diff changeset
526 //=============================================================================
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parents:
diff changeset
527 //------------------------------coalesce---------------------------------------
a61af66fc99e Initial load
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parents:
diff changeset
528 // Aggressive (but pessimistic) copy coalescing of a single block
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duke
parents:
diff changeset
529
a61af66fc99e Initial load
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parents:
diff changeset
530 // The following coalesce pass represents a single round of aggressive
a61af66fc99e Initial load
duke
parents:
diff changeset
531 // pessimistic coalesce. "Aggressive" means no attempt to preserve
a61af66fc99e Initial load
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parents:
diff changeset
532 // colorability when coalescing. This occasionally means more spills, but
a61af66fc99e Initial load
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parents:
diff changeset
533 // it also means fewer rounds of coalescing for better code - and that means
a61af66fc99e Initial load
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parents:
diff changeset
534 // faster compiles.
a61af66fc99e Initial load
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parents:
diff changeset
535
a61af66fc99e Initial load
duke
parents:
diff changeset
536 // "Pessimistic" means we do not hit the fixed point in one pass (and we are
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duke
parents:
diff changeset
537 // reaching for the least fixed point to boot). This is typically solved
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duke
parents:
diff changeset
538 // with a few more rounds of coalescing, but the compiler must run fast. We
a61af66fc99e Initial load
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parents:
diff changeset
539 // could optimistically coalescing everything touching PhiNodes together
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duke
parents:
diff changeset
540 // into one big live range, then check for self-interference. Everywhere
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duke
parents:
diff changeset
541 // the live range interferes with self it would have to be split. Finding
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duke
parents:
diff changeset
542 // the right split points can be done with some heuristics (based on
a61af66fc99e Initial load
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parents:
diff changeset
543 // expected frequency of edges in the live range). In short, it's a real
a61af66fc99e Initial load
duke
parents:
diff changeset
544 // research problem and the timeline is too short to allow such research.
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duke
parents:
diff changeset
545 // Further thoughts: (1) build the LR in a pass, (2) find self-interference
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duke
parents:
diff changeset
546 // in another pass, (3) per each self-conflict, split, (4) split by finding
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duke
parents:
diff changeset
547 // the low-cost cut (min-cut) of the LR, (5) edges in the LR are weighted
a61af66fc99e Initial load
duke
parents:
diff changeset
548 // according to the GCM algorithm (or just exec freq on CFG edges).
a61af66fc99e Initial load
duke
parents:
diff changeset
549
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parents:
diff changeset
550 void PhaseAggressiveCoalesce::coalesce( Block *b ) {
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duke
parents:
diff changeset
551 // Copies are still "virtual" - meaning we have not made them explicitly
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duke
parents:
diff changeset
552 // copies. Instead, Phi functions of successor blocks have mis-matched
a61af66fc99e Initial load
duke
parents:
diff changeset
553 // live-ranges. If I fail to coalesce, I'll have to insert a copy to line
a61af66fc99e Initial load
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parents:
diff changeset
554 // up the live-ranges. Check for Phis in successor blocks.
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duke
parents:
diff changeset
555 uint i;
a61af66fc99e Initial load
duke
parents:
diff changeset
556 for( i=0; i<b->_num_succs; i++ ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
557 Block *bs = b->_succs[i];
a61af66fc99e Initial load
duke
parents:
diff changeset
558 // Find index of 'b' in 'bs' predecessors
a61af66fc99e Initial load
duke
parents:
diff changeset
559 uint j=1;
a61af66fc99e Initial load
duke
parents:
diff changeset
560 while( _phc._cfg._bbs[bs->pred(j)->_idx] != b ) j++;
a61af66fc99e Initial load
duke
parents:
diff changeset
561 // Visit all the Phis in successor block
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duke
parents:
diff changeset
562 for( uint k = 1; k<bs->_nodes.size(); k++ ) {
a61af66fc99e Initial load
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parents:
diff changeset
563 Node *n = bs->_nodes[k];
a61af66fc99e Initial load
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parents:
diff changeset
564 if( !n->is_Phi() ) break;
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duke
parents:
diff changeset
565 combine_these_two( n, n->in(j) );
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parents:
diff changeset
566 }
a61af66fc99e Initial load
duke
parents:
diff changeset
567 } // End of for all successor blocks
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duke
parents:
diff changeset
568
a61af66fc99e Initial load
duke
parents:
diff changeset
569
a61af66fc99e Initial load
duke
parents:
diff changeset
570 // Check _this_ block for 2-address instructions and copies.
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parents:
diff changeset
571 uint cnt = b->end_idx();
a61af66fc99e Initial load
duke
parents:
diff changeset
572 for( i = 1; i<cnt; i++ ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
573 Node *n = b->_nodes[i];
a61af66fc99e Initial load
duke
parents:
diff changeset
574 uint idx;
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duke
parents:
diff changeset
575 // 2-address instructions have a virtual Copy matching their input
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duke
parents:
diff changeset
576 // to their output
a61af66fc99e Initial load
duke
parents:
diff changeset
577 if( n->is_Mach() && (idx = n->as_Mach()->two_adr()) ) {
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duke
parents:
diff changeset
578 MachNode *mach = n->as_Mach();
a61af66fc99e Initial load
duke
parents:
diff changeset
579 combine_these_two( mach, mach->in(idx) );
a61af66fc99e Initial load
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parents:
diff changeset
580 }
a61af66fc99e Initial load
duke
parents:
diff changeset
581 } // End of for all instructions in block
a61af66fc99e Initial load
duke
parents:
diff changeset
582 }
a61af66fc99e Initial load
duke
parents:
diff changeset
583
a61af66fc99e Initial load
duke
parents:
diff changeset
584 //=============================================================================
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parents:
diff changeset
585 //------------------------------PhaseConservativeCoalesce----------------------
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parents:
diff changeset
586 PhaseConservativeCoalesce::PhaseConservativeCoalesce( PhaseChaitin &chaitin ) : PhaseCoalesce(chaitin) {
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duke
parents:
diff changeset
587 _ulr.initialize(_phc._maxlrg);
a61af66fc99e Initial load
duke
parents:
diff changeset
588 }
a61af66fc99e Initial load
duke
parents:
diff changeset
589
a61af66fc99e Initial load
duke
parents:
diff changeset
590 //------------------------------verify-----------------------------------------
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duke
parents:
diff changeset
591 void PhaseConservativeCoalesce::verify() {
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parents:
diff changeset
592 #ifdef ASSERT
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duke
parents:
diff changeset
593 _phc.set_was_low();
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parents:
diff changeset
594 #endif
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duke
parents:
diff changeset
595 }
a61af66fc99e Initial load
duke
parents:
diff changeset
596
a61af66fc99e Initial load
duke
parents:
diff changeset
597 //------------------------------union_helper-----------------------------------
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parents:
diff changeset
598 void PhaseConservativeCoalesce::union_helper( Node *lr1_node, Node *lr2_node, uint lr1, uint lr2, Node *src_def, Node *dst_copy, Node *src_copy, Block *b, uint bindex ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
599 // Join live ranges. Merge larger into smaller. Union lr2 into lr1 in the
a61af66fc99e Initial load
duke
parents:
diff changeset
600 // union-find tree
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duke
parents:
diff changeset
601 _phc.Union( lr1_node, lr2_node );
a61af66fc99e Initial load
duke
parents:
diff changeset
602
a61af66fc99e Initial load
duke
parents:
diff changeset
603 // Single-def live range ONLY if both live ranges are single-def.
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duke
parents:
diff changeset
604 // If both are single def, then src_def powers one live range
a61af66fc99e Initial load
duke
parents:
diff changeset
605 // and def_copy powers the other. After merging, src_def powers
a61af66fc99e Initial load
duke
parents:
diff changeset
606 // the combined live range.
a61af66fc99e Initial load
duke
parents:
diff changeset
607 lrgs(lr1)._def = (lrgs(lr1)._def == NodeSentinel ||
a61af66fc99e Initial load
duke
parents:
diff changeset
608 lrgs(lr2)._def == NodeSentinel )
a61af66fc99e Initial load
duke
parents:
diff changeset
609 ? NodeSentinel : src_def;
a61af66fc99e Initial load
duke
parents:
diff changeset
610 lrgs(lr2)._def = NULL; // No def for lrg 2
a61af66fc99e Initial load
duke
parents:
diff changeset
611 lrgs(lr2).Clear(); // Force empty mask for LRG 2
a61af66fc99e Initial load
duke
parents:
diff changeset
612 //lrgs(lr2)._size = 0; // Live-range 2 goes dead
a61af66fc99e Initial load
duke
parents:
diff changeset
613 lrgs(lr1)._is_oop |= lrgs(lr2)._is_oop;
a61af66fc99e Initial load
duke
parents:
diff changeset
614 lrgs(lr2)._is_oop = 0; // In particular, not an oop for GC info
a61af66fc99e Initial load
duke
parents:
diff changeset
615
a61af66fc99e Initial load
duke
parents:
diff changeset
616 if (lrgs(lr1)._maxfreq < lrgs(lr2)._maxfreq)
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duke
parents:
diff changeset
617 lrgs(lr1)._maxfreq = lrgs(lr2)._maxfreq;
a61af66fc99e Initial load
duke
parents:
diff changeset
618
a61af66fc99e Initial load
duke
parents:
diff changeset
619 // Copy original value instead. Intermediate copies go dead, and
a61af66fc99e Initial load
duke
parents:
diff changeset
620 // the dst_copy becomes useless.
a61af66fc99e Initial load
duke
parents:
diff changeset
621 int didx = dst_copy->is_Copy();
a61af66fc99e Initial load
duke
parents:
diff changeset
622 dst_copy->set_req( didx, src_def );
a61af66fc99e Initial load
duke
parents:
diff changeset
623 // Add copy to free list
a61af66fc99e Initial load
duke
parents:
diff changeset
624 // _phc.free_spillcopy(b->_nodes[bindex]);
a61af66fc99e Initial load
duke
parents:
diff changeset
625 assert( b->_nodes[bindex] == dst_copy, "" );
a61af66fc99e Initial load
duke
parents:
diff changeset
626 dst_copy->replace_by( dst_copy->in(didx) );
a61af66fc99e Initial load
duke
parents:
diff changeset
627 dst_copy->set_req( didx, NULL);
a61af66fc99e Initial load
duke
parents:
diff changeset
628 b->_nodes.remove(bindex);
a61af66fc99e Initial load
duke
parents:
diff changeset
629 if( bindex < b->_ihrp_index ) b->_ihrp_index--;
a61af66fc99e Initial load
duke
parents:
diff changeset
630 if( bindex < b->_fhrp_index ) b->_fhrp_index--;
a61af66fc99e Initial load
duke
parents:
diff changeset
631
a61af66fc99e Initial load
duke
parents:
diff changeset
632 // Stretched lr1; add it to liveness of intermediate blocks
a61af66fc99e Initial load
duke
parents:
diff changeset
633 Block *b2 = _phc._cfg._bbs[src_copy->_idx];
a61af66fc99e Initial load
duke
parents:
diff changeset
634 while( b != b2 ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
635 b = _phc._cfg._bbs[b->pred(1)->_idx];
a61af66fc99e Initial load
duke
parents:
diff changeset
636 _phc._live->live(b)->insert(lr1);
a61af66fc99e Initial load
duke
parents:
diff changeset
637 }
a61af66fc99e Initial load
duke
parents:
diff changeset
638 }
a61af66fc99e Initial load
duke
parents:
diff changeset
639
a61af66fc99e Initial load
duke
parents:
diff changeset
640 //------------------------------compute_separating_interferences---------------
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diff changeset
641 // Factored code from copy_copy that computes extra interferences from
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diff changeset
642 // lengthening a live range by double-coalescing.
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diff changeset
643 uint PhaseConservativeCoalesce::compute_separating_interferences(Node *dst_copy, Node *src_copy, Block *b, uint bindex, RegMask &rm, uint reg_degree, uint rm_size, uint lr1, uint lr2 ) {
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644
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diff changeset
645 assert(!lrgs(lr1)._fat_proj, "cannot coalesce fat_proj");
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parents:
diff changeset
646 assert(!lrgs(lr2)._fat_proj, "cannot coalesce fat_proj");
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parents:
diff changeset
647 Node *prev_copy = dst_copy->in(dst_copy->is_Copy());
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diff changeset
648 Block *b2 = b;
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parents:
diff changeset
649 uint bindex2 = bindex;
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650 while( 1 ) {
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parents:
diff changeset
651 // Find previous instruction
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parents:
diff changeset
652 bindex2--; // Chain backwards 1 instruction
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parents:
diff changeset
653 while( bindex2 == 0 ) { // At block start, find prior block
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diff changeset
654 assert( b2->num_preds() == 2, "cannot double coalesce across c-flow" );
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diff changeset
655 b2 = _phc._cfg._bbs[b2->pred(1)->_idx];
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parents:
diff changeset
656 bindex2 = b2->end_idx()-1;
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parents:
diff changeset
657 }
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parents:
diff changeset
658 // Get prior instruction
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parents:
diff changeset
659 assert(bindex2 < b2->_nodes.size(), "index out of bounds");
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diff changeset
660 Node *x = b2->_nodes[bindex2];
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parents:
diff changeset
661 if( x == prev_copy ) { // Previous copy in copy chain?
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parents:
diff changeset
662 if( prev_copy == src_copy)// Found end of chain and all interferences
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parents:
diff changeset
663 break; // So break out of loop
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parents:
diff changeset
664 // Else work back one in copy chain
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parents:
diff changeset
665 prev_copy = prev_copy->in(prev_copy->is_Copy());
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parents:
diff changeset
666 } else { // Else collect interferences
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diff changeset
667 uint lidx = _phc.Find(x);
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parents:
diff changeset
668 // Found another def of live-range being stretched?
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parents:
diff changeset
669 if( lidx == lr1 ) return max_juint;
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parents:
diff changeset
670 if( lidx == lr2 ) return max_juint;
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parents:
diff changeset
671
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parents:
diff changeset
672 // If we attempt to coalesce across a bound def
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parents:
diff changeset
673 if( lrgs(lidx).is_bound() ) {
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parents:
diff changeset
674 // Do not let the coalesced LRG expect to get the bound color
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diff changeset
675 rm.SUBTRACT( lrgs(lidx).mask() );
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parents:
diff changeset
676 // Recompute rm_size
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parents:
diff changeset
677 rm_size = rm.Size();
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parents:
diff changeset
678 //if( rm._flags ) rm_size += 1000000;
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parents:
diff changeset
679 if( reg_degree >= rm_size ) return max_juint;
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parents:
diff changeset
680 }
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parents:
diff changeset
681 if( rm.overlap(lrgs(lidx).mask()) ) {
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parents:
diff changeset
682 // Insert lidx into union LRG; returns TRUE if actually inserted
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parents:
diff changeset
683 if( _ulr.insert(lidx) ) {
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parents:
diff changeset
684 // Infinite-stack neighbors do not alter colorability, as they
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parents:
diff changeset
685 // can always color to some other color.
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parents:
diff changeset
686 if( !lrgs(lidx).mask().is_AllStack() ) {
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parents:
diff changeset
687 // If this coalesce will make any new neighbor uncolorable,
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parents:
diff changeset
688 // do not coalesce.
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parents:
diff changeset
689 if( lrgs(lidx).just_lo_degree() )
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parents:
diff changeset
690 return max_juint;
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parents:
diff changeset
691 // Bump our degree
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parents:
diff changeset
692 if( ++reg_degree >= rm_size )
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parents:
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693 return max_juint;
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parents:
diff changeset
694 } // End of if not infinite-stack neighbor
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parents:
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695 } // End of if actually inserted
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parents:
diff changeset
696 } // End of if live range overlaps
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parents:
diff changeset
697 } // End of else collect intereferences for 1 node
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parents:
diff changeset
698 } // End of while forever, scan back for intereferences
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parents:
diff changeset
699 return reg_degree;
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parents:
diff changeset
700 }
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parents:
diff changeset
701
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parents:
diff changeset
702 //------------------------------update_ifg-------------------------------------
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diff changeset
703 void PhaseConservativeCoalesce::update_ifg(uint lr1, uint lr2, IndexSet *n_lr1, IndexSet *n_lr2) {
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parents:
diff changeset
704 // Some original neighbors of lr1 might have gone away
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parents:
diff changeset
705 // because the constrained register mask prevented them.
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parents:
diff changeset
706 // Remove lr1 from such neighbors.
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parents:
diff changeset
707 IndexSetIterator one(n_lr1);
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parents:
diff changeset
708 uint neighbor;
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parents:
diff changeset
709 LRG &lrg1 = lrgs(lr1);
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parents:
diff changeset
710 while ((neighbor = one.next()) != 0)
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parents:
diff changeset
711 if( !_ulr.member(neighbor) )
a61af66fc99e Initial load
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parents:
diff changeset
712 if( _phc._ifg->neighbors(neighbor)->remove(lr1) )
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parents:
diff changeset
713 lrgs(neighbor).inc_degree( -lrg1.compute_degree(lrgs(neighbor)) );
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parents:
diff changeset
714
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parents:
diff changeset
715
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parents:
diff changeset
716 // lr2 is now called (coalesced into) lr1.
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parents:
diff changeset
717 // Remove lr2 from the IFG.
a61af66fc99e Initial load
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parents:
diff changeset
718 IndexSetIterator two(n_lr2);
a61af66fc99e Initial load
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parents:
diff changeset
719 LRG &lrg2 = lrgs(lr2);
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parents:
diff changeset
720 while ((neighbor = two.next()) != 0)
a61af66fc99e Initial load
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parents:
diff changeset
721 if( _phc._ifg->neighbors(neighbor)->remove(lr2) )
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parents:
diff changeset
722 lrgs(neighbor).inc_degree( -lrg2.compute_degree(lrgs(neighbor)) );
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parents:
diff changeset
723
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parents:
diff changeset
724 // Some neighbors of intermediate copies now interfere with the
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parents:
diff changeset
725 // combined live range.
a61af66fc99e Initial load
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parents:
diff changeset
726 IndexSetIterator three(&_ulr);
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parents:
diff changeset
727 while ((neighbor = three.next()) != 0)
a61af66fc99e Initial load
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parents:
diff changeset
728 if( _phc._ifg->neighbors(neighbor)->insert(lr1) )
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parents:
diff changeset
729 lrgs(neighbor).inc_degree( lrg1.compute_degree(lrgs(neighbor)) );
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parents:
diff changeset
730 }
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parents:
diff changeset
731
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parents:
diff changeset
732 //------------------------------record_bias------------------------------------
a61af66fc99e Initial load
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parents:
diff changeset
733 static void record_bias( const PhaseIFG *ifg, int lr1, int lr2 ) {
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parents:
diff changeset
734 // Tag copy bias here
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parents:
diff changeset
735 if( !ifg->lrgs(lr1)._copy_bias )
a61af66fc99e Initial load
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parents:
diff changeset
736 ifg->lrgs(lr1)._copy_bias = lr2;
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parents:
diff changeset
737 if( !ifg->lrgs(lr2)._copy_bias )
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parents:
diff changeset
738 ifg->lrgs(lr2)._copy_bias = lr1;
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parents:
diff changeset
739 }
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parents:
diff changeset
740
a61af66fc99e Initial load
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parents:
diff changeset
741 //------------------------------copy_copy--------------------------------------
a61af66fc99e Initial load
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parents:
diff changeset
742 // See if I can coalesce a series of multiple copies together. I need the
a61af66fc99e Initial load
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parents:
diff changeset
743 // final dest copy and the original src copy. They can be the same Node.
a61af66fc99e Initial load
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parents:
diff changeset
744 // Compute the compatible register masks.
a61af66fc99e Initial load
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parents:
diff changeset
745 bool PhaseConservativeCoalesce::copy_copy( Node *dst_copy, Node *src_copy, Block *b, uint bindex ) {
a61af66fc99e Initial load
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parents:
diff changeset
746
a61af66fc99e Initial load
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parents:
diff changeset
747 if( !dst_copy->is_SpillCopy() ) return false;
a61af66fc99e Initial load
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parents:
diff changeset
748 if( !src_copy->is_SpillCopy() ) return false;
a61af66fc99e Initial load
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parents:
diff changeset
749 Node *src_def = src_copy->in(src_copy->is_Copy());
a61af66fc99e Initial load
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parents:
diff changeset
750 uint lr1 = _phc.Find(dst_copy);
a61af66fc99e Initial load
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parents:
diff changeset
751 uint lr2 = _phc.Find(src_def );
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parents:
diff changeset
752
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parents:
diff changeset
753 // Same live ranges already?
a61af66fc99e Initial load
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parents:
diff changeset
754 if( lr1 == lr2 ) return false;
a61af66fc99e Initial load
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parents:
diff changeset
755
a61af66fc99e Initial load
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parents:
diff changeset
756 // Interfere?
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parents:
diff changeset
757 if( _phc._ifg->test_edge_sq( lr1, lr2 ) ) return false;
a61af66fc99e Initial load
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parents:
diff changeset
758
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parents:
diff changeset
759 // Not an oop->int cast; oop->oop, int->int, AND int->oop are OK.
a61af66fc99e Initial load
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parents:
diff changeset
760 if( !lrgs(lr1)._is_oop && lrgs(lr2)._is_oop ) // not an oop->int cast
a61af66fc99e Initial load
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parents:
diff changeset
761 return false;
a61af66fc99e Initial load
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parents:
diff changeset
762
a61af66fc99e Initial load
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parents:
diff changeset
763 // Coalescing between an aligned live range and a mis-aligned live range?
a61af66fc99e Initial load
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parents:
diff changeset
764 // No, no! Alignment changes how we count degree.
a61af66fc99e Initial load
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parents:
diff changeset
765 if( lrgs(lr1)._fat_proj != lrgs(lr2)._fat_proj )
a61af66fc99e Initial load
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parents:
diff changeset
766 return false;
a61af66fc99e Initial load
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parents:
diff changeset
767
a61af66fc99e Initial load
duke
parents:
diff changeset
768 // Sort; use smaller live-range number
a61af66fc99e Initial load
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parents:
diff changeset
769 Node *lr1_node = dst_copy;
a61af66fc99e Initial load
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parents:
diff changeset
770 Node *lr2_node = src_def;
a61af66fc99e Initial load
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parents:
diff changeset
771 if( lr1 > lr2 ) {
a61af66fc99e Initial load
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parents:
diff changeset
772 uint tmp = lr1; lr1 = lr2; lr2 = tmp;
a61af66fc99e Initial load
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parents:
diff changeset
773 lr1_node = src_def; lr2_node = dst_copy;
a61af66fc99e Initial load
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parents:
diff changeset
774 }
a61af66fc99e Initial load
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parents:
diff changeset
775
a61af66fc99e Initial load
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parents:
diff changeset
776 // Check for compatibility of the 2 live ranges by
a61af66fc99e Initial load
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parents:
diff changeset
777 // intersecting their allowed register sets.
a61af66fc99e Initial load
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parents:
diff changeset
778 RegMask rm = lrgs(lr1).mask();
a61af66fc99e Initial load
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parents:
diff changeset
779 rm.AND(lrgs(lr2).mask());
a61af66fc99e Initial load
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parents:
diff changeset
780 // Number of bits free
a61af66fc99e Initial load
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parents:
diff changeset
781 uint rm_size = rm.Size();
a61af66fc99e Initial load
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parents:
diff changeset
782
a61af66fc99e Initial load
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parents:
diff changeset
783 // If we can use any stack slot, then effective size is infinite
a61af66fc99e Initial load
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parents:
diff changeset
784 if( rm.is_AllStack() ) rm_size += 1000000;
a61af66fc99e Initial load
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parents:
diff changeset
785 // Incompatible masks, no way to coalesce
a61af66fc99e Initial load
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parents:
diff changeset
786 if( rm_size == 0 ) return false;
a61af66fc99e Initial load
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parents:
diff changeset
787
a61af66fc99e Initial load
duke
parents:
diff changeset
788 // Another early bail-out test is when we are double-coalescing and the
a61af66fc99e Initial load
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parents:
diff changeset
789 // 2 copies are seperated by some control flow.
a61af66fc99e Initial load
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parents:
diff changeset
790 if( dst_copy != src_copy ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
791 Block *src_b = _phc._cfg._bbs[src_copy->_idx];
a61af66fc99e Initial load
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parents:
diff changeset
792 Block *b2 = b;
a61af66fc99e Initial load
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parents:
diff changeset
793 while( b2 != src_b ) {
a61af66fc99e Initial load
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parents:
diff changeset
794 if( b2->num_preds() > 2 ){// Found merge-point
a61af66fc99e Initial load
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parents:
diff changeset
795 _phc._lost_opp_cflow_coalesce++;
a61af66fc99e Initial load
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parents:
diff changeset
796 // extra record_bias commented out because Chris believes it is not
a61af66fc99e Initial load
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parents:
diff changeset
797 // productive. Since we can record only 1 bias, we want to choose one
a61af66fc99e Initial load
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parents:
diff changeset
798 // that stands a chance of working and this one probably does not.
a61af66fc99e Initial load
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parents:
diff changeset
799 //record_bias( _phc._lrgs, lr1, lr2 );
a61af66fc99e Initial load
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parents:
diff changeset
800 return false; // To hard to find all interferences
a61af66fc99e Initial load
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parents:
diff changeset
801 }
a61af66fc99e Initial load
duke
parents:
diff changeset
802 b2 = _phc._cfg._bbs[b2->pred(1)->_idx];
a61af66fc99e Initial load
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parents:
diff changeset
803 }
a61af66fc99e Initial load
duke
parents:
diff changeset
804 }
a61af66fc99e Initial load
duke
parents:
diff changeset
805
a61af66fc99e Initial load
duke
parents:
diff changeset
806 // Union the two interference sets together into '_ulr'
a61af66fc99e Initial load
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parents:
diff changeset
807 uint reg_degree = _ulr.lrg_union( lr1, lr2, rm_size, _phc._ifg, rm );
a61af66fc99e Initial load
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parents:
diff changeset
808
a61af66fc99e Initial load
duke
parents:
diff changeset
809 if( reg_degree >= rm_size ) {
a61af66fc99e Initial load
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parents:
diff changeset
810 record_bias( _phc._ifg, lr1, lr2 );
a61af66fc99e Initial load
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parents:
diff changeset
811 return false;
a61af66fc99e Initial load
duke
parents:
diff changeset
812 }
a61af66fc99e Initial load
duke
parents:
diff changeset
813
a61af66fc99e Initial load
duke
parents:
diff changeset
814 // Now I need to compute all the interferences between dst_copy and
a61af66fc99e Initial load
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parents:
diff changeset
815 // src_copy. I'm not willing visit the entire interference graph, so
a61af66fc99e Initial load
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parents:
diff changeset
816 // I limit my search to things in dst_copy's block or in a straight
a61af66fc99e Initial load
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parents:
diff changeset
817 // line of previous blocks. I give up at merge points or when I get
a61af66fc99e Initial load
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parents:
diff changeset
818 // more interferences than my degree. I can stop when I find src_copy.
a61af66fc99e Initial load
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parents:
diff changeset
819 if( dst_copy != src_copy ) {
a61af66fc99e Initial load
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parents:
diff changeset
820 reg_degree = compute_separating_interferences(dst_copy, src_copy, b, bindex, rm, rm_size, reg_degree, lr1, lr2 );
a61af66fc99e Initial load
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parents:
diff changeset
821 if( reg_degree == max_juint ) {
a61af66fc99e Initial load
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parents:
diff changeset
822 record_bias( _phc._ifg, lr1, lr2 );
a61af66fc99e Initial load
duke
parents:
diff changeset
823 return false;
a61af66fc99e Initial load
duke
parents:
diff changeset
824 }
a61af66fc99e Initial load
duke
parents:
diff changeset
825 } // End of if dst_copy & src_copy are different
a61af66fc99e Initial load
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parents:
diff changeset
826
a61af66fc99e Initial load
duke
parents:
diff changeset
827
a61af66fc99e Initial load
duke
parents:
diff changeset
828 // ---- THE COMBINED LRG IS COLORABLE ----
a61af66fc99e Initial load
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parents:
diff changeset
829
a61af66fc99e Initial load
duke
parents:
diff changeset
830 // YEAH - Now coalesce this copy away
a61af66fc99e Initial load
duke
parents:
diff changeset
831 assert( lrgs(lr1).num_regs() == lrgs(lr2).num_regs(), "" );
a61af66fc99e Initial load
duke
parents:
diff changeset
832
a61af66fc99e Initial load
duke
parents:
diff changeset
833 IndexSet *n_lr1 = _phc._ifg->neighbors(lr1);
a61af66fc99e Initial load
duke
parents:
diff changeset
834 IndexSet *n_lr2 = _phc._ifg->neighbors(lr2);
a61af66fc99e Initial load
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parents:
diff changeset
835
a61af66fc99e Initial load
duke
parents:
diff changeset
836 // Update the interference graph
a61af66fc99e Initial load
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parents:
diff changeset
837 update_ifg(lr1, lr2, n_lr1, n_lr2);
a61af66fc99e Initial load
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parents:
diff changeset
838
a61af66fc99e Initial load
duke
parents:
diff changeset
839 _ulr.remove(lr1);
a61af66fc99e Initial load
duke
parents:
diff changeset
840
a61af66fc99e Initial load
duke
parents:
diff changeset
841 // Uncomment the following code to trace Coalescing in great detail.
a61af66fc99e Initial load
duke
parents:
diff changeset
842 //
a61af66fc99e Initial load
duke
parents:
diff changeset
843 //if (false) {
a61af66fc99e Initial load
duke
parents:
diff changeset
844 // tty->cr();
a61af66fc99e Initial load
duke
parents:
diff changeset
845 // tty->print_cr("#######################################");
a61af66fc99e Initial load
duke
parents:
diff changeset
846 // tty->print_cr("union %d and %d", lr1, lr2);
a61af66fc99e Initial load
duke
parents:
diff changeset
847 // n_lr1->dump();
a61af66fc99e Initial load
duke
parents:
diff changeset
848 // n_lr2->dump();
a61af66fc99e Initial load
duke
parents:
diff changeset
849 // tty->print_cr("resulting set is");
a61af66fc99e Initial load
duke
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850 // _ulr.dump();
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851 //}
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852
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853 // Replace n_lr1 with the new combined live range. _ulr will use
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854 // n_lr1's old memory on the next iteration. n_lr2 is cleared to
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855 // send its internal memory to the free list.
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856 _ulr.swap(n_lr1);
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857 _ulr.clear();
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858 n_lr2->clear();
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859
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860 lrgs(lr1).set_degree( _phc._ifg->effective_degree(lr1) );
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861 lrgs(lr2).set_degree( 0 );
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862
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863 // Join live ranges. Merge larger into smaller. Union lr2 into lr1 in the
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864 // union-find tree
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865 union_helper( lr1_node, lr2_node, lr1, lr2, src_def, dst_copy, src_copy, b, bindex );
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866 // Combine register restrictions
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867 lrgs(lr1).set_mask(rm);
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868 lrgs(lr1).compute_set_mask_size();
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869 lrgs(lr1)._cost += lrgs(lr2)._cost;
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870 lrgs(lr1)._area += lrgs(lr2)._area;
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871
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872 // While its uncommon to successfully coalesce live ranges that started out
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873 // being not-lo-degree, it can happen. In any case the combined coalesced
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874 // live range better Simplify nicely.
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875 lrgs(lr1)._was_lo = 1;
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876
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877 // kinda expensive to do all the time
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878 //tty->print_cr("warning: slow verify happening");
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879 //_phc._ifg->verify( &_phc );
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880 return true;
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881 }
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882
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883 //------------------------------coalesce---------------------------------------
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884 // Conservative (but pessimistic) copy coalescing of a single block
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885 void PhaseConservativeCoalesce::coalesce( Block *b ) {
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886 // Bail out on infrequent blocks
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887 if( b->is_uncommon(_phc._cfg._bbs) )
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888 return;
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889 // Check this block for copies.
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890 for( uint i = 1; i<b->end_idx(); i++ ) {
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891 // Check for actual copies on inputs. Coalesce a copy into its
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892 // input if use and copy's input are compatible.
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893 Node *copy1 = b->_nodes[i];
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894 uint idx1 = copy1->is_Copy();
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895 if( !idx1 ) continue; // Not a copy
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896
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897 if( copy_copy(copy1,copy1,b,i) ) {
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898 i--; // Retry, same location in block
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899 PhaseChaitin::_conserv_coalesce++; // Collect stats on success
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900 continue;
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901 }
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902
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903 /* do not attempt pairs. About 1/2 of all pairs can be removed by
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904 post-alloc. The other set are too few to bother.
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905 Node *copy2 = copy1->in(idx1);
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906 uint idx2 = copy2->is_Copy();
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907 if( !idx2 ) continue;
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908 if( copy_copy(copy1,copy2,b,i) ) {
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909 i--; // Retry, same location in block
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910 PhaseChaitin::_conserv_coalesce_pair++; // Collect stats on success
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911 continue;
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912 }
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913 */
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914 }
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915 }