Mercurial > hg > truffle
annotate graal/GraalCompiler/src/com/sun/c1x/target/sparc/SPARC.java @ 2641:d1c5a798b73c
Removed memory map.
author | Thomas Wuerthinger <thomas@wuerthinger.net> |
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date | Wed, 11 May 2011 14:12:24 +0200 |
parents | 16b9a8b5ad39 |
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rev | line source |
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1 /* |
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2 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. |
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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4 * |
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5 * This code is free software; you can redistribute it and/or modify it |
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6 * under the terms of the GNU General Public License version 2 only, as |
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7 * published by the Free Software Foundation. |
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8 * |
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9 * This code is distributed in the hope that it will be useful, but WITHOUT |
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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12 * version 2 for more details (a copy is included in the LICENSE file that |
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13 * accompanied this code). |
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14 * |
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15 * You should have received a copy of the GNU General Public License version |
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16 * 2 along with this work; if not, write to the Free Software Foundation, |
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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18 * |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
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22 */ |
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23 package com.sun.c1x.target.sparc; |
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24 |
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25 import static com.sun.cri.bytecode.Bytecodes.MemoryBarriers.*; |
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26 import static com.sun.cri.ci.CiRegister.RegisterFlag.*; |
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27 |
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28 import com.sun.cri.ci.*; |
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29 |
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30 /** |
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31 * Represents the SPARC architecture. |
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32 * |
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33 * @author Thomas Wuerthinger |
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34 */ |
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35 public class SPARC extends CiArchitecture { |
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36 |
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37 // General purpose CPU registers |
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38 public static final CiRegister g0 = new CiRegister(0, 0, 8, "g0", CPU); |
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39 public static final CiRegister g1 = new CiRegister(1, 1, 8, "g1", CPU); |
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40 public static final CiRegister g2 = new CiRegister(2, 2, 8, "g2", CPU); |
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41 public static final CiRegister g3 = new CiRegister(3, 3, 8, "g3", CPU); |
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42 public static final CiRegister g4 = new CiRegister(4, 4, 8, "g4", CPU); |
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43 public static final CiRegister g5 = new CiRegister(5, 5, 8, "g5", CPU); |
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44 public static final CiRegister g6 = new CiRegister(6, 6, 8, "g6", CPU); |
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45 public static final CiRegister g7 = new CiRegister(7, 7, 8, "g7", CPU); |
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46 |
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47 public static final CiRegister o0 = new CiRegister(8, 8, 8, "o0", CPU); |
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48 public static final CiRegister o1 = new CiRegister(9, 9, 8, "o1", CPU); |
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49 public static final CiRegister o2 = new CiRegister(10, 10, 8, "o2", CPU); |
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50 public static final CiRegister o3 = new CiRegister(11, 11, 8, "o3", CPU); |
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51 public static final CiRegister o4 = new CiRegister(12, 12, 8, "o4", CPU); |
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52 public static final CiRegister o5 = new CiRegister(13, 13, 8, "o5", CPU); |
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53 public static final CiRegister o6 = new CiRegister(14, 14, 8, "o6", CPU); |
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54 public static final CiRegister o7 = new CiRegister(15, 15, 8, "o7", CPU); |
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55 |
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56 public static final CiRegister l0 = new CiRegister(16, 16, 8, "l0", CPU); |
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57 public static final CiRegister l1 = new CiRegister(17, 17, 8, "l1", CPU); |
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58 public static final CiRegister l2 = new CiRegister(18, 18, 8, "l2", CPU); |
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59 public static final CiRegister l3 = new CiRegister(19, 19, 8, "l3", CPU); |
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60 public static final CiRegister l4 = new CiRegister(20, 20, 8, "l4", CPU); |
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61 public static final CiRegister l5 = new CiRegister(21, 21, 8, "l5", CPU); |
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62 public static final CiRegister l6 = new CiRegister(22, 22, 8, "l6", CPU); |
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63 public static final CiRegister l7 = new CiRegister(23, 23, 8, "l7", CPU); |
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64 |
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65 public static final CiRegister i0 = new CiRegister(24, 24, 8, "i0", CPU); |
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66 public static final CiRegister i1 = new CiRegister(25, 25, 8, "i1", CPU); |
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67 public static final CiRegister i2 = new CiRegister(26, 26, 8, "i2", CPU); |
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68 public static final CiRegister i3 = new CiRegister(27, 27, 8, "i3", CPU); |
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69 public static final CiRegister i4 = new CiRegister(28, 28, 8, "i4", CPU); |
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70 public static final CiRegister i5 = new CiRegister(29, 29, 8, "i5", CPU); |
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71 public static final CiRegister i6 = new CiRegister(30, 30, 8, "i6", CPU); |
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72 public static final CiRegister i7 = new CiRegister(31, 31, 8, "i7", CPU); |
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73 |
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74 public static final CiRegister[] cpuRegisters = { |
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75 g0, g1, g2, g3, g4, g5, g6, g7, |
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76 o0, o1, o2, o3, o4, o5, o6, o7, |
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77 l0, l1, l2, l3, l4, l5, l6, l7, |
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78 i0, i1, i2, i3, i4, i5, i6, i7 |
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79 }; |
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80 |
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81 protected SPARC(int wordSize, CiRegister[] registers) { |
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82 super("SPARC", |
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83 wordSize, |
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84 ByteOrder.BigEndian, |
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85 registers, |
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86 LOAD_LOAD | LOAD_STORE | STORE_STORE, |
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87 0, |
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88 i7.encoding + 1, |
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89 0); |
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90 } |
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91 |
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92 @Override |
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93 public boolean isSPARC() { |
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94 return true; |
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95 } |
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96 |
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97 } |