Mercurial > hg > truffle
annotate src/cpu/sparc/vm/assembler_sparc.hpp @ 710:e5b0439ef4ae
6655638: dynamic languages need method handles
Summary: initial implementation, with known omissions (x86/64, sparc, compiler optim., c-oops, C++ interp.)
Reviewed-by: kvn, twisti, never
author | jrose |
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date | Wed, 08 Apr 2009 10:56:49 -0700 |
parents | c89f86385056 |
children | 6b2273dd6fa9 |
rev | line source |
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0 | 1 /* |
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2 * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
20 * CA 95054 USA or visit www.sun.com if you need additional information or | |
21 * have any questions. | |
22 * | |
23 */ | |
24 | |
25 class BiasedLockingCounters; | |
26 | |
27 // <sys/trap.h> promises that the system will not use traps 16-31 | |
28 #define ST_RESERVED_FOR_USER_0 0x10 | |
29 | |
30 /* Written: David Ungar 4/19/97 */ | |
31 | |
32 // Contains all the definitions needed for sparc assembly code generation. | |
33 | |
34 // Register aliases for parts of the system: | |
35 | |
36 // 64 bit values can be kept in g1-g5, o1-o5 and o7 and all 64 bits are safe | |
37 // across context switches in V8+ ABI. Of course, there are no 64 bit regs | |
38 // in V8 ABI. All 64 bits are preserved in V9 ABI for all registers. | |
39 | |
40 // g2-g4 are scratch registers called "application globals". Their | |
41 // meaning is reserved to the "compilation system"--which means us! | |
42 // They are are not supposed to be touched by ordinary C code, although | |
43 // highly-optimized C code might steal them for temps. They are safe | |
44 // across thread switches, and the ABI requires that they be safe | |
45 // across function calls. | |
46 // | |
47 // g1 and g3 are touched by more modules. V8 allows g1 to be clobbered | |
48 // across func calls, and V8+ also allows g5 to be clobbered across | |
49 // func calls. Also, g1 and g5 can get touched while doing shared | |
50 // library loading. | |
51 // | |
52 // We must not touch g7 (it is the thread-self register) and g6 is | |
53 // reserved for certain tools. g0, of course, is always zero. | |
54 // | |
55 // (Sources: SunSoft Compilers Group, thread library engineers.) | |
56 | |
57 // %%%% The interpreter should be revisited to reduce global scratch regs. | |
58 | |
59 // This global always holds the current JavaThread pointer: | |
60 | |
61 REGISTER_DECLARATION(Register, G2_thread , G2); | |
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62 REGISTER_DECLARATION(Register, G6_heapbase , G6); |
0 | 63 |
64 // The following globals are part of the Java calling convention: | |
65 | |
66 REGISTER_DECLARATION(Register, G5_method , G5); | |
67 REGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method); | |
68 REGISTER_DECLARATION(Register, G5_inline_cache_reg , G5_method); | |
69 | |
70 // The following globals are used for the new C1 & interpreter calling convention: | |
71 REGISTER_DECLARATION(Register, Gargs , G4); // pointing to the last argument | |
72 | |
73 // This local is used to preserve G2_thread in the interpreter and in stubs: | |
74 REGISTER_DECLARATION(Register, L7_thread_cache , L7); | |
75 | |
76 // These globals are used as scratch registers in the interpreter: | |
77 | |
78 REGISTER_DECLARATION(Register, Gframe_size , G1); // SAME REG as G1_scratch | |
79 REGISTER_DECLARATION(Register, G1_scratch , G1); // also SAME | |
80 REGISTER_DECLARATION(Register, G3_scratch , G3); | |
81 REGISTER_DECLARATION(Register, G4_scratch , G4); | |
82 | |
83 // These globals are used as short-lived scratch registers in the compiler: | |
84 | |
85 REGISTER_DECLARATION(Register, Gtemp , G5); | |
86 | |
710 | 87 // JSR 292 fixed register usages: |
88 REGISTER_DECLARATION(Register, G5_method_type , G5); | |
89 REGISTER_DECLARATION(Register, G3_method_handle , G3); | |
90 | |
0 | 91 // The compiler requires that G5_megamorphic_method is G5_inline_cache_klass, |
92 // because a single patchable "set" instruction (NativeMovConstReg, | |
93 // or NativeMovConstPatching for compiler1) instruction | |
94 // serves to set up either quantity, depending on whether the compiled | |
95 // call site is an inline cache or is megamorphic. See the function | |
96 // CompiledIC::set_to_megamorphic. | |
97 // | |
710 | 98 // If a inline cache targets an interpreted method, then the |
99 // G5 register will be used twice during the call. First, | |
100 // the call site will be patched to load a compiledICHolder | |
101 // into G5. (This is an ordered pair of ic_klass, method.) | |
102 // The c2i adapter will first check the ic_klass, then load | |
103 // G5_method with the method part of the pair just before | |
104 // jumping into the interpreter. | |
0 | 105 // |
106 // Note that G5_method is only the method-self for the interpreter, | |
107 // and is logically unrelated to G5_megamorphic_method. | |
108 // | |
109 // Invariants on G2_thread (the JavaThread pointer): | |
110 // - it should not be used for any other purpose anywhere | |
111 // - it must be re-initialized by StubRoutines::call_stub() | |
112 // - it must be preserved around every use of call_VM | |
113 | |
114 // We can consider using g2/g3/g4 to cache more values than the | |
115 // JavaThread, such as the card-marking base or perhaps pointers into | |
116 // Eden. It's something of a waste to use them as scratch temporaries, | |
117 // since they are not supposed to be volatile. (Of course, if we find | |
118 // that Java doesn't benefit from application globals, then we can just | |
119 // use them as ordinary temporaries.) | |
120 // | |
121 // Since g1 and g5 (and/or g6) are the volatile (caller-save) registers, | |
122 // it makes sense to use them routinely for procedure linkage, | |
123 // whenever the On registers are not applicable. Examples: G5_method, | |
124 // G5_inline_cache_klass, and a double handful of miscellaneous compiler | |
125 // stubs. This means that compiler stubs, etc., should be kept to a | |
126 // maximum of two or three G-register arguments. | |
127 | |
128 | |
129 // stub frames | |
130 | |
131 REGISTER_DECLARATION(Register, Lentry_args , L0); // pointer to args passed to callee (interpreter) not stub itself | |
132 | |
133 // Interpreter frames | |
134 | |
135 #ifdef CC_INTERP | |
136 REGISTER_DECLARATION(Register, Lstate , L0); // interpreter state object pointer | |
137 REGISTER_DECLARATION(Register, L1_scratch , L1); // scratch | |
138 REGISTER_DECLARATION(Register, Lmirror , L1); // mirror (for native methods only) | |
139 REGISTER_DECLARATION(Register, L2_scratch , L2); | |
140 REGISTER_DECLARATION(Register, L3_scratch , L3); | |
141 REGISTER_DECLARATION(Register, L4_scratch , L4); | |
142 REGISTER_DECLARATION(Register, Lscratch , L5); // C1 uses | |
143 REGISTER_DECLARATION(Register, Lscratch2 , L6); // C1 uses | |
144 REGISTER_DECLARATION(Register, L7_scratch , L7); // constant pool cache | |
145 REGISTER_DECLARATION(Register, O5_savedSP , O5); | |
146 REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply | |
147 // a copy SP, so in 64-bit it's a biased value. The bias | |
148 // is added and removed as needed in the frame code. | |
149 // Interface to signature handler | |
150 REGISTER_DECLARATION(Register, Llocals , L7); // pointer to locals for signature handler | |
151 REGISTER_DECLARATION(Register, Lmethod , L6); // methodOop when calling signature handler | |
152 | |
153 #else | |
154 REGISTER_DECLARATION(Register, Lesp , L0); // expression stack pointer | |
155 REGISTER_DECLARATION(Register, Lbcp , L1); // pointer to next bytecode | |
156 REGISTER_DECLARATION(Register, Lmethod , L2); | |
157 REGISTER_DECLARATION(Register, Llocals , L3); | |
158 REGISTER_DECLARATION(Register, Largs , L3); // pointer to locals for signature handler | |
159 // must match Llocals in asm interpreter | |
160 REGISTER_DECLARATION(Register, Lmonitors , L4); | |
161 REGISTER_DECLARATION(Register, Lbyte_code , L5); | |
162 // When calling out from the interpreter we record SP so that we can remove any extra stack | |
163 // space allocated during adapter transitions. This register is only live from the point | |
164 // of the call until we return. | |
165 REGISTER_DECLARATION(Register, Llast_SP , L5); | |
166 REGISTER_DECLARATION(Register, Lscratch , L5); | |
167 REGISTER_DECLARATION(Register, Lscratch2 , L6); | |
168 REGISTER_DECLARATION(Register, LcpoolCache , L6); // constant pool cache | |
169 | |
170 REGISTER_DECLARATION(Register, O5_savedSP , O5); | |
171 REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply | |
172 // a copy SP, so in 64-bit it's a biased value. The bias | |
173 // is added and removed as needed in the frame code. | |
174 REGISTER_DECLARATION(Register, IdispatchTables , I4); // Base address of the bytecode dispatch tables | |
175 REGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode | |
176 REGISTER_DECLARATION(Register, ImethodDataPtr , I2); // Pointer to the current method data | |
177 #endif /* CC_INTERP */ | |
178 | |
179 // NOTE: Lscratch2 and LcpoolCache point to the same registers in | |
180 // the interpreter code. If Lscratch2 needs to be used for some | |
181 // purpose than LcpoolCache should be restore after that for | |
182 // the interpreter to work right | |
183 // (These assignments must be compatible with L7_thread_cache; see above.) | |
184 | |
185 // Since Lbcp points into the middle of the method object, | |
186 // it is temporarily converted into a "bcx" during GC. | |
187 | |
188 // Exception processing | |
189 // These registers are passed into exception handlers. | |
190 // All exception handlers require the exception object being thrown. | |
191 // In addition, an nmethod's exception handler must be passed | |
192 // the address of the call site within the nmethod, to allow | |
193 // proper selection of the applicable catch block. | |
194 // (Interpreter frames use their own bcp() for this purpose.) | |
195 // | |
196 // The Oissuing_pc value is not always needed. When jumping to a | |
197 // handler that is known to be interpreted, the Oissuing_pc value can be | |
198 // omitted. An actual catch block in compiled code receives (from its | |
199 // nmethod's exception handler) the thrown exception in the Oexception, | |
200 // but it doesn't need the Oissuing_pc. | |
201 // | |
202 // If an exception handler (either interpreted or compiled) | |
203 // discovers there is no applicable catch block, it updates | |
204 // the Oissuing_pc to the continuation PC of its own caller, | |
205 // pops back to that caller's stack frame, and executes that | |
206 // caller's exception handler. Obviously, this process will | |
207 // iterate until the control stack is popped back to a method | |
208 // containing an applicable catch block. A key invariant is | |
209 // that the Oissuing_pc value is always a value local to | |
210 // the method whose exception handler is currently executing. | |
211 // | |
212 // Note: The issuing PC value is __not__ a raw return address (I7 value). | |
213 // It is a "return pc", the address __following__ the call. | |
214 // Raw return addresses are converted to issuing PCs by frame::pc(), | |
215 // or by stubs. Issuing PCs can be used directly with PC range tables. | |
216 // | |
217 REGISTER_DECLARATION(Register, Oexception , O0); // exception being thrown | |
218 REGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from | |
219 | |
220 | |
221 // These must occur after the declarations above | |
222 #ifndef DONT_USE_REGISTER_DEFINES | |
223 | |
224 #define Gthread AS_REGISTER(Register, Gthread) | |
225 #define Gmethod AS_REGISTER(Register, Gmethod) | |
226 #define Gmegamorphic_method AS_REGISTER(Register, Gmegamorphic_method) | |
227 #define Ginline_cache_reg AS_REGISTER(Register, Ginline_cache_reg) | |
228 #define Gargs AS_REGISTER(Register, Gargs) | |
229 #define Lthread_cache AS_REGISTER(Register, Lthread_cache) | |
230 #define Gframe_size AS_REGISTER(Register, Gframe_size) | |
231 #define Gtemp AS_REGISTER(Register, Gtemp) | |
232 | |
233 #ifdef CC_INTERP | |
234 #define Lstate AS_REGISTER(Register, Lstate) | |
235 #define Lesp AS_REGISTER(Register, Lesp) | |
236 #define L1_scratch AS_REGISTER(Register, L1_scratch) | |
237 #define Lmirror AS_REGISTER(Register, Lmirror) | |
238 #define L2_scratch AS_REGISTER(Register, L2_scratch) | |
239 #define L3_scratch AS_REGISTER(Register, L3_scratch) | |
240 #define L4_scratch AS_REGISTER(Register, L4_scratch) | |
241 #define Lscratch AS_REGISTER(Register, Lscratch) | |
242 #define Lscratch2 AS_REGISTER(Register, Lscratch2) | |
243 #define L7_scratch AS_REGISTER(Register, L7_scratch) | |
244 #define Ostate AS_REGISTER(Register, Ostate) | |
245 #else | |
246 #define Lesp AS_REGISTER(Register, Lesp) | |
247 #define Lbcp AS_REGISTER(Register, Lbcp) | |
248 #define Lmethod AS_REGISTER(Register, Lmethod) | |
249 #define Llocals AS_REGISTER(Register, Llocals) | |
250 #define Lmonitors AS_REGISTER(Register, Lmonitors) | |
251 #define Lbyte_code AS_REGISTER(Register, Lbyte_code) | |
252 #define Lscratch AS_REGISTER(Register, Lscratch) | |
253 #define Lscratch2 AS_REGISTER(Register, Lscratch2) | |
254 #define LcpoolCache AS_REGISTER(Register, LcpoolCache) | |
255 #endif /* ! CC_INTERP */ | |
256 | |
257 #define Lentry_args AS_REGISTER(Register, Lentry_args) | |
258 #define I5_savedSP AS_REGISTER(Register, I5_savedSP) | |
259 #define O5_savedSP AS_REGISTER(Register, O5_savedSP) | |
260 #define IdispatchAddress AS_REGISTER(Register, IdispatchAddress) | |
261 #define ImethodDataPtr AS_REGISTER(Register, ImethodDataPtr) | |
262 #define IdispatchTables AS_REGISTER(Register, IdispatchTables) | |
263 | |
264 #define Oexception AS_REGISTER(Register, Oexception) | |
265 #define Oissuing_pc AS_REGISTER(Register, Oissuing_pc) | |
266 | |
267 | |
268 #endif | |
269 | |
270 // Address is an abstraction used to represent a memory location. | |
271 // | |
272 // Note: A register location is represented via a Register, not | |
273 // via an address for efficiency & simplicity reasons. | |
274 | |
275 class Address VALUE_OBJ_CLASS_SPEC { | |
276 private: | |
277 Register _base; | |
278 #ifdef _LP64 | |
279 int _hi32; // bits 63::32 | |
280 int _low32; // bits 31::0 | |
281 #endif | |
282 int _hi; | |
283 int _disp; | |
284 RelocationHolder _rspec; | |
285 | |
286 RelocationHolder rspec_from_rtype(relocInfo::relocType rt, address a = NULL) { | |
287 switch (rt) { | |
288 case relocInfo::external_word_type: | |
289 return external_word_Relocation::spec(a); | |
290 case relocInfo::internal_word_type: | |
291 return internal_word_Relocation::spec(a); | |
292 #ifdef _LP64 | |
293 case relocInfo::opt_virtual_call_type: | |
294 return opt_virtual_call_Relocation::spec(); | |
295 case relocInfo::static_call_type: | |
296 return static_call_Relocation::spec(); | |
297 case relocInfo::runtime_call_type: | |
298 return runtime_call_Relocation::spec(); | |
299 #endif | |
300 case relocInfo::none: | |
301 return RelocationHolder(); | |
302 default: | |
303 ShouldNotReachHere(); | |
304 return RelocationHolder(); | |
305 } | |
306 } | |
307 | |
308 public: | |
309 Address(Register b, address a, relocInfo::relocType rt = relocInfo::none) | |
310 : _rspec(rspec_from_rtype(rt, a)) | |
311 { | |
312 _base = b; | |
313 #ifdef _LP64 | |
314 _hi32 = (intptr_t)a >> 32; // top 32 bits in 64 bit word | |
315 _low32 = (intptr_t)a & ~0; // low 32 bits in 64 bit word | |
316 #endif | |
317 _hi = (intptr_t)a & ~0x3ff; // top 22 bits in low word | |
318 _disp = (intptr_t)a & 0x3ff; // bottom 10 bits | |
319 } | |
320 | |
321 Address(Register b, address a, RelocationHolder const& rspec) | |
322 : _rspec(rspec) | |
323 { | |
324 _base = b; | |
325 #ifdef _LP64 | |
326 _hi32 = (intptr_t)a >> 32; // top 32 bits in 64 bit word | |
327 _low32 = (intptr_t)a & ~0; // low 32 bits in 64 bit word | |
328 #endif | |
329 _hi = (intptr_t)a & ~0x3ff; // top 22 bits | |
330 _disp = (intptr_t)a & 0x3ff; // bottom 10 bits | |
331 } | |
332 | |
333 Address(Register b, intptr_t h, intptr_t d, RelocationHolder const& rspec = RelocationHolder()) | |
334 : _rspec(rspec) | |
335 { | |
336 _base = b; | |
337 #ifdef _LP64 | |
338 // [RGV] Put in Assert to force me to check usage of this constructor | |
339 assert( h == 0, "Check usage of this constructor" ); | |
340 _hi32 = h; | |
341 _low32 = d; | |
342 _hi = h; | |
343 _disp = d; | |
344 #else | |
345 _hi = h; | |
346 _disp = d; | |
347 #endif | |
348 } | |
349 | |
350 Address() | |
351 : _rspec(RelocationHolder()) | |
352 { | |
353 _base = G0; | |
354 #ifdef _LP64 | |
355 _hi32 = 0; | |
356 _low32 = 0; | |
357 #endif | |
358 _hi = 0; | |
359 _disp = 0; | |
360 } | |
361 | |
362 // fancier constructors | |
363 | |
364 enum addr_type { | |
365 extra_in_argument, // in the In registers | |
366 extra_out_argument // in the Outs | |
367 }; | |
368 | |
369 Address( addr_type, int ); | |
370 | |
371 // accessors | |
372 | |
373 Register base() const { return _base; } | |
374 #ifdef _LP64 | |
375 int hi32() const { return _hi32; } | |
376 int low32() const { return _low32; } | |
377 #endif | |
378 int hi() const { return _hi; } | |
379 int disp() const { return _disp; } | |
380 #ifdef _LP64 | |
381 intptr_t value() const { return ((intptr_t)_hi32 << 32) | | |
382 (intptr_t)(uint32_t)_low32; } | |
383 #else | |
384 int value() const { return _hi | _disp; } | |
385 #endif | |
386 const relocInfo::relocType rtype() { return _rspec.type(); } | |
387 const RelocationHolder& rspec() { return _rspec; } | |
388 | |
389 RelocationHolder rspec(int offset) const { | |
390 return offset == 0 ? _rspec : _rspec.plus(offset); | |
391 } | |
392 | |
393 inline bool is_simm13(int offset = 0); // check disp+offset for overflow | |
394 | |
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395 Address plus_disp(int disp) const { // bump disp by a small amount |
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396 Address a = (*this); |
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397 a._disp += disp; |
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398 return a; |
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399 } |
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400 |
0 | 401 Address split_disp() const { // deal with disp overflow |
402 Address a = (*this); | |
403 int hi_disp = _disp & ~0x3ff; | |
404 if (hi_disp != 0) { | |
405 a._disp -= hi_disp; | |
406 a._hi += hi_disp; | |
407 } | |
408 return a; | |
409 } | |
410 | |
411 Address after_save() const { | |
412 Address a = (*this); | |
413 a._base = a._base->after_save(); | |
414 return a; | |
415 } | |
416 | |
417 Address after_restore() const { | |
418 Address a = (*this); | |
419 a._base = a._base->after_restore(); | |
420 return a; | |
421 } | |
422 | |
423 friend class Assembler; | |
424 }; | |
425 | |
426 | |
427 inline Address RegisterImpl::address_in_saved_window() const { | |
428 return (Address(SP, 0, (sp_offset_in_saved_window() * wordSize) + STACK_BIAS)); | |
429 } | |
430 | |
431 | |
432 | |
433 // Argument is an abstraction used to represent an outgoing | |
434 // actual argument or an incoming formal parameter, whether | |
435 // it resides in memory or in a register, in a manner consistent | |
436 // with the SPARC Application Binary Interface, or ABI. This is | |
437 // often referred to as the native or C calling convention. | |
438 | |
439 class Argument VALUE_OBJ_CLASS_SPEC { | |
440 private: | |
441 int _number; | |
442 bool _is_in; | |
443 | |
444 public: | |
445 #ifdef _LP64 | |
446 enum { | |
447 n_register_parameters = 6, // only 6 registers may contain integer parameters | |
448 n_float_register_parameters = 16 // Can have up to 16 floating registers | |
449 }; | |
450 #else | |
451 enum { | |
452 n_register_parameters = 6 // only 6 registers may contain integer parameters | |
453 }; | |
454 #endif | |
455 | |
456 // creation | |
457 Argument(int number, bool is_in) : _number(number), _is_in(is_in) {} | |
458 | |
459 int number() const { return _number; } | |
460 bool is_in() const { return _is_in; } | |
461 bool is_out() const { return !is_in(); } | |
462 | |
463 Argument successor() const { return Argument(number() + 1, is_in()); } | |
464 Argument as_in() const { return Argument(number(), true ); } | |
465 Argument as_out() const { return Argument(number(), false); } | |
466 | |
467 // locating register-based arguments: | |
468 bool is_register() const { return _number < n_register_parameters; } | |
469 | |
470 #ifdef _LP64 | |
471 // locating Floating Point register-based arguments: | |
472 bool is_float_register() const { return _number < n_float_register_parameters; } | |
473 | |
474 FloatRegister as_float_register() const { | |
475 assert(is_float_register(), "must be a register argument"); | |
476 return as_FloatRegister(( number() *2 ) + 1); | |
477 } | |
478 FloatRegister as_double_register() const { | |
479 assert(is_float_register(), "must be a register argument"); | |
480 return as_FloatRegister(( number() *2 )); | |
481 } | |
482 #endif | |
483 | |
484 Register as_register() const { | |
485 assert(is_register(), "must be a register argument"); | |
486 return is_in() ? as_iRegister(number()) : as_oRegister(number()); | |
487 } | |
488 | |
489 // locating memory-based arguments | |
490 Address as_address() const { | |
491 assert(!is_register(), "must be a memory argument"); | |
492 return address_in_frame(); | |
493 } | |
494 | |
495 // When applied to a register-based argument, give the corresponding address | |
496 // into the 6-word area "into which callee may store register arguments" | |
497 // (This is a different place than the corresponding register-save area location.) | |
498 Address address_in_frame() const { | |
499 return Address( is_in() ? Address::extra_in_argument | |
500 : Address::extra_out_argument, | |
501 _number ); | |
502 } | |
503 | |
504 // debugging | |
505 const char* name() const; | |
506 | |
507 friend class Assembler; | |
508 }; | |
509 | |
510 | |
511 // The SPARC Assembler: Pure assembler doing NO optimizations on the instruction | |
512 // level; i.e., what you write | |
513 // is what you get. The Assembler is generating code into a CodeBuffer. | |
514 | |
515 class Assembler : public AbstractAssembler { | |
516 protected: | |
517 | |
518 static void print_instruction(int inst); | |
519 static int patched_branch(int dest_pos, int inst, int inst_pos); | |
520 static int branch_destination(int inst, int pos); | |
521 | |
522 | |
523 friend class AbstractAssembler; | |
524 | |
525 // code patchers need various routines like inv_wdisp() | |
526 friend class NativeInstruction; | |
527 friend class NativeGeneralJump; | |
528 friend class Relocation; | |
529 friend class Label; | |
530 | |
531 public: | |
532 // op carries format info; see page 62 & 267 | |
533 | |
534 enum ops { | |
535 call_op = 1, // fmt 1 | |
536 branch_op = 0, // also sethi (fmt2) | |
537 arith_op = 2, // fmt 3, arith & misc | |
538 ldst_op = 3 // fmt 3, load/store | |
539 }; | |
540 | |
541 enum op2s { | |
542 bpr_op2 = 3, | |
543 fb_op2 = 6, | |
544 fbp_op2 = 5, | |
545 br_op2 = 2, | |
546 bp_op2 = 1, | |
547 cb_op2 = 7, // V8 | |
548 sethi_op2 = 4 | |
549 }; | |
550 | |
551 enum op3s { | |
552 // selected op3s | |
553 add_op3 = 0x00, | |
554 and_op3 = 0x01, | |
555 or_op3 = 0x02, | |
556 xor_op3 = 0x03, | |
557 sub_op3 = 0x04, | |
558 andn_op3 = 0x05, | |
559 orn_op3 = 0x06, | |
560 xnor_op3 = 0x07, | |
561 addc_op3 = 0x08, | |
562 mulx_op3 = 0x09, | |
563 umul_op3 = 0x0a, | |
564 smul_op3 = 0x0b, | |
565 subc_op3 = 0x0c, | |
566 udivx_op3 = 0x0d, | |
567 udiv_op3 = 0x0e, | |
568 sdiv_op3 = 0x0f, | |
569 | |
570 addcc_op3 = 0x10, | |
571 andcc_op3 = 0x11, | |
572 orcc_op3 = 0x12, | |
573 xorcc_op3 = 0x13, | |
574 subcc_op3 = 0x14, | |
575 andncc_op3 = 0x15, | |
576 orncc_op3 = 0x16, | |
577 xnorcc_op3 = 0x17, | |
578 addccc_op3 = 0x18, | |
579 umulcc_op3 = 0x1a, | |
580 smulcc_op3 = 0x1b, | |
581 subccc_op3 = 0x1c, | |
582 udivcc_op3 = 0x1e, | |
583 sdivcc_op3 = 0x1f, | |
584 | |
585 taddcc_op3 = 0x20, | |
586 tsubcc_op3 = 0x21, | |
587 taddcctv_op3 = 0x22, | |
588 tsubcctv_op3 = 0x23, | |
589 mulscc_op3 = 0x24, | |
590 sll_op3 = 0x25, | |
591 sllx_op3 = 0x25, | |
592 srl_op3 = 0x26, | |
593 srlx_op3 = 0x26, | |
594 sra_op3 = 0x27, | |
595 srax_op3 = 0x27, | |
596 rdreg_op3 = 0x28, | |
597 membar_op3 = 0x28, | |
598 | |
599 flushw_op3 = 0x2b, | |
600 movcc_op3 = 0x2c, | |
601 sdivx_op3 = 0x2d, | |
602 popc_op3 = 0x2e, | |
603 movr_op3 = 0x2f, | |
604 | |
605 sir_op3 = 0x30, | |
606 wrreg_op3 = 0x30, | |
607 saved_op3 = 0x31, | |
608 | |
609 fpop1_op3 = 0x34, | |
610 fpop2_op3 = 0x35, | |
611 impdep1_op3 = 0x36, | |
612 impdep2_op3 = 0x37, | |
613 jmpl_op3 = 0x38, | |
614 rett_op3 = 0x39, | |
615 trap_op3 = 0x3a, | |
616 flush_op3 = 0x3b, | |
617 save_op3 = 0x3c, | |
618 restore_op3 = 0x3d, | |
619 done_op3 = 0x3e, | |
620 retry_op3 = 0x3e, | |
621 | |
622 lduw_op3 = 0x00, | |
623 ldub_op3 = 0x01, | |
624 lduh_op3 = 0x02, | |
625 ldd_op3 = 0x03, | |
626 stw_op3 = 0x04, | |
627 stb_op3 = 0x05, | |
628 sth_op3 = 0x06, | |
629 std_op3 = 0x07, | |
630 ldsw_op3 = 0x08, | |
631 ldsb_op3 = 0x09, | |
632 ldsh_op3 = 0x0a, | |
633 ldx_op3 = 0x0b, | |
634 | |
635 ldstub_op3 = 0x0d, | |
636 stx_op3 = 0x0e, | |
637 swap_op3 = 0x0f, | |
638 | |
639 lduwa_op3 = 0x10, | |
640 ldxa_op3 = 0x1b, | |
641 | |
642 stwa_op3 = 0x14, | |
643 stxa_op3 = 0x1e, | |
644 | |
645 ldf_op3 = 0x20, | |
646 ldfsr_op3 = 0x21, | |
647 ldqf_op3 = 0x22, | |
648 lddf_op3 = 0x23, | |
649 stf_op3 = 0x24, | |
650 stfsr_op3 = 0x25, | |
651 stqf_op3 = 0x26, | |
652 stdf_op3 = 0x27, | |
653 | |
654 prefetch_op3 = 0x2d, | |
655 | |
656 | |
657 ldc_op3 = 0x30, | |
658 ldcsr_op3 = 0x31, | |
659 lddc_op3 = 0x33, | |
660 stc_op3 = 0x34, | |
661 stcsr_op3 = 0x35, | |
662 stdcq_op3 = 0x36, | |
663 stdc_op3 = 0x37, | |
664 | |
665 casa_op3 = 0x3c, | |
666 casxa_op3 = 0x3e, | |
667 | |
668 alt_bit_op3 = 0x10, | |
669 cc_bit_op3 = 0x10 | |
670 }; | |
671 | |
672 enum opfs { | |
673 // selected opfs | |
674 fmovs_opf = 0x01, | |
675 fmovd_opf = 0x02, | |
676 | |
677 fnegs_opf = 0x05, | |
678 fnegd_opf = 0x06, | |
679 | |
680 fadds_opf = 0x41, | |
681 faddd_opf = 0x42, | |
682 fsubs_opf = 0x45, | |
683 fsubd_opf = 0x46, | |
684 | |
685 fmuls_opf = 0x49, | |
686 fmuld_opf = 0x4a, | |
687 fdivs_opf = 0x4d, | |
688 fdivd_opf = 0x4e, | |
689 | |
690 fcmps_opf = 0x51, | |
691 fcmpd_opf = 0x52, | |
692 | |
693 fstox_opf = 0x81, | |
694 fdtox_opf = 0x82, | |
695 fxtos_opf = 0x84, | |
696 fxtod_opf = 0x88, | |
697 fitos_opf = 0xc4, | |
698 fdtos_opf = 0xc6, | |
699 fitod_opf = 0xc8, | |
700 fstod_opf = 0xc9, | |
701 fstoi_opf = 0xd1, | |
702 fdtoi_opf = 0xd2 | |
703 }; | |
704 | |
705 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7 }; | |
706 | |
707 enum Condition { | |
708 // for FBfcc & FBPfcc instruction | |
709 f_never = 0, | |
710 f_notEqual = 1, | |
711 f_notZero = 1, | |
712 f_lessOrGreater = 2, | |
713 f_unorderedOrLess = 3, | |
714 f_less = 4, | |
715 f_unorderedOrGreater = 5, | |
716 f_greater = 6, | |
717 f_unordered = 7, | |
718 f_always = 8, | |
719 f_equal = 9, | |
720 f_zero = 9, | |
721 f_unorderedOrEqual = 10, | |
722 f_greaterOrEqual = 11, | |
723 f_unorderedOrGreaterOrEqual = 12, | |
724 f_lessOrEqual = 13, | |
725 f_unorderedOrLessOrEqual = 14, | |
726 f_ordered = 15, | |
727 | |
728 // V8 coproc, pp 123 v8 manual | |
729 | |
730 cp_always = 8, | |
731 cp_never = 0, | |
732 cp_3 = 7, | |
733 cp_2 = 6, | |
734 cp_2or3 = 5, | |
735 cp_1 = 4, | |
736 cp_1or3 = 3, | |
737 cp_1or2 = 2, | |
738 cp_1or2or3 = 1, | |
739 cp_0 = 9, | |
740 cp_0or3 = 10, | |
741 cp_0or2 = 11, | |
742 cp_0or2or3 = 12, | |
743 cp_0or1 = 13, | |
744 cp_0or1or3 = 14, | |
745 cp_0or1or2 = 15, | |
746 | |
747 | |
748 // for integers | |
749 | |
750 never = 0, | |
751 equal = 1, | |
752 zero = 1, | |
753 lessEqual = 2, | |
754 less = 3, | |
755 lessEqualUnsigned = 4, | |
756 lessUnsigned = 5, | |
757 carrySet = 5, | |
758 negative = 6, | |
759 overflowSet = 7, | |
760 always = 8, | |
761 notEqual = 9, | |
762 notZero = 9, | |
763 greater = 10, | |
764 greaterEqual = 11, | |
765 greaterUnsigned = 12, | |
766 greaterEqualUnsigned = 13, | |
767 carryClear = 13, | |
768 positive = 14, | |
769 overflowClear = 15 | |
770 }; | |
771 | |
772 enum CC { | |
773 icc = 0, xcc = 2, | |
774 // ptr_cc is the correct condition code for a pointer or intptr_t: | |
775 ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc), | |
776 fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3 | |
777 }; | |
778 | |
779 enum PrefetchFcn { | |
780 severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4 | |
781 }; | |
782 | |
783 public: | |
784 // Helper functions for groups of instructions | |
785 | |
786 enum Predict { pt = 1, pn = 0 }; // pt = predict taken | |
787 | |
788 enum Membar_mask_bits { // page 184, v9 | |
789 StoreStore = 1 << 3, | |
790 LoadStore = 1 << 2, | |
791 StoreLoad = 1 << 1, | |
792 LoadLoad = 1 << 0, | |
793 | |
794 Sync = 1 << 6, | |
795 MemIssue = 1 << 5, | |
796 Lookaside = 1 << 4 | |
797 }; | |
798 | |
799 // test if x is within signed immediate range for nbits | |
800 static bool is_simm(int x, int nbits) { return -( 1 << nbits-1 ) <= x && x < ( 1 << nbits-1 ); } | |
801 | |
802 // test if -4096 <= x <= 4095 | |
803 static bool is_simm13(int x) { return is_simm(x, 13); } | |
804 | |
805 enum ASIs { // page 72, v9 | |
806 ASI_PRIMARY = 0x80, | |
807 ASI_PRIMARY_LITTLE = 0x88 | |
808 // add more from book as needed | |
809 }; | |
810 | |
811 protected: | |
812 // helpers | |
813 | |
814 // x is supposed to fit in a field "nbits" wide | |
815 // and be sign-extended. Check the range. | |
816 | |
817 static void assert_signed_range(intptr_t x, int nbits) { | |
818 assert( nbits == 32 | |
819 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1), | |
820 "value out of range"); | |
821 } | |
822 | |
823 static void assert_signed_word_disp_range(intptr_t x, int nbits) { | |
824 assert( (x & 3) == 0, "not word aligned"); | |
825 assert_signed_range(x, nbits + 2); | |
826 } | |
827 | |
828 static void assert_unsigned_const(int x, int nbits) { | |
829 assert( juint(x) < juint(1 << nbits), "unsigned constant out of range"); | |
830 } | |
831 | |
832 // fields: note bits numbered from LSB = 0, | |
833 // fields known by inclusive bit range | |
834 | |
835 static int fmask(juint hi_bit, juint lo_bit) { | |
836 assert( hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits"); | |
837 return (1 << ( hi_bit-lo_bit + 1 )) - 1; | |
838 } | |
839 | |
840 // inverse of u_field | |
841 | |
842 static int inv_u_field(int x, int hi_bit, int lo_bit) { | |
843 juint r = juint(x) >> lo_bit; | |
844 r &= fmask( hi_bit, lo_bit); | |
845 return int(r); | |
846 } | |
847 | |
848 | |
849 // signed version: extract from field and sign-extend | |
850 | |
851 static int inv_s_field(int x, int hi_bit, int lo_bit) { | |
852 int sign_shift = 31 - hi_bit; | |
853 return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit); | |
854 } | |
855 | |
856 // given a field that ranges from hi_bit to lo_bit (inclusive, | |
857 // LSB = 0), and an unsigned value for the field, | |
858 // shift it into the field | |
859 | |
860 #ifdef ASSERT | |
861 static int u_field(int x, int hi_bit, int lo_bit) { | |
862 assert( ( x & ~fmask(hi_bit, lo_bit)) == 0, | |
863 "value out of range"); | |
864 int r = x << lo_bit; | |
865 assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking"); | |
866 return r; | |
867 } | |
868 #else | |
869 // make sure this is inlined as it will reduce code size significantly | |
870 #define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit)) | |
871 #endif | |
872 | |
873 static int inv_op( int x ) { return inv_u_field(x, 31, 30); } | |
874 static int inv_op2( int x ) { return inv_u_field(x, 24, 22); } | |
875 static int inv_op3( int x ) { return inv_u_field(x, 24, 19); } | |
876 static int inv_cond( int x ){ return inv_u_field(x, 28, 25); } | |
877 | |
878 static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; } | |
879 | |
880 static Register inv_rd( int x ) { return as_Register(inv_u_field(x, 29, 25)); } | |
881 static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); } | |
882 static Register inv_rs2( int x ) { return as_Register(inv_u_field(x, 4, 0)); } | |
883 | |
884 static int op( int x) { return u_field(x, 31, 30); } | |
885 static int rd( Register r) { return u_field(r->encoding(), 29, 25); } | |
886 static int fcn( int x) { return u_field(x, 29, 25); } | |
887 static int op3( int x) { return u_field(x, 24, 19); } | |
888 static int rs1( Register r) { return u_field(r->encoding(), 18, 14); } | |
889 static int rs2( Register r) { return u_field(r->encoding(), 4, 0); } | |
890 static int annul( bool a) { return u_field(a ? 1 : 0, 29, 29); } | |
891 static int cond( int x) { return u_field(x, 28, 25); } | |
892 static int cond_mov( int x) { return u_field(x, 17, 14); } | |
893 static int rcond( RCondition x) { return u_field(x, 12, 10); } | |
894 static int op2( int x) { return u_field(x, 24, 22); } | |
895 static int predict( bool p) { return u_field(p ? 1 : 0, 19, 19); } | |
896 static int branchcc( CC fcca) { return u_field(fcca, 21, 20); } | |
897 static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); } | |
898 static int imm_asi( int x) { return u_field(x, 12, 5); } | |
899 static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); } | |
900 static int opf_low6( int w) { return u_field(w, 10, 5); } | |
901 static int opf_low5( int w) { return u_field(w, 9, 5); } | |
902 static int trapcc( CC cc) { return u_field(cc, 12, 11); } | |
903 static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit | |
904 static int opf( int x) { return u_field(x, 13, 5); } | |
905 | |
906 static int opf_cc( CC c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); } | |
907 static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); } | |
908 | |
909 static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); }; | |
910 static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); }; | |
911 static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); }; | |
912 | |
913 // some float instructions use this encoding on the op3 field | |
914 static int alt_op3(int op, FloatRegisterImpl::Width w) { | |
915 int r; | |
916 switch(w) { | |
917 case FloatRegisterImpl::S: r = op + 0; break; | |
918 case FloatRegisterImpl::D: r = op + 3; break; | |
919 case FloatRegisterImpl::Q: r = op + 2; break; | |
920 default: ShouldNotReachHere(); break; | |
921 } | |
922 return op3(r); | |
923 } | |
924 | |
925 | |
926 // compute inverse of simm | |
927 static int inv_simm(int x, int nbits) { | |
928 return (int)(x << (32 - nbits)) >> (32 - nbits); | |
929 } | |
930 | |
931 static int inv_simm13( int x ) { return inv_simm(x, 13); } | |
932 | |
933 // signed immediate, in low bits, nbits long | |
934 static int simm(int x, int nbits) { | |
935 assert_signed_range(x, nbits); | |
936 return x & (( 1 << nbits ) - 1); | |
937 } | |
938 | |
939 // compute inverse of wdisp16 | |
940 static intptr_t inv_wdisp16(int x, intptr_t pos) { | |
941 int lo = x & (( 1 << 14 ) - 1); | |
942 int hi = (x >> 20) & 3; | |
943 if (hi >= 2) hi |= ~1; | |
944 return (((hi << 14) | lo) << 2) + pos; | |
945 } | |
946 | |
947 // word offset, 14 bits at LSend, 2 bits at B21, B20 | |
948 static int wdisp16(intptr_t x, intptr_t off) { | |
949 intptr_t xx = x - off; | |
950 assert_signed_word_disp_range(xx, 16); | |
951 int r = (xx >> 2) & ((1 << 14) - 1) | |
952 | ( ( (xx>>(2+14)) & 3 ) << 20 ); | |
953 assert( inv_wdisp16(r, off) == x, "inverse is not inverse"); | |
954 return r; | |
955 } | |
956 | |
957 | |
958 // word displacement in low-order nbits bits | |
959 | |
960 static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) { | |
961 int pre_sign_extend = x & (( 1 << nbits ) - 1); | |
962 int r = pre_sign_extend >= ( 1 << (nbits-1) ) | |
963 ? pre_sign_extend | ~(( 1 << nbits ) - 1) | |
964 : pre_sign_extend; | |
965 return (r << 2) + pos; | |
966 } | |
967 | |
968 static int wdisp( intptr_t x, intptr_t off, int nbits ) { | |
969 intptr_t xx = x - off; | |
970 assert_signed_word_disp_range(xx, nbits); | |
971 int r = (xx >> 2) & (( 1 << nbits ) - 1); | |
972 assert( inv_wdisp( r, off, nbits ) == x, "inverse not inverse"); | |
973 return r; | |
974 } | |
975 | |
976 | |
977 // Extract the top 32 bits in a 64 bit word | |
978 static int32_t hi32( int64_t x ) { | |
979 int32_t r = int32_t( (uint64_t)x >> 32 ); | |
980 return r; | |
981 } | |
982 | |
983 // given a sethi instruction, extract the constant, left-justified | |
984 static int inv_hi22( int x ) { | |
985 return x << 10; | |
986 } | |
987 | |
988 // create an imm22 field, given a 32-bit left-justified constant | |
989 static int hi22( int x ) { | |
990 int r = int( juint(x) >> 10 ); | |
991 assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'"); | |
992 return r; | |
993 } | |
994 | |
995 // create a low10 __value__ (not a field) for a given a 32-bit constant | |
996 static int low10( int x ) { | |
997 return x & ((1 << 10) - 1); | |
998 } | |
999 | |
1000 // instruction only in v9 | |
1001 static void v9_only() { assert( VM_Version::v9_instructions_work(), "This instruction only works on SPARC V9"); } | |
1002 | |
1003 // instruction only in v8 | |
1004 static void v8_only() { assert( VM_Version::v8_instructions_work(), "This instruction only works on SPARC V8"); } | |
1005 | |
1006 // instruction deprecated in v9 | |
1007 static void v9_dep() { } // do nothing for now | |
1008 | |
1009 // some float instructions only exist for single prec. on v8 | |
1010 static void v8_s_only(FloatRegisterImpl::Width w) { if (w != FloatRegisterImpl::S) v9_only(); } | |
1011 | |
1012 // v8 has no CC field | |
1013 static void v8_no_cc(CC cc) { if (cc) v9_only(); } | |
1014 | |
1015 protected: | |
1016 // Simple delay-slot scheme: | |
1017 // In order to check the programmer, the assembler keeps track of deley slots. | |
1018 // It forbids CTIs in delay slots (conservative, but should be OK). | |
1019 // Also, when putting an instruction into a delay slot, you must say | |
1020 // asm->delayed()->add(...), in order to check that you don't omit | |
1021 // delay-slot instructions. | |
1022 // To implement this, we use a simple FSA | |
1023 | |
1024 #ifdef ASSERT | |
1025 #define CHECK_DELAY | |
1026 #endif | |
1027 #ifdef CHECK_DELAY | |
1028 enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state; | |
1029 #endif | |
1030 | |
1031 public: | |
1032 // Tells assembler next instruction must NOT be in delay slot. | |
1033 // Use at start of multinstruction macros. | |
1034 void assert_not_delayed() { | |
1035 // This is a separate overloading to avoid creation of string constants | |
1036 // in non-asserted code--with some compilers this pollutes the object code. | |
1037 #ifdef CHECK_DELAY | |
1038 assert_not_delayed("next instruction should not be a delay slot"); | |
1039 #endif | |
1040 } | |
1041 void assert_not_delayed(const char* msg) { | |
1042 #ifdef CHECK_DELAY | |
1043 assert_msg ( delay_state == no_delay, msg); | |
1044 #endif | |
1045 } | |
1046 | |
1047 protected: | |
1048 // Delay slot helpers | |
1049 // cti is called when emitting control-transfer instruction, | |
1050 // BEFORE doing the emitting. | |
1051 // Only effective when assertion-checking is enabled. | |
1052 void cti() { | |
1053 #ifdef CHECK_DELAY | |
1054 assert_not_delayed("cti should not be in delay slot"); | |
1055 #endif | |
1056 } | |
1057 | |
1058 // called when emitting cti with a delay slot, AFTER emitting | |
1059 void has_delay_slot() { | |
1060 #ifdef CHECK_DELAY | |
1061 assert_not_delayed("just checking"); | |
1062 delay_state = at_delay_slot; | |
1063 #endif | |
1064 } | |
1065 | |
1066 public: | |
1067 // Tells assembler you know that next instruction is delayed | |
1068 Assembler* delayed() { | |
1069 #ifdef CHECK_DELAY | |
1070 assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot"); | |
1071 delay_state = filling_delay_slot; | |
1072 #endif | |
1073 return this; | |
1074 } | |
1075 | |
1076 void flush() { | |
1077 #ifdef CHECK_DELAY | |
1078 assert ( delay_state == no_delay, "ending code with a delay slot"); | |
1079 #endif | |
1080 AbstractAssembler::flush(); | |
1081 } | |
1082 | |
1083 inline void emit_long(int); // shadows AbstractAssembler::emit_long | |
1084 inline void emit_data(int x) { emit_long(x); } | |
1085 inline void emit_data(int, RelocationHolder const&); | |
1086 inline void emit_data(int, relocInfo::relocType rtype); | |
1087 // helper for above fcns | |
1088 inline void check_delay(); | |
1089 | |
1090 | |
1091 public: | |
1092 // instructions, refer to page numbers in the SPARC Architecture Manual, V9 | |
1093 | |
1094 // pp 135 (addc was addx in v8) | |
1095 | |
1096 inline void add( Register s1, Register s2, Register d ); | |
1097 inline void add( Register s1, int simm13a, Register d, relocInfo::relocType rtype = relocInfo::none); | |
1098 inline void add( Register s1, int simm13a, Register d, RelocationHolder const& rspec); | |
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1099 inline void add( Register s1, RegisterOrConstant s2, Register d, int offset = 0); |
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1100 inline void add( const Address& a, Register d, int offset = 0); |
0 | 1101 |
1102 void addcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1103 void addcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1104 void addc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | rs2(s2) ); } | |
1105 void addc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1106 void addccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1107 void addccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1108 | |
1109 // pp 136 | |
1110 | |
1111 inline void bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none ); | |
1112 inline void bpr( RCondition c, bool a, Predict p, Register s1, Label& L); | |
1113 | |
1114 protected: // use MacroAssembler::br instead | |
1115 | |
1116 // pp 138 | |
1117 | |
1118 inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none ); | |
1119 inline void fb( Condition c, bool a, Label& L ); | |
1120 | |
1121 // pp 141 | |
1122 | |
1123 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); | |
1124 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L ); | |
1125 | |
1126 public: | |
1127 | |
1128 // pp 144 | |
1129 | |
1130 inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none ); | |
1131 inline void br( Condition c, bool a, Label& L ); | |
1132 | |
1133 // pp 146 | |
1134 | |
1135 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); | |
1136 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L ); | |
1137 | |
1138 // pp 121 (V8) | |
1139 | |
1140 inline void cb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none ); | |
1141 inline void cb( Condition c, bool a, Label& L ); | |
1142 | |
1143 // pp 149 | |
1144 | |
1145 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type ); | |
1146 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type ); | |
1147 | |
1148 // pp 150 | |
1149 | |
1150 // These instructions compare the contents of s2 with the contents of | |
1151 // memory at address in s1. If the values are equal, the contents of memory | |
1152 // at address s1 is swapped with the data in d. If the values are not equal, | |
1153 // the the contents of memory at s1 is loaded into d, without the swap. | |
1154 | |
1155 void casa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); } | |
1156 void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); } | |
1157 | |
1158 // pp 152 | |
1159 | |
1160 void udiv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | rs2(s2)); } | |
1161 void udiv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1162 void sdiv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | rs2(s2)); } | |
1163 void sdiv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1164 void udivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); } | |
1165 void udivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1166 void sdivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); } | |
1167 void sdivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1168 | |
1169 // pp 155 | |
1170 | |
1171 void done() { v9_only(); cti(); emit_long( op(arith_op) | fcn(0) | op3(done_op3) ); } | |
1172 void retry() { v9_only(); cti(); emit_long( op(arith_op) | fcn(1) | op3(retry_op3) ); } | |
1173 | |
1174 // pp 156 | |
1175 | |
1176 void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); } | |
1177 void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); } | |
1178 | |
1179 // pp 157 | |
1180 | |
1181 void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc); emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); } | |
1182 void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc); emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); } | |
1183 | |
1184 // pp 159 | |
1185 | |
1186 void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); } | |
1187 void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); } | |
1188 | |
1189 // pp 160 | |
1190 | |
1191 void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); } | |
1192 | |
1193 // pp 161 | |
1194 | |
1195 void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, w)); } | |
1196 void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, w)); } | |
1197 | |
1198 // pp 162 | |
1199 | |
1200 void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); } | |
1201 | |
1202 void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); } | |
1203 | |
1204 // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fnegs is the only instruction available | |
1205 // on v8 to do negation of single, double and quad precision floats. | |
1206 | |
1207 void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(sd, w)); else emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x05) | fs2(sd, w)); } | |
1208 | |
1209 void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); } | |
1210 | |
1211 // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fabss is the only instruction available | |
1212 // on v8 to do abs operation on single/double/quad precision floats. | |
1213 | |
1214 void fabs( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(sd, w)); else emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x09) | fs2(sd, w)); } | |
1215 | |
1216 // pp 163 | |
1217 | |
1218 void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); } | |
1219 void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); } | |
1220 void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); } | |
1221 | |
1222 // pp 164 | |
1223 | |
1224 void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); } | |
1225 | |
1226 // pp 165 | |
1227 | |
1228 inline void flush( Register s1, Register s2 ); | |
1229 inline void flush( Register s1, int simm13a); | |
1230 | |
1231 // pp 167 | |
1232 | |
1233 void flushw() { v9_only(); emit_long( op(arith_op) | op3(flushw_op3) ); } | |
1234 | |
1235 // pp 168 | |
1236 | |
1237 void illtrap( int const22a) { if (const22a != 0) v9_only(); emit_long( op(branch_op) | u_field(const22a, 21, 0) ); } | |
1238 // v8 unimp == illtrap(0) | |
1239 | |
1240 // pp 169 | |
1241 | |
1242 void impdep1( int id1, int const19a ) { v9_only(); emit_long( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); } | |
1243 void impdep2( int id1, int const19a ) { v9_only(); emit_long( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); } | |
1244 | |
1245 // pp 149 (v8) | |
1246 | |
1247 void cpop1( int opc, int cr1, int cr2, int crd ) { v8_only(); emit_long( op(arith_op) | fcn(crd) | op3(impdep1_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); } | |
1248 void cpop2( int opc, int cr1, int cr2, int crd ) { v8_only(); emit_long( op(arith_op) | fcn(crd) | op3(impdep2_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); } | |
1249 | |
1250 // pp 170 | |
1251 | |
1252 void jmpl( Register s1, Register s2, Register d ); | |
1253 void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() ); | |
1254 | |
1255 inline void jmpl( Address& a, Register d, int offset = 0); | |
1256 | |
1257 // 171 | |
1258 | |
1259 inline void ldf( FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d ); | |
1260 inline void ldf( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d ); | |
1261 | |
1262 inline void ldf( FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset = 0); | |
1263 | |
1264 | |
1265 inline void ldfsr( Register s1, Register s2 ); | |
1266 inline void ldfsr( Register s1, int simm13a); | |
1267 inline void ldxfsr( Register s1, Register s2 ); | |
1268 inline void ldxfsr( Register s1, int simm13a); | |
1269 | |
1270 // pp 94 (v8) | |
1271 | |
1272 inline void ldc( Register s1, Register s2, int crd ); | |
1273 inline void ldc( Register s1, int simm13a, int crd); | |
1274 inline void lddc( Register s1, Register s2, int crd ); | |
1275 inline void lddc( Register s1, int simm13a, int crd); | |
1276 inline void ldcsr( Register s1, Register s2, int crd ); | |
1277 inline void ldcsr( Register s1, int simm13a, int crd); | |
1278 | |
1279 | |
1280 // 173 | |
1281 | |
1282 void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1283 void ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1284 | |
1285 // pp 175, lduw is ld on v8 | |
1286 | |
1287 inline void ldsb( Register s1, Register s2, Register d ); | |
1288 inline void ldsb( Register s1, int simm13a, Register d); | |
1289 inline void ldsh( Register s1, Register s2, Register d ); | |
1290 inline void ldsh( Register s1, int simm13a, Register d); | |
1291 inline void ldsw( Register s1, Register s2, Register d ); | |
1292 inline void ldsw( Register s1, int simm13a, Register d); | |
1293 inline void ldub( Register s1, Register s2, Register d ); | |
1294 inline void ldub( Register s1, int simm13a, Register d); | |
1295 inline void lduh( Register s1, Register s2, Register d ); | |
1296 inline void lduh( Register s1, int simm13a, Register d); | |
1297 inline void lduw( Register s1, Register s2, Register d ); | |
1298 inline void lduw( Register s1, int simm13a, Register d); | |
1299 inline void ldx( Register s1, Register s2, Register d ); | |
1300 inline void ldx( Register s1, int simm13a, Register d); | |
1301 inline void ld( Register s1, Register s2, Register d ); | |
1302 inline void ld( Register s1, int simm13a, Register d); | |
1303 inline void ldd( Register s1, Register s2, Register d ); | |
1304 inline void ldd( Register s1, int simm13a, Register d); | |
1305 | |
1306 inline void ldsb( const Address& a, Register d, int offset = 0 ); | |
1307 inline void ldsh( const Address& a, Register d, int offset = 0 ); | |
1308 inline void ldsw( const Address& a, Register d, int offset = 0 ); | |
1309 inline void ldub( const Address& a, Register d, int offset = 0 ); | |
1310 inline void lduh( const Address& a, Register d, int offset = 0 ); | |
1311 inline void lduw( const Address& a, Register d, int offset = 0 ); | |
1312 inline void ldx( const Address& a, Register d, int offset = 0 ); | |
1313 inline void ld( const Address& a, Register d, int offset = 0 ); | |
1314 inline void ldd( const Address& a, Register d, int offset = 0 ); | |
1315 | |
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1316 inline void ldub( Register s1, RegisterOrConstant s2, Register d ); |
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1317 inline void ldsb( Register s1, RegisterOrConstant s2, Register d ); |
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1318 inline void lduh( Register s1, RegisterOrConstant s2, Register d ); |
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1319 inline void ldsh( Register s1, RegisterOrConstant s2, Register d ); |
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1320 inline void lduw( Register s1, RegisterOrConstant s2, Register d ); |
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1321 inline void ldsw( Register s1, RegisterOrConstant s2, Register d ); |
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1322 inline void ldx( Register s1, RegisterOrConstant s2, Register d ); |
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1323 inline void ld( Register s1, RegisterOrConstant s2, Register d ); |
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1324 inline void ldd( Register s1, RegisterOrConstant s2, Register d ); |
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1325 |
0 | 1326 // pp 177 |
1327 | |
1328 void ldsba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1329 void ldsba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1330 void ldsha( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1331 void ldsha( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1332 void ldswa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1333 void ldswa( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1334 void lduba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1335 void lduba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1336 void lduha( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1337 void lduha( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1338 void lduwa( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1339 void lduwa( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1340 void ldxa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1341 void ldxa( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1342 void ldda( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1343 void ldda( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1344 | |
1345 // pp 179 | |
1346 | |
1347 inline void ldstub( Register s1, Register s2, Register d ); | |
1348 inline void ldstub( Register s1, int simm13a, Register d); | |
1349 | |
1350 // pp 180 | |
1351 | |
1352 void ldstuba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1353 void ldstuba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1354 | |
1355 // pp 181 | |
1356 | |
1357 void and3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); } | |
1358 void and3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1359 void andcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1360 void andcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1361 void andn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); } | |
1362 void andn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1363 void andncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1364 void andncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1365 void or3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); } | |
1366 void or3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1367 void orcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1368 void orcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1369 void orn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); } | |
1370 void orn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1371 void orncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1372 void orncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1373 void xor3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); } | |
1374 void xor3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1375 void xorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1376 void xorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1377 void xnor( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); } | |
1378 void xnor( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1379 void xnorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1380 void xnorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1381 | |
1382 // pp 183 | |
1383 | |
1384 void membar( Membar_mask_bits const7a ) { v9_only(); emit_long( op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field( int(const7a), 6, 0)); } | |
1385 | |
1386 // pp 185 | |
1387 | |
1388 void fmov( FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); } | |
1389 | |
1390 // pp 189 | |
1391 | |
1392 void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); } | |
1393 | |
1394 // pp 191 | |
1395 | |
1396 void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2) ); } | |
1397 void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11) ); } | |
1398 | |
1399 // pp 195 | |
1400 | |
1401 void movr( RCondition c, Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); } | |
1402 void movr( RCondition c, Register s1, int simm10a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); } | |
1403 | |
1404 // pp 196 | |
1405 | |
1406 void mulx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); } | |
1407 void mulx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1408 void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); } | |
1409 void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1410 void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); } | |
1411 void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1412 | |
1413 // pp 197 | |
1414 | |
1415 void umul( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | rs2(s2) ); } | |
1416 void umul( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1417 void smul( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | rs2(s2) ); } | |
1418 void smul( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1419 void umulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1420 void umulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1421 void smulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1422 void smulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1423 | |
1424 // pp 199 | |
1425 | |
1426 void mulscc( Register s1, Register s2, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | rs2(s2) ); } | |
1427 void mulscc( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1428 | |
1429 // pp 201 | |
1430 | |
1431 void nop() { emit_long( op(branch_op) | op2(sethi_op2) ); } | |
1432 | |
1433 | |
1434 // pp 202 | |
1435 | |
1436 void popc( Register s, Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); } | |
1437 void popc( int simm13a, Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); } | |
1438 | |
1439 // pp 203 | |
1440 | |
1441 void prefetch( Register s1, Register s2, PrefetchFcn f); | |
1442 void prefetch( Register s1, int simm13a, PrefetchFcn f); | |
1443 void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1444 void prefetcha( Register s1, int simm13a, PrefetchFcn f ) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1445 | |
1446 inline void prefetch(const Address& a, PrefetchFcn F, int offset = 0); | |
1447 | |
1448 // pp 208 | |
1449 | |
1450 // not implementing read privileged register | |
1451 | |
1452 inline void rdy( Register d) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); } | |
1453 inline void rdccr( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); } | |
1454 inline void rdasi( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); } | |
1455 inline void rdtick( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); } // Spoon! | |
1456 inline void rdpc( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); } | |
1457 inline void rdfprs( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); } | |
1458 | |
1459 // pp 213 | |
1460 | |
1461 inline void rett( Register s1, Register s2); | |
1462 inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none); | |
1463 | |
1464 // pp 214 | |
1465 | |
1466 void save( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2) ); } | |
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1467 void save( Register s1, int simm13a, Register d ) { |
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1468 // make sure frame is at least large enough for the register save area |
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1469 assert(-simm13a >= 16 * wordSize, "frame too small"); |
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1470 emit_long( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); |
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1471 } |
0 | 1472 |
1473 void restore( Register s1 = G0, Register s2 = G0, Register d = G0 ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2) ); } | |
1474 void restore( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1475 | |
1476 // pp 216 | |
1477 | |
1478 void saved() { v9_only(); emit_long( op(arith_op) | fcn(0) | op3(saved_op3)); } | |
1479 void restored() { v9_only(); emit_long( op(arith_op) | fcn(1) | op3(saved_op3)); } | |
1480 | |
1481 // pp 217 | |
1482 | |
1483 inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() ); | |
1484 // pp 218 | |
1485 | |
1486 void sll( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2) ); } | |
1487 void sll( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); } | |
1488 void srl( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2) ); } | |
1489 void srl( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); } | |
1490 void sra( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2) ); } | |
1491 void sra( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); } | |
1492 | |
1493 void sllx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2) ); } | |
1494 void sllx( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); } | |
1495 void srlx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2) ); } | |
1496 void srlx( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); } | |
1497 void srax( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2) ); } | |
1498 void srax( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); } | |
1499 | |
1500 // pp 220 | |
1501 | |
1502 void sir( int simm13a ) { emit_long( op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); } | |
1503 | |
1504 // pp 221 | |
1505 | |
1506 void stbar() { emit_long( op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); } | |
1507 | |
1508 // pp 222 | |
1509 | |
1510 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2 ); | |
1511 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a); | |
1512 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset = 0); | |
1513 | |
1514 inline void stfsr( Register s1, Register s2 ); | |
1515 inline void stfsr( Register s1, int simm13a); | |
1516 inline void stxfsr( Register s1, Register s2 ); | |
1517 inline void stxfsr( Register s1, int simm13a); | |
1518 | |
1519 // pp 224 | |
1520 | |
1521 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1522 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1523 | |
1524 // p 226 | |
1525 | |
1526 inline void stb( Register d, Register s1, Register s2 ); | |
1527 inline void stb( Register d, Register s1, int simm13a); | |
1528 inline void sth( Register d, Register s1, Register s2 ); | |
1529 inline void sth( Register d, Register s1, int simm13a); | |
1530 inline void stw( Register d, Register s1, Register s2 ); | |
1531 inline void stw( Register d, Register s1, int simm13a); | |
1532 inline void st( Register d, Register s1, Register s2 ); | |
1533 inline void st( Register d, Register s1, int simm13a); | |
1534 inline void stx( Register d, Register s1, Register s2 ); | |
1535 inline void stx( Register d, Register s1, int simm13a); | |
1536 inline void std( Register d, Register s1, Register s2 ); | |
1537 inline void std( Register d, Register s1, int simm13a); | |
1538 | |
1539 inline void stb( Register d, const Address& a, int offset = 0 ); | |
1540 inline void sth( Register d, const Address& a, int offset = 0 ); | |
1541 inline void stw( Register d, const Address& a, int offset = 0 ); | |
1542 inline void stx( Register d, const Address& a, int offset = 0 ); | |
1543 inline void st( Register d, const Address& a, int offset = 0 ); | |
1544 inline void std( Register d, const Address& a, int offset = 0 ); | |
1545 | |
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1546 inline void stb( Register d, Register s1, RegisterOrConstant s2 ); |
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1547 inline void sth( Register d, Register s1, RegisterOrConstant s2 ); |
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1548 inline void stw( Register d, Register s1, RegisterOrConstant s2 ); |
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1549 inline void stx( Register d, Register s1, RegisterOrConstant s2 ); |
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1550 inline void std( Register d, Register s1, RegisterOrConstant s2 ); |
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1551 inline void st( Register d, Register s1, RegisterOrConstant s2 ); |
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1552 |
0 | 1553 // pp 177 |
1554 | |
1555 void stba( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1556 void stba( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1557 void stha( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1558 void stha( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1559 void stwa( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1560 void stwa( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1561 void stxa( Register d, Register s1, Register s2, int ia ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1562 void stxa( Register d, Register s1, int simm13a ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1563 void stda( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1564 void stda( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1565 | |
1566 // pp 97 (v8) | |
1567 | |
1568 inline void stc( int crd, Register s1, Register s2 ); | |
1569 inline void stc( int crd, Register s1, int simm13a); | |
1570 inline void stdc( int crd, Register s1, Register s2 ); | |
1571 inline void stdc( int crd, Register s1, int simm13a); | |
1572 inline void stcsr( int crd, Register s1, Register s2 ); | |
1573 inline void stcsr( int crd, Register s1, int simm13a); | |
1574 inline void stdcq( int crd, Register s1, Register s2 ); | |
1575 inline void stdcq( int crd, Register s1, int simm13a); | |
1576 | |
1577 // pp 230 | |
1578 | |
1579 void sub( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | rs2(s2) ); } | |
1580 void sub( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1581 void subcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); } | |
1582 void subcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1583 void subc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | rs2(s2) ); } | |
1584 void subc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1585 void subccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1586 void subccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1587 | |
1588 // pp 231 | |
1589 | |
1590 inline void swap( Register s1, Register s2, Register d ); | |
1591 inline void swap( Register s1, int simm13a, Register d); | |
1592 inline void swap( Address& a, Register d, int offset = 0 ); | |
1593 | |
1594 // pp 232 | |
1595 | |
1596 void swapa( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1597 void swapa( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1598 | |
1599 // pp 234, note op in book is wrong, see pp 268 | |
1600 | |
1601 void taddcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | rs2(s2) ); } | |
1602 void taddcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1603 void taddcctv( Register s1, Register s2, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | rs2(s2) ); } | |
1604 void taddcctv( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1605 | |
1606 // pp 235 | |
1607 | |
1608 void tsubcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | rs2(s2) ); } | |
1609 void tsubcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1610 void tsubcctv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | rs2(s2) ); } | |
1611 void tsubcctv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1612 | |
1613 // pp 237 | |
1614 | |
1615 void trap( Condition c, CC cc, Register s1, Register s2 ) { v8_no_cc(cc); emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); } | |
1616 void trap( Condition c, CC cc, Register s1, int trapa ) { v8_no_cc(cc); emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); } | |
1617 // simple uncond. trap | |
1618 void trap( int trapa ) { trap( always, icc, G0, trapa ); } | |
1619 | |
1620 // pp 239 omit write priv register for now | |
1621 | |
1622 inline void wry( Register d) { v9_dep(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); } | |
1623 inline void wrccr(Register s) { v9_only(); emit_long( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); } | |
1624 inline void wrccr(Register s, int simm13a) { v9_only(); emit_long( op(arith_op) | | |
1625 rs1(s) | | |
1626 op3(wrreg_op3) | | |
1627 u_field(2, 29, 25) | | |
1628 u_field(1, 13, 13) | | |
1629 simm(simm13a, 13)); } | |
1630 inline void wrasi( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); } | |
1631 inline void wrfprs( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); } | |
1632 | |
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1633 // For a given register condition, return the appropriate condition code |
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1634 // Condition (the one you would use to get the same effect after "tst" on |
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1635 // the target register.) |
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1636 Assembler::Condition reg_cond_to_cc_cond(RCondition in); |
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1637 |
0 | 1638 |
1639 // Creation | |
1640 Assembler(CodeBuffer* code) : AbstractAssembler(code) { | |
1641 #ifdef CHECK_DELAY | |
1642 delay_state = no_delay; | |
1643 #endif | |
1644 } | |
1645 | |
1646 // Testing | |
1647 #ifndef PRODUCT | |
1648 void test_v9(); | |
1649 void test_v8_onlys(); | |
1650 #endif | |
1651 }; | |
1652 | |
1653 | |
1654 class RegistersForDebugging : public StackObj { | |
1655 public: | |
1656 intptr_t i[8], l[8], o[8], g[8]; | |
1657 float f[32]; | |
1658 double d[32]; | |
1659 | |
1660 void print(outputStream* s); | |
1661 | |
1662 static int i_offset(int j) { return offset_of(RegistersForDebugging, i[j]); } | |
1663 static int l_offset(int j) { return offset_of(RegistersForDebugging, l[j]); } | |
1664 static int o_offset(int j) { return offset_of(RegistersForDebugging, o[j]); } | |
1665 static int g_offset(int j) { return offset_of(RegistersForDebugging, g[j]); } | |
1666 static int f_offset(int j) { return offset_of(RegistersForDebugging, f[j]); } | |
1667 static int d_offset(int j) { return offset_of(RegistersForDebugging, d[j / 2]); } | |
1668 | |
1669 // gen asm code to save regs | |
1670 static void save_registers(MacroAssembler* a); | |
1671 | |
1672 // restore global registers in case C code disturbed them | |
1673 static void restore_registers(MacroAssembler* a, Register r); | |
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1674 |
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1675 |
0 | 1676 }; |
1677 | |
1678 | |
1679 // MacroAssembler extends Assembler by a few frequently used macros. | |
1680 // | |
1681 // Most of the standard SPARC synthetic ops are defined here. | |
1682 // Instructions for which a 'better' code sequence exists depending | |
1683 // on arguments should also go in here. | |
1684 | |
1685 #define JMP2(r1, r2) jmp(r1, r2, __FILE__, __LINE__) | |
1686 #define JMP(r1, off) jmp(r1, off, __FILE__, __LINE__) | |
1687 #define JUMP(a, off) jump(a, off, __FILE__, __LINE__) | |
1688 #define JUMPL(a, d, off) jumpl(a, d, off, __FILE__, __LINE__) | |
1689 | |
1690 | |
1691 class MacroAssembler: public Assembler { | |
1692 protected: | |
1693 // Support for VM calls | |
1694 // This is the base routine called by the different versions of call_VM_leaf. The interpreter | |
1695 // may customize this version by overriding it for its purposes (e.g., to save/restore | |
1696 // additional registers when doing a VM call). | |
1697 #ifdef CC_INTERP | |
1698 #define VIRTUAL | |
1699 #else | |
1700 #define VIRTUAL virtual | |
1701 #endif | |
1702 | |
1703 VIRTUAL void call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments); | |
1704 | |
1705 // | |
1706 // It is imperative that all calls into the VM are handled via the call_VM macros. | |
1707 // They make sure that the stack linkage is setup correctly. call_VM's correspond | |
1708 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. | |
1709 // | |
1710 // This is the base routine called by the different versions of call_VM. The interpreter | |
1711 // may customize this version by overriding it for its purposes (e.g., to save/restore | |
1712 // additional registers when doing a VM call). | |
1713 // | |
1714 // A non-volatile java_thread_cache register should be specified so | |
1715 // that the G2_thread value can be preserved across the call. | |
1716 // (If java_thread_cache is noreg, then a slow get_thread call | |
1717 // will re-initialize the G2_thread.) call_VM_base returns the register that contains the | |
1718 // thread. | |
1719 // | |
1720 // If no last_java_sp is specified (noreg) than SP will be used instead. | |
1721 | |
1722 virtual void call_VM_base( | |
1723 Register oop_result, // where an oop-result ends up if any; use noreg otherwise | |
1724 Register java_thread_cache, // the thread if computed before ; use noreg otherwise | |
1725 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise | |
1726 address entry_point, // the entry point | |
1727 int number_of_arguments, // the number of arguments (w/o thread) to pop after call | |
1728 bool check_exception=true // flag which indicates if exception should be checked | |
1729 ); | |
1730 | |
1731 // This routine should emit JVMTI PopFrame and ForceEarlyReturn handling code. | |
1732 // The implementation is only non-empty for the InterpreterMacroAssembler, | |
1733 // as only the interpreter handles and ForceEarlyReturn PopFrame requests. | |
1734 virtual void check_and_handle_popframe(Register scratch_reg); | |
1735 virtual void check_and_handle_earlyret(Register scratch_reg); | |
1736 | |
1737 public: | |
1738 MacroAssembler(CodeBuffer* code) : Assembler(code) {} | |
1739 | |
1740 // Support for NULL-checks | |
1741 // | |
1742 // Generates code that causes a NULL OS exception if the content of reg is NULL. | |
1743 // If the accessed location is M[reg + offset] and the offset is known, provide the | |
1744 // offset. No explicit code generation is needed if the offset is within a certain | |
1745 // range (0 <= offset <= page_size). | |
1746 // | |
1747 // %%%%%% Currently not done for SPARC | |
1748 | |
1749 void null_check(Register reg, int offset = -1); | |
1750 static bool needs_explicit_null_check(intptr_t offset); | |
1751 | |
1752 // support for delayed instructions | |
1753 MacroAssembler* delayed() { Assembler::delayed(); return this; } | |
1754 | |
1755 // branches that use right instruction for v8 vs. v9 | |
1756 inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); | |
1757 inline void br( Condition c, bool a, Predict p, Label& L ); | |
1758 inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); | |
1759 inline void fb( Condition c, bool a, Predict p, Label& L ); | |
1760 | |
1761 // compares register with zero and branches (V9 and V8 instructions) | |
1762 void br_zero( Condition c, bool a, Predict p, Register s1, Label& L); | |
1763 // Compares a pointer register with zero and branches on (not)null. | |
1764 // Does a test & branch on 32-bit systems and a register-branch on 64-bit. | |
1765 void br_null ( Register s1, bool a, Predict p, Label& L ); | |
1766 void br_notnull( Register s1, bool a, Predict p, Label& L ); | |
1767 | |
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1768 // These versions will do the most efficient thing on v8 and v9. Perhaps |
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1769 // this is what the routine above was meant to do, but it didn't (and |
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1770 // didn't cover both target address kinds.) |
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1771 void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none ); |
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1772 void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, Label& L); |
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1773 |
0 | 1774 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); |
1775 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L ); | |
1776 | |
1777 // Branch that tests xcc in LP64 and icc in !LP64 | |
1778 inline void brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); | |
1779 inline void brx( Condition c, bool a, Predict p, Label& L ); | |
1780 | |
1781 // unconditional short branch | |
1782 inline void ba( bool a, Label& L ); | |
1783 | |
1784 // Branch that tests fp condition codes | |
1785 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); | |
1786 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L ); | |
1787 | |
1788 // get PC the best way | |
1789 inline int get_pc( Register d ); | |
1790 | |
1791 // Sparc shorthands(pp 85, V8 manual, pp 289 V9 manual) | |
1792 inline void cmp( Register s1, Register s2 ) { subcc( s1, s2, G0 ); } | |
1793 inline void cmp( Register s1, int simm13a ) { subcc( s1, simm13a, G0 ); } | |
1794 | |
1795 inline void jmp( Register s1, Register s2 ); | |
1796 inline void jmp( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() ); | |
1797 | |
1798 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type ); | |
1799 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type ); | |
1800 inline void callr( Register s1, Register s2 ); | |
1801 inline void callr( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() ); | |
1802 | |
1803 // Emits nothing on V8 | |
1804 inline void iprefetch( address d, relocInfo::relocType rt = relocInfo::none ); | |
1805 inline void iprefetch( Label& L); | |
1806 | |
1807 inline void tst( Register s ) { orcc( G0, s, G0 ); } | |
1808 | |
1809 #ifdef PRODUCT | |
1810 inline void ret( bool trace = TraceJumps ) { if (trace) { | |
1811 mov(I7, O7); // traceable register | |
1812 JMP(O7, 2 * BytesPerInstWord); | |
1813 } else { | |
1814 jmpl( I7, 2 * BytesPerInstWord, G0 ); | |
1815 } | |
1816 } | |
1817 | |
1818 inline void retl( bool trace = TraceJumps ) { if (trace) JMP(O7, 2 * BytesPerInstWord); | |
1819 else jmpl( O7, 2 * BytesPerInstWord, G0 ); } | |
1820 #else | |
1821 void ret( bool trace = TraceJumps ); | |
1822 void retl( bool trace = TraceJumps ); | |
1823 #endif /* PRODUCT */ | |
1824 | |
1825 // Required platform-specific helpers for Label::patch_instructions. | |
1826 // They _shadow_ the declarations in AbstractAssembler, which are undefined. | |
1827 void pd_patch_instruction(address branch, address target); | |
1828 #ifndef PRODUCT | |
1829 static void pd_print_patched_instruction(address branch); | |
1830 #endif | |
1831 | |
1832 // sethi Macro handles optimizations and relocations | |
1833 void sethi( Address& a, bool ForceRelocatable = false ); | |
1834 void sethi( intptr_t imm22a, Register d, bool ForceRelocatable = false, RelocationHolder const& rspec = RelocationHolder()); | |
1835 | |
1836 // compute the size of a sethi/set | |
1837 static int size_of_sethi( address a, bool worst_case = false ); | |
1838 static int worst_case_size_of_set(); | |
1839 | |
1840 // set may be either setsw or setuw (high 32 bits may be zero or sign) | |
1841 void set( intptr_t value, Register d, RelocationHolder const& rspec = RelocationHolder() ); | |
1842 void setsw( int value, Register d, RelocationHolder const& rspec = RelocationHolder() ); | |
1843 void set64( jlong value, Register d, Register tmp); | |
1844 | |
1845 // sign-extend 32 to 64 | |
1846 inline void signx( Register s, Register d ) { sra( s, G0, d); } | |
1847 inline void signx( Register d ) { sra( d, G0, d); } | |
1848 | |
1849 inline void not1( Register s, Register d ) { xnor( s, G0, d ); } | |
1850 inline void not1( Register d ) { xnor( d, G0, d ); } | |
1851 | |
1852 inline void neg( Register s, Register d ) { sub( G0, s, d ); } | |
1853 inline void neg( Register d ) { sub( G0, d, d ); } | |
1854 | |
1855 inline void cas( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY); } | |
1856 inline void casx( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY); } | |
1857 // Functions for isolating 64 bit atomic swaps for LP64 | |
1858 // cas_ptr will perform cas for 32 bit VM's and casx for 64 bit VM's | |
1859 inline void cas_ptr( Register s1, Register s2, Register d) { | |
1860 #ifdef _LP64 | |
1861 casx( s1, s2, d ); | |
1862 #else | |
1863 cas( s1, s2, d ); | |
1864 #endif | |
1865 } | |
1866 | |
1867 // Functions for isolating 64 bit shifts for LP64 | |
1868 inline void sll_ptr( Register s1, Register s2, Register d ); | |
1869 inline void sll_ptr( Register s1, int imm6a, Register d ); | |
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1870 inline void sll_ptr( Register s1, RegisterOrConstant s2, Register d ); |
0 | 1871 inline void srl_ptr( Register s1, Register s2, Register d ); |
1872 inline void srl_ptr( Register s1, int imm6a, Register d ); | |
1873 | |
1874 // little-endian | |
1875 inline void casl( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY_LITTLE); } | |
1876 inline void casxl( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY_LITTLE); } | |
1877 | |
1878 inline void inc( Register d, int const13 = 1 ) { add( d, const13, d); } | |
1879 inline void inccc( Register d, int const13 = 1 ) { addcc( d, const13, d); } | |
1880 | |
1881 inline void dec( Register d, int const13 = 1 ) { sub( d, const13, d); } | |
1882 inline void deccc( Register d, int const13 = 1 ) { subcc( d, const13, d); } | |
1883 | |
1884 inline void btst( Register s1, Register s2 ) { andcc( s1, s2, G0 ); } | |
1885 inline void btst( int simm13a, Register s ) { andcc( s, simm13a, G0 ); } | |
1886 | |
1887 inline void bset( Register s1, Register s2 ) { or3( s1, s2, s2 ); } | |
1888 inline void bset( int simm13a, Register s ) { or3( s, simm13a, s ); } | |
1889 | |
1890 inline void bclr( Register s1, Register s2 ) { andn( s1, s2, s2 ); } | |
1891 inline void bclr( int simm13a, Register s ) { andn( s, simm13a, s ); } | |
1892 | |
1893 inline void btog( Register s1, Register s2 ) { xor3( s1, s2, s2 ); } | |
1894 inline void btog( int simm13a, Register s ) { xor3( s, simm13a, s ); } | |
1895 | |
1896 inline void clr( Register d ) { or3( G0, G0, d ); } | |
1897 | |
1898 inline void clrb( Register s1, Register s2); | |
1899 inline void clrh( Register s1, Register s2); | |
1900 inline void clr( Register s1, Register s2); | |
1901 inline void clrx( Register s1, Register s2); | |
1902 | |
1903 inline void clrb( Register s1, int simm13a); | |
1904 inline void clrh( Register s1, int simm13a); | |
1905 inline void clr( Register s1, int simm13a); | |
1906 inline void clrx( Register s1, int simm13a); | |
1907 | |
1908 // copy & clear upper word | |
1909 inline void clruw( Register s, Register d ) { srl( s, G0, d); } | |
1910 // clear upper word | |
1911 inline void clruwu( Register d ) { srl( d, G0, d); } | |
1912 | |
1913 // membar psuedo instruction. takes into account target memory model. | |
1914 inline void membar( Assembler::Membar_mask_bits const7a ); | |
1915 | |
1916 // returns if membar generates anything. | |
1917 inline bool membar_has_effect( Assembler::Membar_mask_bits const7a ); | |
1918 | |
1919 // mov pseudo instructions | |
1920 inline void mov( Register s, Register d) { | |
1921 if ( s != d ) or3( G0, s, d); | |
1922 else assert_not_delayed(); // Put something useful in the delay slot! | |
1923 } | |
1924 | |
1925 inline void mov_or_nop( Register s, Register d) { | |
1926 if ( s != d ) or3( G0, s, d); | |
1927 else nop(); | |
1928 } | |
1929 | |
1930 inline void mov( int simm13a, Register d) { or3( G0, simm13a, d); } | |
1931 | |
1932 // address pseudos: make these names unlike instruction names to avoid confusion | |
1933 inline void split_disp( Address& a, Register temp ); | |
1934 inline intptr_t load_pc_address( Register reg, int bytes_to_skip ); | |
1935 inline void load_address( Address& a, int offset = 0 ); | |
1936 inline void load_contents( Address& a, Register d, int offset = 0 ); | |
1937 inline void load_ptr_contents( Address& a, Register d, int offset = 0 ); | |
1938 inline void store_contents( Register s, Address& a, int offset = 0 ); | |
1939 inline void store_ptr_contents( Register s, Address& a, int offset = 0 ); | |
1940 inline void jumpl_to( Address& a, Register d, int offset = 0 ); | |
1941 inline void jump_to( Address& a, int offset = 0 ); | |
710 | 1942 inline void jump_indirect_to( Address& a, Register temp, int ld_offset = 0, int jmp_offset = 0 ); |
0 | 1943 |
1944 // ring buffer traceable jumps | |
1945 | |
1946 void jmp2( Register r1, Register r2, const char* file, int line ); | |
1947 void jmp ( Register r1, int offset, const char* file, int line ); | |
1948 | |
1949 void jumpl( Address& a, Register d, int offset, const char* file, int line ); | |
1950 void jump ( Address& a, int offset, const char* file, int line ); | |
1951 | |
1952 | |
1953 // argument pseudos: | |
1954 | |
1955 inline void load_argument( Argument& a, Register d ); | |
1956 inline void store_argument( Register s, Argument& a ); | |
1957 inline void store_ptr_argument( Register s, Argument& a ); | |
1958 inline void store_float_argument( FloatRegister s, Argument& a ); | |
1959 inline void store_double_argument( FloatRegister s, Argument& a ); | |
1960 inline void store_long_argument( Register s, Argument& a ); | |
1961 | |
1962 // handy macros: | |
1963 | |
1964 inline void round_to( Register r, int modulus ) { | |
1965 assert_not_delayed(); | |
1966 inc( r, modulus - 1 ); | |
1967 and3( r, -modulus, r ); | |
1968 } | |
1969 | |
1970 // -------------------------------------------------- | |
1971 | |
1972 // Functions for isolating 64 bit loads for LP64 | |
1973 // ld_ptr will perform ld for 32 bit VM's and ldx for 64 bit VM's | |
1974 // st_ptr will perform st for 32 bit VM's and stx for 64 bit VM's | |
1975 inline void ld_ptr( Register s1, Register s2, Register d ); | |
1976 inline void ld_ptr( Register s1, int simm13a, Register d); | |
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1977 inline void ld_ptr( Register s1, RegisterOrConstant s2, Register d ); |
0 | 1978 inline void ld_ptr( const Address& a, Register d, int offset = 0 ); |
1979 inline void st_ptr( Register d, Register s1, Register s2 ); | |
1980 inline void st_ptr( Register d, Register s1, int simm13a); | |
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1981 inline void st_ptr( Register d, Register s1, RegisterOrConstant s2 ); |
0 | 1982 inline void st_ptr( Register d, const Address& a, int offset = 0 ); |
1983 | |
1984 // ld_long will perform ld for 32 bit VM's and ldx for 64 bit VM's | |
1985 // st_long will perform st for 32 bit VM's and stx for 64 bit VM's | |
1986 inline void ld_long( Register s1, Register s2, Register d ); | |
1987 inline void ld_long( Register s1, int simm13a, Register d ); | |
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1988 inline void ld_long( Register s1, RegisterOrConstant s2, Register d ); |
0 | 1989 inline void ld_long( const Address& a, Register d, int offset = 0 ); |
1990 inline void st_long( Register d, Register s1, Register s2 ); | |
1991 inline void st_long( Register d, Register s1, int simm13a ); | |
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1992 inline void st_long( Register d, Register s1, RegisterOrConstant s2 ); |
0 | 1993 inline void st_long( Register d, const Address& a, int offset = 0 ); |
1994 | |
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1995 // Loading values by size and signed-ness |
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1996 void load_sized_value(Register s1, RegisterOrConstant s2, Register d, |
622
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1997 int size_in_bytes, bool is_signed); |
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1998 |
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1999 // Helpers for address formation. |
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2000 // They update the dest in place, whether it is a register or constant. |
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2001 // They emit no code at all if src is a constant zero. |
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2002 // If dest is a constant and src is a register, the temp argument |
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2003 // is required, and becomes the result. |
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2004 // If dest is a register and src is a non-simm13 constant, |
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2005 // the temp argument is required, and is used to materialize the constant. |
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2006 void regcon_inc_ptr( RegisterOrConstant& dest, RegisterOrConstant src, |
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2007 Register temp = noreg ); |
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2008 void regcon_sll_ptr( RegisterOrConstant& dest, RegisterOrConstant src, |
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2009 Register temp = noreg ); |
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2010 RegisterOrConstant ensure_rs2(RegisterOrConstant rs2, Register sethi_temp) { |
623
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2011 guarantee(sethi_temp != noreg, "constant offset overflow"); |
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2012 if (is_simm13(rs2.constant_or_zero())) |
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2013 return rs2; // register or short constant |
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2014 set(rs2.as_constant(), sethi_temp); |
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2015 return sethi_temp; |
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2016 } |
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2017 |
0 | 2018 // -------------------------------------------------- |
2019 | |
2020 public: | |
2021 // traps as per trap.h (SPARC ABI?) | |
2022 | |
2023 void breakpoint_trap(); | |
2024 void breakpoint_trap(Condition c, CC cc = icc); | |
2025 void flush_windows_trap(); | |
2026 void clean_windows_trap(); | |
2027 void get_psr_trap(); | |
2028 void set_psr_trap(); | |
2029 | |
2030 // V8/V9 flush_windows | |
2031 void flush_windows(); | |
2032 | |
2033 // Support for serializing memory accesses between threads | |
2034 void serialize_memory(Register thread, Register tmp1, Register tmp2); | |
2035 | |
2036 // Stack frame creation/removal | |
2037 void enter(); | |
2038 void leave(); | |
2039 | |
2040 // V8/V9 integer multiply | |
2041 void mult(Register s1, Register s2, Register d); | |
2042 void mult(Register s1, int simm13a, Register d); | |
2043 | |
2044 // V8/V9 read and write of condition codes. | |
2045 void read_ccr(Register d); | |
2046 void write_ccr(Register s); | |
2047 | |
2048 // Manipulation of C++ bools | |
2049 // These are idioms to flag the need for care with accessing bools but on | |
2050 // this platform we assume byte size | |
2051 | |
2052 inline void stbool( Register d, const Address& a, int offset = 0 ) { stb(d, a, offset); } | |
2053 inline void ldbool( const Address& a, Register d, int offset = 0 ) { ldsb( a, d, offset ); } | |
2054 inline void tstbool( Register s ) { tst(s); } | |
2055 inline void movbool( bool boolconst, Register d) { mov( (int) boolconst, d); } | |
2056 | |
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2057 // klass oop manipulations if compressed |
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2058 void load_klass(Register src_oop, Register klass); |
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2059 void store_klass(Register klass, Register dst_oop); |
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2060 void store_klass_gap(Register s, Register dst_oop); |
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2061 |
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2062 // oop manipulations |
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2063 void load_heap_oop(const Address& s, Register d, int offset = 0); |
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2064 void load_heap_oop(Register s1, Register s2, Register d); |
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2065 void load_heap_oop(Register s1, int simm13a, Register d); |
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2066 void store_heap_oop(Register d, Register s1, Register s2); |
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2067 void store_heap_oop(Register d, Register s1, int simm13a); |
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2068 void store_heap_oop(Register d, const Address& a, int offset = 0); |
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2069 |
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2070 void encode_heap_oop(Register src, Register dst); |
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2071 void encode_heap_oop(Register r) { |
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2072 encode_heap_oop(r, r); |
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2073 } |
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2074 void decode_heap_oop(Register src, Register dst); |
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2075 void decode_heap_oop(Register r) { |
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2076 decode_heap_oop(r, r); |
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2077 } |
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2078 void encode_heap_oop_not_null(Register r); |
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2079 void decode_heap_oop_not_null(Register r); |
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2080 void encode_heap_oop_not_null(Register src, Register dst); |
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2081 void decode_heap_oop_not_null(Register src, Register dst); |
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2082 |
0 | 2083 // Support for managing the JavaThread pointer (i.e.; the reference to |
2084 // thread-local information). | |
2085 void get_thread(); // load G2_thread | |
2086 void verify_thread(); // verify G2_thread contents | |
2087 void save_thread (const Register threache); // save to cache | |
2088 void restore_thread(const Register thread_cache); // restore from cache | |
2089 | |
2090 // Support for last Java frame (but use call_VM instead where possible) | |
2091 void set_last_Java_frame(Register last_java_sp, Register last_Java_pc); | |
2092 void reset_last_Java_frame(void); | |
2093 | |
2094 // Call into the VM. | |
2095 // Passes the thread pointer (in O0) as a prepended argument. | |
2096 // Makes sure oop return values are visible to the GC. | |
2097 void call_VM(Register oop_result, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); | |
2098 void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true); | |
2099 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); | |
2100 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); | |
2101 | |
2102 // these overloadings are not presently used on SPARC: | |
2103 void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); | |
2104 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); | |
2105 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); | |
2106 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); | |
2107 | |
2108 void call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments = 0); | |
2109 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1); | |
2110 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2); | |
2111 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3); | |
2112 | |
2113 void get_vm_result (Register oop_result); | |
2114 void get_vm_result_2(Register oop_result); | |
2115 | |
2116 // vm result is currently getting hijacked to for oop preservation | |
2117 void set_vm_result(Register oop_result); | |
2118 | |
2119 // if call_VM_base was called with check_exceptions=false, then call | |
2120 // check_and_forward_exception to handle exceptions when it is safe | |
2121 void check_and_forward_exception(Register scratch_reg); | |
2122 | |
2123 private: | |
2124 // For V8 | |
2125 void read_ccr_trap(Register ccr_save); | |
2126 void write_ccr_trap(Register ccr_save1, Register scratch1, Register scratch2); | |
2127 | |
2128 #ifdef ASSERT | |
2129 // For V8 debugging. Uses V8 instruction sequence and checks | |
2130 // result with V9 insturctions rdccr and wrccr. | |
2131 // Uses Gscatch and Gscatch2 | |
2132 void read_ccr_v8_assert(Register ccr_save); | |
2133 void write_ccr_v8_assert(Register ccr_save); | |
2134 #endif // ASSERT | |
2135 | |
2136 public: | |
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2137 |
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2138 // Write to card table for - register is destroyed afterwards. |
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2139 void card_table_write(jbyte* byte_map_base, Register tmp, Register obj); |
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2140 |
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2141 void card_write_barrier_post(Register store_addr, Register new_val, Register tmp); |
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2142 |
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2143 #ifndef SERIALGC |
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2144 // Array store and offset |
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2145 void g1_write_barrier_pre(Register obj, Register index, int offset, Register tmp, bool preserve_o_regs); |
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2146 |
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2147 void g1_write_barrier_post(Register store_addr, Register new_val, Register tmp); |
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2148 |
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2149 // May do filtering, depending on the boolean arguments. |
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2150 void g1_card_table_write(jbyte* byte_map_base, |
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2151 Register tmp, Register obj, Register new_val, |
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2152 bool region_filter, bool null_filter); |
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2153 #endif // SERIALGC |
0 | 2154 |
2155 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack | |
2156 void push_fTOS(); | |
2157 | |
2158 // pops double TOS element from CPU stack and pushes on FPU stack | |
2159 void pop_fTOS(); | |
2160 | |
2161 void empty_FPU_stack(); | |
2162 | |
2163 void push_IU_state(); | |
2164 void pop_IU_state(); | |
2165 | |
2166 void push_FPU_state(); | |
2167 void pop_FPU_state(); | |
2168 | |
2169 void push_CPU_state(); | |
2170 void pop_CPU_state(); | |
2171 | |
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2172 // if heap base register is used - reinit it with the correct value |
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2173 void reinit_heapbase(); |
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2174 |
0 | 2175 // Debugging |
2176 void _verify_oop(Register reg, const char * msg, const char * file, int line); | |
2177 void _verify_oop_addr(Address addr, const char * msg, const char * file, int line); | |
2178 | |
2179 #define verify_oop(reg) _verify_oop(reg, "broken oop " #reg, __FILE__, __LINE__) | |
2180 #define verify_oop_addr(addr) _verify_oop_addr(addr, "broken oop addr ", __FILE__, __LINE__) | |
2181 | |
2182 // only if +VerifyOops | |
2183 void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); | |
2184 // only if +VerifyFPU | |
2185 void stop(const char* msg); // prints msg, dumps registers and stops execution | |
2186 void warn(const char* msg); // prints msg, but don't stop | |
2187 void untested(const char* what = ""); | |
2188 void unimplemented(const char* what = "") { char* b = new char[1024]; sprintf(b, "unimplemented: %s", what); stop(b); } | |
2189 void should_not_reach_here() { stop("should not reach here"); } | |
2190 void print_CPU_state(); | |
2191 | |
2192 // oops in code | |
2193 Address allocate_oop_address( jobject obj, Register d ); // allocate_index | |
2194 Address constant_oop_address( jobject obj, Register d ); // find_index | |
2195 inline void set_oop ( jobject obj, Register d ); // uses allocate_oop_address | |
2196 inline void set_oop_constant( jobject obj, Register d ); // uses constant_oop_address | |
2197 inline void set_oop ( Address obj_addr ); // same as load_address | |
2198 | |
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2199 void set_narrow_oop( jobject obj, Register d ); |
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2200 |
0 | 2201 // nop padding |
2202 void align(int modulus); | |
2203 | |
2204 // declare a safepoint | |
2205 void safepoint(); | |
2206 | |
2207 // factor out part of stop into subroutine to save space | |
2208 void stop_subroutine(); | |
2209 // factor out part of verify_oop into subroutine to save space | |
2210 void verify_oop_subroutine(); | |
2211 | |
2212 // side-door communication with signalHandler in os_solaris.cpp | |
2213 static address _verify_oop_implicit_branch[3]; | |
2214 | |
2215 #ifndef PRODUCT | |
2216 static void test(); | |
2217 #endif | |
2218 | |
2219 // convert an incoming arglist to varargs format; put the pointer in d | |
2220 void set_varargs( Argument a, Register d ); | |
2221 | |
2222 int total_frame_size_in_bytes(int extraWords); | |
2223 | |
2224 // used when extraWords known statically | |
2225 void save_frame(int extraWords); | |
2226 void save_frame_c1(int size_in_bytes); | |
2227 // make a frame, and simultaneously pass up one or two register value | |
2228 // into the new register window | |
2229 void save_frame_and_mov(int extraWords, Register s1, Register d1, Register s2 = Register(), Register d2 = Register()); | |
2230 | |
2231 // give no. (outgoing) params, calc # of words will need on frame | |
2232 void calc_mem_param_words(Register Rparam_words, Register Rresult); | |
2233 | |
2234 // used to calculate frame size dynamically | |
2235 // result is in bytes and must be negated for save inst | |
2236 void calc_frame_size(Register extraWords, Register resultReg); | |
2237 | |
2238 // calc and also save | |
2239 void calc_frame_size_and_save(Register extraWords, Register resultReg); | |
2240 | |
2241 static void debug(char* msg, RegistersForDebugging* outWindow); | |
2242 | |
2243 // implementations of bytecodes used by both interpreter and compiler | |
2244 | |
2245 void lcmp( Register Ra_hi, Register Ra_low, | |
2246 Register Rb_hi, Register Rb_low, | |
2247 Register Rresult); | |
2248 | |
2249 void lneg( Register Rhi, Register Rlow ); | |
2250 | |
2251 void lshl( Register Rin_high, Register Rin_low, Register Rcount, | |
2252 Register Rout_high, Register Rout_low, Register Rtemp ); | |
2253 | |
2254 void lshr( Register Rin_high, Register Rin_low, Register Rcount, | |
2255 Register Rout_high, Register Rout_low, Register Rtemp ); | |
2256 | |
2257 void lushr( Register Rin_high, Register Rin_low, Register Rcount, | |
2258 Register Rout_high, Register Rout_low, Register Rtemp ); | |
2259 | |
2260 #ifdef _LP64 | |
2261 void lcmp( Register Ra, Register Rb, Register Rresult); | |
2262 #endif | |
2263 | |
2264 void float_cmp( bool is_float, int unordered_result, | |
2265 FloatRegister Fa, FloatRegister Fb, | |
2266 Register Rresult); | |
2267 | |
2268 void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); | |
2269 void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { Assembler::fneg(w, sd); } | |
2270 void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); | |
2271 void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); | |
2272 | |
2273 void save_all_globals_into_locals(); | |
2274 void restore_globals_from_locals(); | |
2275 | |
2276 void casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, | |
2277 address lock_addr=0, bool use_call_vm=false); | |
2278 void cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, | |
2279 address lock_addr=0, bool use_call_vm=false); | |
2280 void casn (Register addr_reg, Register cmp_reg, Register set_reg) ; | |
2281 | |
2282 // These set the icc condition code to equal if the lock succeeded | |
2283 // and notEqual if it failed and requires a slow case | |
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2284 void compiler_lock_object(Register Roop, Register Rmark, Register Rbox, |
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2285 Register Rscratch, |
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2286 BiasedLockingCounters* counters = NULL, |
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2287 bool try_bias = UseBiasedLocking); |
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2288 void compiler_unlock_object(Register Roop, Register Rmark, Register Rbox, |
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2289 Register Rscratch, |
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2290 bool try_bias = UseBiasedLocking); |
0 | 2291 |
2292 // Biased locking support | |
2293 // Upon entry, lock_reg must point to the lock record on the stack, | |
2294 // obj_reg must contain the target object, and mark_reg must contain | |
2295 // the target object's header. | |
2296 // Destroys mark_reg if an attempt is made to bias an anonymously | |
2297 // biased lock. In this case a failure will go either to the slow | |
2298 // case or fall through with the notEqual condition code set with | |
2299 // the expectation that the slow case in the runtime will be called. | |
2300 // In the fall-through case where the CAS-based lock is done, | |
2301 // mark_reg is not destroyed. | |
2302 void biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg, | |
2303 Label& done, Label* slow_case = NULL, | |
2304 BiasedLockingCounters* counters = NULL); | |
2305 // Upon entry, the base register of mark_addr must contain the oop. | |
2306 // Destroys temp_reg. | |
2307 | |
2308 // If allow_delay_slot_filling is set to true, the next instruction | |
2309 // emitted after this one will go in an annulled delay slot if the | |
2310 // biased locking exit case failed. | |
2311 void biased_locking_exit(Address mark_addr, Register temp_reg, Label& done, bool allow_delay_slot_filling = false); | |
2312 | |
2313 // allocation | |
2314 void eden_allocate( | |
2315 Register obj, // result: pointer to object after successful allocation | |
2316 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise | |
2317 int con_size_in_bytes, // object size in bytes if known at compile time | |
2318 Register t1, // temp register | |
2319 Register t2, // temp register | |
2320 Label& slow_case // continuation point if fast allocation fails | |
2321 ); | |
2322 void tlab_allocate( | |
2323 Register obj, // result: pointer to object after successful allocation | |
2324 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise | |
2325 int con_size_in_bytes, // object size in bytes if known at compile time | |
2326 Register t1, // temp register | |
2327 Label& slow_case // continuation point if fast allocation fails | |
2328 ); | |
2329 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); | |
2330 | |
623
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2331 // interface method calling |
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2332 void lookup_interface_method(Register recv_klass, |
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2333 Register intf_klass, |
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2334 RegisterOrConstant itable_index, |
623
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2335 Register method_result, |
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2336 Register temp_reg, Register temp2_reg, |
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2337 Label& no_such_interface); |
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2338 |
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2339 // Test sub_klass against super_klass, with fast and slow paths. |
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2340 |
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2341 // The fast path produces a tri-state answer: yes / no / maybe-slow. |
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2342 // One of the three labels can be NULL, meaning take the fall-through. |
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2343 // If super_check_offset is -1, the value is loaded up from super_klass. |
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2344 // No registers are killed, except temp_reg and temp2_reg. |
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2345 // If super_check_offset is not -1, temp2_reg is not used and can be noreg. |
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2346 void check_klass_subtype_fast_path(Register sub_klass, |
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2347 Register super_klass, |
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2348 Register temp_reg, |
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2349 Register temp2_reg, |
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2350 Label* L_success, |
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2351 Label* L_failure, |
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2352 Label* L_slow_path, |
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2353 RegisterOrConstant super_check_offset = RegisterOrConstant(-1), |
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2354 Register instanceof_hack = noreg); |
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2355 |
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2356 // The rest of the type check; must be wired to a corresponding fast path. |
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2357 // It does not repeat the fast path logic, so don't use it standalone. |
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2358 // The temp_reg can be noreg, if no temps are available. |
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2359 // It can also be sub_klass or super_klass, meaning it's OK to kill that one. |
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2360 // Updates the sub's secondary super cache as necessary. |
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2361 void check_klass_subtype_slow_path(Register sub_klass, |
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2362 Register super_klass, |
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2363 Register temp_reg, |
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2364 Register temp2_reg, |
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2365 Register temp3_reg, |
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2366 Register temp4_reg, |
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2367 Label* L_success, |
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2368 Label* L_failure); |
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2369 |
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2370 // Simplified, combined version, good for typical uses. |
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2371 // Falls through on failure. |
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2372 void check_klass_subtype(Register sub_klass, |
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2373 Register super_klass, |
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2374 Register temp_reg, |
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2375 Register temp2_reg, |
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2376 Label& L_success); |
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2377 |
710 | 2378 // method handles (JSR 292) |
2379 void check_method_handle_type(Register mtype_reg, Register mh_reg, | |
2380 Register temp_reg, | |
2381 Label& wrong_method_type); | |
2382 void jump_to_method_handle_entry(Register mh_reg, Register temp_reg); | |
2383 // offset relative to Gargs of argument at tos[arg_slot]. | |
2384 // (arg_slot == 0 means the last argument, not the first). | |
2385 RegisterOrConstant argument_offset(RegisterOrConstant arg_slot, | |
2386 int extra_slot_offset = 0); | |
2387 | |
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2388 |
0 | 2389 // Stack overflow checking |
2390 | |
2391 // Note: this clobbers G3_scratch | |
2392 void bang_stack_with_offset(int offset) { | |
2393 // stack grows down, caller passes positive offset | |
2394 assert(offset > 0, "must bang with negative offset"); | |
2395 set((-offset)+STACK_BIAS, G3_scratch); | |
2396 st(G0, SP, G3_scratch); | |
2397 } | |
2398 | |
2399 // Writes to stack successive pages until offset reached to check for | |
2400 // stack overflow + shadow pages. Clobbers tsp and scratch registers. | |
2401 void bang_stack_size(Register Rsize, Register Rtsp, Register Rscratch); | |
2402 | |
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2403 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, Register tmp, int offset); |
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2404 |
0 | 2405 void verify_tlab(); |
2406 | |
2407 Condition negate_condition(Condition cond); | |
2408 | |
2409 // Helper functions for statistics gathering. | |
2410 // Conditionally (non-atomically) increments passed counter address, preserving condition codes. | |
2411 void cond_inc(Condition cond, address counter_addr, Register Rtemp1, Register Rtemp2); | |
2412 // Unconditional increment. | |
2413 void inc_counter(address counter_addr, Register Rtemp1, Register Rtemp2); | |
2414 | |
2415 #undef VIRTUAL | |
2416 | |
2417 }; | |
2418 | |
2419 /** | |
2420 * class SkipIfEqual: | |
2421 * | |
2422 * Instantiating this class will result in assembly code being output that will | |
2423 * jump around any code emitted between the creation of the instance and it's | |
2424 * automatic destruction at the end of a scope block, depending on the value of | |
2425 * the flag passed to the constructor, which will be checked at run-time. | |
2426 */ | |
2427 class SkipIfEqual : public StackObj { | |
2428 private: | |
2429 MacroAssembler* _masm; | |
2430 Label _label; | |
2431 | |
2432 public: | |
2433 // 'temp' is a temp register that this object can use (and trash) | |
2434 SkipIfEqual(MacroAssembler*, Register temp, | |
2435 const bool* flag_addr, Assembler::Condition condition); | |
2436 ~SkipIfEqual(); | |
2437 }; | |
2438 | |
2439 #ifdef ASSERT | |
2440 // On RISC, there's no benefit to verifying instruction boundaries. | |
2441 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; } | |
2442 #endif |