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1 /*
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2 * Copyright 1999-2008 Sun Microsystems, Inc. All Rights Reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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20 * CA 95054 USA or visit www.sun.com if you need additional information or
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21 * have any questions.
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22 *
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23 */
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24
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25 # include "incls/_precompiled.incl"
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26 # include "incls/_c1_FrameMap_x86.cpp.incl"
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27
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28 const int FrameMap::pd_c_runtime_reserved_arg_size = 0;
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29
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30 LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool) {
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31 LIR_Opr opr = LIR_OprFact::illegalOpr;
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32 VMReg r_1 = reg->first();
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33 VMReg r_2 = reg->second();
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34 if (r_1->is_stack()) {
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35 // Convert stack slot to an SP offset
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36 // The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value
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37 // so we must add it in here.
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38 int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
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39 opr = LIR_OprFact::address(new LIR_Address(rsp_opr, st_off, type));
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40 } else if (r_1->is_Register()) {
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41 Register reg = r_1->as_Register();
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304
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42 if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
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43 Register reg2 = r_2->as_Register();
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304
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44 #ifdef _LP64
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45 assert(reg2 == reg, "must be same register");
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46 opr = as_long_opr(reg);
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47 #else
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48 opr = as_long_opr(reg2, reg);
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304
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49 #endif // _LP64
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50 } else if (type == T_OBJECT || type == T_ARRAY) {
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51 opr = as_oop_opr(reg);
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52 } else {
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53 opr = as_opr(reg);
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54 }
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55 } else if (r_1->is_FloatRegister()) {
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56 assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
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57 int num = r_1->as_FloatRegister()->encoding();
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58 if (type == T_FLOAT) {
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59 opr = LIR_OprFact::single_fpu(num);
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60 } else {
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61 opr = LIR_OprFact::double_fpu(num);
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62 }
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63 } else if (r_1->is_XMMRegister()) {
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64 assert(type == T_DOUBLE || type == T_FLOAT, "wrong type");
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65 int num = r_1->as_XMMRegister()->encoding();
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66 if (type == T_FLOAT) {
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67 opr = LIR_OprFact::single_xmm(num);
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68 } else {
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69 opr = LIR_OprFact::double_xmm(num);
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70 }
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71 } else {
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72 ShouldNotReachHere();
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73 }
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74 return opr;
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75 }
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76
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77
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78 LIR_Opr FrameMap::rsi_opr;
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79 LIR_Opr FrameMap::rdi_opr;
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80 LIR_Opr FrameMap::rbx_opr;
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81 LIR_Opr FrameMap::rax_opr;
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82 LIR_Opr FrameMap::rdx_opr;
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83 LIR_Opr FrameMap::rcx_opr;
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84 LIR_Opr FrameMap::rsp_opr;
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85 LIR_Opr FrameMap::rbp_opr;
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86
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87 LIR_Opr FrameMap::receiver_opr;
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88
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89 LIR_Opr FrameMap::rsi_oop_opr;
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90 LIR_Opr FrameMap::rdi_oop_opr;
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91 LIR_Opr FrameMap::rbx_oop_opr;
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92 LIR_Opr FrameMap::rax_oop_opr;
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93 LIR_Opr FrameMap::rdx_oop_opr;
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94 LIR_Opr FrameMap::rcx_oop_opr;
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95
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304
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96 LIR_Opr FrameMap::long0_opr;
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97 LIR_Opr FrameMap::long1_opr;
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98 LIR_Opr FrameMap::fpu0_float_opr;
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99 LIR_Opr FrameMap::fpu0_double_opr;
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100 LIR_Opr FrameMap::xmm0_float_opr;
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101 LIR_Opr FrameMap::xmm0_double_opr;
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102
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304
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103 #ifdef _LP64
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104
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105 LIR_Opr FrameMap::r8_opr;
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106 LIR_Opr FrameMap::r9_opr;
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107 LIR_Opr FrameMap::r10_opr;
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108 LIR_Opr FrameMap::r11_opr;
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109 LIR_Opr FrameMap::r12_opr;
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110 LIR_Opr FrameMap::r13_opr;
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111 LIR_Opr FrameMap::r14_opr;
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112 LIR_Opr FrameMap::r15_opr;
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113
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114 // r10 and r15 can never contain oops since they aren't available to
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115 // the allocator
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116 LIR_Opr FrameMap::r8_oop_opr;
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117 LIR_Opr FrameMap::r9_oop_opr;
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118 LIR_Opr FrameMap::r11_oop_opr;
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119 LIR_Opr FrameMap::r12_oop_opr;
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120 LIR_Opr FrameMap::r13_oop_opr;
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121 LIR_Opr FrameMap::r14_oop_opr;
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122 #endif // _LP64
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123
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124 LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, };
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125 LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, };
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126 LIR_Opr FrameMap::_caller_save_xmm_regs[] = { 0, };
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127
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128 XMMRegister FrameMap::_xmm_regs [] = { 0, };
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129
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130 XMMRegister FrameMap::nr2xmmreg(int rnr) {
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131 assert(_init_done, "tables not initialized");
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132 return _xmm_regs[rnr];
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133 }
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134
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135 //--------------------------------------------------------
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136 // FrameMap
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137 //--------------------------------------------------------
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138
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139 void FrameMap::init() {
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140 if (_init_done) return;
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141
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304
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142 assert(nof_cpu_regs == LP64_ONLY(16) NOT_LP64(8), "wrong number of CPU registers");
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143 map_register(0, rsi); rsi_opr = LIR_OprFact::single_cpu(0);
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144 map_register(1, rdi); rdi_opr = LIR_OprFact::single_cpu(1);
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145 map_register(2, rbx); rbx_opr = LIR_OprFact::single_cpu(2);
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146 map_register(3, rax); rax_opr = LIR_OprFact::single_cpu(3);
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147 map_register(4, rdx); rdx_opr = LIR_OprFact::single_cpu(4);
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148 map_register(5, rcx); rcx_opr = LIR_OprFact::single_cpu(5);
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149
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304
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150 #ifndef _LP64
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151 // The unallocatable registers are at the end
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152 map_register(6, rsp);
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153 map_register(7, rbp);
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154 #else
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155 map_register( 6, r8); r8_opr = LIR_OprFact::single_cpu(6);
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156 map_register( 7, r9); r9_opr = LIR_OprFact::single_cpu(7);
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157 map_register( 8, r11); r11_opr = LIR_OprFact::single_cpu(8);
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158 map_register( 9, r12); r12_opr = LIR_OprFact::single_cpu(9);
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159 map_register(10, r13); r13_opr = LIR_OprFact::single_cpu(10);
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160 map_register(11, r14); r14_opr = LIR_OprFact::single_cpu(11);
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161 // The unallocatable registers are at the end
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162 map_register(12, r10); r10_opr = LIR_OprFact::single_cpu(12);
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163 map_register(13, r15); r15_opr = LIR_OprFact::single_cpu(13);
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164 map_register(14, rsp);
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165 map_register(15, rbp);
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166 #endif // _LP64
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167
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168 #ifdef _LP64
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169 long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 3 /*eax*/);
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170 long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 2 /*ebx*/);
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171 #else
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172 long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 4 /*edx*/);
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173 long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 5 /*ecx*/);
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174 #endif // _LP64
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175 fpu0_float_opr = LIR_OprFact::single_fpu(0);
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176 fpu0_double_opr = LIR_OprFact::double_fpu(0);
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177 xmm0_float_opr = LIR_OprFact::single_xmm(0);
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178 xmm0_double_opr = LIR_OprFact::double_xmm(0);
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179
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180 _caller_save_cpu_regs[0] = rsi_opr;
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181 _caller_save_cpu_regs[1] = rdi_opr;
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182 _caller_save_cpu_regs[2] = rbx_opr;
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183 _caller_save_cpu_regs[3] = rax_opr;
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184 _caller_save_cpu_regs[4] = rdx_opr;
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185 _caller_save_cpu_regs[5] = rcx_opr;
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186
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304
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187 #ifdef _LP64
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188 _caller_save_cpu_regs[6] = r8_opr;
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189 _caller_save_cpu_regs[7] = r9_opr;
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190 _caller_save_cpu_regs[8] = r11_opr;
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191 _caller_save_cpu_regs[9] = r12_opr;
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192 _caller_save_cpu_regs[10] = r13_opr;
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193 _caller_save_cpu_regs[11] = r14_opr;
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194 #endif // _LP64
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195
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196
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197 _xmm_regs[0] = xmm0;
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198 _xmm_regs[1] = xmm1;
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199 _xmm_regs[2] = xmm2;
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200 _xmm_regs[3] = xmm3;
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201 _xmm_regs[4] = xmm4;
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202 _xmm_regs[5] = xmm5;
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203 _xmm_regs[6] = xmm6;
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204 _xmm_regs[7] = xmm7;
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205
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304
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206 #ifdef _LP64
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207 _xmm_regs[8] = xmm8;
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208 _xmm_regs[9] = xmm9;
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209 _xmm_regs[10] = xmm10;
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210 _xmm_regs[11] = xmm11;
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211 _xmm_regs[12] = xmm12;
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212 _xmm_regs[13] = xmm13;
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213 _xmm_regs[14] = xmm14;
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214 _xmm_regs[15] = xmm15;
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215 #endif // _LP64
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216
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217 for (int i = 0; i < 8; i++) {
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218 _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i);
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219 }
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220
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221 for (int i = 0; i < nof_caller_save_xmm_regs ; i++) {
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222 _caller_save_xmm_regs[i] = LIR_OprFact::single_xmm(i);
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223 }
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224
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225 _init_done = true;
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226
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304
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227 rsi_oop_opr = as_oop_opr(rsi);
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228 rdi_oop_opr = as_oop_opr(rdi);
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229 rbx_oop_opr = as_oop_opr(rbx);
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230 rax_oop_opr = as_oop_opr(rax);
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231 rdx_oop_opr = as_oop_opr(rdx);
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232 rcx_oop_opr = as_oop_opr(rcx);
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233
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234 rsp_opr = as_pointer_opr(rsp);
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235 rbp_opr = as_pointer_opr(rbp);
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236
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237 #ifdef _LP64
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238 r8_oop_opr = as_oop_opr(r8);
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239 r9_oop_opr = as_oop_opr(r9);
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240 r11_oop_opr = as_oop_opr(r11);
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241 r12_oop_opr = as_oop_opr(r12);
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242 r13_oop_opr = as_oop_opr(r13);
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243 r14_oop_opr = as_oop_opr(r14);
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244 #endif // _LP64
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245
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246 VMRegPair regs;
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247 BasicType sig_bt = T_OBJECT;
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248 SharedRuntime::java_calling_convention(&sig_bt, ®s, 1, true);
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249 receiver_opr = as_oop_opr(regs.first()->as_Register());
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250
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251 }
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252
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253
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254 Address FrameMap::make_new_address(ByteSize sp_offset) const {
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255 // for rbp, based address use this:
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256 // return Address(rbp, in_bytes(sp_offset) - (framesize() - 2) * 4);
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257 return Address(rsp, in_bytes(sp_offset));
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258 }
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259
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260
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261 // ----------------mapping-----------------------
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262 // all mapping is based on rbp, addressing, except for simple leaf methods where we access
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263 // the locals rsp based (and no frame is built)
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264
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265
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266 // Frame for simple leaf methods (quick entries)
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267 //
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268 // +----------+
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269 // | ret addr | <- TOS
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270 // +----------+
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271 // | args |
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272 // | ...... |
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273
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274 // Frame for standard methods
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275 //
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276 // | .........| <- TOS
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277 // | locals |
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278 // +----------+
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279 // | old rbp, | <- EBP
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280 // +----------+
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281 // | ret addr |
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282 // +----------+
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283 // | args |
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284 // | .........|
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285
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286
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287 // For OopMaps, map a local variable or spill index to an VMRegImpl name.
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288 // This is the offset from sp() in the frame of the slot for the index,
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289 // skewed by VMRegImpl::stack0 to indicate a stack location (vs.a register.)
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290 //
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291 // framesize +
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292 // stack0 stack0 0 <- VMReg
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293 // | | <registers> |
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294 // ...........|..............|.............|
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295 // 0 1 2 3 x x 4 5 6 ... | <- local indices
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296 // ^ ^ sp() ( x x indicate link
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297 // | | and return addr)
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298 // arguments non-argument locals
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299
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300
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301 VMReg FrameMap::fpu_regname (int n) {
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302 // Return the OptoReg name for the fpu stack slot "n"
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303 // A spilled fpu stack slot comprises to two single-word OptoReg's.
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304 return as_FloatRegister(n)->as_VMReg();
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305 }
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306
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307 LIR_Opr FrameMap::stack_pointer() {
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308 return FrameMap::rsp_opr;
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309 }
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310
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311
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312 bool FrameMap::validate_frame() {
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313 return true;
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314 }
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