Mercurial > hg > truffle
annotate src/cpu/ppc/vm/vmreg_ppc.inline.hpp @ 21863:f4822d122041 jdk8u45-b11
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author | asaha |
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date | Sat, 07 Mar 2015 16:26:10 -0800 |
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1 /* |
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2 * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved. |
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3 * Copyright 2012, 2013 SAP AG. All rights reserved. |
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4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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5 * |
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6 * This code is free software; you can redistribute it and/or modify it |
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7 * under the terms of the GNU General Public License version 2 only, as |
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8 * published by the Free Software Foundation. |
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9 * |
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10 * This code is distributed in the hope that it will be useful, but WITHOUT |
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11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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13 * version 2 for more details (a copy is included in the LICENSE file that |
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14 * accompanied this code). |
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15 * |
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16 * You should have received a copy of the GNU General Public License version |
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17 * 2 along with this work; if not, write to the Free Software Foundation, |
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18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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19 * |
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20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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21 * or visit www.oracle.com if you need additional information or have any |
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22 * questions. |
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23 * |
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24 */ |
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25 |
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26 #ifndef CPU_PPC_VM_VMREG_PPC_INLINE_HPP |
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27 #define CPU_PPC_VM_VMREG_PPC_INLINE_HPP |
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28 |
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29 inline VMReg RegisterImpl::as_VMReg() { |
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30 if (this == noreg) return VMRegImpl::Bad(); |
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31 return VMRegImpl::as_VMReg(encoding() << 1); |
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32 } |
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33 |
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34 // Since we don't have two halfs here, don't multiply by 2. |
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35 inline VMReg ConditionRegisterImpl::as_VMReg() { |
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36 return VMRegImpl::as_VMReg((encoding()) + ConcreteRegisterImpl::max_fpr); |
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37 } |
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38 |
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39 inline VMReg FloatRegisterImpl::as_VMReg() { |
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40 return VMRegImpl::as_VMReg((encoding() << 1) + ConcreteRegisterImpl::max_gpr); |
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41 } |
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42 |
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43 inline VMReg SpecialRegisterImpl::as_VMReg() { |
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44 return VMRegImpl::as_VMReg((encoding()) + ConcreteRegisterImpl::max_cnd); |
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45 } |
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46 |
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47 inline bool VMRegImpl::is_Register() { |
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48 return (unsigned int)value() < (unsigned int)ConcreteRegisterImpl::max_gpr; |
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49 } |
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50 |
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51 inline bool VMRegImpl::is_FloatRegister() { |
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52 return value() >= ConcreteRegisterImpl::max_gpr && |
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53 value() < ConcreteRegisterImpl::max_fpr; |
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54 } |
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55 |
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56 inline Register VMRegImpl::as_Register() { |
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57 assert(is_Register() && is_even(value()), "even-aligned GPR name"); |
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58 return ::as_Register(value()>>1); |
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59 } |
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60 |
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61 inline FloatRegister VMRegImpl::as_FloatRegister() { |
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62 assert(is_FloatRegister() && is_even(value()), "must be"); |
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63 return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) >> 1); |
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64 } |
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65 |
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66 inline bool VMRegImpl::is_concrete() { |
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67 assert(is_reg(), "must be"); |
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68 return is_even(value()); |
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69 } |
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70 |
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71 #endif // CPU_PPC_VM_VMREG_PPC_INLINE_HPP |