Mercurial > hg > truffle
annotate src/cpu/x86/vm/vm_version_x86.cpp @ 1252:f516d5d7a019
6910605: C2: NullPointerException/ClassCaseException is thrown when C2 with DeoptimizeALot is used
Summary: Set the reexecute bit for runtime calls _new_array_Java when they used for _multianewarray bytecode.
Reviewed-by: never
author | kvn |
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date | Mon, 08 Feb 2010 12:20:09 -0800 |
parents | 323bd24c6520 |
children | c18cbe5936b8 |
rev | line source |
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585 | 1 /* |
2 * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved. | |
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
20 * CA 95054 USA or visit www.sun.com if you need additional information or | |
21 * have any questions. | |
22 * | |
23 */ | |
24 | |
25 # include "incls/_precompiled.incl" | |
26 # include "incls/_vm_version_x86.cpp.incl" | |
27 | |
28 | |
29 int VM_Version::_cpu; | |
30 int VM_Version::_model; | |
31 int VM_Version::_stepping; | |
32 int VM_Version::_cpuFeatures; | |
33 const char* VM_Version::_features_str = ""; | |
34 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; | |
35 | |
36 static BufferBlob* stub_blob; | |
37 static const int stub_size = 300; | |
38 | |
39 extern "C" { | |
40 typedef void (*getPsrInfo_stub_t)(void*); | |
41 } | |
42 static getPsrInfo_stub_t getPsrInfo_stub = NULL; | |
43 | |
44 | |
45 class VM_Version_StubGenerator: public StubCodeGenerator { | |
46 public: | |
47 | |
48 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {} | |
49 | |
50 address generate_getPsrInfo() { | |
51 // Flags to test CPU type. | |
52 const uint32_t EFL_AC = 0x40000; | |
53 const uint32_t EFL_ID = 0x200000; | |
54 // Values for when we don't have a CPUID instruction. | |
55 const int CPU_FAMILY_SHIFT = 8; | |
56 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT); | |
57 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT); | |
58 | |
59 Label detect_486, cpu486, detect_586, std_cpuid1; | |
60 Label ext_cpuid1, ext_cpuid5, done; | |
61 | |
62 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub"); | |
63 # define __ _masm-> | |
64 | |
65 address start = __ pc(); | |
66 | |
67 // | |
68 // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info); | |
69 // | |
70 // LP64: rcx and rdx are first and second argument registers on windows | |
71 | |
72 __ push(rbp); | |
73 #ifdef _LP64 | |
74 __ mov(rbp, c_rarg0); // cpuid_info address | |
75 #else | |
76 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address | |
77 #endif | |
78 __ push(rbx); | |
79 __ push(rsi); | |
80 __ pushf(); // preserve rbx, and flags | |
81 __ pop(rax); | |
82 __ push(rax); | |
83 __ mov(rcx, rax); | |
84 // | |
85 // if we are unable to change the AC flag, we have a 386 | |
86 // | |
87 __ xorl(rax, EFL_AC); | |
88 __ push(rax); | |
89 __ popf(); | |
90 __ pushf(); | |
91 __ pop(rax); | |
92 __ cmpptr(rax, rcx); | |
93 __ jccb(Assembler::notEqual, detect_486); | |
94 | |
95 __ movl(rax, CPU_FAMILY_386); | |
96 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); | |
97 __ jmp(done); | |
98 | |
99 // | |
100 // If we are unable to change the ID flag, we have a 486 which does | |
101 // not support the "cpuid" instruction. | |
102 // | |
103 __ bind(detect_486); | |
104 __ mov(rax, rcx); | |
105 __ xorl(rax, EFL_ID); | |
106 __ push(rax); | |
107 __ popf(); | |
108 __ pushf(); | |
109 __ pop(rax); | |
110 __ cmpptr(rcx, rax); | |
111 __ jccb(Assembler::notEqual, detect_586); | |
112 | |
113 __ bind(cpu486); | |
114 __ movl(rax, CPU_FAMILY_486); | |
115 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); | |
116 __ jmp(done); | |
117 | |
118 // | |
119 // At this point, we have a chip which supports the "cpuid" instruction | |
120 // | |
121 __ bind(detect_586); | |
122 __ xorl(rax, rax); | |
123 __ cpuid(); | |
124 __ orl(rax, rax); | |
125 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input | |
126 // value of at least 1, we give up and | |
127 // assume a 486 | |
128 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); | |
129 __ movl(Address(rsi, 0), rax); | |
130 __ movl(Address(rsi, 4), rbx); | |
131 __ movl(Address(rsi, 8), rcx); | |
132 __ movl(Address(rsi,12), rdx); | |
133 | |
134 __ cmpl(rax, 3); // Is cpuid(0x4) supported? | |
135 __ jccb(Assembler::belowEqual, std_cpuid1); | |
136 | |
137 // | |
138 // cpuid(0x4) Deterministic cache params | |
139 // | |
140 __ movl(rax, 4); | |
141 __ xorl(rcx, rcx); // L1 cache | |
142 __ cpuid(); | |
143 __ push(rax); | |
144 __ andl(rax, 0x1f); // Determine if valid cache parameters used | |
145 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache | |
146 __ pop(rax); | |
147 __ jccb(Assembler::equal, std_cpuid1); | |
148 | |
149 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset()))); | |
150 __ movl(Address(rsi, 0), rax); | |
151 __ movl(Address(rsi, 4), rbx); | |
152 __ movl(Address(rsi, 8), rcx); | |
153 __ movl(Address(rsi,12), rdx); | |
154 | |
155 // | |
156 // Standard cpuid(0x1) | |
157 // | |
158 __ bind(std_cpuid1); | |
159 __ movl(rax, 1); | |
160 __ cpuid(); | |
161 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); | |
162 __ movl(Address(rsi, 0), rax); | |
163 __ movl(Address(rsi, 4), rbx); | |
164 __ movl(Address(rsi, 8), rcx); | |
165 __ movl(Address(rsi,12), rdx); | |
166 | |
167 __ movl(rax, 0x80000000); | |
168 __ cpuid(); | |
169 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported? | |
170 __ jcc(Assembler::belowEqual, done); | |
171 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported? | |
172 __ jccb(Assembler::belowEqual, ext_cpuid1); | |
173 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported? | |
174 __ jccb(Assembler::belowEqual, ext_cpuid5); | |
175 // | |
176 // Extended cpuid(0x80000008) | |
177 // | |
178 __ movl(rax, 0x80000008); | |
179 __ cpuid(); | |
180 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset()))); | |
181 __ movl(Address(rsi, 0), rax); | |
182 __ movl(Address(rsi, 4), rbx); | |
183 __ movl(Address(rsi, 8), rcx); | |
184 __ movl(Address(rsi,12), rdx); | |
185 | |
186 // | |
187 // Extended cpuid(0x80000005) | |
188 // | |
189 __ bind(ext_cpuid5); | |
190 __ movl(rax, 0x80000005); | |
191 __ cpuid(); | |
192 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset()))); | |
193 __ movl(Address(rsi, 0), rax); | |
194 __ movl(Address(rsi, 4), rbx); | |
195 __ movl(Address(rsi, 8), rcx); | |
196 __ movl(Address(rsi,12), rdx); | |
197 | |
198 // | |
199 // Extended cpuid(0x80000001) | |
200 // | |
201 __ bind(ext_cpuid1); | |
202 __ movl(rax, 0x80000001); | |
203 __ cpuid(); | |
204 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset()))); | |
205 __ movl(Address(rsi, 0), rax); | |
206 __ movl(Address(rsi, 4), rbx); | |
207 __ movl(Address(rsi, 8), rcx); | |
208 __ movl(Address(rsi,12), rdx); | |
209 | |
210 // | |
211 // return | |
212 // | |
213 __ bind(done); | |
214 __ popf(); | |
215 __ pop(rsi); | |
216 __ pop(rbx); | |
217 __ pop(rbp); | |
218 __ ret(0); | |
219 | |
220 # undef __ | |
221 | |
222 return start; | |
223 }; | |
224 }; | |
225 | |
226 | |
227 void VM_Version::get_processor_features() { | |
228 | |
229 _cpu = 4; // 486 by default | |
230 _model = 0; | |
231 _stepping = 0; | |
232 _cpuFeatures = 0; | |
233 _logical_processors_per_package = 1; | |
234 | |
235 if (!Use486InstrsOnly) { | |
236 // Get raw processor info | |
237 getPsrInfo_stub(&_cpuid_info); | |
238 assert_is_initialized(); | |
239 _cpu = extended_cpu_family(); | |
240 _model = extended_cpu_model(); | |
241 _stepping = cpu_stepping(); | |
242 | |
243 if (cpu_family() > 4) { // it supports CPUID | |
244 _cpuFeatures = feature_flags(); | |
245 // Logical processors are only available on P4s and above, | |
246 // and only if hyperthreading is available. | |
247 _logical_processors_per_package = logical_processor_count(); | |
248 } | |
249 } | |
250 | |
251 _supports_cx8 = supports_cmpxchg8(); | |
252 | |
253 #ifdef _LP64 | |
254 // OS should support SSE for x64 and hardware should support at least SSE2. | |
255 if (!VM_Version::supports_sse2()) { | |
256 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported"); | |
257 } | |
1060 | 258 // in 64 bit the use of SSE2 is the minimum |
259 if (UseSSE < 2) UseSSE = 2; | |
585 | 260 #endif |
261 | |
262 // If the OS doesn't support SSE, we can't use this feature even if the HW does | |
263 if (!os::supports_sse()) | |
264 _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2); | |
265 | |
266 if (UseSSE < 4) { | |
267 _cpuFeatures &= ~CPU_SSE4_1; | |
268 _cpuFeatures &= ~CPU_SSE4_2; | |
269 } | |
270 | |
271 if (UseSSE < 3) { | |
272 _cpuFeatures &= ~CPU_SSE3; | |
273 _cpuFeatures &= ~CPU_SSSE3; | |
274 _cpuFeatures &= ~CPU_SSE4A; | |
275 } | |
276 | |
277 if (UseSSE < 2) | |
278 _cpuFeatures &= ~CPU_SSE2; | |
279 | |
280 if (UseSSE < 1) | |
281 _cpuFeatures &= ~CPU_SSE; | |
282 | |
283 if (logical_processors_per_package() == 1) { | |
284 // HT processor could be installed on a system which doesn't support HT. | |
285 _cpuFeatures &= ~CPU_HT; | |
286 } | |
287 | |
288 char buf[256]; | |
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289 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
585 | 290 cores_per_cpu(), threads_per_core(), |
291 cpu_family(), _model, _stepping, | |
292 (supports_cmov() ? ", cmov" : ""), | |
293 (supports_cmpxchg8() ? ", cx8" : ""), | |
294 (supports_fxsr() ? ", fxsr" : ""), | |
295 (supports_mmx() ? ", mmx" : ""), | |
296 (supports_sse() ? ", sse" : ""), | |
297 (supports_sse2() ? ", sse2" : ""), | |
298 (supports_sse3() ? ", sse3" : ""), | |
299 (supports_ssse3()? ", ssse3": ""), | |
300 (supports_sse4_1() ? ", sse4.1" : ""), | |
301 (supports_sse4_2() ? ", sse4.2" : ""), | |
643
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302 (supports_popcnt() ? ", popcnt" : ""), |
585 | 303 (supports_mmx_ext() ? ", mmxext" : ""), |
304 (supports_3dnow() ? ", 3dnow" : ""), | |
305 (supports_3dnow2() ? ", 3dnowext" : ""), | |
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306 (supports_lzcnt() ? ", lzcnt": ""), |
585 | 307 (supports_sse4a() ? ", sse4a": ""), |
308 (supports_ht() ? ", ht": "")); | |
309 _features_str = strdup(buf); | |
310 | |
311 // UseSSE is set to the smaller of what hardware supports and what | |
312 // the command line requires. I.e., you cannot set UseSSE to 2 on | |
313 // older Pentiums which do not support it. | |
314 if( UseSSE > 4 ) UseSSE=4; | |
315 if( UseSSE < 0 ) UseSSE=0; | |
316 if( !supports_sse4_1() ) // Drop to 3 if no SSE4 support | |
317 UseSSE = MIN2((intx)3,UseSSE); | |
318 if( !supports_sse3() ) // Drop to 2 if no SSE3 support | |
319 UseSSE = MIN2((intx)2,UseSSE); | |
320 if( !supports_sse2() ) // Drop to 1 if no SSE2 support | |
321 UseSSE = MIN2((intx)1,UseSSE); | |
322 if( !supports_sse () ) // Drop to 0 if no SSE support | |
323 UseSSE = 0; | |
324 | |
325 // On new cpus instructions which update whole XMM register should be used | |
326 // to prevent partial register stall due to dependencies on high half. | |
327 // | |
328 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem) | |
329 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem) | |
330 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm). | |
331 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm). | |
332 | |
333 if( is_amd() ) { // AMD cpus specific settings | |
334 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) { | |
335 // Use it on new AMD cpus starting from Opteron. | |
336 UseAddressNop = true; | |
337 } | |
338 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) { | |
339 // Use it on new AMD cpus starting from Opteron. | |
340 UseNewLongLShift = true; | |
341 } | |
342 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { | |
343 if( supports_sse4a() ) { | |
344 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron | |
345 } else { | |
346 UseXmmLoadAndClearUpper = false; | |
347 } | |
348 } | |
349 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { | |
350 if( supports_sse4a() ) { | |
351 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h' | |
352 } else { | |
353 UseXmmRegToRegMoveAll = false; | |
354 } | |
355 } | |
356 if( FLAG_IS_DEFAULT(UseXmmI2F) ) { | |
357 if( supports_sse4a() ) { | |
358 UseXmmI2F = true; | |
359 } else { | |
360 UseXmmI2F = false; | |
361 } | |
362 } | |
363 if( FLAG_IS_DEFAULT(UseXmmI2D) ) { | |
364 if( supports_sse4a() ) { | |
365 UseXmmI2D = true; | |
366 } else { | |
367 UseXmmI2D = false; | |
368 } | |
369 } | |
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370 |
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371 // Use count leading zeros count instruction if available. |
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372 if (supports_lzcnt()) { |
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373 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) { |
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374 UseCountLeadingZerosInstruction = true; |
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375 } |
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376 } |
585 | 377 } |
378 | |
379 if( is_intel() ) { // Intel cpus specific settings | |
380 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) { | |
381 UseStoreImmI16 = false; // don't use it on Intel cpus | |
382 } | |
383 if( cpu_family() == 6 || cpu_family() == 15 ) { | |
384 if( FLAG_IS_DEFAULT(UseAddressNop) ) { | |
385 // Use it on all Intel cpus starting from PentiumPro | |
386 UseAddressNop = true; | |
387 } | |
388 } | |
389 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { | |
390 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus | |
391 } | |
392 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { | |
393 if( supports_sse3() ) { | |
394 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus | |
395 } else { | |
396 UseXmmRegToRegMoveAll = false; | |
397 } | |
398 } | |
399 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus | |
400 #ifdef COMPILER2 | |
401 if( FLAG_IS_DEFAULT(MaxLoopPad) ) { | |
402 // For new Intel cpus do the next optimization: | |
403 // don't align the beginning of a loop if there are enough instructions | |
404 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp) | |
405 // in current fetch line (OptoLoopAlignment) or the padding | |
406 // is big (> MaxLoopPad). | |
407 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of | |
408 // generated NOP instructions. 11 is the largest size of one | |
409 // address NOP instruction '0F 1F' (see Assembler::nop(i)). | |
410 MaxLoopPad = 11; | |
411 } | |
412 #endif // COMPILER2 | |
413 if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) { | |
414 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus | |
415 } | |
416 if( supports_sse4_2() && supports_ht() ) { // Newest Intel cpus | |
417 if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) { | |
418 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus | |
419 } | |
420 } | |
681 | 421 if( supports_sse4_2() && UseSSE >= 4 ) { |
422 if( FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { | |
423 UseSSE42Intrinsics = true; | |
424 } | |
425 } | |
585 | 426 } |
427 } | |
428 | |
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429 // Use population count instruction if available. |
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430 if (supports_popcnt()) { |
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431 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
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432 UsePopCountInstruction = true; |
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433 } |
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434 } |
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435 |
585 | 436 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value"); |
437 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value"); | |
438 | |
439 // set valid Prefetch instruction | |
440 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0; | |
441 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3; | |
442 if( ReadPrefetchInstr == 3 && !supports_3dnow() ) ReadPrefetchInstr = 0; | |
443 if( !supports_sse() && supports_3dnow() ) ReadPrefetchInstr = 3; | |
444 | |
445 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0; | |
446 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3; | |
447 if( AllocatePrefetchInstr == 3 && !supports_3dnow() ) AllocatePrefetchInstr=0; | |
448 if( !supports_sse() && supports_3dnow() ) AllocatePrefetchInstr = 3; | |
449 | |
450 // Allocation prefetch settings | |
451 intx cache_line_size = L1_data_cache_line_size(); | |
452 if( cache_line_size > AllocatePrefetchStepSize ) | |
453 AllocatePrefetchStepSize = cache_line_size; | |
454 if( FLAG_IS_DEFAULT(AllocatePrefetchLines) ) | |
455 AllocatePrefetchLines = 3; // Optimistic value | |
456 assert(AllocatePrefetchLines > 0, "invalid value"); | |
457 if( AllocatePrefetchLines < 1 ) // set valid value in product VM | |
458 AllocatePrefetchLines = 1; // Conservative value | |
459 | |
460 AllocatePrefetchDistance = allocate_prefetch_distance(); | |
461 AllocatePrefetchStyle = allocate_prefetch_style(); | |
462 | |
463 if( AllocatePrefetchStyle == 2 && is_intel() && | |
464 cpu_family() == 6 && supports_sse3() ) { // watermark prefetching on Core | |
465 #ifdef _LP64 | |
466 AllocatePrefetchDistance = 384; | |
467 #else | |
468 AllocatePrefetchDistance = 320; | |
469 #endif | |
470 } | |
471 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value"); | |
472 | |
473 #ifdef _LP64 | |
474 // Prefetch settings | |
475 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); | |
476 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); | |
477 PrefetchFieldsAhead = prefetch_fields_ahead(); | |
478 #endif | |
479 | |
480 #ifndef PRODUCT | |
481 if (PrintMiscellaneous && Verbose) { | |
482 tty->print_cr("Logical CPUs per core: %u", | |
483 logical_processors_per_package()); | |
484 tty->print_cr("UseSSE=%d",UseSSE); | |
485 tty->print("Allocation: "); | |
486 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow()) { | |
487 tty->print_cr("no prefetching"); | |
488 } else { | |
489 if (UseSSE == 0 && supports_3dnow()) { | |
490 tty->print("PREFETCHW"); | |
491 } else if (UseSSE >= 1) { | |
492 if (AllocatePrefetchInstr == 0) { | |
493 tty->print("PREFETCHNTA"); | |
494 } else if (AllocatePrefetchInstr == 1) { | |
495 tty->print("PREFETCHT0"); | |
496 } else if (AllocatePrefetchInstr == 2) { | |
497 tty->print("PREFETCHT2"); | |
498 } else if (AllocatePrefetchInstr == 3) { | |
499 tty->print("PREFETCHW"); | |
500 } | |
501 } | |
502 if (AllocatePrefetchLines > 1) { | |
503 tty->print_cr(" %d, %d lines with step %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize); | |
504 } else { | |
505 tty->print_cr(" %d, one line", AllocatePrefetchDistance); | |
506 } | |
507 } | |
508 | |
509 if (PrefetchCopyIntervalInBytes > 0) { | |
510 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes); | |
511 } | |
512 if (PrefetchScanIntervalInBytes > 0) { | |
513 tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes); | |
514 } | |
515 if (PrefetchFieldsAhead > 0) { | |
516 tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead); | |
517 } | |
518 } | |
519 #endif // !PRODUCT | |
520 } | |
521 | |
522 void VM_Version::initialize() { | |
523 ResourceMark rm; | |
524 // Making this stub must be FIRST use of assembler | |
525 | |
526 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size); | |
527 if (stub_blob == NULL) { | |
528 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub"); | |
529 } | |
530 CodeBuffer c(stub_blob->instructions_begin(), | |
531 stub_blob->instructions_size()); | |
532 VM_Version_StubGenerator g(&c); | |
533 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t, | |
534 g.generate_getPsrInfo()); | |
535 | |
536 get_processor_features(); | |
537 } |