Mercurial > hg > truffle
annotate src/share/vm/c1/c1_LinearScan.cpp @ 14257:f7eeaff95a25
8029464: assert(ft == ttkp->cast_to_ptr_type(jtkp->ptr()) || ft->isa_narrowoop()
Summary: Fix the assert check for narrow klass pointer.
Reviewed-by: twisti, kvn
author | roland |
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date | Mon, 13 Jan 2014 16:16:25 -0800 |
parents | de6a9e811145 |
children | 4ca6dc0799b6 15766b73dc1d |
rev | line source |
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0 | 1 /* |
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2 * Copyright (c) 2005, 2013, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
26 #include "c1/c1_CFGPrinter.hpp" | |
27 #include "c1/c1_CodeStubs.hpp" | |
28 #include "c1/c1_Compilation.hpp" | |
29 #include "c1/c1_FrameMap.hpp" | |
30 #include "c1/c1_IR.hpp" | |
31 #include "c1/c1_LIRGenerator.hpp" | |
32 #include "c1/c1_LinearScan.hpp" | |
33 #include "c1/c1_ValueStack.hpp" | |
34 #include "utilities/bitMap.inline.hpp" | |
35 #ifdef TARGET_ARCH_x86 | |
36 # include "vmreg_x86.inline.hpp" | |
37 #endif | |
38 #ifdef TARGET_ARCH_sparc | |
39 # include "vmreg_sparc.inline.hpp" | |
40 #endif | |
41 #ifdef TARGET_ARCH_zero | |
42 # include "vmreg_zero.inline.hpp" | |
43 #endif | |
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44 #ifdef TARGET_ARCH_arm |
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45 # include "vmreg_arm.inline.hpp" |
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46 #endif |
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47 #ifdef TARGET_ARCH_ppc |
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48 # include "vmreg_ppc.inline.hpp" |
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49 #endif |
0 | 50 |
51 | |
52 #ifndef PRODUCT | |
53 | |
54 static LinearScanStatistic _stat_before_alloc; | |
55 static LinearScanStatistic _stat_after_asign; | |
56 static LinearScanStatistic _stat_final; | |
57 | |
58 static LinearScanTimers _total_timer; | |
59 | |
60 // helper macro for short definition of timer | |
61 #define TIME_LINEAR_SCAN(timer_name) TraceTime _block_timer("", _total_timer.timer(LinearScanTimers::timer_name), TimeLinearScan || TimeEachLinearScan, Verbose); | |
62 | |
63 // helper macro for short definition of trace-output inside code | |
64 #define TRACE_LINEAR_SCAN(level, code) \ | |
65 if (TraceLinearScanLevel >= level) { \ | |
66 code; \ | |
67 } | |
68 | |
69 #else | |
70 | |
71 #define TIME_LINEAR_SCAN(timer_name) | |
72 #define TRACE_LINEAR_SCAN(level, code) | |
73 | |
74 #endif | |
75 | |
76 // Map BasicType to spill size in 32-bit words, matching VMReg's notion of words | |
77 #ifdef _LP64 | |
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78 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 2, 2, 0, 2, 1, 2, 1, -1}; |
0 | 79 #else |
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80 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 1, 1, 0, 1, -1, 1, 1, -1}; |
0 | 81 #endif |
82 | |
83 | |
84 // Implementation of LinearScan | |
85 | |
86 LinearScan::LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map) | |
87 : _compilation(ir->compilation()) | |
88 , _ir(ir) | |
89 , _gen(gen) | |
90 , _frame_map(frame_map) | |
91 , _num_virtual_regs(gen->max_virtual_register_number()) | |
92 , _has_fpu_registers(false) | |
93 , _num_calls(-1) | |
94 , _max_spills(0) | |
95 , _unused_spill_slot(-1) | |
96 , _intervals(0) // initialized later with correct length | |
97 , _new_intervals_from_allocation(new IntervalList()) | |
98 , _sorted_intervals(NULL) | |
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99 , _needs_full_resort(false) |
0 | 100 , _lir_ops(0) // initialized later with correct length |
101 , _block_of_op(0) // initialized later with correct length | |
102 , _has_info(0) | |
103 , _has_call(0) | |
104 , _scope_value_cache(0) // initialized later with correct length | |
105 , _interval_in_loop(0, 0) // initialized later with correct length | |
106 , _cached_blocks(*ir->linear_scan_order()) | |
304 | 107 #ifdef X86 |
0 | 108 , _fpu_stack_allocator(NULL) |
109 #endif | |
110 { | |
111 assert(this->ir() != NULL, "check if valid"); | |
112 assert(this->compilation() != NULL, "check if valid"); | |
113 assert(this->gen() != NULL, "check if valid"); | |
114 assert(this->frame_map() != NULL, "check if valid"); | |
115 } | |
116 | |
117 | |
118 // ********** functions for converting LIR-Operands to register numbers | |
119 // | |
120 // Emulate a flat register file comprising physical integer registers, | |
121 // physical floating-point registers and virtual registers, in that order. | |
122 // Virtual registers already have appropriate numbers, since V0 is | |
123 // the number of physical registers. | |
124 // Returns -1 for hi word if opr is a single word operand. | |
125 // | |
126 // Note: the inverse operation (calculating an operand for register numbers) | |
127 // is done in calc_operand_for_interval() | |
128 | |
129 int LinearScan::reg_num(LIR_Opr opr) { | |
130 assert(opr->is_register(), "should not call this otherwise"); | |
131 | |
132 if (opr->is_virtual_register()) { | |
133 assert(opr->vreg_number() >= nof_regs, "found a virtual register with a fixed-register number"); | |
134 return opr->vreg_number(); | |
135 } else if (opr->is_single_cpu()) { | |
136 return opr->cpu_regnr(); | |
137 } else if (opr->is_double_cpu()) { | |
138 return opr->cpu_regnrLo(); | |
304 | 139 #ifdef X86 |
0 | 140 } else if (opr->is_single_xmm()) { |
141 return opr->fpu_regnr() + pd_first_xmm_reg; | |
142 } else if (opr->is_double_xmm()) { | |
143 return opr->fpu_regnrLo() + pd_first_xmm_reg; | |
144 #endif | |
145 } else if (opr->is_single_fpu()) { | |
146 return opr->fpu_regnr() + pd_first_fpu_reg; | |
147 } else if (opr->is_double_fpu()) { | |
148 return opr->fpu_regnrLo() + pd_first_fpu_reg; | |
149 } else { | |
150 ShouldNotReachHere(); | |
304 | 151 return -1; |
0 | 152 } |
153 } | |
154 | |
155 int LinearScan::reg_numHi(LIR_Opr opr) { | |
156 assert(opr->is_register(), "should not call this otherwise"); | |
157 | |
158 if (opr->is_virtual_register()) { | |
159 return -1; | |
160 } else if (opr->is_single_cpu()) { | |
161 return -1; | |
162 } else if (opr->is_double_cpu()) { | |
163 return opr->cpu_regnrHi(); | |
304 | 164 #ifdef X86 |
0 | 165 } else if (opr->is_single_xmm()) { |
166 return -1; | |
167 } else if (opr->is_double_xmm()) { | |
168 return -1; | |
169 #endif | |
170 } else if (opr->is_single_fpu()) { | |
171 return -1; | |
172 } else if (opr->is_double_fpu()) { | |
173 return opr->fpu_regnrHi() + pd_first_fpu_reg; | |
174 } else { | |
175 ShouldNotReachHere(); | |
304 | 176 return -1; |
0 | 177 } |
178 } | |
179 | |
180 | |
181 // ********** functions for classification of intervals | |
182 | |
183 bool LinearScan::is_precolored_interval(const Interval* i) { | |
184 return i->reg_num() < LinearScan::nof_regs; | |
185 } | |
186 | |
187 bool LinearScan::is_virtual_interval(const Interval* i) { | |
188 return i->reg_num() >= LIR_OprDesc::vreg_base; | |
189 } | |
190 | |
191 bool LinearScan::is_precolored_cpu_interval(const Interval* i) { | |
192 return i->reg_num() < LinearScan::nof_cpu_regs; | |
193 } | |
194 | |
195 bool LinearScan::is_virtual_cpu_interval(const Interval* i) { | |
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196 #if defined(__SOFTFP__) || defined(E500V2) |
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197 return i->reg_num() >= LIR_OprDesc::vreg_base; |
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198 #else |
0 | 199 return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() != T_FLOAT && i->type() != T_DOUBLE); |
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200 #endif // __SOFTFP__ or E500V2 |
0 | 201 } |
202 | |
203 bool LinearScan::is_precolored_fpu_interval(const Interval* i) { | |
204 return i->reg_num() >= LinearScan::nof_cpu_regs && i->reg_num() < LinearScan::nof_regs; | |
205 } | |
206 | |
207 bool LinearScan::is_virtual_fpu_interval(const Interval* i) { | |
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208 #if defined(__SOFTFP__) || defined(E500V2) |
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209 return false; |
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210 #else |
0 | 211 return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE); |
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212 #endif // __SOFTFP__ or E500V2 |
0 | 213 } |
214 | |
215 bool LinearScan::is_in_fpu_register(const Interval* i) { | |
216 // fixed intervals not needed for FPU stack allocation | |
217 return i->reg_num() >= nof_regs && pd_first_fpu_reg <= i->assigned_reg() && i->assigned_reg() <= pd_last_fpu_reg; | |
218 } | |
219 | |
220 bool LinearScan::is_oop_interval(const Interval* i) { | |
221 // fixed intervals never contain oops | |
222 return i->reg_num() >= nof_regs && i->type() == T_OBJECT; | |
223 } | |
224 | |
225 | |
226 // ********** General helper functions | |
227 | |
228 // compute next unused stack index that can be used for spilling | |
229 int LinearScan::allocate_spill_slot(bool double_word) { | |
230 int spill_slot; | |
231 if (double_word) { | |
232 if ((_max_spills & 1) == 1) { | |
233 // alignment of double-word values | |
234 // the hole because of the alignment is filled with the next single-word value | |
235 assert(_unused_spill_slot == -1, "wasting a spill slot"); | |
236 _unused_spill_slot = _max_spills; | |
237 _max_spills++; | |
238 } | |
239 spill_slot = _max_spills; | |
240 _max_spills += 2; | |
241 | |
242 } else if (_unused_spill_slot != -1) { | |
243 // re-use hole that was the result of a previous double-word alignment | |
244 spill_slot = _unused_spill_slot; | |
245 _unused_spill_slot = -1; | |
246 | |
247 } else { | |
248 spill_slot = _max_spills; | |
249 _max_spills++; | |
250 } | |
251 | |
252 int result = spill_slot + LinearScan::nof_regs + frame_map()->argcount(); | |
253 | |
254 // the class OopMapValue uses only 11 bits for storing the name of the | |
255 // oop location. So a stack slot bigger than 2^11 leads to an overflow | |
256 // that is not reported in product builds. Prevent this by checking the | |
257 // spill slot here (altough this value and the later used location name | |
258 // are slightly different) | |
259 if (result > 2000) { | |
260 bailout("too many stack slots used"); | |
261 } | |
262 | |
263 return result; | |
264 } | |
265 | |
266 void LinearScan::assign_spill_slot(Interval* it) { | |
267 // assign the canonical spill slot of the parent (if a part of the interval | |
268 // is already spilled) or allocate a new spill slot | |
269 if (it->canonical_spill_slot() >= 0) { | |
270 it->assign_reg(it->canonical_spill_slot()); | |
271 } else { | |
272 int spill = allocate_spill_slot(type2spill_size[it->type()] == 2); | |
273 it->set_canonical_spill_slot(spill); | |
274 it->assign_reg(spill); | |
275 } | |
276 } | |
277 | |
278 void LinearScan::propagate_spill_slots() { | |
279 if (!frame_map()->finalize_frame(max_spills())) { | |
280 bailout("frame too large"); | |
281 } | |
282 } | |
283 | |
284 // create a new interval with a predefined reg_num | |
285 // (only used for parent intervals that are created during the building phase) | |
286 Interval* LinearScan::create_interval(int reg_num) { | |
287 assert(_intervals.at(reg_num) == NULL, "overwriting exisiting interval"); | |
288 | |
289 Interval* interval = new Interval(reg_num); | |
290 _intervals.at_put(reg_num, interval); | |
291 | |
292 // assign register number for precolored intervals | |
293 if (reg_num < LIR_OprDesc::vreg_base) { | |
294 interval->assign_reg(reg_num); | |
295 } | |
296 return interval; | |
297 } | |
298 | |
299 // assign a new reg_num to the interval and append it to the list of intervals | |
300 // (only used for child intervals that are created during register allocation) | |
301 void LinearScan::append_interval(Interval* it) { | |
302 it->set_reg_num(_intervals.length()); | |
303 _intervals.append(it); | |
304 _new_intervals_from_allocation->append(it); | |
305 } | |
306 | |
307 // copy the vreg-flags if an interval is split | |
308 void LinearScan::copy_register_flags(Interval* from, Interval* to) { | |
309 if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::byte_reg)) { | |
310 gen()->set_vreg_flag(to->reg_num(), LIRGenerator::byte_reg); | |
311 } | |
312 if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::callee_saved)) { | |
313 gen()->set_vreg_flag(to->reg_num(), LIRGenerator::callee_saved); | |
314 } | |
315 | |
316 // Note: do not copy the must_start_in_memory flag because it is not necessary for child | |
317 // intervals (only the very beginning of the interval must be in memory) | |
318 } | |
319 | |
320 | |
321 // ********** spill move optimization | |
322 // eliminate moves from register to stack if stack slot is known to be correct | |
323 | |
324 // called during building of intervals | |
325 void LinearScan::change_spill_definition_pos(Interval* interval, int def_pos) { | |
326 assert(interval->is_split_parent(), "can only be called for split parents"); | |
327 | |
328 switch (interval->spill_state()) { | |
329 case noDefinitionFound: | |
330 assert(interval->spill_definition_pos() == -1, "must no be set before"); | |
331 interval->set_spill_definition_pos(def_pos); | |
332 interval->set_spill_state(oneDefinitionFound); | |
333 break; | |
334 | |
335 case oneDefinitionFound: | |
336 assert(def_pos <= interval->spill_definition_pos(), "positions are processed in reverse order when intervals are created"); | |
337 if (def_pos < interval->spill_definition_pos() - 2) { | |
338 // second definition found, so no spill optimization possible for this interval | |
339 interval->set_spill_state(noOptimization); | |
340 } else { | |
341 // two consecutive definitions (because of two-operand LIR form) | |
342 assert(block_of_op_with_id(def_pos) == block_of_op_with_id(interval->spill_definition_pos()), "block must be equal"); | |
343 } | |
344 break; | |
345 | |
346 case noOptimization: | |
347 // nothing to do | |
348 break; | |
349 | |
350 default: | |
351 assert(false, "other states not allowed at this time"); | |
352 } | |
353 } | |
354 | |
355 // called during register allocation | |
356 void LinearScan::change_spill_state(Interval* interval, int spill_pos) { | |
357 switch (interval->spill_state()) { | |
358 case oneDefinitionFound: { | |
359 int def_loop_depth = block_of_op_with_id(interval->spill_definition_pos())->loop_depth(); | |
360 int spill_loop_depth = block_of_op_with_id(spill_pos)->loop_depth(); | |
361 | |
362 if (def_loop_depth < spill_loop_depth) { | |
363 // the loop depth of the spilling position is higher then the loop depth | |
364 // at the definition of the interval -> move write to memory out of loop | |
365 // by storing at definitin of the interval | |
366 interval->set_spill_state(storeAtDefinition); | |
367 } else { | |
368 // the interval is currently spilled only once, so for now there is no | |
369 // reason to store the interval at the definition | |
370 interval->set_spill_state(oneMoveInserted); | |
371 } | |
372 break; | |
373 } | |
374 | |
375 case oneMoveInserted: { | |
376 // the interval is spilled more then once, so it is better to store it to | |
377 // memory at the definition | |
378 interval->set_spill_state(storeAtDefinition); | |
379 break; | |
380 } | |
381 | |
382 case storeAtDefinition: | |
383 case startInMemory: | |
384 case noOptimization: | |
385 case noDefinitionFound: | |
386 // nothing to do | |
387 break; | |
388 | |
389 default: | |
390 assert(false, "other states not allowed at this time"); | |
391 } | |
392 } | |
393 | |
394 | |
395 bool LinearScan::must_store_at_definition(const Interval* i) { | |
396 return i->is_split_parent() && i->spill_state() == storeAtDefinition; | |
397 } | |
398 | |
399 // called once before asignment of register numbers | |
400 void LinearScan::eliminate_spill_moves() { | |
401 TIME_LINEAR_SCAN(timer_eliminate_spill_moves); | |
402 TRACE_LINEAR_SCAN(3, tty->print_cr("***** Eliminating unnecessary spill moves")); | |
403 | |
404 // collect all intervals that must be stored after their definion. | |
405 // the list is sorted by Interval::spill_definition_pos | |
406 Interval* interval; | |
407 Interval* temp_list; | |
408 create_unhandled_lists(&interval, &temp_list, must_store_at_definition, NULL); | |
409 | |
410 #ifdef ASSERT | |
411 Interval* prev = NULL; | |
412 Interval* temp = interval; | |
413 while (temp != Interval::end()) { | |
414 assert(temp->spill_definition_pos() > 0, "invalid spill definition pos"); | |
415 if (prev != NULL) { | |
416 assert(temp->from() >= prev->from(), "intervals not sorted"); | |
417 assert(temp->spill_definition_pos() >= prev->spill_definition_pos(), "when intervals are sorted by from, then they must also be sorted by spill_definition_pos"); | |
418 } | |
419 | |
420 assert(temp->canonical_spill_slot() >= LinearScan::nof_regs, "interval has no spill slot assigned"); | |
421 assert(temp->spill_definition_pos() >= temp->from(), "invalid order"); | |
422 assert(temp->spill_definition_pos() <= temp->from() + 2, "only intervals defined once at their start-pos can be optimized"); | |
423 | |
424 TRACE_LINEAR_SCAN(4, tty->print_cr("interval %d (from %d to %d) must be stored at %d", temp->reg_num(), temp->from(), temp->to(), temp->spill_definition_pos())); | |
425 | |
426 temp = temp->next(); | |
427 } | |
428 #endif | |
429 | |
430 LIR_InsertionBuffer insertion_buffer; | |
431 int num_blocks = block_count(); | |
432 for (int i = 0; i < num_blocks; i++) { | |
433 BlockBegin* block = block_at(i); | |
434 LIR_OpList* instructions = block->lir()->instructions_list(); | |
435 int num_inst = instructions->length(); | |
436 bool has_new = false; | |
437 | |
438 // iterate all instructions of the block. skip the first because it is always a label | |
439 for (int j = 1; j < num_inst; j++) { | |
440 LIR_Op* op = instructions->at(j); | |
441 int op_id = op->id(); | |
442 | |
443 if (op_id == -1) { | |
444 // remove move from register to stack if the stack slot is guaranteed to be correct. | |
445 // only moves that have been inserted by LinearScan can be removed. | |
446 assert(op->code() == lir_move, "only moves can have a op_id of -1"); | |
447 assert(op->as_Op1() != NULL, "move must be LIR_Op1"); | |
448 assert(op->as_Op1()->result_opr()->is_virtual(), "LinearScan inserts only moves to virtual registers"); | |
449 | |
450 LIR_Op1* op1 = (LIR_Op1*)op; | |
451 Interval* interval = interval_at(op1->result_opr()->vreg_number()); | |
452 | |
453 if (interval->assigned_reg() >= LinearScan::nof_regs && interval->always_in_memory()) { | |
454 // move target is a stack slot that is always correct, so eliminate instruction | |
455 TRACE_LINEAR_SCAN(4, tty->print_cr("eliminating move from interval %d to %d", op1->in_opr()->vreg_number(), op1->result_opr()->vreg_number())); | |
456 instructions->at_put(j, NULL); // NULL-instructions are deleted by assign_reg_num | |
457 } | |
458 | |
459 } else { | |
460 // insert move from register to stack just after the beginning of the interval | |
461 assert(interval == Interval::end() || interval->spill_definition_pos() >= op_id, "invalid order"); | |
462 assert(interval == Interval::end() || (interval->is_split_parent() && interval->spill_state() == storeAtDefinition), "invalid interval"); | |
463 | |
464 while (interval != Interval::end() && interval->spill_definition_pos() == op_id) { | |
465 if (!has_new) { | |
466 // prepare insertion buffer (appended when all instructions of the block are processed) | |
467 insertion_buffer.init(block->lir()); | |
468 has_new = true; | |
469 } | |
470 | |
471 LIR_Opr from_opr = operand_for_interval(interval); | |
472 LIR_Opr to_opr = canonical_spill_opr(interval); | |
473 assert(from_opr->is_fixed_cpu() || from_opr->is_fixed_fpu(), "from operand must be a register"); | |
474 assert(to_opr->is_stack(), "to operand must be a stack slot"); | |
475 | |
476 insertion_buffer.move(j, from_opr, to_opr); | |
477 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting move after definition of interval %d to stack slot %d at op_id %d", interval->reg_num(), interval->canonical_spill_slot() - LinearScan::nof_regs, op_id)); | |
478 | |
479 interval = interval->next(); | |
480 } | |
481 } | |
482 } // end of instruction iteration | |
483 | |
484 if (has_new) { | |
485 block->lir()->append(&insertion_buffer); | |
486 } | |
487 } // end of block iteration | |
488 | |
489 assert(interval == Interval::end(), "missed an interval"); | |
490 } | |
491 | |
492 | |
493 // ********** Phase 1: number all instructions in all blocks | |
494 // Compute depth-first and linear scan block orders, and number LIR_Op nodes for linear scan. | |
495 | |
496 void LinearScan::number_instructions() { | |
497 { | |
498 // dummy-timer to measure the cost of the timer itself | |
499 // (this time is then subtracted from all other timers to get the real value) | |
500 TIME_LINEAR_SCAN(timer_do_nothing); | |
501 } | |
502 TIME_LINEAR_SCAN(timer_number_instructions); | |
503 | |
504 // Assign IDs to LIR nodes and build a mapping, lir_ops, from ID to LIR_Op node. | |
505 int num_blocks = block_count(); | |
506 int num_instructions = 0; | |
507 int i; | |
508 for (i = 0; i < num_blocks; i++) { | |
509 num_instructions += block_at(i)->lir()->instructions_list()->length(); | |
510 } | |
511 | |
512 // initialize with correct length | |
513 _lir_ops = LIR_OpArray(num_instructions); | |
514 _block_of_op = BlockBeginArray(num_instructions); | |
515 | |
516 int op_id = 0; | |
517 int idx = 0; | |
518 | |
519 for (i = 0; i < num_blocks; i++) { | |
520 BlockBegin* block = block_at(i); | |
521 block->set_first_lir_instruction_id(op_id); | |
522 LIR_OpList* instructions = block->lir()->instructions_list(); | |
523 | |
524 int num_inst = instructions->length(); | |
525 for (int j = 0; j < num_inst; j++) { | |
526 LIR_Op* op = instructions->at(j); | |
527 op->set_id(op_id); | |
528 | |
529 _lir_ops.at_put(idx, op); | |
530 _block_of_op.at_put(idx, block); | |
531 assert(lir_op_with_id(op_id) == op, "must match"); | |
532 | |
533 idx++; | |
534 op_id += 2; // numbering of lir_ops by two | |
535 } | |
536 block->set_last_lir_instruction_id(op_id - 2); | |
537 } | |
538 assert(idx == num_instructions, "must match"); | |
539 assert(idx * 2 == op_id, "must match"); | |
540 | |
541 _has_call = BitMap(num_instructions); _has_call.clear(); | |
542 _has_info = BitMap(num_instructions); _has_info.clear(); | |
543 } | |
544 | |
545 | |
546 // ********** Phase 2: compute local live sets separately for each block | |
547 // (sets live_gen and live_kill for each block) | |
548 | |
549 void LinearScan::set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill) { | |
550 LIR_Opr opr = value->operand(); | |
551 Constant* con = value->as_Constant(); | |
552 | |
553 // check some asumptions about debug information | |
554 assert(!value->type()->is_illegal(), "if this local is used by the interpreter it shouldn't be of indeterminate type"); | |
555 assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands"); | |
556 assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands"); | |
557 | |
558 if ((con == NULL || con->is_pinned()) && opr->is_register()) { | |
559 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); | |
560 int reg = opr->vreg_number(); | |
561 if (!live_kill.at(reg)) { | |
562 live_gen.set_bit(reg); | |
563 TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for value %c%d, LIR op_id %d, register number %d", value->type()->tchar(), value->id(), op->id(), reg)); | |
564 } | |
565 } | |
566 } | |
567 | |
568 | |
569 void LinearScan::compute_local_live_sets() { | |
570 TIME_LINEAR_SCAN(timer_compute_local_live_sets); | |
571 | |
572 int num_blocks = block_count(); | |
573 int live_size = live_set_size(); | |
574 bool local_has_fpu_registers = false; | |
575 int local_num_calls = 0; | |
576 LIR_OpVisitState visitor; | |
577 | |
578 BitMap2D local_interval_in_loop = BitMap2D(_num_virtual_regs, num_loops()); | |
579 local_interval_in_loop.clear(); | |
580 | |
581 // iterate all blocks | |
582 for (int i = 0; i < num_blocks; i++) { | |
583 BlockBegin* block = block_at(i); | |
584 | |
585 BitMap live_gen(live_size); live_gen.clear(); | |
586 BitMap live_kill(live_size); live_kill.clear(); | |
587 | |
588 if (block->is_set(BlockBegin::exception_entry_flag)) { | |
589 // Phi functions at the begin of an exception handler are | |
590 // implicitly defined (= killed) at the beginning of the block. | |
591 for_each_phi_fun(block, phi, | |
592 live_kill.set_bit(phi->operand()->vreg_number()) | |
593 ); | |
594 } | |
595 | |
596 LIR_OpList* instructions = block->lir()->instructions_list(); | |
597 int num_inst = instructions->length(); | |
598 | |
599 // iterate all instructions of the block. skip the first because it is always a label | |
600 assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label"); | |
601 for (int j = 1; j < num_inst; j++) { | |
602 LIR_Op* op = instructions->at(j); | |
603 | |
604 // visit operation to collect all operands | |
605 visitor.visit(op); | |
606 | |
607 if (visitor.has_call()) { | |
608 _has_call.set_bit(op->id() >> 1); | |
609 local_num_calls++; | |
610 } | |
611 if (visitor.info_count() > 0) { | |
612 _has_info.set_bit(op->id() >> 1); | |
613 } | |
614 | |
615 // iterate input operands of instruction | |
616 int k, n, reg; | |
617 n = visitor.opr_count(LIR_OpVisitState::inputMode); | |
618 for (k = 0; k < n; k++) { | |
619 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k); | |
620 assert(opr->is_register(), "visitor should only return register operands"); | |
621 | |
622 if (opr->is_virtual_register()) { | |
623 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); | |
624 reg = opr->vreg_number(); | |
625 if (!live_kill.at(reg)) { | |
626 live_gen.set_bit(reg); | |
627 TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for register %d at instruction %d", reg, op->id())); | |
628 } | |
629 if (block->loop_index() >= 0) { | |
630 local_interval_in_loop.set_bit(reg, block->loop_index()); | |
631 } | |
632 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu(); | |
633 } | |
634 | |
635 #ifdef ASSERT | |
636 // fixed intervals are never live at block boundaries, so | |
637 // they need not be processed in live sets. | |
638 // this is checked by these assertions to be sure about it. | |
639 // the entry block may have incoming values in registers, which is ok. | |
640 if (!opr->is_virtual_register() && block != ir()->start()) { | |
641 reg = reg_num(opr); | |
642 if (is_processed_reg_num(reg)) { | |
643 assert(live_kill.at(reg), "using fixed register that is not defined in this block"); | |
644 } | |
645 reg = reg_numHi(opr); | |
646 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { | |
647 assert(live_kill.at(reg), "using fixed register that is not defined in this block"); | |
648 } | |
649 } | |
650 #endif | |
651 } | |
652 | |
653 // Add uses of live locals from interpreter's point of view for proper debug information generation | |
654 n = visitor.info_count(); | |
655 for (k = 0; k < n; k++) { | |
656 CodeEmitInfo* info = visitor.info_at(k); | |
657 ValueStack* stack = info->stack(); | |
658 for_each_state_value(stack, value, | |
659 set_live_gen_kill(value, op, live_gen, live_kill) | |
660 ); | |
661 } | |
662 | |
663 // iterate temp operands of instruction | |
664 n = visitor.opr_count(LIR_OpVisitState::tempMode); | |
665 for (k = 0; k < n; k++) { | |
666 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k); | |
667 assert(opr->is_register(), "visitor should only return register operands"); | |
668 | |
669 if (opr->is_virtual_register()) { | |
670 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); | |
671 reg = opr->vreg_number(); | |
672 live_kill.set_bit(reg); | |
673 if (block->loop_index() >= 0) { | |
674 local_interval_in_loop.set_bit(reg, block->loop_index()); | |
675 } | |
676 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu(); | |
677 } | |
678 | |
679 #ifdef ASSERT | |
680 // fixed intervals are never live at block boundaries, so | |
681 // they need not be processed in live sets | |
682 // process them only in debug mode so that this can be checked | |
683 if (!opr->is_virtual_register()) { | |
684 reg = reg_num(opr); | |
685 if (is_processed_reg_num(reg)) { | |
686 live_kill.set_bit(reg_num(opr)); | |
687 } | |
688 reg = reg_numHi(opr); | |
689 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { | |
690 live_kill.set_bit(reg); | |
691 } | |
692 } | |
693 #endif | |
694 } | |
695 | |
696 // iterate output operands of instruction | |
697 n = visitor.opr_count(LIR_OpVisitState::outputMode); | |
698 for (k = 0; k < n; k++) { | |
699 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k); | |
700 assert(opr->is_register(), "visitor should only return register operands"); | |
701 | |
702 if (opr->is_virtual_register()) { | |
703 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); | |
704 reg = opr->vreg_number(); | |
705 live_kill.set_bit(reg); | |
706 if (block->loop_index() >= 0) { | |
707 local_interval_in_loop.set_bit(reg, block->loop_index()); | |
708 } | |
709 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu(); | |
710 } | |
711 | |
712 #ifdef ASSERT | |
713 // fixed intervals are never live at block boundaries, so | |
714 // they need not be processed in live sets | |
715 // process them only in debug mode so that this can be checked | |
716 if (!opr->is_virtual_register()) { | |
717 reg = reg_num(opr); | |
718 if (is_processed_reg_num(reg)) { | |
719 live_kill.set_bit(reg_num(opr)); | |
720 } | |
721 reg = reg_numHi(opr); | |
722 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { | |
723 live_kill.set_bit(reg); | |
724 } | |
725 } | |
726 #endif | |
727 } | |
728 } // end of instruction iteration | |
729 | |
730 block->set_live_gen (live_gen); | |
731 block->set_live_kill(live_kill); | |
732 block->set_live_in (BitMap(live_size)); block->live_in().clear(); | |
733 block->set_live_out (BitMap(live_size)); block->live_out().clear(); | |
734 | |
735 TRACE_LINEAR_SCAN(4, tty->print("live_gen B%d ", block->block_id()); print_bitmap(block->live_gen())); | |
736 TRACE_LINEAR_SCAN(4, tty->print("live_kill B%d ", block->block_id()); print_bitmap(block->live_kill())); | |
737 } // end of block iteration | |
738 | |
739 // propagate local calculated information into LinearScan object | |
740 _has_fpu_registers = local_has_fpu_registers; | |
741 compilation()->set_has_fpu_code(local_has_fpu_registers); | |
742 | |
743 _num_calls = local_num_calls; | |
744 _interval_in_loop = local_interval_in_loop; | |
745 } | |
746 | |
747 | |
748 // ********** Phase 3: perform a backward dataflow analysis to compute global live sets | |
749 // (sets live_in and live_out for each block) | |
750 | |
751 void LinearScan::compute_global_live_sets() { | |
752 TIME_LINEAR_SCAN(timer_compute_global_live_sets); | |
753 | |
754 int num_blocks = block_count(); | |
755 bool change_occurred; | |
756 bool change_occurred_in_block; | |
757 int iteration_count = 0; | |
758 BitMap live_out(live_set_size()); live_out.clear(); // scratch set for calculations | |
759 | |
760 // Perform a backward dataflow analysis to compute live_out and live_in for each block. | |
761 // The loop is executed until a fixpoint is reached (no changes in an iteration) | |
762 // Exception handlers must be processed because not all live values are | |
763 // present in the state array, e.g. because of global value numbering | |
764 do { | |
765 change_occurred = false; | |
766 | |
767 // iterate all blocks in reverse order | |
768 for (int i = num_blocks - 1; i >= 0; i--) { | |
769 BlockBegin* block = block_at(i); | |
770 | |
771 change_occurred_in_block = false; | |
772 | |
773 // live_out(block) is the union of live_in(sux), for successors sux of block | |
774 int n = block->number_of_sux(); | |
775 int e = block->number_of_exception_handlers(); | |
776 if (n + e > 0) { | |
777 // block has successors | |
778 if (n > 0) { | |
779 live_out.set_from(block->sux_at(0)->live_in()); | |
780 for (int j = 1; j < n; j++) { | |
781 live_out.set_union(block->sux_at(j)->live_in()); | |
782 } | |
783 } else { | |
784 live_out.clear(); | |
785 } | |
786 for (int j = 0; j < e; j++) { | |
787 live_out.set_union(block->exception_handler_at(j)->live_in()); | |
788 } | |
789 | |
790 if (!block->live_out().is_same(live_out)) { | |
791 // A change occurred. Swap the old and new live out sets to avoid copying. | |
792 BitMap temp = block->live_out(); | |
793 block->set_live_out(live_out); | |
794 live_out = temp; | |
795 | |
796 change_occurred = true; | |
797 change_occurred_in_block = true; | |
798 } | |
799 } | |
800 | |
801 if (iteration_count == 0 || change_occurred_in_block) { | |
802 // live_in(block) is the union of live_gen(block) with (live_out(block) & !live_kill(block)) | |
803 // note: live_in has to be computed only in first iteration or if live_out has changed! | |
804 BitMap live_in = block->live_in(); | |
805 live_in.set_from(block->live_out()); | |
806 live_in.set_difference(block->live_kill()); | |
807 live_in.set_union(block->live_gen()); | |
808 } | |
809 | |
810 #ifndef PRODUCT | |
811 if (TraceLinearScanLevel >= 4) { | |
812 char c = ' '; | |
813 if (iteration_count == 0 || change_occurred_in_block) { | |
814 c = '*'; | |
815 } | |
816 tty->print("(%d) live_in%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_in()); | |
817 tty->print("(%d) live_out%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_out()); | |
818 } | |
819 #endif | |
820 } | |
821 iteration_count++; | |
822 | |
823 if (change_occurred && iteration_count > 50) { | |
824 BAILOUT("too many iterations in compute_global_live_sets"); | |
825 } | |
826 } while (change_occurred); | |
827 | |
828 | |
829 #ifdef ASSERT | |
830 // check that fixed intervals are not live at block boundaries | |
831 // (live set must be empty at fixed intervals) | |
832 for (int i = 0; i < num_blocks; i++) { | |
833 BlockBegin* block = block_at(i); | |
834 for (int j = 0; j < LIR_OprDesc::vreg_base; j++) { | |
835 assert(block->live_in().at(j) == false, "live_in set of fixed register must be empty"); | |
836 assert(block->live_out().at(j) == false, "live_out set of fixed register must be empty"); | |
837 assert(block->live_gen().at(j) == false, "live_gen set of fixed register must be empty"); | |
838 } | |
839 } | |
840 #endif | |
841 | |
842 // check that the live_in set of the first block is empty | |
843 BitMap live_in_args(ir()->start()->live_in().size()); | |
844 live_in_args.clear(); | |
845 if (!ir()->start()->live_in().is_same(live_in_args)) { | |
846 #ifdef ASSERT | |
847 tty->print_cr("Error: live_in set of first block must be empty (when this fails, virtual registers are used before they are defined)"); | |
848 tty->print_cr("affected registers:"); | |
849 print_bitmap(ir()->start()->live_in()); | |
850 | |
851 // print some additional information to simplify debugging | |
852 for (unsigned int i = 0; i < ir()->start()->live_in().size(); i++) { | |
853 if (ir()->start()->live_in().at(i)) { | |
854 Instruction* instr = gen()->instruction_for_vreg(i); | |
855 tty->print_cr("* vreg %d (HIR instruction %c%d)", i, instr == NULL ? ' ' : instr->type()->tchar(), instr == NULL ? 0 : instr->id()); | |
856 | |
857 for (int j = 0; j < num_blocks; j++) { | |
858 BlockBegin* block = block_at(j); | |
859 if (block->live_gen().at(i)) { | |
860 tty->print_cr(" used in block B%d", block->block_id()); | |
861 } | |
862 if (block->live_kill().at(i)) { | |
863 tty->print_cr(" defined in block B%d", block->block_id()); | |
864 } | |
865 } | |
866 } | |
867 } | |
868 | |
869 #endif | |
870 // when this fails, virtual registers are used before they are defined. | |
871 assert(false, "live_in set of first block must be empty"); | |
872 // bailout of if this occurs in product mode. | |
873 bailout("live_in set of first block not empty"); | |
874 } | |
875 } | |
876 | |
877 | |
878 // ********** Phase 4: build intervals | |
879 // (fills the list _intervals) | |
880 | |
881 void LinearScan::add_use(Value value, int from, int to, IntervalUseKind use_kind) { | |
882 assert(!value->type()->is_illegal(), "if this value is used by the interpreter it shouldn't be of indeterminate type"); | |
883 LIR_Opr opr = value->operand(); | |
884 Constant* con = value->as_Constant(); | |
885 | |
886 if ((con == NULL || con->is_pinned()) && opr->is_register()) { | |
887 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); | |
888 add_use(opr, from, to, use_kind); | |
889 } | |
890 } | |
891 | |
892 | |
893 void LinearScan::add_def(LIR_Opr opr, int def_pos, IntervalUseKind use_kind) { | |
894 TRACE_LINEAR_SCAN(2, tty->print(" def "); opr->print(tty); tty->print_cr(" def_pos %d (%d)", def_pos, use_kind)); | |
895 assert(opr->is_register(), "should not be called otherwise"); | |
896 | |
897 if (opr->is_virtual_register()) { | |
898 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); | |
899 add_def(opr->vreg_number(), def_pos, use_kind, opr->type_register()); | |
900 | |
901 } else { | |
902 int reg = reg_num(opr); | |
903 if (is_processed_reg_num(reg)) { | |
904 add_def(reg, def_pos, use_kind, opr->type_register()); | |
905 } | |
906 reg = reg_numHi(opr); | |
907 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { | |
908 add_def(reg, def_pos, use_kind, opr->type_register()); | |
909 } | |
910 } | |
911 } | |
912 | |
913 void LinearScan::add_use(LIR_Opr opr, int from, int to, IntervalUseKind use_kind) { | |
914 TRACE_LINEAR_SCAN(2, tty->print(" use "); opr->print(tty); tty->print_cr(" from %d to %d (%d)", from, to, use_kind)); | |
915 assert(opr->is_register(), "should not be called otherwise"); | |
916 | |
917 if (opr->is_virtual_register()) { | |
918 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); | |
919 add_use(opr->vreg_number(), from, to, use_kind, opr->type_register()); | |
920 | |
921 } else { | |
922 int reg = reg_num(opr); | |
923 if (is_processed_reg_num(reg)) { | |
924 add_use(reg, from, to, use_kind, opr->type_register()); | |
925 } | |
926 reg = reg_numHi(opr); | |
927 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { | |
928 add_use(reg, from, to, use_kind, opr->type_register()); | |
929 } | |
930 } | |
931 } | |
932 | |
933 void LinearScan::add_temp(LIR_Opr opr, int temp_pos, IntervalUseKind use_kind) { | |
934 TRACE_LINEAR_SCAN(2, tty->print(" temp "); opr->print(tty); tty->print_cr(" temp_pos %d (%d)", temp_pos, use_kind)); | |
935 assert(opr->is_register(), "should not be called otherwise"); | |
936 | |
937 if (opr->is_virtual_register()) { | |
938 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); | |
939 add_temp(opr->vreg_number(), temp_pos, use_kind, opr->type_register()); | |
940 | |
941 } else { | |
942 int reg = reg_num(opr); | |
943 if (is_processed_reg_num(reg)) { | |
944 add_temp(reg, temp_pos, use_kind, opr->type_register()); | |
945 } | |
946 reg = reg_numHi(opr); | |
947 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { | |
948 add_temp(reg, temp_pos, use_kind, opr->type_register()); | |
949 } | |
950 } | |
951 } | |
952 | |
953 | |
954 void LinearScan::add_def(int reg_num, int def_pos, IntervalUseKind use_kind, BasicType type) { | |
955 Interval* interval = interval_at(reg_num); | |
956 if (interval != NULL) { | |
957 assert(interval->reg_num() == reg_num, "wrong interval"); | |
958 | |
959 if (type != T_ILLEGAL) { | |
960 interval->set_type(type); | |
961 } | |
962 | |
963 Range* r = interval->first(); | |
964 if (r->from() <= def_pos) { | |
965 // Update the starting point (when a range is first created for a use, its | |
966 // start is the beginning of the current block until a def is encountered.) | |
967 r->set_from(def_pos); | |
968 interval->add_use_pos(def_pos, use_kind); | |
969 | |
970 } else { | |
971 // Dead value - make vacuous interval | |
972 // also add use_kind for dead intervals | |
973 interval->add_range(def_pos, def_pos + 1); | |
974 interval->add_use_pos(def_pos, use_kind); | |
975 TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: def of reg %d at %d occurs without use", reg_num, def_pos)); | |
976 } | |
977 | |
978 } else { | |
979 // Dead value - make vacuous interval | |
980 // also add use_kind for dead intervals | |
981 interval = create_interval(reg_num); | |
982 if (type != T_ILLEGAL) { | |
983 interval->set_type(type); | |
984 } | |
985 | |
986 interval->add_range(def_pos, def_pos + 1); | |
987 interval->add_use_pos(def_pos, use_kind); | |
988 TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: dead value %d at %d in live intervals", reg_num, def_pos)); | |
989 } | |
990 | |
991 change_spill_definition_pos(interval, def_pos); | |
992 if (use_kind == noUse && interval->spill_state() <= startInMemory) { | |
993 // detection of method-parameters and roundfp-results | |
994 // TODO: move this directly to position where use-kind is computed | |
995 interval->set_spill_state(startInMemory); | |
996 } | |
997 } | |
998 | |
999 void LinearScan::add_use(int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type) { | |
1000 Interval* interval = interval_at(reg_num); | |
1001 if (interval == NULL) { | |
1002 interval = create_interval(reg_num); | |
1003 } | |
1004 assert(interval->reg_num() == reg_num, "wrong interval"); | |
1005 | |
1006 if (type != T_ILLEGAL) { | |
1007 interval->set_type(type); | |
1008 } | |
1009 | |
1010 interval->add_range(from, to); | |
1011 interval->add_use_pos(to, use_kind); | |
1012 } | |
1013 | |
1014 void LinearScan::add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type) { | |
1015 Interval* interval = interval_at(reg_num); | |
1016 if (interval == NULL) { | |
1017 interval = create_interval(reg_num); | |
1018 } | |
1019 assert(interval->reg_num() == reg_num, "wrong interval"); | |
1020 | |
1021 if (type != T_ILLEGAL) { | |
1022 interval->set_type(type); | |
1023 } | |
1024 | |
1025 interval->add_range(temp_pos, temp_pos + 1); | |
1026 interval->add_use_pos(temp_pos, use_kind); | |
1027 } | |
1028 | |
1029 | |
1030 // the results of this functions are used for optimizing spilling and reloading | |
1031 // if the functions return shouldHaveRegister and the interval is spilled, | |
1032 // it is not reloaded to a register. | |
1033 IntervalUseKind LinearScan::use_kind_of_output_operand(LIR_Op* op, LIR_Opr opr) { | |
1034 if (op->code() == lir_move) { | |
1035 assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1"); | |
1036 LIR_Op1* move = (LIR_Op1*)op; | |
1037 LIR_Opr res = move->result_opr(); | |
1038 bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory); | |
1039 | |
1040 if (result_in_memory) { | |
1041 // Begin of an interval with must_start_in_memory set. | |
1042 // This interval will always get a stack slot first, so return noUse. | |
1043 return noUse; | |
1044 | |
1045 } else if (move->in_opr()->is_stack()) { | |
1046 // method argument (condition must be equal to handle_method_arguments) | |
1047 return noUse; | |
1048 | |
1049 } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) { | |
1050 // Move from register to register | |
1051 if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) { | |
1052 // special handling of phi-function moves inside osr-entry blocks | |
1053 // input operand must have a register instead of output operand (leads to better register allocation) | |
1054 return shouldHaveRegister; | |
1055 } | |
1056 } | |
1057 } | |
1058 | |
1059 if (opr->is_virtual() && | |
1060 gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::must_start_in_memory)) { | |
1061 // result is a stack-slot, so prevent immediate reloading | |
1062 return noUse; | |
1063 } | |
1064 | |
1065 // all other operands require a register | |
1066 return mustHaveRegister; | |
1067 } | |
1068 | |
1069 IntervalUseKind LinearScan::use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr) { | |
1070 if (op->code() == lir_move) { | |
1071 assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1"); | |
1072 LIR_Op1* move = (LIR_Op1*)op; | |
1073 LIR_Opr res = move->result_opr(); | |
1074 bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory); | |
1075 | |
1076 if (result_in_memory) { | |
1077 // Move to an interval with must_start_in_memory set. | |
1078 // To avoid moves from stack to stack (not allowed) force the input operand to a register | |
1079 return mustHaveRegister; | |
1080 | |
1081 } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) { | |
1082 // Move from register to register | |
1083 if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) { | |
1084 // special handling of phi-function moves inside osr-entry blocks | |
1085 // input operand must have a register instead of output operand (leads to better register allocation) | |
1086 return mustHaveRegister; | |
1087 } | |
1088 | |
1089 // The input operand is not forced to a register (moves from stack to register are allowed), | |
1090 // but it is faster if the input operand is in a register | |
1091 return shouldHaveRegister; | |
1092 } | |
1093 } | |
1094 | |
1095 | |
304 | 1096 #ifdef X86 |
0 | 1097 if (op->code() == lir_cmove) { |
1098 // conditional moves can handle stack operands | |
1099 assert(op->result_opr()->is_register(), "result must always be in a register"); | |
1100 return shouldHaveRegister; | |
1101 } | |
1102 | |
1103 // optimizations for second input operand of arithmehtic operations on Intel | |
1104 // this operand is allowed to be on the stack in some cases | |
1105 BasicType opr_type = opr->type_register(); | |
1106 if (opr_type == T_FLOAT || opr_type == T_DOUBLE) { | |
1107 if ((UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2) { | |
1108 // SSE float instruction (T_DOUBLE only supported with SSE2) | |
1109 switch (op->code()) { | |
1110 case lir_cmp: | |
1111 case lir_add: | |
1112 case lir_sub: | |
1113 case lir_mul: | |
1114 case lir_div: | |
1115 { | |
1116 assert(op->as_Op2() != NULL, "must be LIR_Op2"); | |
1117 LIR_Op2* op2 = (LIR_Op2*)op; | |
1118 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) { | |
1119 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register"); | |
1120 return shouldHaveRegister; | |
1121 } | |
1122 } | |
1123 } | |
1124 } else { | |
1125 // FPU stack float instruction | |
1126 switch (op->code()) { | |
1127 case lir_add: | |
1128 case lir_sub: | |
1129 case lir_mul: | |
1130 case lir_div: | |
1131 { | |
1132 assert(op->as_Op2() != NULL, "must be LIR_Op2"); | |
1133 LIR_Op2* op2 = (LIR_Op2*)op; | |
1134 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) { | |
1135 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register"); | |
1136 return shouldHaveRegister; | |
1137 } | |
1138 } | |
1139 } | |
1140 } | |
13044 | 1141 // We want to sometimes use logical operations on pointers, in particular in GC barriers. |
1142 // Since 64bit logical operations do not current support operands on stack, we have to make sure | |
1143 // T_OBJECT doesn't get spilled along with T_LONG. | |
1144 } else if (opr_type != T_LONG LP64_ONLY(&& opr_type != T_OBJECT)) { | |
0 | 1145 // integer instruction (note: long operands must always be in register) |
1146 switch (op->code()) { | |
1147 case lir_cmp: | |
1148 case lir_add: | |
1149 case lir_sub: | |
1150 case lir_logic_and: | |
1151 case lir_logic_or: | |
1152 case lir_logic_xor: | |
1153 { | |
1154 assert(op->as_Op2() != NULL, "must be LIR_Op2"); | |
1155 LIR_Op2* op2 = (LIR_Op2*)op; | |
1156 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) { | |
1157 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register"); | |
1158 return shouldHaveRegister; | |
1159 } | |
1160 } | |
1161 } | |
1162 } | |
304 | 1163 #endif // X86 |
0 | 1164 |
1165 // all other operands require a register | |
1166 return mustHaveRegister; | |
1167 } | |
1168 | |
1169 | |
1170 void LinearScan::handle_method_arguments(LIR_Op* op) { | |
1171 // special handling for method arguments (moves from stack to virtual register): | |
1172 // the interval gets no register assigned, but the stack slot. | |
1173 // it is split before the first use by the register allocator. | |
1174 | |
1175 if (op->code() == lir_move) { | |
1176 assert(op->as_Op1() != NULL, "must be LIR_Op1"); | |
1177 LIR_Op1* move = (LIR_Op1*)op; | |
1178 | |
1179 if (move->in_opr()->is_stack()) { | |
1180 #ifdef ASSERT | |
1181 int arg_size = compilation()->method()->arg_size(); | |
1182 LIR_Opr o = move->in_opr(); | |
1183 if (o->is_single_stack()) { | |
1184 assert(o->single_stack_ix() >= 0 && o->single_stack_ix() < arg_size, "out of range"); | |
1185 } else if (o->is_double_stack()) { | |
1186 assert(o->double_stack_ix() >= 0 && o->double_stack_ix() < arg_size, "out of range"); | |
1187 } else { | |
1188 ShouldNotReachHere(); | |
1189 } | |
1190 | |
1191 assert(move->id() > 0, "invalid id"); | |
1192 assert(block_of_op_with_id(move->id())->number_of_preds() == 0, "move from stack must be in first block"); | |
1193 assert(move->result_opr()->is_virtual(), "result of move must be a virtual register"); | |
1194 | |
1195 TRACE_LINEAR_SCAN(4, tty->print_cr("found move from stack slot %d to vreg %d", o->is_single_stack() ? o->single_stack_ix() : o->double_stack_ix(), reg_num(move->result_opr()))); | |
1196 #endif | |
1197 | |
1198 Interval* interval = interval_at(reg_num(move->result_opr())); | |
1199 | |
1200 int stack_slot = LinearScan::nof_regs + (move->in_opr()->is_single_stack() ? move->in_opr()->single_stack_ix() : move->in_opr()->double_stack_ix()); | |
1201 interval->set_canonical_spill_slot(stack_slot); | |
1202 interval->assign_reg(stack_slot); | |
1203 } | |
1204 } | |
1205 } | |
1206 | |
1207 void LinearScan::handle_doubleword_moves(LIR_Op* op) { | |
1208 // special handling for doubleword move from memory to register: | |
1209 // in this case the registers of the input address and the result | |
1210 // registers must not overlap -> add a temp range for the input registers | |
1211 if (op->code() == lir_move) { | |
1212 assert(op->as_Op1() != NULL, "must be LIR_Op1"); | |
1213 LIR_Op1* move = (LIR_Op1*)op; | |
1214 | |
1215 if (move->result_opr()->is_double_cpu() && move->in_opr()->is_pointer()) { | |
1216 LIR_Address* address = move->in_opr()->as_address_ptr(); | |
1217 if (address != NULL) { | |
1218 if (address->base()->is_valid()) { | |
1219 add_temp(address->base(), op->id(), noUse); | |
1220 } | |
1221 if (address->index()->is_valid()) { | |
1222 add_temp(address->index(), op->id(), noUse); | |
1223 } | |
1224 } | |
1225 } | |
1226 } | |
1227 } | |
1228 | |
1229 void LinearScan::add_register_hints(LIR_Op* op) { | |
1230 switch (op->code()) { | |
1231 case lir_move: // fall through | |
1232 case lir_convert: { | |
1233 assert(op->as_Op1() != NULL, "lir_move, lir_convert must be LIR_Op1"); | |
1234 LIR_Op1* move = (LIR_Op1*)op; | |
1235 | |
1236 LIR_Opr move_from = move->in_opr(); | |
1237 LIR_Opr move_to = move->result_opr(); | |
1238 | |
1239 if (move_to->is_register() && move_from->is_register()) { | |
1240 Interval* from = interval_at(reg_num(move_from)); | |
1241 Interval* to = interval_at(reg_num(move_to)); | |
1242 if (from != NULL && to != NULL) { | |
1243 to->set_register_hint(from); | |
1244 TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", move->id(), from->reg_num(), to->reg_num())); | |
1245 } | |
1246 } | |
1247 break; | |
1248 } | |
1249 case lir_cmove: { | |
1250 assert(op->as_Op2() != NULL, "lir_cmove must be LIR_Op2"); | |
1251 LIR_Op2* cmove = (LIR_Op2*)op; | |
1252 | |
1253 LIR_Opr move_from = cmove->in_opr1(); | |
1254 LIR_Opr move_to = cmove->result_opr(); | |
1255 | |
1256 if (move_to->is_register() && move_from->is_register()) { | |
1257 Interval* from = interval_at(reg_num(move_from)); | |
1258 Interval* to = interval_at(reg_num(move_to)); | |
1259 if (from != NULL && to != NULL) { | |
1260 to->set_register_hint(from); | |
1261 TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num())); | |
1262 } | |
1263 } | |
1264 break; | |
1265 } | |
1266 } | |
1267 } | |
1268 | |
1269 | |
1270 void LinearScan::build_intervals() { | |
1271 TIME_LINEAR_SCAN(timer_build_intervals); | |
1272 | |
1273 // initialize interval list with expected number of intervals | |
1274 // (32 is added to have some space for split children without having to resize the list) | |
1275 _intervals = IntervalList(num_virtual_regs() + 32); | |
1276 // initialize all slots that are used by build_intervals | |
1277 _intervals.at_put_grow(num_virtual_regs() - 1, NULL, NULL); | |
1278 | |
1279 // create a list with all caller-save registers (cpu, fpu, xmm) | |
1280 // when an instruction is a call, a temp range is created for all these registers | |
1281 int num_caller_save_registers = 0; | |
1282 int caller_save_registers[LinearScan::nof_regs]; | |
1283 | |
1284 int i; | |
2002 | 1285 for (i = 0; i < FrameMap::nof_caller_save_cpu_regs(); i++) { |
0 | 1286 LIR_Opr opr = FrameMap::caller_save_cpu_reg_at(i); |
1287 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands"); | |
1288 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register"); | |
1289 caller_save_registers[num_caller_save_registers++] = reg_num(opr); | |
1290 } | |
1291 | |
1292 // temp ranges for fpu registers are only created when the method has | |
1293 // virtual fpu operands. Otherwise no allocation for fpu registers is | |
1294 // perfomed and so the temp ranges would be useless | |
1295 if (has_fpu_registers()) { | |
304 | 1296 #ifdef X86 |
0 | 1297 if (UseSSE < 2) { |
1298 #endif | |
1299 for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) { | |
1300 LIR_Opr opr = FrameMap::caller_save_fpu_reg_at(i); | |
1301 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands"); | |
1302 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register"); | |
1303 caller_save_registers[num_caller_save_registers++] = reg_num(opr); | |
1304 } | |
304 | 1305 #ifdef X86 |
0 | 1306 } |
1307 if (UseSSE > 0) { | |
1308 for (i = 0; i < FrameMap::nof_caller_save_xmm_regs; i++) { | |
1309 LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(i); | |
1310 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands"); | |
1311 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register"); | |
1312 caller_save_registers[num_caller_save_registers++] = reg_num(opr); | |
1313 } | |
1314 } | |
1315 #endif | |
1316 } | |
1317 assert(num_caller_save_registers <= LinearScan::nof_regs, "out of bounds"); | |
1318 | |
1319 | |
1320 LIR_OpVisitState visitor; | |
1321 | |
1322 // iterate all blocks in reverse order | |
1323 for (i = block_count() - 1; i >= 0; i--) { | |
1324 BlockBegin* block = block_at(i); | |
1325 LIR_OpList* instructions = block->lir()->instructions_list(); | |
1326 int block_from = block->first_lir_instruction_id(); | |
1327 int block_to = block->last_lir_instruction_id(); | |
1328 | |
1329 assert(block_from == instructions->at(0)->id(), "must be"); | |
1330 assert(block_to == instructions->at(instructions->length() - 1)->id(), "must be"); | |
1331 | |
1332 // Update intervals for registers live at the end of this block; | |
1333 BitMap live = block->live_out(); | |
304 | 1334 int size = (int)live.size(); |
1335 for (int number = (int)live.get_next_one_offset(0, size); number < size; number = (int)live.get_next_one_offset(number + 1, size)) { | |
0 | 1336 assert(live.at(number), "should not stop here otherwise"); |
1337 assert(number >= LIR_OprDesc::vreg_base, "fixed intervals must not be live on block bounds"); | |
1338 TRACE_LINEAR_SCAN(2, tty->print_cr("live in %d to %d", number, block_to + 2)); | |
1339 | |
1340 add_use(number, block_from, block_to + 2, noUse, T_ILLEGAL); | |
1341 | |
1342 // add special use positions for loop-end blocks when the | |
1343 // interval is used anywhere inside this loop. It's possible | |
1344 // that the block was part of a non-natural loop, so it might | |
1345 // have an invalid loop index. | |
1346 if (block->is_set(BlockBegin::linear_scan_loop_end_flag) && | |
1347 block->loop_index() != -1 && | |
1348 is_interval_in_loop(number, block->loop_index())) { | |
1349 interval_at(number)->add_use_pos(block_to + 1, loopEndMarker); | |
1350 } | |
1351 } | |
1352 | |
1353 // iterate all instructions of the block in reverse order. | |
1354 // skip the first instruction because it is always a label | |
1355 // definitions of intervals are processed before uses | |
1356 assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label"); | |
1357 for (int j = instructions->length() - 1; j >= 1; j--) { | |
1358 LIR_Op* op = instructions->at(j); | |
1359 int op_id = op->id(); | |
1360 | |
1361 // visit operation to collect all operands | |
1362 visitor.visit(op); | |
1363 | |
1364 // add a temp range for each register if operation destroys caller-save registers | |
1365 if (visitor.has_call()) { | |
1366 for (int k = 0; k < num_caller_save_registers; k++) { | |
1367 add_temp(caller_save_registers[k], op_id, noUse, T_ILLEGAL); | |
1368 } | |
1369 TRACE_LINEAR_SCAN(4, tty->print_cr("operation destroys all caller-save registers")); | |
1370 } | |
1371 | |
1372 // Add any platform dependent temps | |
1373 pd_add_temps(op); | |
1374 | |
1375 // visit definitions (output and temp operands) | |
1376 int k, n; | |
1377 n = visitor.opr_count(LIR_OpVisitState::outputMode); | |
1378 for (k = 0; k < n; k++) { | |
1379 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k); | |
1380 assert(opr->is_register(), "visitor should only return register operands"); | |
1381 add_def(opr, op_id, use_kind_of_output_operand(op, opr)); | |
1382 } | |
1383 | |
1384 n = visitor.opr_count(LIR_OpVisitState::tempMode); | |
1385 for (k = 0; k < n; k++) { | |
1386 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k); | |
1387 assert(opr->is_register(), "visitor should only return register operands"); | |
1388 add_temp(opr, op_id, mustHaveRegister); | |
1389 } | |
1390 | |
1391 // visit uses (input operands) | |
1392 n = visitor.opr_count(LIR_OpVisitState::inputMode); | |
1393 for (k = 0; k < n; k++) { | |
1394 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k); | |
1395 assert(opr->is_register(), "visitor should only return register operands"); | |
1396 add_use(opr, block_from, op_id, use_kind_of_input_operand(op, opr)); | |
1397 } | |
1398 | |
1399 // Add uses of live locals from interpreter's point of view for proper | |
1400 // debug information generation | |
1401 // Treat these operands as temp values (if the life range is extended | |
1402 // to a call site, the value would be in a register at the call otherwise) | |
1403 n = visitor.info_count(); | |
1404 for (k = 0; k < n; k++) { | |
1405 CodeEmitInfo* info = visitor.info_at(k); | |
1406 ValueStack* stack = info->stack(); | |
1407 for_each_state_value(stack, value, | |
1408 add_use(value, block_from, op_id + 1, noUse); | |
1409 ); | |
1410 } | |
1411 | |
1412 // special steps for some instructions (especially moves) | |
1413 handle_method_arguments(op); | |
1414 handle_doubleword_moves(op); | |
1415 add_register_hints(op); | |
1416 | |
1417 } // end of instruction iteration | |
1418 } // end of block iteration | |
1419 | |
1420 | |
1421 // add the range [0, 1[ to all fixed intervals | |
1422 // -> the register allocator need not handle unhandled fixed intervals | |
1423 for (int n = 0; n < LinearScan::nof_regs; n++) { | |
1424 Interval* interval = interval_at(n); | |
1425 if (interval != NULL) { | |
1426 interval->add_range(0, 1); | |
1427 } | |
1428 } | |
1429 } | |
1430 | |
1431 | |
1432 // ********** Phase 5: actual register allocation | |
1433 | |
1434 int LinearScan::interval_cmp(Interval** a, Interval** b) { | |
1435 if (*a != NULL) { | |
1436 if (*b != NULL) { | |
1437 return (*a)->from() - (*b)->from(); | |
1438 } else { | |
1439 return -1; | |
1440 } | |
1441 } else { | |
1442 if (*b != NULL) { | |
1443 return 1; | |
1444 } else { | |
1445 return 0; | |
1446 } | |
1447 } | |
1448 } | |
1449 | |
1450 #ifndef PRODUCT | |
1451 bool LinearScan::is_sorted(IntervalArray* intervals) { | |
1452 int from = -1; | |
1453 int i, j; | |
1454 for (i = 0; i < intervals->length(); i ++) { | |
1455 Interval* it = intervals->at(i); | |
1456 if (it != NULL) { | |
1457 if (from > it->from()) { | |
1458 assert(false, ""); | |
1459 return false; | |
1460 } | |
1461 from = it->from(); | |
1462 } | |
1463 } | |
1464 | |
1465 // check in both directions if sorted list and unsorted list contain same intervals | |
1466 for (i = 0; i < interval_count(); i++) { | |
1467 if (interval_at(i) != NULL) { | |
1468 int num_found = 0; | |
1469 for (j = 0; j < intervals->length(); j++) { | |
1470 if (interval_at(i) == intervals->at(j)) { | |
1471 num_found++; | |
1472 } | |
1473 } | |
1474 assert(num_found == 1, "lists do not contain same intervals"); | |
1475 } | |
1476 } | |
1477 for (j = 0; j < intervals->length(); j++) { | |
1478 int num_found = 0; | |
1479 for (i = 0; i < interval_count(); i++) { | |
1480 if (interval_at(i) == intervals->at(j)) { | |
1481 num_found++; | |
1482 } | |
1483 } | |
1484 assert(num_found == 1, "lists do not contain same intervals"); | |
1485 } | |
1486 | |
1487 return true; | |
1488 } | |
1489 #endif | |
1490 | |
1491 void LinearScan::add_to_list(Interval** first, Interval** prev, Interval* interval) { | |
1492 if (*prev != NULL) { | |
1493 (*prev)->set_next(interval); | |
1494 } else { | |
1495 *first = interval; | |
1496 } | |
1497 *prev = interval; | |
1498 } | |
1499 | |
1500 void LinearScan::create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)) { | |
1501 assert(is_sorted(_sorted_intervals), "interval list is not sorted"); | |
1502 | |
1503 *list1 = *list2 = Interval::end(); | |
1504 | |
1505 Interval* list1_prev = NULL; | |
1506 Interval* list2_prev = NULL; | |
1507 Interval* v; | |
1508 | |
1509 const int n = _sorted_intervals->length(); | |
1510 for (int i = 0; i < n; i++) { | |
1511 v = _sorted_intervals->at(i); | |
1512 if (v == NULL) continue; | |
1513 | |
1514 if (is_list1(v)) { | |
1515 add_to_list(list1, &list1_prev, v); | |
1516 } else if (is_list2 == NULL || is_list2(v)) { | |
1517 add_to_list(list2, &list2_prev, v); | |
1518 } | |
1519 } | |
1520 | |
1521 if (list1_prev != NULL) list1_prev->set_next(Interval::end()); | |
1522 if (list2_prev != NULL) list2_prev->set_next(Interval::end()); | |
1523 | |
1524 assert(list1_prev == NULL || list1_prev->next() == Interval::end(), "linear list ends not with sentinel"); | |
1525 assert(list2_prev == NULL || list2_prev->next() == Interval::end(), "linear list ends not with sentinel"); | |
1526 } | |
1527 | |
1528 | |
1529 void LinearScan::sort_intervals_before_allocation() { | |
1530 TIME_LINEAR_SCAN(timer_sort_intervals_before); | |
1531 | |
2081
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1532 if (_needs_full_resort) { |
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1533 // There is no known reason why this should occur but just in case... |
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1534 assert(false, "should never occur"); |
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1535 // Re-sort existing interval list because an Interval::from() has changed |
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1536 _sorted_intervals->sort(interval_cmp); |
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1537 _needs_full_resort = false; |
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1538 } |
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1539 |
0 | 1540 IntervalList* unsorted_list = &_intervals; |
1541 int unsorted_len = unsorted_list->length(); | |
1542 int sorted_len = 0; | |
1543 int unsorted_idx; | |
1544 int sorted_idx = 0; | |
1545 int sorted_from_max = -1; | |
1546 | |
1547 // calc number of items for sorted list (sorted list must not contain NULL values) | |
1548 for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) { | |
1549 if (unsorted_list->at(unsorted_idx) != NULL) { | |
1550 sorted_len++; | |
1551 } | |
1552 } | |
1553 IntervalArray* sorted_list = new IntervalArray(sorted_len); | |
1554 | |
1555 // special sorting algorithm: the original interval-list is almost sorted, | |
1556 // only some intervals are swapped. So this is much faster than a complete QuickSort | |
1557 for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) { | |
1558 Interval* cur_interval = unsorted_list->at(unsorted_idx); | |
1559 | |
1560 if (cur_interval != NULL) { | |
1561 int cur_from = cur_interval->from(); | |
1562 | |
1563 if (sorted_from_max <= cur_from) { | |
1564 sorted_list->at_put(sorted_idx++, cur_interval); | |
1565 sorted_from_max = cur_interval->from(); | |
1566 } else { | |
1567 // the asumption that the intervals are already sorted failed, | |
1568 // so this interval must be sorted in manually | |
1569 int j; | |
1570 for (j = sorted_idx - 1; j >= 0 && cur_from < sorted_list->at(j)->from(); j--) { | |
1571 sorted_list->at_put(j + 1, sorted_list->at(j)); | |
1572 } | |
1573 sorted_list->at_put(j + 1, cur_interval); | |
1574 sorted_idx++; | |
1575 } | |
1576 } | |
1577 } | |
1578 _sorted_intervals = sorted_list; | |
2081
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1579 assert(is_sorted(_sorted_intervals), "intervals unsorted"); |
0 | 1580 } |
1581 | |
1582 void LinearScan::sort_intervals_after_allocation() { | |
1583 TIME_LINEAR_SCAN(timer_sort_intervals_after); | |
1584 | |
2081
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1585 if (_needs_full_resort) { |
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1586 // Re-sort existing interval list because an Interval::from() has changed |
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1587 _sorted_intervals->sort(interval_cmp); |
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1588 _needs_full_resort = false; |
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1589 } |
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1590 |
0 | 1591 IntervalArray* old_list = _sorted_intervals; |
1592 IntervalList* new_list = _new_intervals_from_allocation; | |
1593 int old_len = old_list->length(); | |
1594 int new_len = new_list->length(); | |
1595 | |
1596 if (new_len == 0) { | |
1597 // no intervals have been added during allocation, so sorted list is already up to date | |
2081
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1598 assert(is_sorted(_sorted_intervals), "intervals unsorted"); |
0 | 1599 return; |
1600 } | |
1601 | |
1602 // conventional sort-algorithm for new intervals | |
1603 new_list->sort(interval_cmp); | |
1604 | |
1605 // merge old and new list (both already sorted) into one combined list | |
1606 IntervalArray* combined_list = new IntervalArray(old_len + new_len); | |
1607 int old_idx = 0; | |
1608 int new_idx = 0; | |
1609 | |
1610 while (old_idx + new_idx < old_len + new_len) { | |
1611 if (new_idx >= new_len || (old_idx < old_len && old_list->at(old_idx)->from() <= new_list->at(new_idx)->from())) { | |
1612 combined_list->at_put(old_idx + new_idx, old_list->at(old_idx)); | |
1613 old_idx++; | |
1614 } else { | |
1615 combined_list->at_put(old_idx + new_idx, new_list->at(new_idx)); | |
1616 new_idx++; | |
1617 } | |
1618 } | |
1619 | |
1620 _sorted_intervals = combined_list; | |
2081
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1621 assert(is_sorted(_sorted_intervals), "intervals unsorted"); |
0 | 1622 } |
1623 | |
1624 | |
1625 void LinearScan::allocate_registers() { | |
1626 TIME_LINEAR_SCAN(timer_allocate_registers); | |
1627 | |
1628 Interval* precolored_cpu_intervals, *not_precolored_cpu_intervals; | |
1629 Interval* precolored_fpu_intervals, *not_precolored_fpu_intervals; | |
1630 | |
1631 create_unhandled_lists(&precolored_cpu_intervals, ¬_precolored_cpu_intervals, is_precolored_cpu_interval, is_virtual_cpu_interval); | |
1632 if (has_fpu_registers()) { | |
1633 create_unhandled_lists(&precolored_fpu_intervals, ¬_precolored_fpu_intervals, is_precolored_fpu_interval, is_virtual_fpu_interval); | |
1634 #ifdef ASSERT | |
1635 } else { | |
1636 // fpu register allocation is omitted because no virtual fpu registers are present | |
1637 // just check this again... | |
1638 create_unhandled_lists(&precolored_fpu_intervals, ¬_precolored_fpu_intervals, is_precolored_fpu_interval, is_virtual_fpu_interval); | |
1639 assert(not_precolored_fpu_intervals == Interval::end(), "missed an uncolored fpu interval"); | |
1640 #endif | |
1641 } | |
1642 | |
1643 // allocate cpu registers | |
1644 LinearScanWalker cpu_lsw(this, precolored_cpu_intervals, not_precolored_cpu_intervals); | |
1645 cpu_lsw.walk(); | |
1646 cpu_lsw.finish_allocation(); | |
1647 | |
1648 if (has_fpu_registers()) { | |
1649 // allocate fpu registers | |
1650 LinearScanWalker fpu_lsw(this, precolored_fpu_intervals, not_precolored_fpu_intervals); | |
1651 fpu_lsw.walk(); | |
1652 fpu_lsw.finish_allocation(); | |
1653 } | |
1654 } | |
1655 | |
1656 | |
1657 // ********** Phase 6: resolve data flow | |
1658 // (insert moves at edges between blocks if intervals have been split) | |
1659 | |
1660 // wrapper for Interval::split_child_at_op_id that performs a bailout in product mode | |
1661 // instead of returning NULL | |
1662 Interval* LinearScan::split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode) { | |
1663 Interval* result = interval->split_child_at_op_id(op_id, mode); | |
1664 if (result != NULL) { | |
1665 return result; | |
1666 } | |
1667 | |
1668 assert(false, "must find an interval, but do a clean bailout in product mode"); | |
1669 result = new Interval(LIR_OprDesc::vreg_base); | |
1670 result->assign_reg(0); | |
1671 result->set_type(T_INT); | |
1672 BAILOUT_("LinearScan: interval is NULL", result); | |
1673 } | |
1674 | |
1675 | |
1676 Interval* LinearScan::interval_at_block_begin(BlockBegin* block, int reg_num) { | |
1677 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds"); | |
1678 assert(interval_at(reg_num) != NULL, "no interval found"); | |
1679 | |
1680 return split_child_at_op_id(interval_at(reg_num), block->first_lir_instruction_id(), LIR_OpVisitState::outputMode); | |
1681 } | |
1682 | |
1683 Interval* LinearScan::interval_at_block_end(BlockBegin* block, int reg_num) { | |
1684 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds"); | |
1685 assert(interval_at(reg_num) != NULL, "no interval found"); | |
1686 | |
1687 return split_child_at_op_id(interval_at(reg_num), block->last_lir_instruction_id() + 1, LIR_OpVisitState::outputMode); | |
1688 } | |
1689 | |
1690 Interval* LinearScan::interval_at_op_id(int reg_num, int op_id) { | |
1691 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds"); | |
1692 assert(interval_at(reg_num) != NULL, "no interval found"); | |
1693 | |
1694 return split_child_at_op_id(interval_at(reg_num), op_id, LIR_OpVisitState::inputMode); | |
1695 } | |
1696 | |
1697 | |
1698 void LinearScan::resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) { | |
1699 DEBUG_ONLY(move_resolver.check_empty()); | |
1700 | |
1701 const int num_regs = num_virtual_regs(); | |
1702 const int size = live_set_size(); | |
1703 const BitMap live_at_edge = to_block->live_in(); | |
1704 | |
1705 // visit all registers where the live_at_edge bit is set | |
304 | 1706 for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) { |
0 | 1707 assert(r < num_regs, "live information set for not exisiting interval"); |
1708 assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge"); | |
1709 | |
1710 Interval* from_interval = interval_at_block_end(from_block, r); | |
1711 Interval* to_interval = interval_at_block_begin(to_block, r); | |
1712 | |
1713 if (from_interval != to_interval && (from_interval->assigned_reg() != to_interval->assigned_reg() || from_interval->assigned_regHi() != to_interval->assigned_regHi())) { | |
1714 // need to insert move instruction | |
1715 move_resolver.add_mapping(from_interval, to_interval); | |
1716 } | |
1717 } | |
1718 } | |
1719 | |
1720 | |
1721 void LinearScan::resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) { | |
1722 if (from_block->number_of_sux() <= 1) { | |
1723 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at end of from_block B%d", from_block->block_id())); | |
1724 | |
1725 LIR_OpList* instructions = from_block->lir()->instructions_list(); | |
1726 LIR_OpBranch* branch = instructions->last()->as_OpBranch(); | |
1727 if (branch != NULL) { | |
1728 // insert moves before branch | |
1729 assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump"); | |
1730 move_resolver.set_insert_position(from_block->lir(), instructions->length() - 2); | |
1731 } else { | |
1732 move_resolver.set_insert_position(from_block->lir(), instructions->length() - 1); | |
1733 } | |
1734 | |
1735 } else { | |
1736 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at beginning of to_block B%d", to_block->block_id())); | |
1737 #ifdef ASSERT | |
1738 assert(from_block->lir()->instructions_list()->at(0)->as_OpLabel() != NULL, "block does not start with a label"); | |
1739 | |
1740 // because the number of predecessor edges matches the number of | |
1741 // successor edges, blocks which are reached by switch statements | |
1742 // may have be more than one predecessor but it will be guaranteed | |
1743 // that all predecessors will be the same. | |
1744 for (int i = 0; i < to_block->number_of_preds(); i++) { | |
1745 assert(from_block == to_block->pred_at(i), "all critical edges must be broken"); | |
1746 } | |
1747 #endif | |
1748 | |
1749 move_resolver.set_insert_position(to_block->lir(), 0); | |
1750 } | |
1751 } | |
1752 | |
1753 | |
1754 // insert necessary moves (spilling or reloading) at edges between blocks if interval has been split | |
1755 void LinearScan::resolve_data_flow() { | |
1756 TIME_LINEAR_SCAN(timer_resolve_data_flow); | |
1757 | |
1758 int num_blocks = block_count(); | |
1759 MoveResolver move_resolver(this); | |
1760 BitMap block_completed(num_blocks); block_completed.clear(); | |
1761 BitMap already_resolved(num_blocks); already_resolved.clear(); | |
1762 | |
1763 int i; | |
1764 for (i = 0; i < num_blocks; i++) { | |
1765 BlockBegin* block = block_at(i); | |
1766 | |
1767 // check if block has only one predecessor and only one successor | |
1768 if (block->number_of_preds() == 1 && block->number_of_sux() == 1 && block->number_of_exception_handlers() == 0) { | |
1769 LIR_OpList* instructions = block->lir()->instructions_list(); | |
1770 assert(instructions->at(0)->code() == lir_label, "block must start with label"); | |
1771 assert(instructions->last()->code() == lir_branch, "block with successors must end with branch"); | |
1772 assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block with successor must end with unconditional branch"); | |
1773 | |
1774 // check if block is empty (only label and branch) | |
1775 if (instructions->length() == 2) { | |
1776 BlockBegin* pred = block->pred_at(0); | |
1777 BlockBegin* sux = block->sux_at(0); | |
1778 | |
1779 // prevent optimization of two consecutive blocks | |
1780 if (!block_completed.at(pred->linear_scan_number()) && !block_completed.at(sux->linear_scan_number())) { | |
1781 TRACE_LINEAR_SCAN(3, tty->print_cr("**** optimizing empty block B%d (pred: B%d, sux: B%d)", block->block_id(), pred->block_id(), sux->block_id())); | |
1782 block_completed.set_bit(block->linear_scan_number()); | |
1783 | |
1784 // directly resolve between pred and sux (without looking at the empty block between) | |
1785 resolve_collect_mappings(pred, sux, move_resolver); | |
1786 if (move_resolver.has_mappings()) { | |
1787 move_resolver.set_insert_position(block->lir(), 0); | |
1788 move_resolver.resolve_and_append_moves(); | |
1789 } | |
1790 } | |
1791 } | |
1792 } | |
1793 } | |
1794 | |
1795 | |
1796 for (i = 0; i < num_blocks; i++) { | |
1797 if (!block_completed.at(i)) { | |
1798 BlockBegin* from_block = block_at(i); | |
1799 already_resolved.set_from(block_completed); | |
1800 | |
1801 int num_sux = from_block->number_of_sux(); | |
1802 for (int s = 0; s < num_sux; s++) { | |
1803 BlockBegin* to_block = from_block->sux_at(s); | |
1804 | |
1805 // check for duplicate edges between the same blocks (can happen with switch blocks) | |
1806 if (!already_resolved.at(to_block->linear_scan_number())) { | |
1807 TRACE_LINEAR_SCAN(3, tty->print_cr("**** processing edge between B%d and B%d", from_block->block_id(), to_block->block_id())); | |
1808 already_resolved.set_bit(to_block->linear_scan_number()); | |
1809 | |
1810 // collect all intervals that have been split between from_block and to_block | |
1811 resolve_collect_mappings(from_block, to_block, move_resolver); | |
1812 if (move_resolver.has_mappings()) { | |
1813 resolve_find_insert_pos(from_block, to_block, move_resolver); | |
1814 move_resolver.resolve_and_append_moves(); | |
1815 } | |
1816 } | |
1817 } | |
1818 } | |
1819 } | |
1820 } | |
1821 | |
1822 | |
1823 void LinearScan::resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver) { | |
1824 if (interval_at(reg_num) == NULL) { | |
1825 // if a phi function is never used, no interval is created -> ignore this | |
1826 return; | |
1827 } | |
1828 | |
1829 Interval* interval = interval_at_block_begin(block, reg_num); | |
1830 int reg = interval->assigned_reg(); | |
1831 int regHi = interval->assigned_regHi(); | |
1832 | |
1833 if ((reg < nof_regs && interval->always_in_memory()) || | |
1834 (use_fpu_stack_allocation() && reg >= pd_first_fpu_reg && reg <= pd_last_fpu_reg)) { | |
1835 // the interval is split to get a short range that is located on the stack | |
1836 // in the following two cases: | |
1837 // * the interval started in memory (e.g. method parameter), but is currently in a register | |
1838 // this is an optimization for exception handling that reduces the number of moves that | |
1839 // are necessary for resolving the states when an exception uses this exception handler | |
1840 // * the interval would be on the fpu stack at the begin of the exception handler | |
1841 // this is not allowed because of the complicated fpu stack handling on Intel | |
1842 | |
1843 // range that will be spilled to memory | |
1844 int from_op_id = block->first_lir_instruction_id(); | |
1845 int to_op_id = from_op_id + 1; // short live range of length 1 | |
1846 assert(interval->from() <= from_op_id && interval->to() >= to_op_id, | |
1847 "no split allowed between exception entry and first instruction"); | |
1848 | |
1849 if (interval->from() != from_op_id) { | |
1850 // the part before from_op_id is unchanged | |
1851 interval = interval->split(from_op_id); | |
1852 interval->assign_reg(reg, regHi); | |
1853 append_interval(interval); | |
2081
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1854 } else { |
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1855 _needs_full_resort = true; |
0 | 1856 } |
1857 assert(interval->from() == from_op_id, "must be true now"); | |
1858 | |
1859 Interval* spilled_part = interval; | |
1860 if (interval->to() != to_op_id) { | |
1861 // the part after to_op_id is unchanged | |
1862 spilled_part = interval->split_from_start(to_op_id); | |
1863 append_interval(spilled_part); | |
1864 move_resolver.add_mapping(spilled_part, interval); | |
1865 } | |
1866 assign_spill_slot(spilled_part); | |
1867 | |
1868 assert(spilled_part->from() == from_op_id && spilled_part->to() == to_op_id, "just checking"); | |
1869 } | |
1870 } | |
1871 | |
1872 void LinearScan::resolve_exception_entry(BlockBegin* block, MoveResolver &move_resolver) { | |
1873 assert(block->is_set(BlockBegin::exception_entry_flag), "should not call otherwise"); | |
1874 DEBUG_ONLY(move_resolver.check_empty()); | |
1875 | |
1876 // visit all registers where the live_in bit is set | |
1877 int size = live_set_size(); | |
304 | 1878 for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) { |
0 | 1879 resolve_exception_entry(block, r, move_resolver); |
1880 } | |
1881 | |
1882 // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately | |
1883 for_each_phi_fun(block, phi, | |
1884 resolve_exception_entry(block, phi->operand()->vreg_number(), move_resolver) | |
1885 ); | |
1886 | |
1887 if (move_resolver.has_mappings()) { | |
1888 // insert moves after first instruction | |
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1889 move_resolver.set_insert_position(block->lir(), 0); |
0 | 1890 move_resolver.resolve_and_append_moves(); |
1891 } | |
1892 } | |
1893 | |
1894 | |
1895 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver) { | |
1896 if (interval_at(reg_num) == NULL) { | |
1897 // if a phi function is never used, no interval is created -> ignore this | |
1898 return; | |
1899 } | |
1900 | |
1901 // the computation of to_interval is equal to resolve_collect_mappings, | |
1902 // but from_interval is more complicated because of phi functions | |
1903 BlockBegin* to_block = handler->entry_block(); | |
1904 Interval* to_interval = interval_at_block_begin(to_block, reg_num); | |
1905 | |
1906 if (phi != NULL) { | |
1907 // phi function of the exception entry block | |
1908 // no moves are created for this phi function in the LIR_Generator, so the | |
1909 // interval at the throwing instruction must be searched using the operands | |
1910 // of the phi function | |
1911 Value from_value = phi->operand_at(handler->phi_operand()); | |
1912 | |
1913 // with phi functions it can happen that the same from_value is used in | |
1914 // multiple mappings, so notify move-resolver that this is allowed | |
1915 move_resolver.set_multiple_reads_allowed(); | |
1916 | |
1917 Constant* con = from_value->as_Constant(); | |
1918 if (con != NULL && !con->is_pinned()) { | |
1919 // unpinned constants may have no register, so add mapping from constant to interval | |
1920 move_resolver.add_mapping(LIR_OprFact::value_type(con->type()), to_interval); | |
1921 } else { | |
1922 // search split child at the throwing op_id | |
1923 Interval* from_interval = interval_at_op_id(from_value->operand()->vreg_number(), throwing_op_id); | |
1924 move_resolver.add_mapping(from_interval, to_interval); | |
1925 } | |
1926 | |
1927 } else { | |
1928 // no phi function, so use reg_num also for from_interval | |
1929 // search split child at the throwing op_id | |
1930 Interval* from_interval = interval_at_op_id(reg_num, throwing_op_id); | |
1931 if (from_interval != to_interval) { | |
1932 // optimization to reduce number of moves: when to_interval is on stack and | |
1933 // the stack slot is known to be always correct, then no move is necessary | |
1934 if (!from_interval->always_in_memory() || from_interval->canonical_spill_slot() != to_interval->assigned_reg()) { | |
1935 move_resolver.add_mapping(from_interval, to_interval); | |
1936 } | |
1937 } | |
1938 } | |
1939 } | |
1940 | |
1941 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver) { | |
1942 TRACE_LINEAR_SCAN(4, tty->print_cr("resolving exception handler B%d: throwing_op_id=%d", handler->entry_block()->block_id(), throwing_op_id)); | |
1943 | |
1944 DEBUG_ONLY(move_resolver.check_empty()); | |
1945 assert(handler->lir_op_id() == -1, "already processed this xhandler"); | |
1946 DEBUG_ONLY(handler->set_lir_op_id(throwing_op_id)); | |
1947 assert(handler->entry_code() == NULL, "code already present"); | |
1948 | |
1949 // visit all registers where the live_in bit is set | |
1950 BlockBegin* block = handler->entry_block(); | |
1951 int size = live_set_size(); | |
304 | 1952 for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) { |
0 | 1953 resolve_exception_edge(handler, throwing_op_id, r, NULL, move_resolver); |
1954 } | |
1955 | |
1956 // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately | |
1957 for_each_phi_fun(block, phi, | |
1958 resolve_exception_edge(handler, throwing_op_id, phi->operand()->vreg_number(), phi, move_resolver) | |
1959 ); | |
1960 | |
1961 if (move_resolver.has_mappings()) { | |
1962 LIR_List* entry_code = new LIR_List(compilation()); | |
1963 move_resolver.set_insert_position(entry_code, 0); | |
1964 move_resolver.resolve_and_append_moves(); | |
1965 | |
1966 entry_code->jump(handler->entry_block()); | |
1967 handler->set_entry_code(entry_code); | |
1968 } | |
1969 } | |
1970 | |
1971 | |
1972 void LinearScan::resolve_exception_handlers() { | |
1973 MoveResolver move_resolver(this); | |
1974 LIR_OpVisitState visitor; | |
1975 int num_blocks = block_count(); | |
1976 | |
1977 int i; | |
1978 for (i = 0; i < num_blocks; i++) { | |
1979 BlockBegin* block = block_at(i); | |
1980 if (block->is_set(BlockBegin::exception_entry_flag)) { | |
1981 resolve_exception_entry(block, move_resolver); | |
1982 } | |
1983 } | |
1984 | |
1985 for (i = 0; i < num_blocks; i++) { | |
1986 BlockBegin* block = block_at(i); | |
1987 LIR_List* ops = block->lir(); | |
1988 int num_ops = ops->length(); | |
1989 | |
1990 // iterate all instructions of the block. skip the first because it is always a label | |
1991 assert(visitor.no_operands(ops->at(0)), "first operation must always be a label"); | |
1992 for (int j = 1; j < num_ops; j++) { | |
1993 LIR_Op* op = ops->at(j); | |
1994 int op_id = op->id(); | |
1995 | |
1996 if (op_id != -1 && has_info(op_id)) { | |
1997 // visit operation to collect all operands | |
1998 visitor.visit(op); | |
1999 assert(visitor.info_count() > 0, "should not visit otherwise"); | |
2000 | |
2001 XHandlers* xhandlers = visitor.all_xhandler(); | |
2002 int n = xhandlers->length(); | |
2003 for (int k = 0; k < n; k++) { | |
2004 resolve_exception_edge(xhandlers->handler_at(k), op_id, move_resolver); | |
2005 } | |
2006 | |
2007 #ifdef ASSERT | |
2008 } else { | |
2009 visitor.visit(op); | |
2010 assert(visitor.all_xhandler()->length() == 0, "missed exception handler"); | |
2011 #endif | |
2012 } | |
2013 } | |
2014 } | |
2015 } | |
2016 | |
2017 | |
2018 // ********** Phase 7: assign register numbers back to LIR | |
2019 // (includes computation of debug information and oop maps) | |
2020 | |
2021 VMReg LinearScan::vm_reg_for_interval(Interval* interval) { | |
2022 VMReg reg = interval->cached_vm_reg(); | |
2023 if (!reg->is_valid() ) { | |
2024 reg = vm_reg_for_operand(operand_for_interval(interval)); | |
2025 interval->set_cached_vm_reg(reg); | |
2026 } | |
2027 assert(reg == vm_reg_for_operand(operand_for_interval(interval)), "wrong cached value"); | |
2028 return reg; | |
2029 } | |
2030 | |
2031 VMReg LinearScan::vm_reg_for_operand(LIR_Opr opr) { | |
2032 assert(opr->is_oop(), "currently only implemented for oop operands"); | |
2033 return frame_map()->regname(opr); | |
2034 } | |
2035 | |
2036 | |
2037 LIR_Opr LinearScan::operand_for_interval(Interval* interval) { | |
2038 LIR_Opr opr = interval->cached_opr(); | |
2039 if (opr->is_illegal()) { | |
2040 opr = calc_operand_for_interval(interval); | |
2041 interval->set_cached_opr(opr); | |
2042 } | |
2043 | |
2044 assert(opr == calc_operand_for_interval(interval), "wrong cached value"); | |
2045 return opr; | |
2046 } | |
2047 | |
2048 LIR_Opr LinearScan::calc_operand_for_interval(const Interval* interval) { | |
2049 int assigned_reg = interval->assigned_reg(); | |
2050 BasicType type = interval->type(); | |
2051 | |
2052 if (assigned_reg >= nof_regs) { | |
2053 // stack slot | |
2054 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); | |
2055 return LIR_OprFact::stack(assigned_reg - nof_regs, type); | |
2056 | |
2057 } else { | |
2058 // register | |
2059 switch (type) { | |
2060 case T_OBJECT: { | |
2061 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); | |
2062 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); | |
2063 return LIR_OprFact::single_cpu_oop(assigned_reg); | |
2064 } | |
2065 | |
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2066 case T_ADDRESS: { |
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2067 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); |
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2068 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); |
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2069 return LIR_OprFact::single_cpu_address(assigned_reg); |
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2070 } |
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2071 |
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2072 case T_METADATA: { |
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2073 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); |
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2074 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); |
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2075 return LIR_OprFact::single_cpu_metadata(assigned_reg); |
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2076 } |
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2077 |
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2078 #ifdef __SOFTFP__ |
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2079 case T_FLOAT: // fall through |
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2080 #endif // __SOFTFP__ |
0 | 2081 case T_INT: { |
2082 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); | |
2083 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); | |
2084 return LIR_OprFact::single_cpu(assigned_reg); | |
2085 } | |
2086 | |
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2087 #ifdef __SOFTFP__ |
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2088 case T_DOUBLE: // fall through |
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2089 #endif // __SOFTFP__ |
0 | 2090 case T_LONG: { |
2091 int assigned_regHi = interval->assigned_regHi(); | |
2092 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); | |
2093 assert(num_physical_regs(T_LONG) == 1 || | |
2094 (assigned_regHi >= pd_first_cpu_reg && assigned_regHi <= pd_last_cpu_reg), "no cpu register"); | |
2095 | |
2096 assert(assigned_reg != assigned_regHi, "invalid allocation"); | |
2097 assert(num_physical_regs(T_LONG) == 1 || assigned_reg < assigned_regHi, | |
2098 "register numbers must be sorted (ensure that e.g. a move from eax,ebx to ebx,eax can not occur)"); | |
2099 assert((assigned_regHi != any_reg) ^ (num_physical_regs(T_LONG) == 1), "must be match"); | |
2100 if (requires_adjacent_regs(T_LONG)) { | |
2101 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even"); | |
2102 } | |
2103 | |
2104 #ifdef _LP64 | |
2105 return LIR_OprFact::double_cpu(assigned_reg, assigned_reg); | |
2106 #else | |
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2107 #if defined(SPARC) || defined(PPC) |
0 | 2108 return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg); |
2109 #else | |
2110 return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi); | |
304 | 2111 #endif // SPARC |
2112 #endif // LP64 | |
0 | 2113 } |
2114 | |
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2115 #ifndef __SOFTFP__ |
0 | 2116 case T_FLOAT: { |
304 | 2117 #ifdef X86 |
0 | 2118 if (UseSSE >= 1) { |
2119 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register"); | |
2120 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); | |
2121 return LIR_OprFact::single_xmm(assigned_reg - pd_first_xmm_reg); | |
2122 } | |
2123 #endif | |
2124 | |
2125 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); | |
2126 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); | |
2127 return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg); | |
2128 } | |
2129 | |
2130 case T_DOUBLE: { | |
304 | 2131 #ifdef X86 |
0 | 2132 if (UseSSE >= 2) { |
2133 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register"); | |
2134 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)"); | |
2135 return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg); | |
2136 } | |
2137 #endif | |
2138 | |
2139 #ifdef SPARC | |
2140 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); | |
2141 assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register"); | |
2142 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even"); | |
2143 LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg); | |
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2144 #elif defined(ARM) |
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2145 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); |
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2146 assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register"); |
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2147 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even"); |
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2148 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg); |
0 | 2149 #else |
2150 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); | |
2151 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)"); | |
2152 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg); | |
2153 #endif | |
2154 return result; | |
2155 } | |
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2156 #endif // __SOFTFP__ |
0 | 2157 |
2158 default: { | |
2159 ShouldNotReachHere(); | |
2160 return LIR_OprFact::illegalOpr; | |
2161 } | |
2162 } | |
2163 } | |
2164 } | |
2165 | |
2166 LIR_Opr LinearScan::canonical_spill_opr(Interval* interval) { | |
2167 assert(interval->canonical_spill_slot() >= nof_regs, "canonical spill slot not set"); | |
2168 return LIR_OprFact::stack(interval->canonical_spill_slot() - nof_regs, interval->type()); | |
2169 } | |
2170 | |
2171 LIR_Opr LinearScan::color_lir_opr(LIR_Opr opr, int op_id, LIR_OpVisitState::OprMode mode) { | |
2172 assert(opr->is_virtual(), "should not call this otherwise"); | |
2173 | |
2174 Interval* interval = interval_at(opr->vreg_number()); | |
2175 assert(interval != NULL, "interval must exist"); | |
2176 | |
2177 if (op_id != -1) { | |
2178 #ifdef ASSERT | |
2179 BlockBegin* block = block_of_op_with_id(op_id); | |
2180 if (block->number_of_sux() <= 1 && op_id == block->last_lir_instruction_id()) { | |
2181 // check if spill moves could have been appended at the end of this block, but | |
2182 // before the branch instruction. So the split child information for this branch would | |
2183 // be incorrect. | |
2184 LIR_OpBranch* branch = block->lir()->instructions_list()->last()->as_OpBranch(); | |
2185 if (branch != NULL) { | |
2186 if (block->live_out().at(opr->vreg_number())) { | |
2187 assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump"); | |
2188 assert(false, "can't get split child for the last branch of a block because the information would be incorrect (moves are inserted before the branch in resolve_data_flow)"); | |
2189 } | |
2190 } | |
2191 } | |
2192 #endif | |
2193 | |
2194 // operands are not changed when an interval is split during allocation, | |
2195 // so search the right interval here | |
2196 interval = split_child_at_op_id(interval, op_id, mode); | |
2197 } | |
2198 | |
2199 LIR_Opr res = operand_for_interval(interval); | |
2200 | |
304 | 2201 #ifdef X86 |
0 | 2202 // new semantic for is_last_use: not only set on definite end of interval, |
2203 // but also before hole | |
2204 // This may still miss some cases (e.g. for dead values), but it is not necessary that the | |
2205 // last use information is completely correct | |
2206 // information is only needed for fpu stack allocation | |
2207 if (res->is_fpu_register()) { | |
2208 if (opr->is_last_use() || op_id == interval->to() || (op_id != -1 && interval->has_hole_between(op_id, op_id + 1))) { | |
2209 assert(op_id == -1 || !is_block_begin(op_id), "holes at begin of block may also result from control flow"); | |
2210 res = res->make_last_use(); | |
2211 } | |
2212 } | |
2213 #endif | |
2214 | |
2215 assert(!gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::callee_saved) || !FrameMap::is_caller_save_register(res), "bad allocation"); | |
2216 | |
2217 return res; | |
2218 } | |
2219 | |
2220 | |
2221 #ifdef ASSERT | |
2222 // some methods used to check correctness of debug information | |
2223 | |
2224 void assert_no_register_values(GrowableArray<ScopeValue*>* values) { | |
2225 if (values == NULL) { | |
2226 return; | |
2227 } | |
2228 | |
2229 for (int i = 0; i < values->length(); i++) { | |
2230 ScopeValue* value = values->at(i); | |
2231 | |
2232 if (value->is_location()) { | |
2233 Location location = ((LocationValue*)value)->location(); | |
2234 assert(location.where() == Location::on_stack, "value is in register"); | |
2235 } | |
2236 } | |
2237 } | |
2238 | |
2239 void assert_no_register_values(GrowableArray<MonitorValue*>* values) { | |
2240 if (values == NULL) { | |
2241 return; | |
2242 } | |
2243 | |
2244 for (int i = 0; i < values->length(); i++) { | |
2245 MonitorValue* value = values->at(i); | |
2246 | |
2247 if (value->owner()->is_location()) { | |
2248 Location location = ((LocationValue*)value->owner())->location(); | |
2249 assert(location.where() == Location::on_stack, "owner is in register"); | |
2250 } | |
2251 assert(value->basic_lock().where() == Location::on_stack, "basic_lock is in register"); | |
2252 } | |
2253 } | |
2254 | |
2255 void assert_equal(Location l1, Location l2) { | |
2256 assert(l1.where() == l2.where() && l1.type() == l2.type() && l1.offset() == l2.offset(), ""); | |
2257 } | |
2258 | |
2259 void assert_equal(ScopeValue* v1, ScopeValue* v2) { | |
2260 if (v1->is_location()) { | |
2261 assert(v2->is_location(), ""); | |
2262 assert_equal(((LocationValue*)v1)->location(), ((LocationValue*)v2)->location()); | |
2263 } else if (v1->is_constant_int()) { | |
2264 assert(v2->is_constant_int(), ""); | |
2265 assert(((ConstantIntValue*)v1)->value() == ((ConstantIntValue*)v2)->value(), ""); | |
2266 } else if (v1->is_constant_double()) { | |
2267 assert(v2->is_constant_double(), ""); | |
2268 assert(((ConstantDoubleValue*)v1)->value() == ((ConstantDoubleValue*)v2)->value(), ""); | |
2269 } else if (v1->is_constant_long()) { | |
2270 assert(v2->is_constant_long(), ""); | |
2271 assert(((ConstantLongValue*)v1)->value() == ((ConstantLongValue*)v2)->value(), ""); | |
2272 } else if (v1->is_constant_oop()) { | |
2273 assert(v2->is_constant_oop(), ""); | |
2274 assert(((ConstantOopWriteValue*)v1)->value() == ((ConstantOopWriteValue*)v2)->value(), ""); | |
2275 } else { | |
2276 ShouldNotReachHere(); | |
2277 } | |
2278 } | |
2279 | |
2280 void assert_equal(MonitorValue* m1, MonitorValue* m2) { | |
2281 assert_equal(m1->owner(), m2->owner()); | |
2282 assert_equal(m1->basic_lock(), m2->basic_lock()); | |
2283 } | |
2284 | |
2285 void assert_equal(IRScopeDebugInfo* d1, IRScopeDebugInfo* d2) { | |
2286 assert(d1->scope() == d2->scope(), "not equal"); | |
2287 assert(d1->bci() == d2->bci(), "not equal"); | |
2288 | |
2289 if (d1->locals() != NULL) { | |
2290 assert(d1->locals() != NULL && d2->locals() != NULL, "not equal"); | |
2291 assert(d1->locals()->length() == d2->locals()->length(), "not equal"); | |
2292 for (int i = 0; i < d1->locals()->length(); i++) { | |
2293 assert_equal(d1->locals()->at(i), d2->locals()->at(i)); | |
2294 } | |
2295 } else { | |
2296 assert(d1->locals() == NULL && d2->locals() == NULL, "not equal"); | |
2297 } | |
2298 | |
2299 if (d1->expressions() != NULL) { | |
2300 assert(d1->expressions() != NULL && d2->expressions() != NULL, "not equal"); | |
2301 assert(d1->expressions()->length() == d2->expressions()->length(), "not equal"); | |
2302 for (int i = 0; i < d1->expressions()->length(); i++) { | |
2303 assert_equal(d1->expressions()->at(i), d2->expressions()->at(i)); | |
2304 } | |
2305 } else { | |
2306 assert(d1->expressions() == NULL && d2->expressions() == NULL, "not equal"); | |
2307 } | |
2308 | |
2309 if (d1->monitors() != NULL) { | |
2310 assert(d1->monitors() != NULL && d2->monitors() != NULL, "not equal"); | |
2311 assert(d1->monitors()->length() == d2->monitors()->length(), "not equal"); | |
2312 for (int i = 0; i < d1->monitors()->length(); i++) { | |
2313 assert_equal(d1->monitors()->at(i), d2->monitors()->at(i)); | |
2314 } | |
2315 } else { | |
2316 assert(d1->monitors() == NULL && d2->monitors() == NULL, "not equal"); | |
2317 } | |
2318 | |
2319 if (d1->caller() != NULL) { | |
2320 assert(d1->caller() != NULL && d2->caller() != NULL, "not equal"); | |
2321 assert_equal(d1->caller(), d2->caller()); | |
2322 } else { | |
2323 assert(d1->caller() == NULL && d2->caller() == NULL, "not equal"); | |
2324 } | |
2325 } | |
2326 | |
2327 void check_stack_depth(CodeEmitInfo* info, int stack_end) { | |
1819 | 2328 if (info->stack()->bci() != SynchronizationEntryBCI && !info->scope()->method()->is_native()) { |
2329 Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->stack()->bci()); | |
0 | 2330 switch (code) { |
2331 case Bytecodes::_ifnull : // fall through | |
2332 case Bytecodes::_ifnonnull : // fall through | |
2333 case Bytecodes::_ifeq : // fall through | |
2334 case Bytecodes::_ifne : // fall through | |
2335 case Bytecodes::_iflt : // fall through | |
2336 case Bytecodes::_ifge : // fall through | |
2337 case Bytecodes::_ifgt : // fall through | |
2338 case Bytecodes::_ifle : // fall through | |
2339 case Bytecodes::_if_icmpeq : // fall through | |
2340 case Bytecodes::_if_icmpne : // fall through | |
2341 case Bytecodes::_if_icmplt : // fall through | |
2342 case Bytecodes::_if_icmpge : // fall through | |
2343 case Bytecodes::_if_icmpgt : // fall through | |
2344 case Bytecodes::_if_icmple : // fall through | |
2345 case Bytecodes::_if_acmpeq : // fall through | |
2346 case Bytecodes::_if_acmpne : | |
2347 assert(stack_end >= -Bytecodes::depth(code), "must have non-empty expression stack at if bytecode"); | |
2348 break; | |
2349 } | |
2350 } | |
2351 } | |
2352 | |
2353 #endif // ASSERT | |
2354 | |
2355 | |
2356 IntervalWalker* LinearScan::init_compute_oop_maps() { | |
2357 // setup lists of potential oops for walking | |
2358 Interval* oop_intervals; | |
2359 Interval* non_oop_intervals; | |
2360 | |
2361 create_unhandled_lists(&oop_intervals, &non_oop_intervals, is_oop_interval, NULL); | |
2362 | |
2363 // intervals that have no oops inside need not to be processed | |
2364 // to ensure a walking until the last instruction id, add a dummy interval | |
2365 // with a high operation id | |
2366 non_oop_intervals = new Interval(any_reg); | |
2367 non_oop_intervals->add_range(max_jint - 2, max_jint - 1); | |
2368 | |
2369 return new IntervalWalker(this, oop_intervals, non_oop_intervals); | |
2370 } | |
2371 | |
2372 | |
2373 OopMap* LinearScan::compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site) { | |
2374 TRACE_LINEAR_SCAN(3, tty->print_cr("creating oop map at op_id %d", op->id())); | |
2375 | |
2376 // walk before the current operation -> intervals that start at | |
2377 // the operation (= output operands of the operation) are not | |
2378 // included in the oop map | |
2379 iw->walk_before(op->id()); | |
2380 | |
2381 int frame_size = frame_map()->framesize(); | |
2382 int arg_count = frame_map()->oop_map_arg_count(); | |
2383 OopMap* map = new OopMap(frame_size, arg_count); | |
2384 | |
2385 // Check if this is a patch site. | |
2386 bool is_patch_info = false; | |
2387 if (op->code() == lir_move) { | |
2388 assert(!is_call_site, "move must not be a call site"); | |
2389 assert(op->as_Op1() != NULL, "move must be LIR_Op1"); | |
2390 LIR_Op1* move = (LIR_Op1*)op; | |
2391 | |
2392 is_patch_info = move->patch_code() != lir_patch_none; | |
2393 } | |
2394 | |
2395 // Iterate through active intervals | |
2396 for (Interval* interval = iw->active_first(fixedKind); interval != Interval::end(); interval = interval->next()) { | |
2397 int assigned_reg = interval->assigned_reg(); | |
2398 | |
2399 assert(interval->current_from() <= op->id() && op->id() <= interval->current_to(), "interval should not be active otherwise"); | |
2400 assert(interval->assigned_regHi() == any_reg, "oop must be single word"); | |
2401 assert(interval->reg_num() >= LIR_OprDesc::vreg_base, "fixed interval found"); | |
2402 | |
2403 // Check if this range covers the instruction. Intervals that | |
2404 // start or end at the current operation are not included in the | |
2405 // oop map, except in the case of patching moves. For patching | |
2406 // moves, any intervals which end at this instruction are included | |
2407 // in the oop map since we may safepoint while doing the patch | |
2408 // before we've consumed the inputs. | |
2409 if (is_patch_info || op->id() < interval->current_to()) { | |
2410 | |
2411 // caller-save registers must not be included into oop-maps at calls | |
2412 assert(!is_call_site || assigned_reg >= nof_regs || !is_caller_save(assigned_reg), "interval is in a caller-save register at a call -> register will be overwritten"); | |
2413 | |
2414 VMReg name = vm_reg_for_interval(interval); | |
3908
7588156f5cf9
7051798: SA-JDI: NPE in Frame.addressOfStackSlot(Frame.java:244)
never
parents:
2426
diff
changeset
|
2415 set_oop(map, name); |
0 | 2416 |
2417 // Spill optimization: when the stack value is guaranteed to be always correct, | |
2418 // then it must be added to the oop map even if the interval is currently in a register | |
2419 if (interval->always_in_memory() && | |
2420 op->id() > interval->spill_definition_pos() && | |
2421 interval->assigned_reg() != interval->canonical_spill_slot()) { | |
2422 assert(interval->spill_definition_pos() > 0, "position not set correctly"); | |
2423 assert(interval->canonical_spill_slot() >= LinearScan::nof_regs, "no spill slot assigned"); | |
2424 assert(interval->assigned_reg() < LinearScan::nof_regs, "interval is on stack, so stack slot is registered twice"); | |
2425 | |
3908
7588156f5cf9
7051798: SA-JDI: NPE in Frame.addressOfStackSlot(Frame.java:244)
never
parents:
2426
diff
changeset
|
2426 set_oop(map, frame_map()->slot_regname(interval->canonical_spill_slot() - LinearScan::nof_regs)); |
0 | 2427 } |
2428 } | |
2429 } | |
2430 | |
2431 // add oops from lock stack | |
2432 assert(info->stack() != NULL, "CodeEmitInfo must always have a stack"); | |
1819 | 2433 int locks_count = info->stack()->total_locks_size(); |
0 | 2434 for (int i = 0; i < locks_count; i++) { |
3908
7588156f5cf9
7051798: SA-JDI: NPE in Frame.addressOfStackSlot(Frame.java:244)
never
parents:
2426
diff
changeset
|
2435 set_oop(map, frame_map()->monitor_object_regname(i)); |
0 | 2436 } |
2437 | |
2438 return map; | |
2439 } | |
2440 | |
2441 | |
2442 void LinearScan::compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op) { | |
2443 assert(visitor.info_count() > 0, "no oop map needed"); | |
2444 | |
2445 // compute oop_map only for first CodeEmitInfo | |
2446 // because it is (in most cases) equal for all other infos of the same operation | |
2447 CodeEmitInfo* first_info = visitor.info_at(0); | |
2448 OopMap* first_oop_map = compute_oop_map(iw, op, first_info, visitor.has_call()); | |
2449 | |
2450 for (int i = 0; i < visitor.info_count(); i++) { | |
2451 CodeEmitInfo* info = visitor.info_at(i); | |
2452 OopMap* oop_map = first_oop_map; | |
2453 | |
2454 if (info->stack()->locks_size() != first_info->stack()->locks_size()) { | |
2455 // this info has a different number of locks then the precomputed oop map | |
2456 // (possible for lock and unlock instructions) -> compute oop map with | |
2457 // correct lock information | |
2458 oop_map = compute_oop_map(iw, op, info, visitor.has_call()); | |
2459 } | |
2460 | |
2461 if (info->_oop_map == NULL) { | |
2462 info->_oop_map = oop_map; | |
2463 } else { | |
2464 // a CodeEmitInfo can not be shared between different LIR-instructions | |
2465 // because interval splitting can occur anywhere between two instructions | |
2466 // and so the oop maps must be different | |
2467 // -> check if the already set oop_map is exactly the one calculated for this operation | |
2468 assert(info->_oop_map == oop_map, "same CodeEmitInfo used for multiple LIR instructions"); | |
2469 } | |
2470 } | |
2471 } | |
2472 | |
2473 | |
2474 // frequently used constants | |
4948
c7401dcad8bf
7143038: SIGSEGV in assert_equal / LinearScan::assign_reg_num
roland
parents:
3999
diff
changeset
|
2475 // Allocate them with new so they are never destroyed (otherwise, a |
c7401dcad8bf
7143038: SIGSEGV in assert_equal / LinearScan::assign_reg_num
roland
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3999
diff
changeset
|
2476 // forced exit could destroy these objects while they are still in |
c7401dcad8bf
7143038: SIGSEGV in assert_equal / LinearScan::assign_reg_num
roland
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3999
diff
changeset
|
2477 // use). |
6197 | 2478 ConstantOopWriteValue* LinearScan::_oop_null_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantOopWriteValue(NULL); |
2479 ConstantIntValue* LinearScan::_int_m1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(-1); | |
2480 ConstantIntValue* LinearScan::_int_0_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(0); | |
2481 ConstantIntValue* LinearScan::_int_1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(1); | |
2482 ConstantIntValue* LinearScan::_int_2_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(2); | |
2483 LocationValue* _illegal_value = new (ResourceObj::C_HEAP, mtCompiler) LocationValue(Location()); | |
0 | 2484 |
2485 void LinearScan::init_compute_debug_info() { | |
2486 // cache for frequently used scope values | |
2487 // (cpu registers and stack slots) | |
2488 _scope_value_cache = ScopeValueArray((LinearScan::nof_cpu_regs + frame_map()->argcount() + max_spills()) * 2, NULL); | |
2489 } | |
2490 | |
2491 MonitorValue* LinearScan::location_for_monitor_index(int monitor_index) { | |
2492 Location loc; | |
2493 if (!frame_map()->location_for_monitor_object(monitor_index, &loc)) { | |
2494 bailout("too large frame"); | |
2495 } | |
2496 ScopeValue* object_scope_value = new LocationValue(loc); | |
2497 | |
2498 if (!frame_map()->location_for_monitor_lock(monitor_index, &loc)) { | |
2499 bailout("too large frame"); | |
2500 } | |
2501 return new MonitorValue(object_scope_value, loc); | |
2502 } | |
2503 | |
2504 LocationValue* LinearScan::location_for_name(int name, Location::Type loc_type) { | |
2505 Location loc; | |
2506 if (!frame_map()->locations_for_slot(name, loc_type, &loc)) { | |
2507 bailout("too large frame"); | |
2508 } | |
2509 return new LocationValue(loc); | |
2510 } | |
2511 | |
2512 | |
2513 int LinearScan::append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) { | |
2514 assert(opr->is_constant(), "should not be called otherwise"); | |
2515 | |
2516 LIR_Const* c = opr->as_constant_ptr(); | |
2517 BasicType t = c->type(); | |
2518 switch (t) { | |
2519 case T_OBJECT: { | |
2520 jobject value = c->as_jobject(); | |
2521 if (value == NULL) { | |
4948
c7401dcad8bf
7143038: SIGSEGV in assert_equal / LinearScan::assign_reg_num
roland
parents:
3999
diff
changeset
|
2522 scope_values->append(_oop_null_scope_value); |
0 | 2523 } else { |
2524 scope_values->append(new ConstantOopWriteValue(c->as_jobject())); | |
2525 } | |
2526 return 1; | |
2527 } | |
2528 | |
2529 case T_INT: // fall through | |
2530 case T_FLOAT: { | |
2531 int value = c->as_jint_bits(); | |
2532 switch (value) { | |
4948
c7401dcad8bf
7143038: SIGSEGV in assert_equal / LinearScan::assign_reg_num
roland
parents:
3999
diff
changeset
|
2533 case -1: scope_values->append(_int_m1_scope_value); break; |
c7401dcad8bf
7143038: SIGSEGV in assert_equal / LinearScan::assign_reg_num
roland
parents:
3999
diff
changeset
|
2534 case 0: scope_values->append(_int_0_scope_value); break; |
c7401dcad8bf
7143038: SIGSEGV in assert_equal / LinearScan::assign_reg_num
roland
parents:
3999
diff
changeset
|
2535 case 1: scope_values->append(_int_1_scope_value); break; |
c7401dcad8bf
7143038: SIGSEGV in assert_equal / LinearScan::assign_reg_num
roland
parents:
3999
diff
changeset
|
2536 case 2: scope_values->append(_int_2_scope_value); break; |
0 | 2537 default: scope_values->append(new ConstantIntValue(c->as_jint_bits())); break; |
2538 } | |
2539 return 1; | |
2540 } | |
2541 | |
2542 case T_LONG: // fall through | |
2543 case T_DOUBLE: { | |
1060 | 2544 #ifdef _LP64 |
4948
c7401dcad8bf
7143038: SIGSEGV in assert_equal / LinearScan::assign_reg_num
roland
parents:
3999
diff
changeset
|
2545 scope_values->append(_int_0_scope_value); |
1060 | 2546 scope_values->append(new ConstantLongValue(c->as_jlong_bits())); |
2547 #else | |
0 | 2548 if (hi_word_offset_in_bytes > lo_word_offset_in_bytes) { |
2549 scope_values->append(new ConstantIntValue(c->as_jint_hi_bits())); | |
2550 scope_values->append(new ConstantIntValue(c->as_jint_lo_bits())); | |
2551 } else { | |
2552 scope_values->append(new ConstantIntValue(c->as_jint_lo_bits())); | |
2553 scope_values->append(new ConstantIntValue(c->as_jint_hi_bits())); | |
2554 } | |
1060 | 2555 #endif |
0 | 2556 return 2; |
2557 } | |
2558 | |
1297
c466efa608d5
6932496: c1: deoptimization of jsr subroutine fails on sparcv9
roland
parents:
1060
diff
changeset
|
2559 case T_ADDRESS: { |
c466efa608d5
6932496: c1: deoptimization of jsr subroutine fails on sparcv9
roland
parents:
1060
diff
changeset
|
2560 #ifdef _LP64 |
c466efa608d5
6932496: c1: deoptimization of jsr subroutine fails on sparcv9
roland
parents:
1060
diff
changeset
|
2561 scope_values->append(new ConstantLongValue(c->as_jint())); |
c466efa608d5
6932496: c1: deoptimization of jsr subroutine fails on sparcv9
roland
parents:
1060
diff
changeset
|
2562 #else |
c466efa608d5
6932496: c1: deoptimization of jsr subroutine fails on sparcv9
roland
parents:
1060
diff
changeset
|
2563 scope_values->append(new ConstantIntValue(c->as_jint())); |
c466efa608d5
6932496: c1: deoptimization of jsr subroutine fails on sparcv9
roland
parents:
1060
diff
changeset
|
2564 #endif |
c466efa608d5
6932496: c1: deoptimization of jsr subroutine fails on sparcv9
roland
parents:
1060
diff
changeset
|
2565 return 1; |
c466efa608d5
6932496: c1: deoptimization of jsr subroutine fails on sparcv9
roland
parents:
1060
diff
changeset
|
2566 } |
c466efa608d5
6932496: c1: deoptimization of jsr subroutine fails on sparcv9
roland
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1060
diff
changeset
|
2567 |
0 | 2568 default: |
2569 ShouldNotReachHere(); | |
304 | 2570 return -1; |
0 | 2571 } |
2572 } | |
2573 | |
2574 int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) { | |
2575 if (opr->is_single_stack()) { | |
2576 int stack_idx = opr->single_stack_ix(); | |
2577 bool is_oop = opr->is_oop_register(); | |
2578 int cache_idx = (stack_idx + LinearScan::nof_cpu_regs) * 2 + (is_oop ? 1 : 0); | |
2579 | |
2580 ScopeValue* sv = _scope_value_cache.at(cache_idx); | |
2581 if (sv == NULL) { | |
2582 Location::Type loc_type = is_oop ? Location::oop : Location::normal; | |
2583 sv = location_for_name(stack_idx, loc_type); | |
2584 _scope_value_cache.at_put(cache_idx, sv); | |
2585 } | |
2586 | |
2587 // check if cached value is correct | |
2588 DEBUG_ONLY(assert_equal(sv, location_for_name(stack_idx, is_oop ? Location::oop : Location::normal))); | |
2589 | |
2590 scope_values->append(sv); | |
2591 return 1; | |
2592 | |
2593 } else if (opr->is_single_cpu()) { | |
2594 bool is_oop = opr->is_oop_register(); | |
2595 int cache_idx = opr->cpu_regnr() * 2 + (is_oop ? 1 : 0); | |
1060 | 2596 Location::Type int_loc_type = NOT_LP64(Location::normal) LP64_ONLY(Location::int_in_long); |
0 | 2597 |
2598 ScopeValue* sv = _scope_value_cache.at(cache_idx); | |
2599 if (sv == NULL) { | |
1060 | 2600 Location::Type loc_type = is_oop ? Location::oop : int_loc_type; |
0 | 2601 VMReg rname = frame_map()->regname(opr); |
2602 sv = new LocationValue(Location::new_reg_loc(loc_type, rname)); | |
2603 _scope_value_cache.at_put(cache_idx, sv); | |
2604 } | |
2605 | |
2606 // check if cached value is correct | |
1060 | 2607 DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : int_loc_type, frame_map()->regname(opr))))); |
0 | 2608 |
2609 scope_values->append(sv); | |
2610 return 1; | |
2611 | |
304 | 2612 #ifdef X86 |
0 | 2613 } else if (opr->is_single_xmm()) { |
2614 VMReg rname = opr->as_xmm_float_reg()->as_VMReg(); | |
2615 LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname)); | |
2616 | |
2617 scope_values->append(sv); | |
2618 return 1; | |
2619 #endif | |
2620 | |
2621 } else if (opr->is_single_fpu()) { | |
304 | 2622 #ifdef X86 |
0 | 2623 // the exact location of fpu stack values is only known |
2624 // during fpu stack allocation, so the stack allocator object | |
2625 // must be present | |
2626 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)"); | |
2627 assert(_fpu_stack_allocator != NULL, "must be present"); | |
2628 opr = _fpu_stack_allocator->to_fpu_stack(opr); | |
2629 #endif | |
2630 | |
2631 Location::Type loc_type = float_saved_as_double ? Location::float_in_dbl : Location::normal; | |
2632 VMReg rname = frame_map()->fpu_regname(opr->fpu_regnr()); | |
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2633 #ifndef __SOFTFP__ |
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2634 #ifndef VM_LITTLE_ENDIAN |
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2635 if (! float_saved_as_double) { |
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2636 // On big endian system, we may have an issue if float registers use only |
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2637 // the low half of the (same) double registers. |
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2638 // Both the float and the double could have the same regnr but would correspond |
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2639 // to two different addresses once saved. |
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2640 |
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2641 // get next safely (no assertion checks) |
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2642 VMReg next = VMRegImpl::as_VMReg(1+rname->value()); |
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2643 if (next->is_reg() && |
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2644 (next->as_FloatRegister() == rname->as_FloatRegister())) { |
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2645 // the back-end does use the same numbering for the double and the float |
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2646 rname = next; // VMReg for the low bits, e.g. the real VMReg for the float |
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2647 } |
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2648 } |
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2649 #endif |
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2650 #endif |
0 | 2651 LocationValue* sv = new LocationValue(Location::new_reg_loc(loc_type, rname)); |
2652 | |
2653 scope_values->append(sv); | |
2654 return 1; | |
2655 | |
2656 } else { | |
2657 // double-size operands | |
2658 | |
2659 ScopeValue* first; | |
2660 ScopeValue* second; | |
2661 | |
2662 if (opr->is_double_stack()) { | |
304 | 2663 #ifdef _LP64 |
2664 Location loc1; | |
2665 Location::Type loc_type = opr->type() == T_LONG ? Location::lng : Location::dbl; | |
2666 if (!frame_map()->locations_for_slot(opr->double_stack_ix(), loc_type, &loc1, NULL)) { | |
2667 bailout("too large frame"); | |
2668 } | |
2669 // Does this reverse on x86 vs. sparc? | |
2670 first = new LocationValue(loc1); | |
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2671 second = _int_0_scope_value; |
304 | 2672 #else |
0 | 2673 Location loc1, loc2; |
2674 if (!frame_map()->locations_for_slot(opr->double_stack_ix(), Location::normal, &loc1, &loc2)) { | |
2675 bailout("too large frame"); | |
2676 } | |
2677 first = new LocationValue(loc1); | |
2678 second = new LocationValue(loc2); | |
304 | 2679 #endif // _LP64 |
0 | 2680 |
2681 } else if (opr->is_double_cpu()) { | |
2682 #ifdef _LP64 | |
2683 VMReg rname_first = opr->as_register_lo()->as_VMReg(); | |
2684 first = new LocationValue(Location::new_reg_loc(Location::lng, rname_first)); | |
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2685 second = _int_0_scope_value; |
0 | 2686 #else |
2687 VMReg rname_first = opr->as_register_lo()->as_VMReg(); | |
2688 VMReg rname_second = opr->as_register_hi()->as_VMReg(); | |
2689 | |
2690 if (hi_word_offset_in_bytes < lo_word_offset_in_bytes) { | |
2691 // lo/hi and swapped relative to first and second, so swap them | |
2692 VMReg tmp = rname_first; | |
2693 rname_first = rname_second; | |
2694 rname_second = tmp; | |
2695 } | |
2696 | |
2697 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first)); | |
2698 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second)); | |
304 | 2699 #endif //_LP64 |
2700 | |
2701 | |
2702 #ifdef X86 | |
0 | 2703 } else if (opr->is_double_xmm()) { |
2704 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation"); | |
2705 VMReg rname_first = opr->as_xmm_double_reg()->as_VMReg(); | |
1369 | 2706 # ifdef _LP64 |
2707 first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first)); | |
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2708 second = _int_0_scope_value; |
1369 | 2709 # else |
0 | 2710 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first)); |
2711 // %%% This is probably a waste but we'll keep things as they were for now | |
2712 if (true) { | |
2713 VMReg rname_second = rname_first->next(); | |
2714 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second)); | |
2715 } | |
1369 | 2716 # endif |
0 | 2717 #endif |
2718 | |
2719 } else if (opr->is_double_fpu()) { | |
2720 // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of | |
304 | 2721 // the double as float registers in the native ordering. On X86, |
0 | 2722 // fpu_regnrLo is a FPU stack slot whose VMReg represents |
2723 // the low-order word of the double and fpu_regnrLo + 1 is the | |
2724 // name for the other half. *first and *second must represent the | |
2725 // least and most significant words, respectively. | |
2726 | |
304 | 2727 #ifdef X86 |
0 | 2728 // the exact location of fpu stack values is only known |
2729 // during fpu stack allocation, so the stack allocator object | |
2730 // must be present | |
2731 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)"); | |
2732 assert(_fpu_stack_allocator != NULL, "must be present"); | |
2733 opr = _fpu_stack_allocator->to_fpu_stack(opr); | |
2734 | |
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2735 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)"); |
0 | 2736 #endif |
2737 #ifdef SPARC | |
2738 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)"); | |
2739 #endif | |
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2740 #ifdef ARM |
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2741 assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)"); |
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2742 #endif |
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2743 #ifdef PPC |
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2744 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)"); |
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2745 #endif |
0 | 2746 |
2345
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2747 #ifdef VM_LITTLE_ENDIAN |
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2748 VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrLo()); |
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2749 #else |
0 | 2750 VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi()); |
2345
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2751 #endif |
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2752 |
1369 | 2753 #ifdef _LP64 |
2754 first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first)); | |
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2755 second = _int_0_scope_value; |
1369 | 2756 #else |
0 | 2757 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first)); |
2758 // %%% This is probably a waste but we'll keep things as they were for now | |
2759 if (true) { | |
2760 VMReg rname_second = rname_first->next(); | |
2761 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second)); | |
2762 } | |
1369 | 2763 #endif |
0 | 2764 |
2765 } else { | |
2766 ShouldNotReachHere(); | |
2767 first = NULL; | |
2768 second = NULL; | |
2769 } | |
2770 | |
2771 assert(first != NULL && second != NULL, "must be set"); | |
2772 // The convention the interpreter uses is that the second local | |
2773 // holds the first raw word of the native double representation. | |
2774 // This is actually reasonable, since locals and stack arrays | |
2775 // grow downwards in all implementations. | |
2776 // (If, on some machine, the interpreter's Java locals or stack | |
2777 // were to grow upwards, the embedded doubles would be word-swapped.) | |
2778 scope_values->append(second); | |
2779 scope_values->append(first); | |
2780 return 2; | |
2781 } | |
2782 } | |
2783 | |
2784 | |
2785 int LinearScan::append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values) { | |
2786 if (value != NULL) { | |
2787 LIR_Opr opr = value->operand(); | |
2788 Constant* con = value->as_Constant(); | |
2789 | |
2790 assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands (or illegal if constant is optimized away)"); | |
2791 assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands"); | |
2792 | |
2793 if (con != NULL && !con->is_pinned() && !opr->is_constant()) { | |
2794 // Unpinned constants may have a virtual operand for a part of the lifetime | |
2795 // or may be illegal when it was optimized away, | |
2796 // so always use a constant operand | |
2797 opr = LIR_OprFact::value_type(con->type()); | |
2798 } | |
2799 assert(opr->is_virtual() || opr->is_constant(), "other cases not allowed here"); | |
2800 | |
2801 if (opr->is_virtual()) { | |
2802 LIR_OpVisitState::OprMode mode = LIR_OpVisitState::inputMode; | |
2803 | |
2804 BlockBegin* block = block_of_op_with_id(op_id); | |
2805 if (block->number_of_sux() == 1 && op_id == block->last_lir_instruction_id()) { | |
2806 // generating debug information for the last instruction of a block. | |
2807 // if this instruction is a branch, spill moves are inserted before this branch | |
2808 // and so the wrong operand would be returned (spill moves at block boundaries are not | |
2809 // considered in the live ranges of intervals) | |
2810 // Solution: use the first op_id of the branch target block instead. | |
2811 if (block->lir()->instructions_list()->last()->as_OpBranch() != NULL) { | |
2812 if (block->live_out().at(opr->vreg_number())) { | |
2813 op_id = block->sux_at(0)->first_lir_instruction_id(); | |
2814 mode = LIR_OpVisitState::outputMode; | |
2815 } | |
2816 } | |
2817 } | |
2818 | |
2819 // Get current location of operand | |
2820 // The operand must be live because debug information is considered when building the intervals | |
2821 // if the interval is not live, color_lir_opr will cause an assertion failure | |
2822 opr = color_lir_opr(opr, op_id, mode); | |
2823 assert(!has_call(op_id) || opr->is_stack() || !is_caller_save(reg_num(opr)), "can not have caller-save register operands at calls"); | |
2824 | |
2825 // Append to ScopeValue array | |
2826 return append_scope_value_for_operand(opr, scope_values); | |
2827 | |
2828 } else { | |
2829 assert(value->as_Constant() != NULL, "all other instructions have only virtual operands"); | |
2830 assert(opr->is_constant(), "operand must be constant"); | |
2831 | |
2832 return append_scope_value_for_constant(opr, scope_values); | |
2833 } | |
2834 } else { | |
2835 // append a dummy value because real value not needed | |
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2836 scope_values->append(_illegal_value); |
0 | 2837 return 1; |
2838 } | |
2839 } | |
2840 | |
2841 | |
1819 | 2842 IRScopeDebugInfo* LinearScan::compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state) { |
0 | 2843 IRScopeDebugInfo* caller_debug_info = NULL; |
1819 | 2844 |
2845 ValueStack* caller_state = cur_state->caller_state(); | |
0 | 2846 if (caller_state != NULL) { |
2847 // process recursively to compute outermost scope first | |
1819 | 2848 caller_debug_info = compute_debug_info_for_scope(op_id, cur_scope->caller(), caller_state, innermost_state); |
0 | 2849 } |
2850 | |
2851 // initialize these to null. | |
2852 // If we don't need deopt info or there are no locals, expressions or monitors, | |
2853 // then these get recorded as no information and avoids the allocation of 0 length arrays. | |
2854 GrowableArray<ScopeValue*>* locals = NULL; | |
2855 GrowableArray<ScopeValue*>* expressions = NULL; | |
2856 GrowableArray<MonitorValue*>* monitors = NULL; | |
2857 | |
2858 // describe local variable values | |
1819 | 2859 int nof_locals = cur_state->locals_size(); |
0 | 2860 if (nof_locals > 0) { |
2861 locals = new GrowableArray<ScopeValue*>(nof_locals); | |
2862 | |
2863 int pos = 0; | |
2864 while (pos < nof_locals) { | |
2865 assert(pos < cur_state->locals_size(), "why not?"); | |
2866 | |
2867 Value local = cur_state->local_at(pos); | |
2868 pos += append_scope_value(op_id, local, locals); | |
2869 | |
2870 assert(locals->length() == pos, "must match"); | |
2871 } | |
2872 assert(locals->length() == cur_scope->method()->max_locals(), "wrong number of locals"); | |
2873 assert(locals->length() == cur_state->locals_size(), "wrong number of locals"); | |
1819 | 2874 } else if (cur_scope->method()->max_locals() > 0) { |
2875 assert(cur_state->kind() == ValueStack::EmptyExceptionState, "should be"); | |
2876 nof_locals = cur_scope->method()->max_locals(); | |
2877 locals = new GrowableArray<ScopeValue*>(nof_locals); | |
2878 for(int i = 0; i < nof_locals; i++) { | |
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2879 locals->append(_illegal_value); |
1819 | 2880 } |
2881 } | |
0 | 2882 |
2883 // describe expression stack | |
1819 | 2884 int nof_stack = cur_state->stack_size(); |
0 | 2885 if (nof_stack > 0) { |
2886 expressions = new GrowableArray<ScopeValue*>(nof_stack); | |
2887 | |
1819 | 2888 int pos = 0; |
2889 while (pos < nof_stack) { | |
2890 Value expression = cur_state->stack_at_inc(pos); | |
0 | 2891 append_scope_value(op_id, expression, expressions); |
2892 | |
1819 | 2893 assert(expressions->length() == pos, "must match"); |
2894 } | |
2895 assert(expressions->length() == cur_state->stack_size(), "wrong number of stack entries"); | |
0 | 2896 } |
2897 | |
2898 // describe monitors | |
1819 | 2899 int nof_locks = cur_state->locks_size(); |
0 | 2900 if (nof_locks > 0) { |
1819 | 2901 int lock_offset = cur_state->caller_state() != NULL ? cur_state->caller_state()->total_locks_size() : 0; |
0 | 2902 monitors = new GrowableArray<MonitorValue*>(nof_locks); |
1819 | 2903 for (int i = 0; i < nof_locks; i++) { |
2904 monitors->append(location_for_monitor_index(lock_offset + i)); | |
2905 } | |
2906 } | |
2907 | |
2908 return new IRScopeDebugInfo(cur_scope, cur_state->bci(), locals, expressions, monitors, caller_debug_info); | |
0 | 2909 } |
2910 | |
2911 | |
2912 void LinearScan::compute_debug_info(CodeEmitInfo* info, int op_id) { | |
2913 TRACE_LINEAR_SCAN(3, tty->print_cr("creating debug information at op_id %d", op_id)); | |
2914 | |
2915 IRScope* innermost_scope = info->scope(); | |
2916 ValueStack* innermost_state = info->stack(); | |
2917 | |
2918 assert(innermost_scope != NULL && innermost_state != NULL, "why is it missing?"); | |
2919 | |
1819 | 2920 DEBUG_ONLY(check_stack_depth(info, innermost_state->stack_size())); |
0 | 2921 |
2922 if (info->_scope_debug_info == NULL) { | |
2923 // compute debug information | |
1819 | 2924 info->_scope_debug_info = compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state); |
0 | 2925 } else { |
2926 // debug information already set. Check that it is correct from the current point of view | |
1819 | 2927 DEBUG_ONLY(assert_equal(info->_scope_debug_info, compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state))); |
0 | 2928 } |
2929 } | |
2930 | |
2931 | |
2932 void LinearScan::assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw) { | |
2933 LIR_OpVisitState visitor; | |
2934 int num_inst = instructions->length(); | |
2935 bool has_dead = false; | |
2936 | |
2937 for (int j = 0; j < num_inst; j++) { | |
2938 LIR_Op* op = instructions->at(j); | |
2939 if (op == NULL) { // this can happen when spill-moves are removed in eliminate_spill_moves | |
2940 has_dead = true; | |
2941 continue; | |
2942 } | |
2943 int op_id = op->id(); | |
2944 | |
2945 // visit instruction to get list of operands | |
2946 visitor.visit(op); | |
2947 | |
2948 // iterate all modes of the visitor and process all virtual operands | |
2949 for_each_visitor_mode(mode) { | |
2950 int n = visitor.opr_count(mode); | |
2951 for (int k = 0; k < n; k++) { | |
2952 LIR_Opr opr = visitor.opr_at(mode, k); | |
2953 if (opr->is_virtual_register()) { | |
2954 visitor.set_opr_at(mode, k, color_lir_opr(opr, op_id, mode)); | |
2955 } | |
2956 } | |
2957 } | |
2958 | |
2959 if (visitor.info_count() > 0) { | |
2960 // exception handling | |
2961 if (compilation()->has_exception_handlers()) { | |
2962 XHandlers* xhandlers = visitor.all_xhandler(); | |
2963 int n = xhandlers->length(); | |
2964 for (int k = 0; k < n; k++) { | |
2965 XHandler* handler = xhandlers->handler_at(k); | |
2966 if (handler->entry_code() != NULL) { | |
2967 assign_reg_num(handler->entry_code()->instructions_list(), NULL); | |
2968 } | |
2969 } | |
2970 } else { | |
2971 assert(visitor.all_xhandler()->length() == 0, "missed exception handler"); | |
2972 } | |
2973 | |
2974 // compute oop map | |
2975 assert(iw != NULL, "needed for compute_oop_map"); | |
2976 compute_oop_map(iw, visitor, op); | |
2977 | |
2978 // compute debug information | |
2979 if (!use_fpu_stack_allocation()) { | |
2980 // compute debug information if fpu stack allocation is not needed. | |
2981 // when fpu stack allocation is needed, the debug information can not | |
2982 // be computed here because the exact location of fpu operands is not known | |
2983 // -> debug information is created inside the fpu stack allocator | |
2984 int n = visitor.info_count(); | |
2985 for (int k = 0; k < n; k++) { | |
2986 compute_debug_info(visitor.info_at(k), op_id); | |
2987 } | |
2988 } | |
2989 } | |
2990 | |
2991 #ifdef ASSERT | |
2992 // make sure we haven't made the op invalid. | |
2993 op->verify(); | |
2994 #endif | |
2995 | |
2996 // remove useless moves | |
2997 if (op->code() == lir_move) { | |
2998 assert(op->as_Op1() != NULL, "move must be LIR_Op1"); | |
2999 LIR_Op1* move = (LIR_Op1*)op; | |
3000 LIR_Opr src = move->in_opr(); | |
3001 LIR_Opr dst = move->result_opr(); | |
3002 if (dst == src || | |
3003 !dst->is_pointer() && !src->is_pointer() && | |
3004 src->is_same_register(dst)) { | |
3005 instructions->at_put(j, NULL); | |
3006 has_dead = true; | |
3007 } | |
3008 } | |
3009 } | |
3010 | |
3011 if (has_dead) { | |
3012 // iterate all instructions of the block and remove all null-values. | |
3013 int insert_point = 0; | |
3014 for (int j = 0; j < num_inst; j++) { | |
3015 LIR_Op* op = instructions->at(j); | |
3016 if (op != NULL) { | |
3017 if (insert_point != j) { | |
3018 instructions->at_put(insert_point, op); | |
3019 } | |
3020 insert_point++; | |
3021 } | |
3022 } | |
3023 instructions->truncate(insert_point); | |
3024 } | |
3025 } | |
3026 | |
3027 void LinearScan::assign_reg_num() { | |
3028 TIME_LINEAR_SCAN(timer_assign_reg_num); | |
3029 | |
3030 init_compute_debug_info(); | |
3031 IntervalWalker* iw = init_compute_oop_maps(); | |
3032 | |
3033 int num_blocks = block_count(); | |
3034 for (int i = 0; i < num_blocks; i++) { | |
3035 BlockBegin* block = block_at(i); | |
3036 assign_reg_num(block->lir()->instructions_list(), iw); | |
3037 } | |
3038 } | |
3039 | |
3040 | |
3041 void LinearScan::do_linear_scan() { | |
3042 NOT_PRODUCT(_total_timer.begin_method()); | |
3043 | |
3044 number_instructions(); | |
3045 | |
3046 NOT_PRODUCT(print_lir(1, "Before Register Allocation")); | |
3047 | |
3048 compute_local_live_sets(); | |
3049 compute_global_live_sets(); | |
3050 CHECK_BAILOUT(); | |
3051 | |
3052 build_intervals(); | |
3053 CHECK_BAILOUT(); | |
3054 sort_intervals_before_allocation(); | |
3055 | |
3056 NOT_PRODUCT(print_intervals("Before Register Allocation")); | |
3057 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_before_alloc)); | |
3058 | |
3059 allocate_registers(); | |
3060 CHECK_BAILOUT(); | |
3061 | |
3062 resolve_data_flow(); | |
3063 if (compilation()->has_exception_handlers()) { | |
3064 resolve_exception_handlers(); | |
3065 } | |
3066 // fill in number of spill slots into frame_map | |
3067 propagate_spill_slots(); | |
3068 CHECK_BAILOUT(); | |
3069 | |
3070 NOT_PRODUCT(print_intervals("After Register Allocation")); | |
3071 NOT_PRODUCT(print_lir(2, "LIR after register allocation:")); | |
3072 | |
3073 sort_intervals_after_allocation(); | |
722
a134d9824964
6828024: verification of fixed interval usage is too weak
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337
diff
changeset
|
3074 |
a134d9824964
6828024: verification of fixed interval usage is too weak
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diff
changeset
|
3075 DEBUG_ONLY(verify()); |
a134d9824964
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|
3076 |
0 | 3077 eliminate_spill_moves(); |
3078 assign_reg_num(); | |
3079 CHECK_BAILOUT(); | |
3080 | |
3081 NOT_PRODUCT(print_lir(2, "LIR after assignment of register numbers:")); | |
3082 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_after_asign)); | |
3083 | |
3084 { TIME_LINEAR_SCAN(timer_allocate_fpu_stack); | |
3085 | |
3086 if (use_fpu_stack_allocation()) { | |
3087 allocate_fpu_stack(); // Only has effect on Intel | |
3088 NOT_PRODUCT(print_lir(2, "LIR after FPU stack allocation:")); | |
3089 } | |
3090 } | |
3091 | |
3092 { TIME_LINEAR_SCAN(timer_optimize_lir); | |
3093 | |
3094 EdgeMoveOptimizer::optimize(ir()->code()); | |
3095 ControlFlowOptimizer::optimize(ir()->code()); | |
3096 // check that cfg is still correct after optimizations | |
3097 ir()->verify(); | |
3098 } | |
3099 | |
3100 NOT_PRODUCT(print_lir(1, "Before Code Generation", false)); | |
3101 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_final)); | |
3102 NOT_PRODUCT(_total_timer.end_method(this)); | |
3103 } | |
3104 | |
3105 | |
3106 // ********** Printing functions | |
3107 | |
3108 #ifndef PRODUCT | |
3109 | |
3110 void LinearScan::print_timers(double total) { | |
3111 _total_timer.print(total); | |
3112 } | |
3113 | |
3114 void LinearScan::print_statistics() { | |
3115 _stat_before_alloc.print("before allocation"); | |
3116 _stat_after_asign.print("after assignment of register"); | |
3117 _stat_final.print("after optimization"); | |
3118 } | |
3119 | |
3120 void LinearScan::print_bitmap(BitMap& b) { | |
3121 for (unsigned int i = 0; i < b.size(); i++) { | |
3122 if (b.at(i)) tty->print("%d ", i); | |
3123 } | |
3124 tty->cr(); | |
3125 } | |
3126 | |
3127 void LinearScan::print_intervals(const char* label) { | |
3128 if (TraceLinearScanLevel >= 1) { | |
3129 int i; | |
3130 tty->cr(); | |
3131 tty->print_cr("%s", label); | |
3132 | |
3133 for (i = 0; i < interval_count(); i++) { | |
3134 Interval* interval = interval_at(i); | |
3135 if (interval != NULL) { | |
3136 interval->print(); | |
3137 } | |
3138 } | |
3139 | |
3140 tty->cr(); | |
3141 tty->print_cr("--- Basic Blocks ---"); | |
3142 for (i = 0; i < block_count(); i++) { | |
3143 BlockBegin* block = block_at(i); | |
3144 tty->print("B%d [%d, %d, %d, %d] ", block->block_id(), block->first_lir_instruction_id(), block->last_lir_instruction_id(), block->loop_index(), block->loop_depth()); | |
3145 } | |
3146 tty->cr(); | |
3147 tty->cr(); | |
3148 } | |
3149 | |
3150 if (PrintCFGToFile) { | |
3151 CFGPrinter::print_intervals(&_intervals, label); | |
3152 } | |
3153 } | |
3154 | |
3155 void LinearScan::print_lir(int level, const char* label, bool hir_valid) { | |
3156 if (TraceLinearScanLevel >= level) { | |
3157 tty->cr(); | |
3158 tty->print_cr("%s", label); | |
3159 print_LIR(ir()->linear_scan_order()); | |
3160 tty->cr(); | |
3161 } | |
3162 | |
3163 if (level == 1 && PrintCFGToFile) { | |
3164 CFGPrinter::print_cfg(ir()->linear_scan_order(), label, hir_valid, true); | |
3165 } | |
3166 } | |
3167 | |
3168 #endif //PRODUCT | |
3169 | |
3170 | |
3171 // ********** verification functions for allocation | |
3172 // (check that all intervals have a correct register and that no registers are overwritten) | |
3173 #ifdef ASSERT | |
3174 | |
3175 void LinearScan::verify() { | |
3176 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying intervals ******************************************")); | |
3177 verify_intervals(); | |
3178 | |
3179 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that no oops are in fixed intervals ****************")); | |
3180 verify_no_oops_in_fixed_intervals(); | |
3181 | |
3182 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that unpinned constants are not alive across block boundaries")); | |
3183 verify_constants(); | |
3184 | |
3185 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying register allocation ********************************")); | |
3186 verify_registers(); | |
3187 | |
3188 TRACE_LINEAR_SCAN(2, tty->print_cr("********* no errors found **********************************************")); | |
3189 } | |
3190 | |
3191 void LinearScan::verify_intervals() { | |
3192 int len = interval_count(); | |
3193 bool has_error = false; | |
3194 | |
3195 for (int i = 0; i < len; i++) { | |
3196 Interval* i1 = interval_at(i); | |
3197 if (i1 == NULL) continue; | |
3198 | |
3199 i1->check_split_children(); | |
3200 | |
3201 if (i1->reg_num() != i) { | |
3202 tty->print_cr("Interval %d is on position %d in list", i1->reg_num(), i); i1->print(); tty->cr(); | |
3203 has_error = true; | |
3204 } | |
3205 | |
3206 if (i1->reg_num() >= LIR_OprDesc::vreg_base && i1->type() == T_ILLEGAL) { | |
3207 tty->print_cr("Interval %d has no type assigned", i1->reg_num()); i1->print(); tty->cr(); | |
3208 has_error = true; | |
3209 } | |
3210 | |
3211 if (i1->assigned_reg() == any_reg) { | |
3212 tty->print_cr("Interval %d has no register assigned", i1->reg_num()); i1->print(); tty->cr(); | |
3213 has_error = true; | |
3214 } | |
3215 | |
3216 if (i1->assigned_reg() == i1->assigned_regHi()) { | |
3217 tty->print_cr("Interval %d: low and high register equal", i1->reg_num()); i1->print(); tty->cr(); | |
3218 has_error = true; | |
3219 } | |
3220 | |
3221 if (!is_processed_reg_num(i1->assigned_reg())) { | |
3222 tty->print_cr("Can not have an Interval for an ignored register"); i1->print(); tty->cr(); | |
3223 has_error = true; | |
3224 } | |
3225 | |
3226 if (i1->first() == Range::end()) { | |
3227 tty->print_cr("Interval %d has no Range", i1->reg_num()); i1->print(); tty->cr(); | |
3228 has_error = true; | |
3229 } | |
3230 | |
3231 for (Range* r = i1->first(); r != Range::end(); r = r->next()) { | |
3232 if (r->from() >= r->to()) { | |
3233 tty->print_cr("Interval %d has zero length range", i1->reg_num()); i1->print(); tty->cr(); | |
3234 has_error = true; | |
3235 } | |
3236 } | |
3237 | |
3238 for (int j = i + 1; j < len; j++) { | |
3239 Interval* i2 = interval_at(j); | |
3240 if (i2 == NULL) continue; | |
3241 | |
3242 // special intervals that are created in MoveResolver | |
3243 // -> ignore them because the range information has no meaning there | |
3244 if (i1->from() == 1 && i1->to() == 2) continue; | |
3245 if (i2->from() == 1 && i2->to() == 2) continue; | |
3246 | |
3247 int r1 = i1->assigned_reg(); | |
3248 int r1Hi = i1->assigned_regHi(); | |
3249 int r2 = i2->assigned_reg(); | |
3250 int r2Hi = i2->assigned_regHi(); | |
3251 if (i1->intersects(i2) && (r1 == r2 || r1 == r2Hi || (r1Hi != any_reg && (r1Hi == r2 || r1Hi == r2Hi)))) { | |
3252 tty->print_cr("Intervals %d and %d overlap and have the same register assigned", i1->reg_num(), i2->reg_num()); | |
3253 i1->print(); tty->cr(); | |
3254 i2->print(); tty->cr(); | |
3255 has_error = true; | |
3256 } | |
3257 } | |
3258 } | |
3259 | |
3260 assert(has_error == false, "register allocation invalid"); | |
3261 } | |
3262 | |
3263 | |
3264 void LinearScan::verify_no_oops_in_fixed_intervals() { | |
722
a134d9824964
6828024: verification of fixed interval usage is too weak
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parents:
337
diff
changeset
|
3265 Interval* fixed_intervals; |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3266 Interval* other_intervals; |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3267 create_unhandled_lists(&fixed_intervals, &other_intervals, is_precolored_cpu_interval, NULL); |
a134d9824964
6828024: verification of fixed interval usage is too weak
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parents:
337
diff
changeset
|
3268 |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3269 // to ensure a walking until the last instruction id, add a dummy interval |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3270 // with a high operation id |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3271 other_intervals = new Interval(any_reg); |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3272 other_intervals->add_range(max_jint - 2, max_jint - 1); |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3273 IntervalWalker* iw = new IntervalWalker(this, fixed_intervals, other_intervals); |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3274 |
0 | 3275 LIR_OpVisitState visitor; |
3276 for (int i = 0; i < block_count(); i++) { | |
3277 BlockBegin* block = block_at(i); | |
3278 | |
3279 LIR_OpList* instructions = block->lir()->instructions_list(); | |
3280 | |
3281 for (int j = 0; j < instructions->length(); j++) { | |
3282 LIR_Op* op = instructions->at(j); | |
3283 int op_id = op->id(); | |
3284 | |
3285 visitor.visit(op); | |
3286 | |
722
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3287 if (visitor.info_count() > 0) { |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3288 iw->walk_before(op->id()); |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3289 bool check_live = true; |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3290 if (op->code() == lir_move) { |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3291 LIR_Op1* move = (LIR_Op1*)op; |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3292 check_live = (move->patch_code() == lir_patch_none); |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3293 } |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3294 LIR_OpBranch* branch = op->as_OpBranch(); |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3295 if (branch != NULL && branch->stub() != NULL && branch->stub()->is_exception_throw_stub()) { |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3296 // Don't bother checking the stub in this case since the |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3297 // exception stub will never return to normal control flow. |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3298 check_live = false; |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3299 } |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3300 |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3301 // Make sure none of the fixed registers is live across an |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3302 // oopmap since we can't handle that correctly. |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3303 if (check_live) { |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3304 for (Interval* interval = iw->active_first(fixedKind); |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3305 interval != Interval::end(); |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3306 interval = interval->next()) { |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3307 if (interval->current_to() > op->id() + 1) { |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3308 // This interval is live out of this op so make sure |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3309 // that this interval represents some value that's |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3310 // referenced by this op either as an input or output. |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3311 bool ok = false; |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3312 for_each_visitor_mode(mode) { |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3313 int n = visitor.opr_count(mode); |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3314 for (int k = 0; k < n; k++) { |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3315 LIR_Opr opr = visitor.opr_at(mode, k); |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3316 if (opr->is_fixed_cpu()) { |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3317 if (interval_at(reg_num(opr)) == interval) { |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3318 ok = true; |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3319 break; |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3320 } |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3321 int hi = reg_numHi(opr); |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3322 if (hi != -1 && interval_at(hi) == interval) { |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3323 ok = true; |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3324 break; |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3325 } |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3326 } |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3327 } |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3328 } |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3329 assert(ok, "fixed intervals should never be live across an oopmap point"); |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3330 } |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3331 } |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3332 } |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3333 } |
a134d9824964
6828024: verification of fixed interval usage is too weak
never
parents:
337
diff
changeset
|
3334 |
0 | 3335 // oop-maps at calls do not contain registers, so check is not needed |
3336 if (!visitor.has_call()) { | |
3337 | |
3338 for_each_visitor_mode(mode) { | |
3339 int n = visitor.opr_count(mode); | |
3340 for (int k = 0; k < n; k++) { | |
3341 LIR_Opr opr = visitor.opr_at(mode, k); | |
3342 | |
3343 if (opr->is_fixed_cpu() && opr->is_oop()) { | |
3344 // operand is a non-virtual cpu register and contains an oop | |
3345 TRACE_LINEAR_SCAN(4, op->print_on(tty); tty->print("checking operand "); opr->print(); tty->cr()); | |
3346 | |
3347 Interval* interval = interval_at(reg_num(opr)); | |
3348 assert(interval != NULL, "no interval"); | |
3349 | |
3350 if (mode == LIR_OpVisitState::inputMode) { | |
3351 if (interval->to() >= op_id + 1) { | |
3352 assert(interval->to() < op_id + 2 || | |
3353 interval->has_hole_between(op_id, op_id + 2), | |
3354 "oop input operand live after instruction"); | |
3355 } | |
3356 } else if (mode == LIR_OpVisitState::outputMode) { | |
3357 if (interval->from() <= op_id - 1) { | |
3358 assert(interval->has_hole_between(op_id - 1, op_id), | |
3359 "oop input operand live after instruction"); | |
3360 } | |
3361 } | |
3362 } | |
3363 } | |
3364 } | |
3365 } | |
3366 } | |
3367 } | |
3368 } | |
3369 | |
3370 | |
3371 void LinearScan::verify_constants() { | |
3372 int num_regs = num_virtual_regs(); | |
3373 int size = live_set_size(); | |
3374 int num_blocks = block_count(); | |
3375 | |
3376 for (int i = 0; i < num_blocks; i++) { | |
3377 BlockBegin* block = block_at(i); | |
3378 BitMap live_at_edge = block->live_in(); | |
3379 | |
3380 // visit all registers where the live_at_edge bit is set | |
304 | 3381 for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) { |
0 | 3382 TRACE_LINEAR_SCAN(4, tty->print("checking interval %d of block B%d", r, block->block_id())); |
3383 | |
3384 Value value = gen()->instruction_for_vreg(r); | |
3385 | |
3386 assert(value != NULL, "all intervals live across block boundaries must have Value"); | |
3387 assert(value->operand()->is_register() && value->operand()->is_virtual(), "value must have virtual operand"); | |
3388 assert(value->operand()->vreg_number() == r, "register number must match"); | |
3389 // TKR assert(value->as_Constant() == NULL || value->is_pinned(), "only pinned constants can be alive accross block boundaries"); | |
3390 } | |
3391 } | |
3392 } | |
3393 | |
3394 | |
3395 class RegisterVerifier: public StackObj { | |
3396 private: | |
3397 LinearScan* _allocator; | |
3398 BlockList _work_list; // all blocks that must be processed | |
3399 IntervalsList _saved_states; // saved information of previous check | |
3400 | |
3401 // simplified access to methods of LinearScan | |
3402 Compilation* compilation() const { return _allocator->compilation(); } | |
3403 Interval* interval_at(int reg_num) const { return _allocator->interval_at(reg_num); } | |
3404 int reg_num(LIR_Opr opr) const { return _allocator->reg_num(opr); } | |
3405 | |
3406 // currently, only registers are processed | |
3407 int state_size() { return LinearScan::nof_regs; } | |
3408 | |
3409 // accessors | |
3410 IntervalList* state_for_block(BlockBegin* block) { return _saved_states.at(block->block_id()); } | |
3411 void set_state_for_block(BlockBegin* block, IntervalList* saved_state) { _saved_states.at_put(block->block_id(), saved_state); } | |
3412 void add_to_work_list(BlockBegin* block) { if (!_work_list.contains(block)) _work_list.append(block); } | |
3413 | |
3414 // helper functions | |
3415 IntervalList* copy(IntervalList* input_state); | |
3416 void state_put(IntervalList* input_state, int reg, Interval* interval); | |
3417 bool check_state(IntervalList* input_state, int reg, Interval* interval); | |
3418 | |
3419 void process_block(BlockBegin* block); | |
3420 void process_xhandler(XHandler* xhandler, IntervalList* input_state); | |
3421 void process_successor(BlockBegin* block, IntervalList* input_state); | |
3422 void process_operations(LIR_List* ops, IntervalList* input_state); | |
3423 | |
3424 public: | |
3425 RegisterVerifier(LinearScan* allocator) | |
3426 : _allocator(allocator) | |
3427 , _work_list(16) | |
3428 , _saved_states(BlockBegin::number_of_blocks(), NULL) | |
3429 { } | |
3430 | |
3431 void verify(BlockBegin* start); | |
3432 }; | |
3433 | |
3434 | |
3435 // entry function from LinearScan that starts the verification | |
3436 void LinearScan::verify_registers() { | |
3437 RegisterVerifier verifier(this); | |
3438 verifier.verify(block_at(0)); | |
3439 } | |
3440 | |
3441 | |
3442 void RegisterVerifier::verify(BlockBegin* start) { | |
3443 // setup input registers (method arguments) for first block | |
3444 IntervalList* input_state = new IntervalList(state_size(), NULL); | |
3445 CallingConvention* args = compilation()->frame_map()->incoming_arguments(); | |
3446 for (int n = 0; n < args->length(); n++) { | |
3447 LIR_Opr opr = args->at(n); | |
3448 if (opr->is_register()) { | |
3449 Interval* interval = interval_at(reg_num(opr)); | |
3450 | |
3451 if (interval->assigned_reg() < state_size()) { | |
3452 input_state->at_put(interval->assigned_reg(), interval); | |
3453 } | |
3454 if (interval->assigned_regHi() != LinearScan::any_reg && interval->assigned_regHi() < state_size()) { | |
3455 input_state->at_put(interval->assigned_regHi(), interval); | |
3456 } | |
3457 } | |
3458 } | |
3459 | |
3460 set_state_for_block(start, input_state); | |
3461 add_to_work_list(start); | |
3462 | |
3463 // main loop for verification | |
3464 do { | |
3465 BlockBegin* block = _work_list.at(0); | |
3466 _work_list.remove_at(0); | |
3467 | |
3468 process_block(block); | |
3469 } while (!_work_list.is_empty()); | |
3470 } | |
3471 | |
3472 void RegisterVerifier::process_block(BlockBegin* block) { | |
3473 TRACE_LINEAR_SCAN(2, tty->cr(); tty->print_cr("process_block B%d", block->block_id())); | |
3474 | |
3475 // must copy state because it is modified | |
3476 IntervalList* input_state = copy(state_for_block(block)); | |
3477 | |
3478 if (TraceLinearScanLevel >= 4) { | |
3479 tty->print_cr("Input-State of intervals:"); | |
3480 tty->print(" "); | |
3481 for (int i = 0; i < state_size(); i++) { | |
3482 if (input_state->at(i) != NULL) { | |
3483 tty->print(" %4d", input_state->at(i)->reg_num()); | |
3484 } else { | |
3485 tty->print(" __"); | |
3486 } | |
3487 } | |
3488 tty->cr(); | |
3489 tty->cr(); | |
3490 } | |
3491 | |
3492 // process all operations of the block | |
3493 process_operations(block->lir(), input_state); | |
3494 | |
3495 // iterate all successors | |
3496 for (int i = 0; i < block->number_of_sux(); i++) { | |
3497 process_successor(block->sux_at(i), input_state); | |
3498 } | |
3499 } | |
3500 | |
3501 void RegisterVerifier::process_xhandler(XHandler* xhandler, IntervalList* input_state) { | |
3502 TRACE_LINEAR_SCAN(2, tty->print_cr("process_xhandler B%d", xhandler->entry_block()->block_id())); | |
3503 | |
3504 // must copy state because it is modified | |
3505 input_state = copy(input_state); | |
3506 | |
3507 if (xhandler->entry_code() != NULL) { | |
3508 process_operations(xhandler->entry_code(), input_state); | |
3509 } | |
3510 process_successor(xhandler->entry_block(), input_state); | |
3511 } | |
3512 | |
3513 void RegisterVerifier::process_successor(BlockBegin* block, IntervalList* input_state) { | |
3514 IntervalList* saved_state = state_for_block(block); | |
3515 | |
3516 if (saved_state != NULL) { | |
3517 // this block was already processed before. | |
3518 // check if new input_state is consistent with saved_state | |
3519 | |
3520 bool saved_state_correct = true; | |
3521 for (int i = 0; i < state_size(); i++) { | |
3522 if (input_state->at(i) != saved_state->at(i)) { | |
3523 // current input_state and previous saved_state assume a different | |
3524 // interval in this register -> assume that this register is invalid | |
3525 if (saved_state->at(i) != NULL) { | |
3526 // invalidate old calculation only if it assumed that | |
3527 // register was valid. when the register was already invalid, | |
3528 // then the old calculation was correct. | |
3529 saved_state_correct = false; | |
3530 saved_state->at_put(i, NULL); | |
3531 | |
3532 TRACE_LINEAR_SCAN(4, tty->print_cr("process_successor B%d: invalidating slot %d", block->block_id(), i)); | |
3533 } | |
3534 } | |
3535 } | |
3536 | |
3537 if (saved_state_correct) { | |
3538 // already processed block with correct input_state | |
3539 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: previous visit already correct", block->block_id())); | |
3540 } else { | |
3541 // must re-visit this block | |
3542 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: must re-visit because input state changed", block->block_id())); | |
3543 add_to_work_list(block); | |
3544 } | |
3545 | |
3546 } else { | |
3547 // block was not processed before, so set initial input_state | |
3548 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: initial visit", block->block_id())); | |
3549 | |
3550 set_state_for_block(block, copy(input_state)); | |
3551 add_to_work_list(block); | |
3552 } | |
3553 } | |
3554 | |
3555 | |
3556 IntervalList* RegisterVerifier::copy(IntervalList* input_state) { | |
3557 IntervalList* copy_state = new IntervalList(input_state->length()); | |
3558 copy_state->push_all(input_state); | |
3559 return copy_state; | |
3560 } | |
3561 | |
3562 void RegisterVerifier::state_put(IntervalList* input_state, int reg, Interval* interval) { | |
3563 if (reg != LinearScan::any_reg && reg < state_size()) { | |
3564 if (interval != NULL) { | |
3565 TRACE_LINEAR_SCAN(4, tty->print_cr(" reg[%d] = %d", reg, interval->reg_num())); | |
3566 } else if (input_state->at(reg) != NULL) { | |
3567 TRACE_LINEAR_SCAN(4, tty->print_cr(" reg[%d] = NULL", reg)); | |
3568 } | |
3569 | |
3570 input_state->at_put(reg, interval); | |
3571 } | |
3572 } | |
3573 | |
3574 bool RegisterVerifier::check_state(IntervalList* input_state, int reg, Interval* interval) { | |
3575 if (reg != LinearScan::any_reg && reg < state_size()) { | |
3576 if (input_state->at(reg) != interval) { | |
3577 tty->print_cr("!! Error in register allocation: register %d does not contain interval %d", reg, interval->reg_num()); | |
3578 return true; | |
3579 } | |
3580 } | |
3581 return false; | |
3582 } | |
3583 | |
3584 void RegisterVerifier::process_operations(LIR_List* ops, IntervalList* input_state) { | |
3585 // visit all instructions of the block | |
3586 LIR_OpVisitState visitor; | |
3587 bool has_error = false; | |
3588 | |
3589 for (int i = 0; i < ops->length(); i++) { | |
3590 LIR_Op* op = ops->at(i); | |
3591 visitor.visit(op); | |
3592 | |
3593 TRACE_LINEAR_SCAN(4, op->print_on(tty)); | |
3594 | |
3595 // check if input operands are correct | |
3596 int j; | |
3597 int n = visitor.opr_count(LIR_OpVisitState::inputMode); | |
3598 for (j = 0; j < n; j++) { | |
3599 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, j); | |
3600 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) { | |
3601 Interval* interval = interval_at(reg_num(opr)); | |
3602 if (op->id() != -1) { | |
3603 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::inputMode); | |
3604 } | |
3605 | |
3606 has_error |= check_state(input_state, interval->assigned_reg(), interval->split_parent()); | |
3607 has_error |= check_state(input_state, interval->assigned_regHi(), interval->split_parent()); | |
3608 | |
3609 // When an operand is marked with is_last_use, then the fpu stack allocator | |
3610 // removes the register from the fpu stack -> the register contains no value | |
3611 if (opr->is_last_use()) { | |
3612 state_put(input_state, interval->assigned_reg(), NULL); | |
3613 state_put(input_state, interval->assigned_regHi(), NULL); | |
3614 } | |
3615 } | |
3616 } | |
3617 | |
3618 // invalidate all caller save registers at calls | |
3619 if (visitor.has_call()) { | |
2002 | 3620 for (j = 0; j < FrameMap::nof_caller_save_cpu_regs(); j++) { |
0 | 3621 state_put(input_state, reg_num(FrameMap::caller_save_cpu_reg_at(j)), NULL); |
3622 } | |
3623 for (j = 0; j < FrameMap::nof_caller_save_fpu_regs; j++) { | |
3624 state_put(input_state, reg_num(FrameMap::caller_save_fpu_reg_at(j)), NULL); | |
3625 } | |
3626 | |
304 | 3627 #ifdef X86 |
0 | 3628 for (j = 0; j < FrameMap::nof_caller_save_xmm_regs; j++) { |
3629 state_put(input_state, reg_num(FrameMap::caller_save_xmm_reg_at(j)), NULL); | |
3630 } | |
3631 #endif | |
3632 } | |
3633 | |
3634 // process xhandler before output and temp operands | |
3635 XHandlers* xhandlers = visitor.all_xhandler(); | |
3636 n = xhandlers->length(); | |
3637 for (int k = 0; k < n; k++) { | |
3638 process_xhandler(xhandlers->handler_at(k), input_state); | |
3639 } | |
3640 | |
3641 // set temp operands (some operations use temp operands also as output operands, so can't set them NULL) | |
3642 n = visitor.opr_count(LIR_OpVisitState::tempMode); | |
3643 for (j = 0; j < n; j++) { | |
3644 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, j); | |
3645 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) { | |
3646 Interval* interval = interval_at(reg_num(opr)); | |
3647 if (op->id() != -1) { | |
3648 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::tempMode); | |
3649 } | |
3650 | |
3651 state_put(input_state, interval->assigned_reg(), interval->split_parent()); | |
3652 state_put(input_state, interval->assigned_regHi(), interval->split_parent()); | |
3653 } | |
3654 } | |
3655 | |
3656 // set output operands | |
3657 n = visitor.opr_count(LIR_OpVisitState::outputMode); | |
3658 for (j = 0; j < n; j++) { | |
3659 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, j); | |
3660 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) { | |
3661 Interval* interval = interval_at(reg_num(opr)); | |
3662 if (op->id() != -1) { | |
3663 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::outputMode); | |
3664 } | |
3665 | |
3666 state_put(input_state, interval->assigned_reg(), interval->split_parent()); | |
3667 state_put(input_state, interval->assigned_regHi(), interval->split_parent()); | |
3668 } | |
3669 } | |
3670 } | |
3671 assert(has_error == false, "Error in register allocation"); | |
3672 } | |
3673 | |
3674 #endif // ASSERT | |
3675 | |
3676 | |
3677 | |
3678 // **** Implementation of MoveResolver ****************************** | |
3679 | |
3680 MoveResolver::MoveResolver(LinearScan* allocator) : | |
3681 _allocator(allocator), | |
3682 _multiple_reads_allowed(false), | |
3683 _mapping_from(8), | |
3684 _mapping_from_opr(8), | |
3685 _mapping_to(8), | |
3686 _insert_list(NULL), | |
3687 _insert_idx(-1), | |
3688 _insertion_buffer() | |
3689 { | |
3690 for (int i = 0; i < LinearScan::nof_regs; i++) { | |
3691 _register_blocked[i] = 0; | |
3692 } | |
3693 DEBUG_ONLY(check_empty()); | |
3694 } | |
3695 | |
3696 | |
3697 #ifdef ASSERT | |
3698 | |
3699 void MoveResolver::check_empty() { | |
3700 assert(_mapping_from.length() == 0 && _mapping_from_opr.length() == 0 && _mapping_to.length() == 0, "list must be empty before and after processing"); | |
3701 for (int i = 0; i < LinearScan::nof_regs; i++) { | |
3702 assert(register_blocked(i) == 0, "register map must be empty before and after processing"); | |
3703 } | |
3704 assert(_multiple_reads_allowed == false, "must have default value"); | |
3705 } | |
3706 | |
3707 void MoveResolver::verify_before_resolve() { | |
3708 assert(_mapping_from.length() == _mapping_from_opr.length(), "length must be equal"); | |
3709 assert(_mapping_from.length() == _mapping_to.length(), "length must be equal"); | |
3710 assert(_insert_list != NULL && _insert_idx != -1, "insert position not set"); | |
3711 | |
3712 int i, j; | |
3713 if (!_multiple_reads_allowed) { | |
3714 for (i = 0; i < _mapping_from.length(); i++) { | |
3715 for (j = i + 1; j < _mapping_from.length(); j++) { | |
3716 assert(_mapping_from.at(i) == NULL || _mapping_from.at(i) != _mapping_from.at(j), "cannot read from same interval twice"); | |
3717 } | |
3718 } | |
3719 } | |
3720 | |
3721 for (i = 0; i < _mapping_to.length(); i++) { | |
3722 for (j = i + 1; j < _mapping_to.length(); j++) { | |
3723 assert(_mapping_to.at(i) != _mapping_to.at(j), "cannot write to same interval twice"); | |
3724 } | |
3725 } | |
3726 | |
3727 | |
3728 BitMap used_regs(LinearScan::nof_regs + allocator()->frame_map()->argcount() + allocator()->max_spills()); | |
3729 used_regs.clear(); | |
3730 if (!_multiple_reads_allowed) { | |
3731 for (i = 0; i < _mapping_from.length(); i++) { | |
3732 Interval* it = _mapping_from.at(i); | |
3733 if (it != NULL) { | |
3734 assert(!used_regs.at(it->assigned_reg()), "cannot read from same register twice"); | |
3735 used_regs.set_bit(it->assigned_reg()); | |
3736 | |
3737 if (it->assigned_regHi() != LinearScan::any_reg) { | |
3738 assert(!used_regs.at(it->assigned_regHi()), "cannot read from same register twice"); | |
3739 used_regs.set_bit(it->assigned_regHi()); | |
3740 } | |
3741 } | |
3742 } | |
3743 } | |
3744 | |
3745 used_regs.clear(); | |
3746 for (i = 0; i < _mapping_to.length(); i++) { | |
3747 Interval* it = _mapping_to.at(i); | |
3748 assert(!used_regs.at(it->assigned_reg()), "cannot write to same register twice"); | |
3749 used_regs.set_bit(it->assigned_reg()); | |
3750 | |
3751 if (it->assigned_regHi() != LinearScan::any_reg) { | |
3752 assert(!used_regs.at(it->assigned_regHi()), "cannot write to same register twice"); | |
3753 used_regs.set_bit(it->assigned_regHi()); | |
3754 } | |
3755 } | |
3756 | |
3757 used_regs.clear(); | |
3758 for (i = 0; i < _mapping_from.length(); i++) { | |
3759 Interval* it = _mapping_from.at(i); | |
3760 if (it != NULL && it->assigned_reg() >= LinearScan::nof_regs) { | |
3761 used_regs.set_bit(it->assigned_reg()); | |
3762 } | |
3763 } | |
3764 for (i = 0; i < _mapping_to.length(); i++) { | |
3765 Interval* it = _mapping_to.at(i); | |
3766 assert(!used_regs.at(it->assigned_reg()) || it->assigned_reg() == _mapping_from.at(i)->assigned_reg(), "stack slots used in _mapping_from must be disjoint to _mapping_to"); | |
3767 } | |
3768 } | |
3769 | |
3770 #endif // ASSERT | |
3771 | |
3772 | |
3773 // mark assigned_reg and assigned_regHi of the interval as blocked | |
3774 void MoveResolver::block_registers(Interval* it) { | |
3775 int reg = it->assigned_reg(); | |
3776 if (reg < LinearScan::nof_regs) { | |
3777 assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used"); | |
3778 set_register_blocked(reg, 1); | |
3779 } | |
3780 reg = it->assigned_regHi(); | |
3781 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) { | |
3782 assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used"); | |
3783 set_register_blocked(reg, 1); | |
3784 } | |
3785 } | |
3786 | |
3787 // mark assigned_reg and assigned_regHi of the interval as unblocked | |
3788 void MoveResolver::unblock_registers(Interval* it) { | |
3789 int reg = it->assigned_reg(); | |
3790 if (reg < LinearScan::nof_regs) { | |
3791 assert(register_blocked(reg) > 0, "register already marked as unused"); | |
3792 set_register_blocked(reg, -1); | |
3793 } | |
3794 reg = it->assigned_regHi(); | |
3795 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) { | |
3796 assert(register_blocked(reg) > 0, "register already marked as unused"); | |
3797 set_register_blocked(reg, -1); | |
3798 } | |
3799 } | |
3800 | |
3801 // check if assigned_reg and assigned_regHi of the to-interval are not blocked (or only blocked by from) | |
3802 bool MoveResolver::save_to_process_move(Interval* from, Interval* to) { | |
3803 int from_reg = -1; | |
3804 int from_regHi = -1; | |
3805 if (from != NULL) { | |
3806 from_reg = from->assigned_reg(); | |
3807 from_regHi = from->assigned_regHi(); | |
3808 } | |
3809 | |
3810 int reg = to->assigned_reg(); | |
3811 if (reg < LinearScan::nof_regs) { | |
3812 if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) { | |
3813 return false; | |
3814 } | |
3815 } | |
3816 reg = to->assigned_regHi(); | |
3817 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) { | |
3818 if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) { | |
3819 return false; | |
3820 } | |
3821 } | |
3822 | |
3823 return true; | |
3824 } | |
3825 | |
3826 | |
3827 void MoveResolver::create_insertion_buffer(LIR_List* list) { | |
3828 assert(!_insertion_buffer.initialized(), "overwriting existing buffer"); | |
3829 _insertion_buffer.init(list); | |
3830 } | |
3831 | |
3832 void MoveResolver::append_insertion_buffer() { | |
3833 if (_insertion_buffer.initialized()) { | |
3834 _insertion_buffer.lir_list()->append(&_insertion_buffer); | |
3835 } | |
3836 assert(!_insertion_buffer.initialized(), "must be uninitialized now"); | |
3837 | |
3838 _insert_list = NULL; | |
3839 _insert_idx = -1; | |
3840 } | |
3841 | |
3842 void MoveResolver::insert_move(Interval* from_interval, Interval* to_interval) { | |
3843 assert(from_interval->reg_num() != to_interval->reg_num(), "from and to interval equal"); | |
3844 assert(from_interval->type() == to_interval->type(), "move between different types"); | |
3845 assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first"); | |
3846 assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer"); | |
3847 | |
3848 LIR_Opr from_opr = LIR_OprFact::virtual_register(from_interval->reg_num(), from_interval->type()); | |
3849 LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type()); | |
3850 | |
3851 if (!_multiple_reads_allowed) { | |
3852 // the last_use flag is an optimization for FPU stack allocation. When the same | |
3853 // input interval is used in more than one move, then it is too difficult to determine | |
3854 // if this move is really the last use. | |
3855 from_opr = from_opr->make_last_use(); | |
3856 } | |
3857 _insertion_buffer.move(_insert_idx, from_opr, to_opr); | |
3858 | |
3859 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: inserted move from register %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi())); | |
3860 } | |
3861 | |
3862 void MoveResolver::insert_move(LIR_Opr from_opr, Interval* to_interval) { | |
3863 assert(from_opr->type() == to_interval->type(), "move between different types"); | |
3864 assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first"); | |
3865 assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer"); | |
3866 | |
3867 LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type()); | |
3868 _insertion_buffer.move(_insert_idx, from_opr, to_opr); | |
3869 | |
3870 TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: inserted move from constant "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi())); | |
3871 } | |
3872 | |
3873 | |
3874 void MoveResolver::resolve_mappings() { | |
3875 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: resolving mappings for Block B%d, index %d", _insert_list->block() != NULL ? _insert_list->block()->block_id() : -1, _insert_idx)); | |
3876 DEBUG_ONLY(verify_before_resolve()); | |
3877 | |
3878 // Block all registers that are used as input operands of a move. | |
3879 // When a register is blocked, no move to this register is emitted. | |
3880 // This is necessary for detecting cycles in moves. | |
3881 int i; | |
3882 for (i = _mapping_from.length() - 1; i >= 0; i--) { | |
3883 Interval* from_interval = _mapping_from.at(i); | |
3884 if (from_interval != NULL) { | |
3885 block_registers(from_interval); | |
3886 } | |
3887 } | |
3888 | |
3889 int spill_candidate = -1; | |
3890 while (_mapping_from.length() > 0) { | |
3891 bool processed_interval = false; | |
3892 | |
3893 for (i = _mapping_from.length() - 1; i >= 0; i--) { | |
3894 Interval* from_interval = _mapping_from.at(i); | |
3895 Interval* to_interval = _mapping_to.at(i); | |
3896 | |
3897 if (save_to_process_move(from_interval, to_interval)) { | |
3898 // this inverval can be processed because target is free | |
3899 if (from_interval != NULL) { | |
3900 insert_move(from_interval, to_interval); | |
3901 unblock_registers(from_interval); | |
3902 } else { | |
3903 insert_move(_mapping_from_opr.at(i), to_interval); | |
3904 } | |
3905 _mapping_from.remove_at(i); | |
3906 _mapping_from_opr.remove_at(i); | |
3907 _mapping_to.remove_at(i); | |
3908 | |
3909 processed_interval = true; | |
3910 } else if (from_interval != NULL && from_interval->assigned_reg() < LinearScan::nof_regs) { | |
3911 // this interval cannot be processed now because target is not free | |
3912 // it starts in a register, so it is a possible candidate for spilling | |
3913 spill_candidate = i; | |
3914 } | |
3915 } | |
3916 | |
3917 if (!processed_interval) { | |
3918 // no move could be processed because there is a cycle in the move list | |
3919 // (e.g. r1 -> r2, r2 -> r1), so one interval must be spilled to memory | |
3920 assert(spill_candidate != -1, "no interval in register for spilling found"); | |
3921 | |
3922 // create a new spill interval and assign a stack slot to it | |
3923 Interval* from_interval = _mapping_from.at(spill_candidate); | |
3924 Interval* spill_interval = new Interval(-1); | |
3925 spill_interval->set_type(from_interval->type()); | |
3926 | |
3927 // add a dummy range because real position is difficult to calculate | |
3928 // Note: this range is a special case when the integrity of the allocation is checked | |
3929 spill_interval->add_range(1, 2); | |
3930 | |
3931 // do not allocate a new spill slot for temporary interval, but | |
3932 // use spill slot assigned to from_interval. Otherwise moves from | |
3933 // one stack slot to another can happen (not allowed by LIR_Assembler | |
3934 int spill_slot = from_interval->canonical_spill_slot(); | |
3935 if (spill_slot < 0) { | |
3936 spill_slot = allocator()->allocate_spill_slot(type2spill_size[spill_interval->type()] == 2); | |
3937 from_interval->set_canonical_spill_slot(spill_slot); | |
3938 } | |
3939 spill_interval->assign_reg(spill_slot); | |
3940 allocator()->append_interval(spill_interval); | |
3941 | |
3942 TRACE_LINEAR_SCAN(4, tty->print_cr("created new Interval %d for spilling", spill_interval->reg_num())); | |
3943 | |
3944 // insert a move from register to stack and update the mapping | |
3945 insert_move(from_interval, spill_interval); | |
3946 _mapping_from.at_put(spill_candidate, spill_interval); | |
3947 unblock_registers(from_interval); | |
3948 } | |
3949 } | |
3950 | |
3951 // reset to default value | |
3952 _multiple_reads_allowed = false; | |
3953 | |
3954 // check that all intervals have been processed | |
3955 DEBUG_ONLY(check_empty()); | |
3956 } | |
3957 | |
3958 | |
3959 void MoveResolver::set_insert_position(LIR_List* insert_list, int insert_idx) { | |
3960 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: setting insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx)); | |
3961 assert(_insert_list == NULL && _insert_idx == -1, "use move_insert_position instead of set_insert_position when data already set"); | |
3962 | |
3963 create_insertion_buffer(insert_list); | |
3964 _insert_list = insert_list; | |
3965 _insert_idx = insert_idx; | |
3966 } | |
3967 | |
3968 void MoveResolver::move_insert_position(LIR_List* insert_list, int insert_idx) { | |
3969 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: moving insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx)); | |
3970 | |
3971 if (_insert_list != NULL && (insert_list != _insert_list || insert_idx != _insert_idx)) { | |
3972 // insert position changed -> resolve current mappings | |
3973 resolve_mappings(); | |
3974 } | |
3975 | |
3976 if (insert_list != _insert_list) { | |
3977 // block changed -> append insertion_buffer because it is | |
3978 // bound to a specific block and create a new insertion_buffer | |
3979 append_insertion_buffer(); | |
3980 create_insertion_buffer(insert_list); | |
3981 } | |
3982 | |
3983 _insert_list = insert_list; | |
3984 _insert_idx = insert_idx; | |
3985 } | |
3986 | |
3987 void MoveResolver::add_mapping(Interval* from_interval, Interval* to_interval) { | |
3988 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: adding mapping from %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi())); | |
3989 | |
3990 _mapping_from.append(from_interval); | |
3991 _mapping_from_opr.append(LIR_OprFact::illegalOpr); | |
3992 _mapping_to.append(to_interval); | |
3993 } | |
3994 | |
3995 | |
3996 void MoveResolver::add_mapping(LIR_Opr from_opr, Interval* to_interval) { | |
3997 TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: adding mapping from "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi())); | |
3998 assert(from_opr->is_constant(), "only for constants"); | |
3999 | |
4000 _mapping_from.append(NULL); | |
4001 _mapping_from_opr.append(from_opr); | |
4002 _mapping_to.append(to_interval); | |
4003 } | |
4004 | |
4005 void MoveResolver::resolve_and_append_moves() { | |
4006 if (has_mappings()) { | |
4007 resolve_mappings(); | |
4008 } | |
4009 append_insertion_buffer(); | |
4010 } | |
4011 | |
4012 | |
4013 | |
4014 // **** Implementation of Range ************************************* | |
4015 | |
4016 Range::Range(int from, int to, Range* next) : | |
4017 _from(from), | |
4018 _to(to), | |
4019 _next(next) | |
4020 { | |
4021 } | |
4022 | |
4023 // initialize sentinel | |
4024 Range* Range::_end = NULL; | |
1584 | 4025 void Range::initialize(Arena* arena) { |
4026 _end = new (arena) Range(max_jint, max_jint, NULL); | |
0 | 4027 } |
4028 | |
4029 int Range::intersects_at(Range* r2) const { | |
4030 const Range* r1 = this; | |
4031 | |
4032 assert(r1 != NULL && r2 != NULL, "null ranges not allowed"); | |
4033 assert(r1 != _end && r2 != _end, "empty ranges not allowed"); | |
4034 | |
4035 do { | |
4036 if (r1->from() < r2->from()) { | |
4037 if (r1->to() <= r2->from()) { | |
4038 r1 = r1->next(); if (r1 == _end) return -1; | |
4039 } else { | |
4040 return r2->from(); | |
4041 } | |
4042 } else if (r2->from() < r1->from()) { | |
4043 if (r2->to() <= r1->from()) { | |
4044 r2 = r2->next(); if (r2 == _end) return -1; | |
4045 } else { | |
4046 return r1->from(); | |
4047 } | |
4048 } else { // r1->from() == r2->from() | |
4049 if (r1->from() == r1->to()) { | |
4050 r1 = r1->next(); if (r1 == _end) return -1; | |
4051 } else if (r2->from() == r2->to()) { | |
4052 r2 = r2->next(); if (r2 == _end) return -1; | |
4053 } else { | |
4054 return r1->from(); | |
4055 } | |
4056 } | |
4057 } while (true); | |
4058 } | |
4059 | |
4060 #ifndef PRODUCT | |
4061 void Range::print(outputStream* out) const { | |
4062 out->print("[%d, %d[ ", _from, _to); | |
4063 } | |
4064 #endif | |
4065 | |
4066 | |
4067 | |
4068 // **** Implementation of Interval ********************************** | |
4069 | |
4070 // initialize sentinel | |
4071 Interval* Interval::_end = NULL; | |
1584 | 4072 void Interval::initialize(Arena* arena) { |
4073 Range::initialize(arena); | |
4074 _end = new (arena) Interval(-1); | |
0 | 4075 } |
4076 | |
4077 Interval::Interval(int reg_num) : | |
4078 _reg_num(reg_num), | |
4079 _type(T_ILLEGAL), | |
4080 _first(Range::end()), | |
4081 _use_pos_and_kinds(12), | |
4082 _current(Range::end()), | |
4083 _next(_end), | |
4084 _state(invalidState), | |
4085 _assigned_reg(LinearScan::any_reg), | |
4086 _assigned_regHi(LinearScan::any_reg), | |
4087 _cached_to(-1), | |
4088 _cached_opr(LIR_OprFact::illegalOpr), | |
4089 _cached_vm_reg(VMRegImpl::Bad()), | |
4090 _split_children(0), | |
4091 _canonical_spill_slot(-1), | |
4092 _insert_move_when_activated(false), | |
4093 _register_hint(NULL), | |
4094 _spill_state(noDefinitionFound), | |
4095 _spill_definition_pos(-1) | |
4096 { | |
4097 _split_parent = this; | |
4098 _current_split_child = this; | |
4099 } | |
4100 | |
4101 int Interval::calc_to() { | |
4102 assert(_first != Range::end(), "interval has no range"); | |
4103 | |
4104 Range* r = _first; | |
4105 while (r->next() != Range::end()) { | |
4106 r = r->next(); | |
4107 } | |
4108 return r->to(); | |
4109 } | |
4110 | |
4111 | |
4112 #ifdef ASSERT | |
4113 // consistency check of split-children | |
4114 void Interval::check_split_children() { | |
4115 if (_split_children.length() > 0) { | |
4116 assert(is_split_parent(), "only split parents can have children"); | |
4117 | |
4118 for (int i = 0; i < _split_children.length(); i++) { | |
4119 Interval* i1 = _split_children.at(i); | |
4120 | |
4121 assert(i1->split_parent() == this, "not a split child of this interval"); | |
4122 assert(i1->type() == type(), "must be equal for all split children"); | |
4123 assert(i1->canonical_spill_slot() == canonical_spill_slot(), "must be equal for all split children"); | |
4124 | |
4125 for (int j = i + 1; j < _split_children.length(); j++) { | |
4126 Interval* i2 = _split_children.at(j); | |
4127 | |
4128 assert(i1->reg_num() != i2->reg_num(), "same register number"); | |
4129 | |
4130 if (i1->from() < i2->from()) { | |
4131 assert(i1->to() <= i2->from() && i1->to() < i2->to(), "intervals overlapping"); | |
4132 } else { | |
4133 assert(i2->from() < i1->from(), "intervals start at same op_id"); | |
4134 assert(i2->to() <= i1->from() && i2->to() < i1->to(), "intervals overlapping"); | |
4135 } | |
4136 } | |
4137 } | |
4138 } | |
4139 } | |
4140 #endif // ASSERT | |
4141 | |
4142 Interval* Interval::register_hint(bool search_split_child) const { | |
4143 if (!search_split_child) { | |
4144 return _register_hint; | |
4145 } | |
4146 | |
4147 if (_register_hint != NULL) { | |
4148 assert(_register_hint->is_split_parent(), "ony split parents are valid hint registers"); | |
4149 | |
4150 if (_register_hint->assigned_reg() >= 0 && _register_hint->assigned_reg() < LinearScan::nof_regs) { | |
4151 return _register_hint; | |
4152 | |
4153 } else if (_register_hint->_split_children.length() > 0) { | |
4154 // search the first split child that has a register assigned | |
4155 int len = _register_hint->_split_children.length(); | |
4156 for (int i = 0; i < len; i++) { | |
4157 Interval* cur = _register_hint->_split_children.at(i); | |
4158 | |
4159 if (cur->assigned_reg() >= 0 && cur->assigned_reg() < LinearScan::nof_regs) { | |
4160 return cur; | |
4161 } | |
4162 } | |
4163 } | |
4164 } | |
4165 | |
4166 // no hint interval found that has a register assigned | |
4167 return NULL; | |
4168 } | |
4169 | |
4170 | |
4171 Interval* Interval::split_child_at_op_id(int op_id, LIR_OpVisitState::OprMode mode) { | |
4172 assert(is_split_parent(), "can only be called for split parents"); | |
4173 assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)"); | |
4174 | |
4175 Interval* result; | |
4176 if (_split_children.length() == 0) { | |
4177 result = this; | |
4178 } else { | |
4179 result = NULL; | |
4180 int len = _split_children.length(); | |
4181 | |
4182 // in outputMode, the end of the interval (op_id == cur->to()) is not valid | |
4183 int to_offset = (mode == LIR_OpVisitState::outputMode ? 0 : 1); | |
4184 | |
4185 int i; | |
4186 for (i = 0; i < len; i++) { | |
4187 Interval* cur = _split_children.at(i); | |
4188 if (cur->from() <= op_id && op_id < cur->to() + to_offset) { | |
4189 if (i > 0) { | |
4190 // exchange current split child to start of list (faster access for next call) | |
4191 _split_children.at_put(i, _split_children.at(0)); | |
4192 _split_children.at_put(0, cur); | |
4193 } | |
4194 | |
4195 // interval found | |
4196 result = cur; | |
4197 break; | |
4198 } | |
4199 } | |
4200 | |
4201 #ifdef ASSERT | |
4202 for (i = 0; i < len; i++) { | |
4203 Interval* tmp = _split_children.at(i); | |
4204 if (tmp != result && tmp->from() <= op_id && op_id < tmp->to() + to_offset) { | |
4205 tty->print_cr("two valid result intervals found for op_id %d: %d and %d", op_id, result->reg_num(), tmp->reg_num()); | |
4206 result->print(); | |
4207 tmp->print(); | |
4208 assert(false, "two valid result intervals found"); | |
4209 } | |
4210 } | |
4211 #endif | |
4212 } | |
4213 | |
4214 assert(result != NULL, "no matching interval found"); | |
4215 assert(result->covers(op_id, mode), "op_id not covered by interval"); | |
4216 | |
4217 return result; | |
4218 } | |
4219 | |
4220 | |
4221 // returns the last split child that ends before the given op_id | |
4222 Interval* Interval::split_child_before_op_id(int op_id) { | |
4223 assert(op_id >= 0, "invalid op_id"); | |
4224 | |
4225 Interval* parent = split_parent(); | |
4226 Interval* result = NULL; | |
4227 | |
4228 int len = parent->_split_children.length(); | |
4229 assert(len > 0, "no split children available"); | |
4230 | |
4231 for (int i = len - 1; i >= 0; i--) { | |
4232 Interval* cur = parent->_split_children.at(i); | |
4233 if (cur->to() <= op_id && (result == NULL || result->to() < cur->to())) { | |
4234 result = cur; | |
4235 } | |
4236 } | |
4237 | |
4238 assert(result != NULL, "no split child found"); | |
4239 return result; | |
4240 } | |
4241 | |
4242 | |
4243 // checks if op_id is covered by any split child | |
4244 bool Interval::split_child_covers(int op_id, LIR_OpVisitState::OprMode mode) { | |
4245 assert(is_split_parent(), "can only be called for split parents"); | |
4246 assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)"); | |
4247 | |
4248 if (_split_children.length() == 0) { | |
4249 // simple case if interval was not split | |
4250 return covers(op_id, mode); | |
4251 | |
4252 } else { | |
4253 // extended case: check all split children | |
4254 int len = _split_children.length(); | |
4255 for (int i = 0; i < len; i++) { | |
4256 Interval* cur = _split_children.at(i); | |
4257 if (cur->covers(op_id, mode)) { | |
4258 return true; | |
4259 } | |
4260 } | |
4261 return false; | |
4262 } | |
4263 } | |
4264 | |
4265 | |
4266 // Note: use positions are sorted descending -> first use has highest index | |
4267 int Interval::first_usage(IntervalUseKind min_use_kind) const { | |
4268 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals"); | |
4269 | |
4270 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { | |
4271 if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) { | |
4272 return _use_pos_and_kinds.at(i); | |
4273 } | |
4274 } | |
4275 return max_jint; | |
4276 } | |
4277 | |
4278 int Interval::next_usage(IntervalUseKind min_use_kind, int from) const { | |
4279 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals"); | |
4280 | |
4281 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { | |
4282 if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) >= min_use_kind) { | |
4283 return _use_pos_and_kinds.at(i); | |
4284 } | |
4285 } | |
4286 return max_jint; | |
4287 } | |
4288 | |
4289 int Interval::next_usage_exact(IntervalUseKind exact_use_kind, int from) const { | |
4290 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals"); | |
4291 | |
4292 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { | |
4293 if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) == exact_use_kind) { | |
4294 return _use_pos_and_kinds.at(i); | |
4295 } | |
4296 } | |
4297 return max_jint; | |
4298 } | |
4299 | |
4300 int Interval::previous_usage(IntervalUseKind min_use_kind, int from) const { | |
4301 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals"); | |
4302 | |
4303 int prev = 0; | |
4304 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { | |
4305 if (_use_pos_and_kinds.at(i) > from) { | |
4306 return prev; | |
4307 } | |
4308 if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) { | |
4309 prev = _use_pos_and_kinds.at(i); | |
4310 } | |
4311 } | |
4312 return prev; | |
4313 } | |
4314 | |
4315 void Interval::add_use_pos(int pos, IntervalUseKind use_kind) { | |
4316 assert(covers(pos, LIR_OpVisitState::inputMode), "use position not covered by live range"); | |
4317 | |
4318 // do not add use positions for precolored intervals because | |
4319 // they are never used | |
4320 if (use_kind != noUse && reg_num() >= LIR_OprDesc::vreg_base) { | |
4321 #ifdef ASSERT | |
4322 assert(_use_pos_and_kinds.length() % 2 == 0, "must be"); | |
4323 for (int i = 0; i < _use_pos_and_kinds.length(); i += 2) { | |
4324 assert(pos <= _use_pos_and_kinds.at(i), "already added a use-position with lower position"); | |
4325 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind"); | |
4326 if (i > 0) { | |
4327 assert(_use_pos_and_kinds.at(i) < _use_pos_and_kinds.at(i - 2), "not sorted descending"); | |
4328 } | |
4329 } | |
4330 #endif | |
4331 | |
4332 // Note: add_use is called in descending order, so list gets sorted | |
4333 // automatically by just appending new use positions | |
4334 int len = _use_pos_and_kinds.length(); | |
4335 if (len == 0 || _use_pos_and_kinds.at(len - 2) > pos) { | |
4336 _use_pos_and_kinds.append(pos); | |
4337 _use_pos_and_kinds.append(use_kind); | |
4338 } else if (_use_pos_and_kinds.at(len - 1) < use_kind) { | |
4339 assert(_use_pos_and_kinds.at(len - 2) == pos, "list not sorted correctly"); | |
4340 _use_pos_and_kinds.at_put(len - 1, use_kind); | |
4341 } | |
4342 } | |
4343 } | |
4344 | |
4345 void Interval::add_range(int from, int to) { | |
4346 assert(from < to, "invalid range"); | |
4347 assert(first() == Range::end() || to < first()->next()->from(), "not inserting at begin of interval"); | |
4348 assert(from <= first()->to(), "not inserting at begin of interval"); | |
4349 | |
4350 if (first()->from() <= to) { | |
4351 // join intersecting ranges | |
4352 first()->set_from(MIN2(from, first()->from())); | |
4353 first()->set_to (MAX2(to, first()->to())); | |
4354 } else { | |
4355 // insert new range | |
4356 _first = new Range(from, to, first()); | |
4357 } | |
4358 } | |
4359 | |
4360 Interval* Interval::new_split_child() { | |
4361 // allocate new interval | |
4362 Interval* result = new Interval(-1); | |
4363 result->set_type(type()); | |
4364 | |
4365 Interval* parent = split_parent(); | |
4366 result->_split_parent = parent; | |
4367 result->set_register_hint(parent); | |
4368 | |
4369 // insert new interval in children-list of parent | |
4370 if (parent->_split_children.length() == 0) { | |
4371 assert(is_split_parent(), "list must be initialized at first split"); | |
4372 | |
4373 parent->_split_children = IntervalList(4); | |
4374 parent->_split_children.append(this); | |
4375 } | |
4376 parent->_split_children.append(result); | |
4377 | |
4378 return result; | |
4379 } | |
4380 | |
4381 // split this interval at the specified position and return | |
4382 // the remainder as a new interval. | |
4383 // | |
4384 // when an interval is split, a bi-directional link is established between the original interval | |
4385 // (the split parent) and the intervals that are split off this interval (the split children) | |
4386 // When a split child is split again, the new created interval is also a direct child | |
4387 // of the original parent (there is no tree of split children stored, but a flat list) | |
4388 // All split children are spilled to the same stack slot (stored in _canonical_spill_slot) | |
4389 // | |
4390 // Note: The new interval has no valid reg_num | |
4391 Interval* Interval::split(int split_pos) { | |
4392 assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals"); | |
4393 | |
4394 // allocate new interval | |
4395 Interval* result = new_split_child(); | |
4396 | |
4397 // split the ranges | |
4398 Range* prev = NULL; | |
4399 Range* cur = _first; | |
4400 while (cur != Range::end() && cur->to() <= split_pos) { | |
4401 prev = cur; | |
4402 cur = cur->next(); | |
4403 } | |
4404 assert(cur != Range::end(), "split interval after end of last range"); | |
4405 | |
4406 if (cur->from() < split_pos) { | |
4407 result->_first = new Range(split_pos, cur->to(), cur->next()); | |
4408 cur->set_to(split_pos); | |
4409 cur->set_next(Range::end()); | |
4410 | |
4411 } else { | |
4412 assert(prev != NULL, "split before start of first range"); | |
4413 result->_first = cur; | |
4414 prev->set_next(Range::end()); | |
4415 } | |
4416 result->_current = result->_first; | |
4417 _cached_to = -1; // clear cached value | |
4418 | |
4419 // split list of use positions | |
4420 int total_len = _use_pos_and_kinds.length(); | |
4421 int start_idx = total_len - 2; | |
4422 while (start_idx >= 0 && _use_pos_and_kinds.at(start_idx) < split_pos) { | |
4423 start_idx -= 2; | |
4424 } | |
4425 | |
4426 intStack new_use_pos_and_kinds(total_len - start_idx); | |
4427 int i; | |
4428 for (i = start_idx + 2; i < total_len; i++) { | |
4429 new_use_pos_and_kinds.append(_use_pos_and_kinds.at(i)); | |
4430 } | |
4431 | |
4432 _use_pos_and_kinds.truncate(start_idx + 2); | |
4433 result->_use_pos_and_kinds = _use_pos_and_kinds; | |
4434 _use_pos_and_kinds = new_use_pos_and_kinds; | |
4435 | |
4436 #ifdef ASSERT | |
4437 assert(_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos"); | |
4438 assert(result->_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos"); | |
4439 assert(_use_pos_and_kinds.length() + result->_use_pos_and_kinds.length() == total_len, "missed some entries"); | |
4440 | |
4441 for (i = 0; i < _use_pos_and_kinds.length(); i += 2) { | |
4442 assert(_use_pos_and_kinds.at(i) < split_pos, "must be"); | |
4443 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind"); | |
4444 } | |
4445 for (i = 0; i < result->_use_pos_and_kinds.length(); i += 2) { | |
4446 assert(result->_use_pos_and_kinds.at(i) >= split_pos, "must be"); | |
4447 assert(result->_use_pos_and_kinds.at(i + 1) >= firstValidKind && result->_use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind"); | |
4448 } | |
4449 #endif | |
4450 | |
4451 return result; | |
4452 } | |
4453 | |
4454 // split this interval at the specified position and return | |
4455 // the head as a new interval (the original interval is the tail) | |
4456 // | |
4457 // Currently, only the first range can be split, and the new interval | |
4458 // must not have split positions | |
4459 Interval* Interval::split_from_start(int split_pos) { | |
4460 assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals"); | |
4461 assert(split_pos > from() && split_pos < to(), "can only split inside interval"); | |
4462 assert(split_pos > _first->from() && split_pos <= _first->to(), "can only split inside first range"); | |
4463 assert(first_usage(noUse) > split_pos, "can not split when use positions are present"); | |
4464 | |
4465 // allocate new interval | |
4466 Interval* result = new_split_child(); | |
4467 | |
4468 // the new created interval has only one range (checked by assertion above), | |
4469 // so the splitting of the ranges is very simple | |
4470 result->add_range(_first->from(), split_pos); | |
4471 | |
4472 if (split_pos == _first->to()) { | |
4473 assert(_first->next() != Range::end(), "must not be at end"); | |
4474 _first = _first->next(); | |
4475 } else { | |
4476 _first->set_from(split_pos); | |
4477 } | |
4478 | |
4479 return result; | |
4480 } | |
4481 | |
4482 | |
4483 // returns true if the op_id is inside the interval | |
4484 bool Interval::covers(int op_id, LIR_OpVisitState::OprMode mode) const { | |
4485 Range* cur = _first; | |
4486 | |
4487 while (cur != Range::end() && cur->to() < op_id) { | |
4488 cur = cur->next(); | |
4489 } | |
4490 if (cur != Range::end()) { | |
4491 assert(cur->to() != cur->next()->from(), "ranges not separated"); | |
4492 | |
4493 if (mode == LIR_OpVisitState::outputMode) { | |
4494 return cur->from() <= op_id && op_id < cur->to(); | |
4495 } else { | |
4496 return cur->from() <= op_id && op_id <= cur->to(); | |
4497 } | |
4498 } | |
4499 return false; | |
4500 } | |
4501 | |
4502 // returns true if the interval has any hole between hole_from and hole_to | |
4503 // (even if the hole has only the length 1) | |
4504 bool Interval::has_hole_between(int hole_from, int hole_to) { | |
4505 assert(hole_from < hole_to, "check"); | |
4506 assert(from() <= hole_from && hole_to <= to(), "index out of interval"); | |
4507 | |
4508 Range* cur = _first; | |
4509 while (cur != Range::end()) { | |
4510 assert(cur->to() < cur->next()->from(), "no space between ranges"); | |
4511 | |
4512 // hole-range starts before this range -> hole | |
4513 if (hole_from < cur->from()) { | |
4514 return true; | |
4515 | |
4516 // hole-range completely inside this range -> no hole | |
4517 } else if (hole_to <= cur->to()) { | |
4518 return false; | |
4519 | |
4520 // overlapping of hole-range with this range -> hole | |
4521 } else if (hole_from <= cur->to()) { | |
4522 return true; | |
4523 } | |
4524 | |
4525 cur = cur->next(); | |
4526 } | |
4527 | |
4528 return false; | |
4529 } | |
4530 | |
4531 | |
4532 #ifndef PRODUCT | |
4533 void Interval::print(outputStream* out) const { | |
4534 const char* SpillState2Name[] = { "no definition", "no spill store", "one spill store", "store at definition", "start in memory", "no optimization" }; | |
4535 const char* UseKind2Name[] = { "N", "L", "S", "M" }; | |
4536 | |
4537 const char* type_name; | |
4538 LIR_Opr opr = LIR_OprFact::illegal(); | |
4539 if (reg_num() < LIR_OprDesc::vreg_base) { | |
4540 type_name = "fixed"; | |
4541 // need a temporary operand for fixed intervals because type() cannot be called | |
4542 if (assigned_reg() >= pd_first_cpu_reg && assigned_reg() <= pd_last_cpu_reg) { | |
4543 opr = LIR_OprFact::single_cpu(assigned_reg()); | |
4544 } else if (assigned_reg() >= pd_first_fpu_reg && assigned_reg() <= pd_last_fpu_reg) { | |
4545 opr = LIR_OprFact::single_fpu(assigned_reg() - pd_first_fpu_reg); | |
304 | 4546 #ifdef X86 |
0 | 4547 } else if (assigned_reg() >= pd_first_xmm_reg && assigned_reg() <= pd_last_xmm_reg) { |
4548 opr = LIR_OprFact::single_xmm(assigned_reg() - pd_first_xmm_reg); | |
4549 #endif | |
4550 } else { | |
4551 ShouldNotReachHere(); | |
4552 } | |
4553 } else { | |
4554 type_name = type2name(type()); | |
2081
7223744c2784
6579789: Internal error "c1_LinearScan.cpp:1429 Error: assert(false,"")" in debuggee with fastdebug VM
never
parents:
2002
diff
changeset
|
4555 if (assigned_reg() != -1 && |
7223744c2784
6579789: Internal error "c1_LinearScan.cpp:1429 Error: assert(false,"")" in debuggee with fastdebug VM
never
parents:
2002
diff
changeset
|
4556 (LinearScan::num_physical_regs(type()) == 1 || assigned_regHi() != -1)) { |
0 | 4557 opr = LinearScan::calc_operand_for_interval(this); |
4558 } | |
4559 } | |
4560 | |
4561 out->print("%d %s ", reg_num(), type_name); | |
4562 if (opr->is_valid()) { | |
4563 out->print("\""); | |
4564 opr->print(out); | |
4565 out->print("\" "); | |
4566 } | |
4567 out->print("%d %d ", split_parent()->reg_num(), (register_hint(false) != NULL ? register_hint(false)->reg_num() : -1)); | |
4568 | |
4569 // print ranges | |
4570 Range* cur = _first; | |
4571 while (cur != Range::end()) { | |
4572 cur->print(out); | |
4573 cur = cur->next(); | |
4574 assert(cur != NULL, "range list not closed with range sentinel"); | |
4575 } | |
4576 | |
4577 // print use positions | |
4578 int prev = 0; | |
4579 assert(_use_pos_and_kinds.length() % 2 == 0, "must be"); | |
4580 for (int i =_use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { | |
4581 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind"); | |
4582 assert(prev < _use_pos_and_kinds.at(i), "use positions not sorted"); | |
4583 | |
4584 out->print("%d %s ", _use_pos_and_kinds.at(i), UseKind2Name[_use_pos_and_kinds.at(i + 1)]); | |
4585 prev = _use_pos_and_kinds.at(i); | |
4586 } | |
4587 | |
4588 out->print(" \"%s\"", SpillState2Name[spill_state()]); | |
4589 out->cr(); | |
4590 } | |
4591 #endif | |
4592 | |
4593 | |
4594 | |
4595 // **** Implementation of IntervalWalker **************************** | |
4596 | |
4597 IntervalWalker::IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first) | |
4598 : _compilation(allocator->compilation()) | |
4599 , _allocator(allocator) | |
4600 { | |
4601 _unhandled_first[fixedKind] = unhandled_fixed_first; | |
4602 _unhandled_first[anyKind] = unhandled_any_first; | |
4603 _active_first[fixedKind] = Interval::end(); | |
4604 _inactive_first[fixedKind] = Interval::end(); | |
4605 _active_first[anyKind] = Interval::end(); | |
4606 _inactive_first[anyKind] = Interval::end(); | |
4607 _current_position = -1; | |
4608 _current = NULL; | |
4609 next_interval(); | |
4610 } | |
4611 | |
4612 | |
4613 // append interval at top of list | |
4614 void IntervalWalker::append_unsorted(Interval** list, Interval* interval) { | |
4615 interval->set_next(*list); *list = interval; | |
4616 } | |
4617 | |
4618 | |
4619 // append interval in order of current range from() | |
4620 void IntervalWalker::append_sorted(Interval** list, Interval* interval) { | |
4621 Interval* prev = NULL; | |
4622 Interval* cur = *list; | |
4623 while (cur->current_from() < interval->current_from()) { | |
4624 prev = cur; cur = cur->next(); | |
4625 } | |
4626 if (prev == NULL) { | |
4627 *list = interval; | |
4628 } else { | |
4629 prev->set_next(interval); | |
4630 } | |
4631 interval->set_next(cur); | |
4632 } | |
4633 | |
4634 void IntervalWalker::append_to_unhandled(Interval** list, Interval* interval) { | |
4635 assert(interval->from() >= current()->current_from(), "cannot append new interval before current walk position"); | |
4636 | |
4637 Interval* prev = NULL; | |
4638 Interval* cur = *list; | |
4639 while (cur->from() < interval->from() || (cur->from() == interval->from() && cur->first_usage(noUse) < interval->first_usage(noUse))) { | |
4640 prev = cur; cur = cur->next(); | |
4641 } | |
4642 if (prev == NULL) { | |
4643 *list = interval; | |
4644 } else { | |
4645 prev->set_next(interval); | |
4646 } | |
4647 interval->set_next(cur); | |
4648 } | |
4649 | |
4650 | |
4651 inline bool IntervalWalker::remove_from_list(Interval** list, Interval* i) { | |
4652 while (*list != Interval::end() && *list != i) { | |
4653 list = (*list)->next_addr(); | |
4654 } | |
4655 if (*list != Interval::end()) { | |
4656 assert(*list == i, "check"); | |
4657 *list = (*list)->next(); | |
4658 return true; | |
4659 } else { | |
4660 return false; | |
4661 } | |
4662 } | |
4663 | |
4664 void IntervalWalker::remove_from_list(Interval* i) { | |
4665 bool deleted; | |
4666 | |
4667 if (i->state() == activeState) { | |
4668 deleted = remove_from_list(active_first_addr(anyKind), i); | |
4669 } else { | |
4670 assert(i->state() == inactiveState, "invalid state"); | |
4671 deleted = remove_from_list(inactive_first_addr(anyKind), i); | |
4672 } | |
4673 | |
4674 assert(deleted, "interval has not been found in list"); | |
4675 } | |
4676 | |
4677 | |
4678 void IntervalWalker::walk_to(IntervalState state, int from) { | |
4679 assert (state == activeState || state == inactiveState, "wrong state"); | |
4680 for_each_interval_kind(kind) { | |
4681 Interval** prev = state == activeState ? active_first_addr(kind) : inactive_first_addr(kind); | |
4682 Interval* next = *prev; | |
4683 while (next->current_from() <= from) { | |
4684 Interval* cur = next; | |
4685 next = cur->next(); | |
4686 | |
4687 bool range_has_changed = false; | |
4688 while (cur->current_to() <= from) { | |
4689 cur->next_range(); | |
4690 range_has_changed = true; | |
4691 } | |
4692 | |
4693 // also handle move from inactive list to active list | |
4694 range_has_changed = range_has_changed || (state == inactiveState && cur->current_from() <= from); | |
4695 | |
4696 if (range_has_changed) { | |
4697 // remove cur from list | |
4698 *prev = next; | |
4699 if (cur->current_at_end()) { | |
4700 // move to handled state (not maintained as a list) | |
4701 cur->set_state(handledState); | |
4702 interval_moved(cur, kind, state, handledState); | |
4703 } else if (cur->current_from() <= from){ | |
4704 // sort into active list | |
4705 append_sorted(active_first_addr(kind), cur); | |
4706 cur->set_state(activeState); | |
4707 if (*prev == cur) { | |
4708 assert(state == activeState, "check"); | |
4709 prev = cur->next_addr(); | |
4710 } | |
4711 interval_moved(cur, kind, state, activeState); | |
4712 } else { | |
4713 // sort into inactive list | |
4714 append_sorted(inactive_first_addr(kind), cur); | |
4715 cur->set_state(inactiveState); | |
4716 if (*prev == cur) { | |
4717 assert(state == inactiveState, "check"); | |
4718 prev = cur->next_addr(); | |
4719 } | |
4720 interval_moved(cur, kind, state, inactiveState); | |
4721 } | |
4722 } else { | |
4723 prev = cur->next_addr(); | |
4724 continue; | |
4725 } | |
4726 } | |
4727 } | |
4728 } | |
4729 | |
4730 | |
4731 void IntervalWalker::next_interval() { | |
4732 IntervalKind kind; | |
4733 Interval* any = _unhandled_first[anyKind]; | |
4734 Interval* fixed = _unhandled_first[fixedKind]; | |
4735 | |
4736 if (any != Interval::end()) { | |
4737 // intervals may start at same position -> prefer fixed interval | |
4738 kind = fixed != Interval::end() && fixed->from() <= any->from() ? fixedKind : anyKind; | |
4739 | |
4740 assert (kind == fixedKind && fixed->from() <= any->from() || | |
4741 kind == anyKind && any->from() <= fixed->from(), "wrong interval!!!"); | |
4742 assert(any == Interval::end() || fixed == Interval::end() || any->from() != fixed->from() || kind == fixedKind, "if fixed and any-Interval start at same position, fixed must be processed first"); | |
4743 | |
4744 } else if (fixed != Interval::end()) { | |
4745 kind = fixedKind; | |
4746 } else { | |
4747 _current = NULL; return; | |
4748 } | |
4749 _current_kind = kind; | |
4750 _current = _unhandled_first[kind]; | |
4751 _unhandled_first[kind] = _current->next(); | |
4752 _current->set_next(Interval::end()); | |
4753 _current->rewind_range(); | |
4754 } | |
4755 | |
4756 | |
4757 void IntervalWalker::walk_to(int lir_op_id) { | |
4758 assert(_current_position <= lir_op_id, "can not walk backwards"); | |
4759 while (current() != NULL) { | |
4760 bool is_active = current()->from() <= lir_op_id; | |
4761 int id = is_active ? current()->from() : lir_op_id; | |
4762 | |
4763 TRACE_LINEAR_SCAN(2, if (_current_position < id) { tty->cr(); tty->print_cr("walk_to(%d) **************************************************************", id); }) | |
4764 | |
4765 // set _current_position prior to call of walk_to | |
4766 _current_position = id; | |
4767 | |
4768 // call walk_to even if _current_position == id | |
4769 walk_to(activeState, id); | |
4770 walk_to(inactiveState, id); | |
4771 | |
4772 if (is_active) { | |
4773 current()->set_state(activeState); | |
4774 if (activate_current()) { | |
4775 append_sorted(active_first_addr(current_kind()), current()); | |
4776 interval_moved(current(), current_kind(), unhandledState, activeState); | |
4777 } | |
4778 | |
4779 next_interval(); | |
4780 } else { | |
4781 return; | |
4782 } | |
4783 } | |
4784 } | |
4785 | |
4786 void IntervalWalker::interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to) { | |
4787 #ifndef PRODUCT | |
4788 if (TraceLinearScanLevel >= 4) { | |
4789 #define print_state(state) \ | |
4790 switch(state) {\ | |
4791 case unhandledState: tty->print("unhandled"); break;\ | |
4792 case activeState: tty->print("active"); break;\ | |
4793 case inactiveState: tty->print("inactive"); break;\ | |
4794 case handledState: tty->print("handled"); break;\ | |
4795 default: ShouldNotReachHere(); \ | |
4796 } | |
4797 | |
4798 print_state(from); tty->print(" to "); print_state(to); | |
4799 tty->fill_to(23); | |
4800 interval->print(); | |
4801 | |
4802 #undef print_state | |
4803 } | |
4804 #endif | |
4805 } | |
4806 | |
4807 | |
4808 | |
4809 // **** Implementation of LinearScanWalker ************************** | |
4810 | |
4811 LinearScanWalker::LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first) | |
4812 : IntervalWalker(allocator, unhandled_fixed_first, unhandled_any_first) | |
4813 , _move_resolver(allocator) | |
4814 { | |
4815 for (int i = 0; i < LinearScan::nof_regs; i++) { | |
4816 _spill_intervals[i] = new IntervalList(2); | |
4817 } | |
4818 } | |
4819 | |
4820 | |
4821 inline void LinearScanWalker::init_use_lists(bool only_process_use_pos) { | |
4822 for (int i = _first_reg; i <= _last_reg; i++) { | |
4823 _use_pos[i] = max_jint; | |
4824 | |
4825 if (!only_process_use_pos) { | |
4826 _block_pos[i] = max_jint; | |
4827 _spill_intervals[i]->clear(); | |
4828 } | |
4829 } | |
4830 } | |
4831 | |
4832 inline void LinearScanWalker::exclude_from_use(int reg) { | |
4833 assert(reg < LinearScan::nof_regs, "interval must have a register assigned (stack slots not allowed)"); | |
4834 if (reg >= _first_reg && reg <= _last_reg) { | |
4835 _use_pos[reg] = 0; | |
4836 } | |
4837 } | |
4838 inline void LinearScanWalker::exclude_from_use(Interval* i) { | |
4839 assert(i->assigned_reg() != any_reg, "interval has no register assigned"); | |
4840 | |
4841 exclude_from_use(i->assigned_reg()); | |
4842 exclude_from_use(i->assigned_regHi()); | |
4843 } | |
4844 | |
4845 inline void LinearScanWalker::set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos) { | |
4846 assert(use_pos != 0, "must use exclude_from_use to set use_pos to 0"); | |
4847 | |
4848 if (reg >= _first_reg && reg <= _last_reg) { | |
4849 if (_use_pos[reg] > use_pos) { | |
4850 _use_pos[reg] = use_pos; | |
4851 } | |
4852 if (!only_process_use_pos) { | |
4853 _spill_intervals[reg]->append(i); | |
4854 } | |
4855 } | |
4856 } | |
4857 inline void LinearScanWalker::set_use_pos(Interval* i, int use_pos, bool only_process_use_pos) { | |
4858 assert(i->assigned_reg() != any_reg, "interval has no register assigned"); | |
4859 if (use_pos != -1) { | |
4860 set_use_pos(i->assigned_reg(), i, use_pos, only_process_use_pos); | |
4861 set_use_pos(i->assigned_regHi(), i, use_pos, only_process_use_pos); | |
4862 } | |
4863 } | |
4864 | |
4865 inline void LinearScanWalker::set_block_pos(int reg, Interval* i, int block_pos) { | |
4866 if (reg >= _first_reg && reg <= _last_reg) { | |
4867 if (_block_pos[reg] > block_pos) { | |
4868 _block_pos[reg] = block_pos; | |
4869 } | |
4870 if (_use_pos[reg] > block_pos) { | |
4871 _use_pos[reg] = block_pos; | |
4872 } | |
4873 } | |
4874 } | |
4875 inline void LinearScanWalker::set_block_pos(Interval* i, int block_pos) { | |
4876 assert(i->assigned_reg() != any_reg, "interval has no register assigned"); | |
4877 if (block_pos != -1) { | |
4878 set_block_pos(i->assigned_reg(), i, block_pos); | |
4879 set_block_pos(i->assigned_regHi(), i, block_pos); | |
4880 } | |
4881 } | |
4882 | |
4883 | |
4884 void LinearScanWalker::free_exclude_active_fixed() { | |
4885 Interval* list = active_first(fixedKind); | |
4886 while (list != Interval::end()) { | |
4887 assert(list->assigned_reg() < LinearScan::nof_regs, "active interval must have a register assigned"); | |
4888 exclude_from_use(list); | |
4889 list = list->next(); | |
4890 } | |
4891 } | |
4892 | |
4893 void LinearScanWalker::free_exclude_active_any() { | |
4894 Interval* list = active_first(anyKind); | |
4895 while (list != Interval::end()) { | |
4896 exclude_from_use(list); | |
4897 list = list->next(); | |
4898 } | |
4899 } | |
4900 | |
4901 void LinearScanWalker::free_collect_inactive_fixed(Interval* cur) { | |
4902 Interval* list = inactive_first(fixedKind); | |
4903 while (list != Interval::end()) { | |
4904 if (cur->to() <= list->current_from()) { | |
4905 assert(list->current_intersects_at(cur) == -1, "must not intersect"); | |
4906 set_use_pos(list, list->current_from(), true); | |
4907 } else { | |
4908 set_use_pos(list, list->current_intersects_at(cur), true); | |
4909 } | |
4910 list = list->next(); | |
4911 } | |
4912 } | |
4913 | |
4914 void LinearScanWalker::free_collect_inactive_any(Interval* cur) { | |
4915 Interval* list = inactive_first(anyKind); | |
4916 while (list != Interval::end()) { | |
4917 set_use_pos(list, list->current_intersects_at(cur), true); | |
4918 list = list->next(); | |
4919 } | |
4920 } | |
4921 | |
4922 void LinearScanWalker::free_collect_unhandled(IntervalKind kind, Interval* cur) { | |
4923 Interval* list = unhandled_first(kind); | |
4924 while (list != Interval::end()) { | |
4925 set_use_pos(list, list->intersects_at(cur), true); | |
4926 if (kind == fixedKind && cur->to() <= list->from()) { | |
4927 set_use_pos(list, list->from(), true); | |
4928 } | |
4929 list = list->next(); | |
4930 } | |
4931 } | |
4932 | |
4933 void LinearScanWalker::spill_exclude_active_fixed() { | |
4934 Interval* list = active_first(fixedKind); | |
4935 while (list != Interval::end()) { | |
4936 exclude_from_use(list); | |
4937 list = list->next(); | |
4938 } | |
4939 } | |
4940 | |
4941 void LinearScanWalker::spill_block_unhandled_fixed(Interval* cur) { | |
4942 Interval* list = unhandled_first(fixedKind); | |
4943 while (list != Interval::end()) { | |
4944 set_block_pos(list, list->intersects_at(cur)); | |
4945 list = list->next(); | |
4946 } | |
4947 } | |
4948 | |
4949 void LinearScanWalker::spill_block_inactive_fixed(Interval* cur) { | |
4950 Interval* list = inactive_first(fixedKind); | |
4951 while (list != Interval::end()) { | |
4952 if (cur->to() > list->current_from()) { | |
4953 set_block_pos(list, list->current_intersects_at(cur)); | |
4954 } else { | |
4955 assert(list->current_intersects_at(cur) == -1, "invalid optimization: intervals intersect"); | |
4956 } | |
4957 | |
4958 list = list->next(); | |
4959 } | |
4960 } | |
4961 | |
4962 void LinearScanWalker::spill_collect_active_any() { | |
4963 Interval* list = active_first(anyKind); | |
4964 while (list != Interval::end()) { | |
4965 set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false); | |
4966 list = list->next(); | |
4967 } | |
4968 } | |
4969 | |
4970 void LinearScanWalker::spill_collect_inactive_any(Interval* cur) { | |
4971 Interval* list = inactive_first(anyKind); | |
4972 while (list != Interval::end()) { | |
4973 if (list->current_intersects(cur)) { | |
4974 set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false); | |
4975 } | |
4976 list = list->next(); | |
4977 } | |
4978 } | |
4979 | |
4980 | |
4981 void LinearScanWalker::insert_move(int op_id, Interval* src_it, Interval* dst_it) { | |
4982 // output all moves here. When source and target are equal, the move is | |
4983 // optimized away later in assign_reg_nums | |
4984 | |
4985 op_id = (op_id + 1) & ~1; | |
4986 BlockBegin* op_block = allocator()->block_of_op_with_id(op_id); | |
4987 assert(op_id > 0 && allocator()->block_of_op_with_id(op_id - 2) == op_block, "cannot insert move at block boundary"); | |
4988 | |
4989 // calculate index of instruction inside instruction list of current block | |
4990 // the minimal index (for a block with no spill moves) can be calculated because the | |
4991 // numbering of instructions is known. | |
4992 // When the block already contains spill moves, the index must be increased until the | |
4993 // correct index is reached. | |
4994 LIR_OpList* list = op_block->lir()->instructions_list(); | |
4995 int index = (op_id - list->at(0)->id()) / 2; | |
4996 assert(list->at(index)->id() <= op_id, "error in calculation"); | |
4997 | |
4998 while (list->at(index)->id() != op_id) { | |
4999 index++; | |
5000 assert(0 <= index && index < list->length(), "index out of bounds"); | |
5001 } | |
5002 assert(1 <= index && index < list->length(), "index out of bounds"); | |
5003 assert(list->at(index)->id() == op_id, "error in calculation"); | |
5004 | |
5005 // insert new instruction before instruction at position index | |
5006 _move_resolver.move_insert_position(op_block->lir(), index - 1); | |
5007 _move_resolver.add_mapping(src_it, dst_it); | |
5008 } | |
5009 | |
5010 | |
5011 int LinearScanWalker::find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos) { | |
5012 int from_block_nr = min_block->linear_scan_number(); | |
5013 int to_block_nr = max_block->linear_scan_number(); | |
5014 | |
5015 assert(0 <= from_block_nr && from_block_nr < block_count(), "out of range"); | |
5016 assert(0 <= to_block_nr && to_block_nr < block_count(), "out of range"); | |
5017 assert(from_block_nr < to_block_nr, "must cross block boundary"); | |
5018 | |
5019 // Try to split at end of max_block. If this would be after | |
5020 // max_split_pos, then use the begin of max_block | |
5021 int optimal_split_pos = max_block->last_lir_instruction_id() + 2; | |
5022 if (optimal_split_pos > max_split_pos) { | |
5023 optimal_split_pos = max_block->first_lir_instruction_id(); | |
5024 } | |
5025 | |
5026 int min_loop_depth = max_block->loop_depth(); | |
5027 for (int i = to_block_nr - 1; i >= from_block_nr; i--) { | |
5028 BlockBegin* cur = block_at(i); | |
5029 | |
5030 if (cur->loop_depth() < min_loop_depth) { | |
5031 // block with lower loop-depth found -> split at the end of this block | |
5032 min_loop_depth = cur->loop_depth(); | |
5033 optimal_split_pos = cur->last_lir_instruction_id() + 2; | |
5034 } | |
5035 } | |
5036 assert(optimal_split_pos > allocator()->max_lir_op_id() || allocator()->is_block_begin(optimal_split_pos), "algorithm must move split pos to block boundary"); | |
5037 | |
5038 return optimal_split_pos; | |
5039 } | |
5040 | |
5041 | |
5042 int LinearScanWalker::find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization) { | |
5043 int optimal_split_pos = -1; | |
5044 if (min_split_pos == max_split_pos) { | |
5045 // trivial case, no optimization of split position possible | |
5046 TRACE_LINEAR_SCAN(4, tty->print_cr(" min-pos and max-pos are equal, no optimization possible")); | |
5047 optimal_split_pos = min_split_pos; | |
5048 | |
5049 } else { | |
5050 assert(min_split_pos < max_split_pos, "must be true then"); | |
5051 assert(min_split_pos > 0, "cannot access min_split_pos - 1 otherwise"); | |
5052 | |
5053 // reason for using min_split_pos - 1: when the minimal split pos is exactly at the | |
5054 // beginning of a block, then min_split_pos is also a possible split position. | |
5055 // Use the block before as min_block, because then min_block->last_lir_instruction_id() + 2 == min_split_pos | |
5056 BlockBegin* min_block = allocator()->block_of_op_with_id(min_split_pos - 1); | |
5057 | |
5058 // reason for using max_split_pos - 1: otherwise there would be an assertion failure | |
5059 // when an interval ends at the end of the last block of the method | |
5060 // (in this case, max_split_pos == allocator()->max_lir_op_id() + 2, and there is no | |
5061 // block at this op_id) | |
5062 BlockBegin* max_block = allocator()->block_of_op_with_id(max_split_pos - 1); | |
5063 | |
5064 assert(min_block->linear_scan_number() <= max_block->linear_scan_number(), "invalid order"); | |
5065 if (min_block == max_block) { | |
5066 // split position cannot be moved to block boundary, so split as late as possible | |
5067 TRACE_LINEAR_SCAN(4, tty->print_cr(" cannot move split pos to block boundary because min_pos and max_pos are in same block")); | |
5068 optimal_split_pos = max_split_pos; | |
5069 | |
5070 } else if (it->has_hole_between(max_split_pos - 1, max_split_pos) && !allocator()->is_block_begin(max_split_pos)) { | |
5071 // Do not move split position if the interval has a hole before max_split_pos. | |
5072 // Intervals resulting from Phi-Functions have more than one definition (marked | |
5073 // as mustHaveRegister) with a hole before each definition. When the register is needed | |
5074 // for the second definition, an earlier reloading is unnecessary. | |
5075 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has hole just before max_split_pos, so splitting at max_split_pos")); | |
5076 optimal_split_pos = max_split_pos; | |
5077 | |
5078 } else { | |
5079 // seach optimal block boundary between min_split_pos and max_split_pos | |
5080 TRACE_LINEAR_SCAN(4, tty->print_cr(" moving split pos to optimal block boundary between block B%d and B%d", min_block->block_id(), max_block->block_id())); | |
5081 | |
5082 if (do_loop_optimization) { | |
5083 // Loop optimization: if a loop-end marker is found between min- and max-position, | |
5084 // then split before this loop | |
5085 int loop_end_pos = it->next_usage_exact(loopEndMarker, min_block->last_lir_instruction_id() + 2); | |
5086 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization: loop end found at pos %d", loop_end_pos)); | |
5087 | |
5088 assert(loop_end_pos > min_split_pos, "invalid order"); | |
5089 if (loop_end_pos < max_split_pos) { | |
5090 // loop-end marker found between min- and max-position | |
5091 // if it is not the end marker for the same loop as the min-position, then move | |
5092 // the max-position to this loop block. | |
5093 // Desired result: uses tagged as shouldHaveRegister inside a loop cause a reloading | |
5094 // of the interval (normally, only mustHaveRegister causes a reloading) | |
5095 BlockBegin* loop_block = allocator()->block_of_op_with_id(loop_end_pos); | |
5096 | |
5097 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval is used in loop that ends in block B%d, so trying to move max_block back from B%d to B%d", loop_block->block_id(), max_block->block_id(), loop_block->block_id())); | |
5098 assert(loop_block != min_block, "loop_block and min_block must be different because block boundary is needed between"); | |
5099 | |
5100 optimal_split_pos = find_optimal_split_pos(min_block, loop_block, loop_block->last_lir_instruction_id() + 2); | |
5101 if (optimal_split_pos == loop_block->last_lir_instruction_id() + 2) { | |
5102 optimal_split_pos = -1; | |
5103 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization not necessary")); | |
5104 } else { | |
5105 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization successful")); | |
5106 } | |
5107 } | |
5108 } | |
5109 | |
5110 if (optimal_split_pos == -1) { | |
5111 // not calculated by loop optimization | |
5112 optimal_split_pos = find_optimal_split_pos(min_block, max_block, max_split_pos); | |
5113 } | |
5114 } | |
5115 } | |
5116 TRACE_LINEAR_SCAN(4, tty->print_cr(" optimal split position: %d", optimal_split_pos)); | |
5117 | |
5118 return optimal_split_pos; | |
5119 } | |
5120 | |
5121 | |
5122 /* | |
5123 split an interval at the optimal position between min_split_pos and | |
5124 max_split_pos in two parts: | |
5125 1) the left part has already a location assigned | |
5126 2) the right part is sorted into to the unhandled-list | |
5127 */ | |
5128 void LinearScanWalker::split_before_usage(Interval* it, int min_split_pos, int max_split_pos) { | |
5129 TRACE_LINEAR_SCAN(2, tty->print ("----- splitting interval: "); it->print()); | |
5130 TRACE_LINEAR_SCAN(2, tty->print_cr(" between %d and %d", min_split_pos, max_split_pos)); | |
5131 | |
5132 assert(it->from() < min_split_pos, "cannot split at start of interval"); | |
5133 assert(current_position() < min_split_pos, "cannot split before current position"); | |
5134 assert(min_split_pos <= max_split_pos, "invalid order"); | |
5135 assert(max_split_pos <= it->to(), "cannot split after end of interval"); | |
5136 | |
5137 int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, true); | |
5138 | |
5139 assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range"); | |
5140 assert(optimal_split_pos <= it->to(), "cannot split after end of interval"); | |
5141 assert(optimal_split_pos > it->from(), "cannot split at start of interval"); | |
5142 | |
5143 if (optimal_split_pos == it->to() && it->next_usage(mustHaveRegister, min_split_pos) == max_jint) { | |
5144 // the split position would be just before the end of the interval | |
5145 // -> no split at all necessary | |
5146 TRACE_LINEAR_SCAN(4, tty->print_cr(" no split necessary because optimal split position is at end of interval")); | |
5147 return; | |
5148 } | |
5149 | |
5150 // must calculate this before the actual split is performed and before split position is moved to odd op_id | |
5151 bool move_necessary = !allocator()->is_block_begin(optimal_split_pos) && !it->has_hole_between(optimal_split_pos - 1, optimal_split_pos); | |
5152 | |
5153 if (!allocator()->is_block_begin(optimal_split_pos)) { | |
5154 // move position before actual instruction (odd op_id) | |
5155 optimal_split_pos = (optimal_split_pos - 1) | 1; | |
5156 } | |
5157 | |
5158 TRACE_LINEAR_SCAN(4, tty->print_cr(" splitting at position %d", optimal_split_pos)); | |
5159 assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary"); | |
5160 assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary"); | |
5161 | |
5162 Interval* split_part = it->split(optimal_split_pos); | |
5163 | |
5164 allocator()->append_interval(split_part); | |
5165 allocator()->copy_register_flags(it, split_part); | |
5166 split_part->set_insert_move_when_activated(move_necessary); | |
5167 append_to_unhandled(unhandled_first_addr(anyKind), split_part); | |
5168 | |
5169 TRACE_LINEAR_SCAN(2, tty->print_cr(" split interval in two parts (insert_move_when_activated: %d)", move_necessary)); | |
5170 TRACE_LINEAR_SCAN(2, tty->print (" "); it->print()); | |
5171 TRACE_LINEAR_SCAN(2, tty->print (" "); split_part->print()); | |
5172 } | |
5173 | |
5174 /* | |
5175 split an interval at the optimal position between min_split_pos and | |
5176 max_split_pos in two parts: | |
5177 1) the left part has already a location assigned | |
5178 2) the right part is always on the stack and therefore ignored in further processing | |
5179 */ | |
5180 void LinearScanWalker::split_for_spilling(Interval* it) { | |
5181 // calculate allowed range of splitting position | |
5182 int max_split_pos = current_position(); | |
5183 int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, max_split_pos) + 1, it->from()); | |
5184 | |
5185 TRACE_LINEAR_SCAN(2, tty->print ("----- splitting and spilling interval: "); it->print()); | |
5186 TRACE_LINEAR_SCAN(2, tty->print_cr(" between %d and %d", min_split_pos, max_split_pos)); | |
5187 | |
5188 assert(it->state() == activeState, "why spill interval that is not active?"); | |
5189 assert(it->from() <= min_split_pos, "cannot split before start of interval"); | |
5190 assert(min_split_pos <= max_split_pos, "invalid order"); | |
5191 assert(max_split_pos < it->to(), "cannot split at end end of interval"); | |
5192 assert(current_position() < it->to(), "interval must not end before current position"); | |
5193 | |
5194 if (min_split_pos == it->from()) { | |
5195 // the whole interval is never used, so spill it entirely to memory | |
5196 TRACE_LINEAR_SCAN(2, tty->print_cr(" spilling entire interval because split pos is at beginning of interval")); | |
5197 assert(it->first_usage(shouldHaveRegister) > current_position(), "interval must not have use position before current_position"); | |
5198 | |
5199 allocator()->assign_spill_slot(it); | |
5200 allocator()->change_spill_state(it, min_split_pos); | |
5201 | |
5202 // Also kick parent intervals out of register to memory when they have no use | |
5203 // position. This avoids short interval in register surrounded by intervals in | |
5204 // memory -> avoid useless moves from memory to register and back | |
5205 Interval* parent = it; | |
5206 while (parent != NULL && parent->is_split_child()) { | |
5207 parent = parent->split_child_before_op_id(parent->from()); | |
5208 | |
5209 if (parent->assigned_reg() < LinearScan::nof_regs) { | |
5210 if (parent->first_usage(shouldHaveRegister) == max_jint) { | |
5211 // parent is never used, so kick it out of its assigned register | |
5212 TRACE_LINEAR_SCAN(4, tty->print_cr(" kicking out interval %d out of its register because it is never used", parent->reg_num())); | |
5213 allocator()->assign_spill_slot(parent); | |
5214 } else { | |
5215 // do not go further back because the register is actually used by the interval | |
5216 parent = NULL; | |
5217 } | |
5218 } | |
5219 } | |
5220 | |
5221 } else { | |
5222 // search optimal split pos, split interval and spill only the right hand part | |
5223 int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, false); | |
5224 | |
5225 assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range"); | |
5226 assert(optimal_split_pos < it->to(), "cannot split at end of interval"); | |
5227 assert(optimal_split_pos >= it->from(), "cannot split before start of interval"); | |
5228 | |
5229 if (!allocator()->is_block_begin(optimal_split_pos)) { | |
5230 // move position before actual instruction (odd op_id) | |
5231 optimal_split_pos = (optimal_split_pos - 1) | 1; | |
5232 } | |
5233 | |
5234 TRACE_LINEAR_SCAN(4, tty->print_cr(" splitting at position %d", optimal_split_pos)); | |
5235 assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary"); | |
5236 assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary"); | |
5237 | |
5238 Interval* spilled_part = it->split(optimal_split_pos); | |
5239 allocator()->append_interval(spilled_part); | |
5240 allocator()->assign_spill_slot(spilled_part); | |
5241 allocator()->change_spill_state(spilled_part, optimal_split_pos); | |
5242 | |
5243 if (!allocator()->is_block_begin(optimal_split_pos)) { | |
5244 TRACE_LINEAR_SCAN(4, tty->print_cr(" inserting move from interval %d to %d", it->reg_num(), spilled_part->reg_num())); | |
5245 insert_move(optimal_split_pos, it, spilled_part); | |
5246 } | |
5247 | |
5248 // the current_split_child is needed later when moves are inserted for reloading | |
5249 assert(spilled_part->current_split_child() == it, "overwriting wrong current_split_child"); | |
5250 spilled_part->make_current_split_child(); | |
5251 | |
5252 TRACE_LINEAR_SCAN(2, tty->print_cr(" split interval in two parts")); | |
5253 TRACE_LINEAR_SCAN(2, tty->print (" "); it->print()); | |
5254 TRACE_LINEAR_SCAN(2, tty->print (" "); spilled_part->print()); | |
5255 } | |
5256 } | |
5257 | |
5258 | |
5259 void LinearScanWalker::split_stack_interval(Interval* it) { | |
5260 int min_split_pos = current_position() + 1; | |
5261 int max_split_pos = MIN2(it->first_usage(shouldHaveRegister), it->to()); | |
5262 | |
5263 split_before_usage(it, min_split_pos, max_split_pos); | |
5264 } | |
5265 | |
5266 void LinearScanWalker::split_when_partial_register_available(Interval* it, int register_available_until) { | |
5267 int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, register_available_until), it->from() + 1); | |
5268 int max_split_pos = register_available_until; | |
5269 | |
5270 split_before_usage(it, min_split_pos, max_split_pos); | |
5271 } | |
5272 | |
5273 void LinearScanWalker::split_and_spill_interval(Interval* it) { | |
5274 assert(it->state() == activeState || it->state() == inactiveState, "other states not allowed"); | |
5275 | |
5276 int current_pos = current_position(); | |
5277 if (it->state() == inactiveState) { | |
5278 // the interval is currently inactive, so no spill slot is needed for now. | |
5279 // when the split part is activated, the interval has a new chance to get a register, | |
5280 // so in the best case no stack slot is necessary | |
5281 assert(it->has_hole_between(current_pos - 1, current_pos + 1), "interval can not be inactive otherwise"); | |
5282 split_before_usage(it, current_pos + 1, current_pos + 1); | |
5283 | |
5284 } else { | |
5285 // search the position where the interval must have a register and split | |
5286 // at the optimal position before. | |
5287 // The new created part is added to the unhandled list and will get a register | |
5288 // when it is activated | |
5289 int min_split_pos = current_pos + 1; | |
5290 int max_split_pos = MIN2(it->next_usage(mustHaveRegister, min_split_pos), it->to()); | |
5291 | |
5292 split_before_usage(it, min_split_pos, max_split_pos); | |
5293 | |
5294 assert(it->next_usage(mustHaveRegister, current_pos) == max_jint, "the remaining part is spilled to stack and therefore has no register"); | |
5295 split_for_spilling(it); | |
5296 } | |
5297 } | |
5298 | |
5299 | |
5300 int LinearScanWalker::find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) { | |
5301 int min_full_reg = any_reg; | |
5302 int max_partial_reg = any_reg; | |
5303 | |
5304 for (int i = _first_reg; i <= _last_reg; i++) { | |
5305 if (i == ignore_reg) { | |
5306 // this register must be ignored | |
5307 | |
5308 } else if (_use_pos[i] >= interval_to) { | |
5309 // this register is free for the full interval | |
5310 if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) { | |
5311 min_full_reg = i; | |
5312 } | |
5313 } else if (_use_pos[i] > reg_needed_until) { | |
5314 // this register is at least free until reg_needed_until | |
5315 if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) { | |
5316 max_partial_reg = i; | |
5317 } | |
5318 } | |
5319 } | |
5320 | |
5321 if (min_full_reg != any_reg) { | |
5322 return min_full_reg; | |
5323 } else if (max_partial_reg != any_reg) { | |
5324 *need_split = true; | |
5325 return max_partial_reg; | |
5326 } else { | |
5327 return any_reg; | |
5328 } | |
5329 } | |
5330 | |
5331 int LinearScanWalker::find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) { | |
5332 assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm"); | |
5333 | |
5334 int min_full_reg = any_reg; | |
5335 int max_partial_reg = any_reg; | |
5336 | |
5337 for (int i = _first_reg; i < _last_reg; i+=2) { | |
5338 if (_use_pos[i] >= interval_to && _use_pos[i + 1] >= interval_to) { | |
5339 // this register is free for the full interval | |
5340 if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) { | |
5341 min_full_reg = i; | |
5342 } | |
5343 } else if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) { | |
5344 // this register is at least free until reg_needed_until | |
5345 if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) { | |
5346 max_partial_reg = i; | |
5347 } | |
5348 } | |
5349 } | |
5350 | |
5351 if (min_full_reg != any_reg) { | |
5352 return min_full_reg; | |
5353 } else if (max_partial_reg != any_reg) { | |
5354 *need_split = true; | |
5355 return max_partial_reg; | |
5356 } else { | |
5357 return any_reg; | |
5358 } | |
5359 } | |
5360 | |
5361 | |
5362 bool LinearScanWalker::alloc_free_reg(Interval* cur) { | |
5363 TRACE_LINEAR_SCAN(2, tty->print("trying to find free register for "); cur->print()); | |
5364 | |
5365 init_use_lists(true); | |
5366 free_exclude_active_fixed(); | |
5367 free_exclude_active_any(); | |
5368 free_collect_inactive_fixed(cur); | |
5369 free_collect_inactive_any(cur); | |
5370 // free_collect_unhandled(fixedKind, cur); | |
5371 assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0"); | |
5372 | |
5373 // _use_pos contains the start of the next interval that has this register assigned | |
5374 // (either as a fixed register or a normal allocated register in the past) | |
5375 // only intervals overlapping with cur are processed, non-overlapping invervals can be ignored safely | |
5376 TRACE_LINEAR_SCAN(4, tty->print_cr(" state of registers:")); | |
5377 TRACE_LINEAR_SCAN(4, for (int i = _first_reg; i <= _last_reg; i++) tty->print_cr(" reg %d: use_pos: %d", i, _use_pos[i])); | |
5378 | |
5379 int hint_reg, hint_regHi; | |
5380 Interval* register_hint = cur->register_hint(); | |
5381 if (register_hint != NULL) { | |
5382 hint_reg = register_hint->assigned_reg(); | |
5383 hint_regHi = register_hint->assigned_regHi(); | |
5384 | |
5385 if (allocator()->is_precolored_cpu_interval(register_hint)) { | |
5386 assert(hint_reg != any_reg && hint_regHi == any_reg, "must be for fixed intervals"); | |
5387 hint_regHi = hint_reg + 1; // connect e.g. eax-edx | |
5388 } | |
5389 TRACE_LINEAR_SCAN(4, tty->print(" hint registers %d, %d from interval ", hint_reg, hint_regHi); register_hint->print()); | |
5390 | |
5391 } else { | |
5392 hint_reg = any_reg; | |
5393 hint_regHi = any_reg; | |
5394 } | |
5395 assert(hint_reg == any_reg || hint_reg != hint_regHi, "hint reg and regHi equal"); | |
5396 assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned to interval"); | |
5397 | |
5398 // the register must be free at least until this position | |
5399 int reg_needed_until = cur->from() + 1; | |
5400 int interval_to = cur->to(); | |
5401 | |
5402 bool need_split = false; | |
5403 int split_pos = -1; | |
5404 int reg = any_reg; | |
5405 int regHi = any_reg; | |
5406 | |
5407 if (_adjacent_regs) { | |
5408 reg = find_free_double_reg(reg_needed_until, interval_to, hint_reg, &need_split); | |
5409 regHi = reg + 1; | |
5410 if (reg == any_reg) { | |
5411 return false; | |
5412 } | |
5413 split_pos = MIN2(_use_pos[reg], _use_pos[regHi]); | |
5414 | |
5415 } else { | |
5416 reg = find_free_reg(reg_needed_until, interval_to, hint_reg, any_reg, &need_split); | |
5417 if (reg == any_reg) { | |
5418 return false; | |
5419 } | |
5420 split_pos = _use_pos[reg]; | |
5421 | |
5422 if (_num_phys_regs == 2) { | |
5423 regHi = find_free_reg(reg_needed_until, interval_to, hint_regHi, reg, &need_split); | |
5424 | |
5425 if (_use_pos[reg] < interval_to && regHi == any_reg) { | |
5426 // do not split interval if only one register can be assigned until the split pos | |
5427 // (when one register is found for the whole interval, split&spill is only | |
5428 // performed for the hi register) | |
5429 return false; | |
5430 | |
5431 } else if (regHi != any_reg) { | |
5432 split_pos = MIN2(split_pos, _use_pos[regHi]); | |
5433 | |
5434 // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax | |
5435 if (reg > regHi) { | |
5436 int temp = reg; | |
5437 reg = regHi; | |
5438 regHi = temp; | |
5439 } | |
5440 } | |
5441 } | |
5442 } | |
5443 | |
5444 cur->assign_reg(reg, regHi); | |
5445 TRACE_LINEAR_SCAN(2, tty->print_cr("selected register %d, %d", reg, regHi)); | |
5446 | |
5447 assert(split_pos > 0, "invalid split_pos"); | |
5448 if (need_split) { | |
5449 // register not available for full interval, so split it | |
5450 split_when_partial_register_available(cur, split_pos); | |
5451 } | |
5452 | |
5453 // only return true if interval is completely assigned | |
5454 return _num_phys_regs == 1 || regHi != any_reg; | |
5455 } | |
5456 | |
5457 | |
5458 int LinearScanWalker::find_locked_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) { | |
5459 int max_reg = any_reg; | |
5460 | |
5461 for (int i = _first_reg; i <= _last_reg; i++) { | |
5462 if (i == ignore_reg) { | |
5463 // this register must be ignored | |
5464 | |
5465 } else if (_use_pos[i] > reg_needed_until) { | |
5466 if (max_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_reg] && max_reg != hint_reg)) { | |
5467 max_reg = i; | |
5468 } | |
5469 } | |
5470 } | |
5471 | |
5472 if (max_reg != any_reg && _block_pos[max_reg] <= interval_to) { | |
5473 *need_split = true; | |
5474 } | |
5475 | |
5476 return max_reg; | |
5477 } | |
5478 | |
5479 int LinearScanWalker::find_locked_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) { | |
5480 assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm"); | |
5481 | |
5482 int max_reg = any_reg; | |
5483 | |
5484 for (int i = _first_reg; i < _last_reg; i+=2) { | |
5485 if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) { | |
5486 if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) { | |
5487 max_reg = i; | |
5488 } | |
5489 } | |
5490 } | |
5491 | |
5492 if (_block_pos[max_reg] <= interval_to || _block_pos[max_reg + 1] <= interval_to) { | |
5493 *need_split = true; | |
5494 } | |
5495 | |
5496 return max_reg; | |
5497 } | |
5498 | |
5499 void LinearScanWalker::split_and_spill_intersecting_intervals(int reg, int regHi) { | |
5500 assert(reg != any_reg, "no register assigned"); | |
5501 | |
5502 for (int i = 0; i < _spill_intervals[reg]->length(); i++) { | |
5503 Interval* it = _spill_intervals[reg]->at(i); | |
5504 remove_from_list(it); | |
5505 split_and_spill_interval(it); | |
5506 } | |
5507 | |
5508 if (regHi != any_reg) { | |
5509 IntervalList* processed = _spill_intervals[reg]; | |
5510 for (int i = 0; i < _spill_intervals[regHi]->length(); i++) { | |
5511 Interval* it = _spill_intervals[regHi]->at(i); | |
5512 if (processed->index_of(it) == -1) { | |
5513 remove_from_list(it); | |
5514 split_and_spill_interval(it); | |
5515 } | |
5516 } | |
5517 } | |
5518 } | |
5519 | |
5520 | |
5521 // Split an Interval and spill it to memory so that cur can be placed in a register | |
5522 void LinearScanWalker::alloc_locked_reg(Interval* cur) { | |
5523 TRACE_LINEAR_SCAN(2, tty->print("need to split and spill to get register for "); cur->print()); | |
5524 | |
5525 // collect current usage of registers | |
5526 init_use_lists(false); | |
5527 spill_exclude_active_fixed(); | |
5528 // spill_block_unhandled_fixed(cur); | |
5529 assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0"); | |
5530 spill_block_inactive_fixed(cur); | |
5531 spill_collect_active_any(); | |
5532 spill_collect_inactive_any(cur); | |
5533 | |
5534 #ifndef PRODUCT | |
5535 if (TraceLinearScanLevel >= 4) { | |
5536 tty->print_cr(" state of registers:"); | |
5537 for (int i = _first_reg; i <= _last_reg; i++) { | |
5538 tty->print(" reg %d: use_pos: %d, block_pos: %d, intervals: ", i, _use_pos[i], _block_pos[i]); | |
5539 for (int j = 0; j < _spill_intervals[i]->length(); j++) { | |
5540 tty->print("%d ", _spill_intervals[i]->at(j)->reg_num()); | |
5541 } | |
5542 tty->cr(); | |
5543 } | |
5544 } | |
5545 #endif | |
5546 | |
5547 // the register must be free at least until this position | |
5548 int reg_needed_until = MIN2(cur->first_usage(mustHaveRegister), cur->from() + 1); | |
5549 int interval_to = cur->to(); | |
5550 assert (reg_needed_until > 0 && reg_needed_until < max_jint, "interval has no use"); | |
5551 | |
5552 int split_pos = 0; | |
5553 int use_pos = 0; | |
5554 bool need_split = false; | |
5555 int reg, regHi; | |
5556 | |
5557 if (_adjacent_regs) { | |
5558 reg = find_locked_double_reg(reg_needed_until, interval_to, any_reg, &need_split); | |
5559 regHi = reg + 1; | |
5560 | |
5561 if (reg != any_reg) { | |
5562 use_pos = MIN2(_use_pos[reg], _use_pos[regHi]); | |
5563 split_pos = MIN2(_block_pos[reg], _block_pos[regHi]); | |
5564 } | |
5565 } else { | |
5566 reg = find_locked_reg(reg_needed_until, interval_to, any_reg, cur->assigned_reg(), &need_split); | |
5567 regHi = any_reg; | |
5568 | |
5569 if (reg != any_reg) { | |
5570 use_pos = _use_pos[reg]; | |
5571 split_pos = _block_pos[reg]; | |
5572 | |
5573 if (_num_phys_regs == 2) { | |
5574 if (cur->assigned_reg() != any_reg) { | |
5575 regHi = reg; | |
5576 reg = cur->assigned_reg(); | |
5577 } else { | |
5578 regHi = find_locked_reg(reg_needed_until, interval_to, any_reg, reg, &need_split); | |
5579 if (regHi != any_reg) { | |
5580 use_pos = MIN2(use_pos, _use_pos[regHi]); | |
5581 split_pos = MIN2(split_pos, _block_pos[regHi]); | |
5582 } | |
5583 } | |
5584 | |
5585 if (regHi != any_reg && reg > regHi) { | |
5586 // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax | |
5587 int temp = reg; | |
5588 reg = regHi; | |
5589 regHi = temp; | |
5590 } | |
5591 } | |
5592 } | |
5593 } | |
5594 | |
5595 if (reg == any_reg || (_num_phys_regs == 2 && regHi == any_reg) || use_pos <= cur->first_usage(mustHaveRegister)) { | |
5596 // the first use of cur is later than the spilling position -> spill cur | |
5597 TRACE_LINEAR_SCAN(4, tty->print_cr("able to spill current interval. first_usage(register): %d, use_pos: %d", cur->first_usage(mustHaveRegister), use_pos)); | |
5598 | |
5599 if (cur->first_usage(mustHaveRegister) <= cur->from() + 1) { | |
5600 assert(false, "cannot spill interval that is used in first instruction (possible reason: no register found)"); | |
5601 // assign a reasonable register and do a bailout in product mode to avoid errors | |
5602 allocator()->assign_spill_slot(cur); | |
5603 BAILOUT("LinearScan: no register found"); | |
5604 } | |
5605 | |
5606 split_and_spill_interval(cur); | |
5607 } else { | |
5608 TRACE_LINEAR_SCAN(4, tty->print_cr("decided to use register %d, %d", reg, regHi)); | |
5609 assert(reg != any_reg && (_num_phys_regs == 1 || regHi != any_reg), "no register found"); | |
5610 assert(split_pos > 0, "invalid split_pos"); | |
5611 assert(need_split == false || split_pos > cur->from(), "splitting interval at from"); | |
5612 | |
5613 cur->assign_reg(reg, regHi); | |
5614 if (need_split) { | |
5615 // register not available for full interval, so split it | |
5616 split_when_partial_register_available(cur, split_pos); | |
5617 } | |
5618 | |
5619 // perform splitting and spilling for all affected intervalls | |
5620 split_and_spill_intersecting_intervals(reg, regHi); | |
5621 } | |
5622 } | |
5623 | |
5624 bool LinearScanWalker::no_allocation_possible(Interval* cur) { | |
304 | 5625 #ifdef X86 |
0 | 5626 // fast calculation of intervals that can never get a register because the |
5627 // the next instruction is a call that blocks all registers | |
5628 // Note: this does not work if callee-saved registers are available (e.g. on Sparc) | |
5629 | |
5630 // check if this interval is the result of a split operation | |
5631 // (an interval got a register until this position) | |
5632 int pos = cur->from(); | |
5633 if ((pos & 1) == 1) { | |
5634 // the current instruction is a call that blocks all registers | |
5635 if (pos < allocator()->max_lir_op_id() && allocator()->has_call(pos + 1)) { | |
5636 TRACE_LINEAR_SCAN(4, tty->print_cr(" free register cannot be available because all registers blocked by following call")); | |
5637 | |
5638 // safety check that there is really no register available | |
5639 assert(alloc_free_reg(cur) == false, "found a register for this interval"); | |
5640 return true; | |
5641 } | |
5642 | |
5643 } | |
5644 #endif | |
5645 return false; | |
5646 } | |
5647 | |
5648 void LinearScanWalker::init_vars_for_alloc(Interval* cur) { | |
5649 BasicType type = cur->type(); | |
5650 _num_phys_regs = LinearScan::num_physical_regs(type); | |
5651 _adjacent_regs = LinearScan::requires_adjacent_regs(type); | |
5652 | |
5653 if (pd_init_regs_for_alloc(cur)) { | |
5654 // the appropriate register range was selected. | |
5655 } else if (type == T_FLOAT || type == T_DOUBLE) { | |
5656 _first_reg = pd_first_fpu_reg; | |
5657 _last_reg = pd_last_fpu_reg; | |
5658 } else { | |
5659 _first_reg = pd_first_cpu_reg; | |
2002 | 5660 _last_reg = FrameMap::last_cpu_reg(); |
0 | 5661 } |
5662 | |
5663 assert(0 <= _first_reg && _first_reg < LinearScan::nof_regs, "out of range"); | |
5664 assert(0 <= _last_reg && _last_reg < LinearScan::nof_regs, "out of range"); | |
5665 } | |
5666 | |
5667 | |
5668 bool LinearScanWalker::is_move(LIR_Op* op, Interval* from, Interval* to) { | |
5669 if (op->code() != lir_move) { | |
5670 return false; | |
5671 } | |
5672 assert(op->as_Op1() != NULL, "move must be LIR_Op1"); | |
5673 | |
5674 LIR_Opr in = ((LIR_Op1*)op)->in_opr(); | |
5675 LIR_Opr res = ((LIR_Op1*)op)->result_opr(); | |
5676 return in->is_virtual() && res->is_virtual() && in->vreg_number() == from->reg_num() && res->vreg_number() == to->reg_num(); | |
5677 } | |
5678 | |
5679 // optimization (especially for phi functions of nested loops): | |
5680 // assign same spill slot to non-intersecting intervals | |
5681 void LinearScanWalker::combine_spilled_intervals(Interval* cur) { | |
5682 if (cur->is_split_child()) { | |
5683 // optimization is only suitable for split parents | |
5684 return; | |
5685 } | |
5686 | |
5687 Interval* register_hint = cur->register_hint(false); | |
5688 if (register_hint == NULL) { | |
5689 // cur is not the target of a move, otherwise register_hint would be set | |
5690 return; | |
5691 } | |
5692 assert(register_hint->is_split_parent(), "register hint must be split parent"); | |
5693 | |
5694 if (cur->spill_state() != noOptimization || register_hint->spill_state() != noOptimization) { | |
5695 // combining the stack slots for intervals where spill move optimization is applied | |
5696 // is not benefitial and would cause problems | |
5697 return; | |
5698 } | |
5699 | |
5700 int begin_pos = cur->from(); | |
5701 int end_pos = cur->to(); | |
5702 if (end_pos > allocator()->max_lir_op_id() || (begin_pos & 1) != 0 || (end_pos & 1) != 0) { | |
5703 // safety check that lir_op_with_id is allowed | |
5704 return; | |
5705 } | |
5706 | |
5707 if (!is_move(allocator()->lir_op_with_id(begin_pos), register_hint, cur) || !is_move(allocator()->lir_op_with_id(end_pos), cur, register_hint)) { | |
5708 // cur and register_hint are not connected with two moves | |
5709 return; | |
5710 } | |
5711 | |
5712 Interval* begin_hint = register_hint->split_child_at_op_id(begin_pos, LIR_OpVisitState::inputMode); | |
5713 Interval* end_hint = register_hint->split_child_at_op_id(end_pos, LIR_OpVisitState::outputMode); | |
5714 if (begin_hint == end_hint || begin_hint->to() != begin_pos || end_hint->from() != end_pos) { | |
5715 // register_hint must be split, otherwise the re-writing of use positions does not work | |
5716 return; | |
5717 } | |
5718 | |
5719 assert(begin_hint->assigned_reg() != any_reg, "must have register assigned"); | |
5720 assert(end_hint->assigned_reg() == any_reg, "must not have register assigned"); | |
5721 assert(cur->first_usage(mustHaveRegister) == begin_pos, "must have use position at begin of interval because of move"); | |
5722 assert(end_hint->first_usage(mustHaveRegister) == end_pos, "must have use position at begin of interval because of move"); | |
5723 | |
5724 if (begin_hint->assigned_reg() < LinearScan::nof_regs) { | |
5725 // register_hint is not spilled at begin_pos, so it would not be benefitial to immediately spill cur | |
5726 return; | |
5727 } | |
5728 assert(register_hint->canonical_spill_slot() != -1, "must be set when part of interval was spilled"); | |
5729 | |
5730 // modify intervals such that cur gets the same stack slot as register_hint | |
5731 // delete use positions to prevent the intervals to get a register at beginning | |
5732 cur->set_canonical_spill_slot(register_hint->canonical_spill_slot()); | |
5733 cur->remove_first_use_pos(); | |
5734 end_hint->remove_first_use_pos(); | |
5735 } | |
5736 | |
5737 | |
5738 // allocate a physical register or memory location to an interval | |
5739 bool LinearScanWalker::activate_current() { | |
5740 Interval* cur = current(); | |
5741 bool result = true; | |
5742 | |
5743 TRACE_LINEAR_SCAN(2, tty->print ("+++++ activating interval "); cur->print()); | |
5744 TRACE_LINEAR_SCAN(4, tty->print_cr(" split_parent: %d, insert_move_when_activated: %d", cur->split_parent()->reg_num(), cur->insert_move_when_activated())); | |
5745 | |
5746 if (cur->assigned_reg() >= LinearScan::nof_regs) { | |
5747 // activating an interval that has a stack slot assigned -> split it at first use position | |
5748 // used for method parameters | |
5749 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has spill slot assigned (method parameter) -> split it before first use")); | |
5750 | |
5751 split_stack_interval(cur); | |
5752 result = false; | |
5753 | |
5754 } else if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::must_start_in_memory)) { | |
5755 // activating an interval that must start in a stack slot, but may get a register later | |
5756 // used for lir_roundfp: rounding is done by store to stack and reload later | |
5757 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval must start in stack slot -> split it before first use")); | |
5758 assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned"); | |
5759 | |
5760 allocator()->assign_spill_slot(cur); | |
5761 split_stack_interval(cur); | |
5762 result = false; | |
5763 | |
5764 } else if (cur->assigned_reg() == any_reg) { | |
5765 // interval has not assigned register -> normal allocation | |
5766 // (this is the normal case for most intervals) | |
5767 TRACE_LINEAR_SCAN(4, tty->print_cr(" normal allocation of register")); | |
5768 | |
5769 // assign same spill slot to non-intersecting intervals | |
5770 combine_spilled_intervals(cur); | |
5771 | |
5772 init_vars_for_alloc(cur); | |
5773 if (no_allocation_possible(cur) || !alloc_free_reg(cur)) { | |
5774 // no empty register available. | |
5775 // split and spill another interval so that this interval gets a register | |
5776 alloc_locked_reg(cur); | |
5777 } | |
5778 | |
5779 // spilled intervals need not be move to active-list | |
5780 if (cur->assigned_reg() >= LinearScan::nof_regs) { | |
5781 result = false; | |
5782 } | |
5783 } | |
5784 | |
5785 // load spilled values that become active from stack slot to register | |
5786 if (cur->insert_move_when_activated()) { | |
5787 assert(cur->is_split_child(), "must be"); | |
5788 assert(cur->current_split_child() != NULL, "must be"); | |
5789 assert(cur->current_split_child()->reg_num() != cur->reg_num(), "cannot insert move between same interval"); | |
5790 TRACE_LINEAR_SCAN(4, tty->print_cr("Inserting move from interval %d to %d because insert_move_when_activated is set", cur->current_split_child()->reg_num(), cur->reg_num())); | |
5791 | |
5792 insert_move(cur->from(), cur->current_split_child(), cur); | |
5793 } | |
5794 cur->make_current_split_child(); | |
5795 | |
5796 return result; // true = interval is moved to active list | |
5797 } | |
5798 | |
5799 | |
5800 // Implementation of EdgeMoveOptimizer | |
5801 | |
5802 EdgeMoveOptimizer::EdgeMoveOptimizer() : | |
5803 _edge_instructions(4), | |
5804 _edge_instructions_idx(4) | |
5805 { | |
5806 } | |
5807 | |
5808 void EdgeMoveOptimizer::optimize(BlockList* code) { | |
5809 EdgeMoveOptimizer optimizer = EdgeMoveOptimizer(); | |
5810 | |
5811 // ignore the first block in the list (index 0 is not processed) | |
5812 for (int i = code->length() - 1; i >= 1; i--) { | |
5813 BlockBegin* block = code->at(i); | |
5814 | |
5815 if (block->number_of_preds() > 1 && !block->is_set(BlockBegin::exception_entry_flag)) { | |
5816 optimizer.optimize_moves_at_block_end(block); | |
5817 } | |
5818 if (block->number_of_sux() == 2) { | |
5819 optimizer.optimize_moves_at_block_begin(block); | |
5820 } | |
5821 } | |
5822 } | |
5823 | |
5824 | |
5825 // clear all internal data structures | |
5826 void EdgeMoveOptimizer::init_instructions() { | |
5827 _edge_instructions.clear(); | |
5828 _edge_instructions_idx.clear(); | |
5829 } | |
5830 | |
5831 // append a lir-instruction-list and the index of the current operation in to the list | |
5832 void EdgeMoveOptimizer::append_instructions(LIR_OpList* instructions, int instructions_idx) { | |
5833 _edge_instructions.append(instructions); | |
5834 _edge_instructions_idx.append(instructions_idx); | |
5835 } | |
5836 | |
5837 // return the current operation of the given edge (predecessor or successor) | |
5838 LIR_Op* EdgeMoveOptimizer::instruction_at(int edge) { | |
5839 LIR_OpList* instructions = _edge_instructions.at(edge); | |
5840 int idx = _edge_instructions_idx.at(edge); | |
5841 | |
5842 if (idx < instructions->length()) { | |
5843 return instructions->at(idx); | |
5844 } else { | |
5845 return NULL; | |
5846 } | |
5847 } | |
5848 | |
5849 // removes the current operation of the given edge (predecessor or successor) | |
5850 void EdgeMoveOptimizer::remove_cur_instruction(int edge, bool decrement_index) { | |
5851 LIR_OpList* instructions = _edge_instructions.at(edge); | |
5852 int idx = _edge_instructions_idx.at(edge); | |
5853 instructions->remove_at(idx); | |
5854 | |
5855 if (decrement_index) { | |
5856 _edge_instructions_idx.at_put(edge, idx - 1); | |
5857 } | |
5858 } | |
5859 | |
5860 | |
5861 bool EdgeMoveOptimizer::operations_different(LIR_Op* op1, LIR_Op* op2) { | |
5862 if (op1 == NULL || op2 == NULL) { | |
5863 // at least one block is already empty -> no optimization possible | |
5864 return true; | |
5865 } | |
5866 | |
5867 if (op1->code() == lir_move && op2->code() == lir_move) { | |
5868 assert(op1->as_Op1() != NULL, "move must be LIR_Op1"); | |
5869 assert(op2->as_Op1() != NULL, "move must be LIR_Op1"); | |
5870 LIR_Op1* move1 = (LIR_Op1*)op1; | |
5871 LIR_Op1* move2 = (LIR_Op1*)op2; | |
5872 if (move1->info() == move2->info() && move1->in_opr() == move2->in_opr() && move1->result_opr() == move2->result_opr()) { | |
5873 // these moves are exactly equal and can be optimized | |
5874 return false; | |
5875 } | |
5876 | |
5877 } else if (op1->code() == lir_fxch && op2->code() == lir_fxch) { | |
5878 assert(op1->as_Op1() != NULL, "fxch must be LIR_Op1"); | |
5879 assert(op2->as_Op1() != NULL, "fxch must be LIR_Op1"); | |
5880 LIR_Op1* fxch1 = (LIR_Op1*)op1; | |
5881 LIR_Op1* fxch2 = (LIR_Op1*)op2; | |
5882 if (fxch1->in_opr()->as_jint() == fxch2->in_opr()->as_jint()) { | |
5883 // equal FPU stack operations can be optimized | |
5884 return false; | |
5885 } | |
5886 | |
5887 } else if (op1->code() == lir_fpop_raw && op2->code() == lir_fpop_raw) { | |
5888 // equal FPU stack operations can be optimized | |
5889 return false; | |
5890 } | |
5891 | |
5892 // no optimization possible | |
5893 return true; | |
5894 } | |
5895 | |
5896 void EdgeMoveOptimizer::optimize_moves_at_block_end(BlockBegin* block) { | |
5897 TRACE_LINEAR_SCAN(4, tty->print_cr("optimizing moves at end of block B%d", block->block_id())); | |
5898 | |
5899 if (block->is_predecessor(block)) { | |
5900 // currently we can't handle this correctly. | |
5901 return; | |
5902 } | |
5903 | |
5904 init_instructions(); | |
5905 int num_preds = block->number_of_preds(); | |
5906 assert(num_preds > 1, "do not call otherwise"); | |
5907 assert(!block->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed"); | |
5908 | |
5909 // setup a list with the lir-instructions of all predecessors | |
5910 int i; | |
5911 for (i = 0; i < num_preds; i++) { | |
5912 BlockBegin* pred = block->pred_at(i); | |
5913 LIR_OpList* pred_instructions = pred->lir()->instructions_list(); | |
5914 | |
5915 if (pred->number_of_sux() != 1) { | |
5916 // this can happen with switch-statements where multiple edges are between | |
5917 // the same blocks. | |
5918 return; | |
5919 } | |
5920 | |
5921 assert(pred->number_of_sux() == 1, "can handle only one successor"); | |
5922 assert(pred->sux_at(0) == block, "invalid control flow"); | |
5923 assert(pred_instructions->last()->code() == lir_branch, "block with successor must end with branch"); | |
5924 assert(pred_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch"); | |
5925 assert(pred_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch"); | |
5926 | |
5927 if (pred_instructions->last()->info() != NULL) { | |
5928 // can not optimize instructions when debug info is needed | |
5929 return; | |
5930 } | |
5931 | |
5932 // ignore the unconditional branch at the end of the block | |
5933 append_instructions(pred_instructions, pred_instructions->length() - 2); | |
5934 } | |
5935 | |
5936 | |
5937 // process lir-instructions while all predecessors end with the same instruction | |
5938 while (true) { | |
5939 LIR_Op* op = instruction_at(0); | |
5940 for (i = 1; i < num_preds; i++) { | |
5941 if (operations_different(op, instruction_at(i))) { | |
5942 // these instructions are different and cannot be optimized -> | |
5943 // no further optimization possible | |
5944 return; | |
5945 } | |
5946 } | |
5947 | |
5948 TRACE_LINEAR_SCAN(4, tty->print("found instruction that is equal in all %d predecessors: ", num_preds); op->print()); | |
5949 | |
5950 // insert the instruction at the beginning of the current block | |
5951 block->lir()->insert_before(1, op); | |
5952 | |
5953 // delete the instruction at the end of all predecessors | |
5954 for (i = 0; i < num_preds; i++) { | |
5955 remove_cur_instruction(i, true); | |
5956 } | |
5957 } | |
5958 } | |
5959 | |
5960 | |
5961 void EdgeMoveOptimizer::optimize_moves_at_block_begin(BlockBegin* block) { | |
5962 TRACE_LINEAR_SCAN(4, tty->print_cr("optimization moves at begin of block B%d", block->block_id())); | |
5963 | |
5964 init_instructions(); | |
5965 int num_sux = block->number_of_sux(); | |
5966 | |
5967 LIR_OpList* cur_instructions = block->lir()->instructions_list(); | |
5968 | |
5969 assert(num_sux == 2, "method should not be called otherwise"); | |
5970 assert(cur_instructions->last()->code() == lir_branch, "block with successor must end with branch"); | |
5971 assert(cur_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch"); | |
5972 assert(cur_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch"); | |
5973 | |
5974 if (cur_instructions->last()->info() != NULL) { | |
5975 // can no optimize instructions when debug info is needed | |
5976 return; | |
5977 } | |
5978 | |
5979 LIR_Op* branch = cur_instructions->at(cur_instructions->length() - 2); | |
5980 if (branch->info() != NULL || (branch->code() != lir_branch && branch->code() != lir_cond_float_branch)) { | |
5981 // not a valid case for optimization | |
5982 // currently, only blocks that end with two branches (conditional branch followed | |
5983 // by unconditional branch) are optimized | |
5984 return; | |
5985 } | |
5986 | |
5987 // now it is guaranteed that the block ends with two branch instructions. | |
5988 // the instructions are inserted at the end of the block before these two branches | |
5989 int insert_idx = cur_instructions->length() - 2; | |
5990 | |
5991 int i; | |
5992 #ifdef ASSERT | |
5993 for (i = insert_idx - 1; i >= 0; i--) { | |
5994 LIR_Op* op = cur_instructions->at(i); | |
5995 if ((op->code() == lir_branch || op->code() == lir_cond_float_branch) && ((LIR_OpBranch*)op)->block() != NULL) { | |
5996 assert(false, "block with two successors can have only two branch instructions"); | |
5997 } | |
5998 } | |
5999 #endif | |
6000 | |
6001 // setup a list with the lir-instructions of all successors | |
6002 for (i = 0; i < num_sux; i++) { | |
6003 BlockBegin* sux = block->sux_at(i); | |
6004 LIR_OpList* sux_instructions = sux->lir()->instructions_list(); | |
6005 | |
6006 assert(sux_instructions->at(0)->code() == lir_label, "block must start with label"); | |
6007 | |
6008 if (sux->number_of_preds() != 1) { | |
6009 // this can happen with switch-statements where multiple edges are between | |
6010 // the same blocks. | |
6011 return; | |
6012 } | |
6013 assert(sux->pred_at(0) == block, "invalid control flow"); | |
6014 assert(!sux->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed"); | |
6015 | |
6016 // ignore the label at the beginning of the block | |
6017 append_instructions(sux_instructions, 1); | |
6018 } | |
6019 | |
6020 // process lir-instructions while all successors begin with the same instruction | |
6021 while (true) { | |
6022 LIR_Op* op = instruction_at(0); | |
6023 for (i = 1; i < num_sux; i++) { | |
6024 if (operations_different(op, instruction_at(i))) { | |
6025 // these instructions are different and cannot be optimized -> | |
6026 // no further optimization possible | |
6027 return; | |
6028 } | |
6029 } | |
6030 | |
6031 TRACE_LINEAR_SCAN(4, tty->print("----- found instruction that is equal in all %d successors: ", num_sux); op->print()); | |
6032 | |
6033 // insert instruction at end of current block | |
6034 block->lir()->insert_before(insert_idx, op); | |
6035 insert_idx++; | |
6036 | |
6037 // delete the instructions at the beginning of all successors | |
6038 for (i = 0; i < num_sux; i++) { | |
6039 remove_cur_instruction(i, false); | |
6040 } | |
6041 } | |
6042 } | |
6043 | |
6044 | |
6045 // Implementation of ControlFlowOptimizer | |
6046 | |
6047 ControlFlowOptimizer::ControlFlowOptimizer() : | |
6048 _original_preds(4) | |
6049 { | |
6050 } | |
6051 | |
6052 void ControlFlowOptimizer::optimize(BlockList* code) { | |
6053 ControlFlowOptimizer optimizer = ControlFlowOptimizer(); | |
6054 | |
6055 // push the OSR entry block to the end so that we're not jumping over it. | |
6056 BlockBegin* osr_entry = code->at(0)->end()->as_Base()->osr_entry(); | |
6057 if (osr_entry) { | |
6058 int index = osr_entry->linear_scan_number(); | |
6059 assert(code->at(index) == osr_entry, "wrong index"); | |
6060 code->remove_at(index); | |
6061 code->append(osr_entry); | |
6062 } | |
6063 | |
6064 optimizer.reorder_short_loops(code); | |
6065 optimizer.delete_empty_blocks(code); | |
6066 optimizer.delete_unnecessary_jumps(code); | |
6067 optimizer.delete_jumps_to_return(code); | |
6068 } | |
6069 | |
6070 void ControlFlowOptimizer::reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx) { | |
6071 int i = header_idx + 1; | |
6072 int max_end = MIN2(header_idx + ShortLoopSize, code->length()); | |
6073 while (i < max_end && code->at(i)->loop_depth() >= header_block->loop_depth()) { | |
6074 i++; | |
6075 } | |
6076 | |
6077 if (i == code->length() || code->at(i)->loop_depth() < header_block->loop_depth()) { | |
6078 int end_idx = i - 1; | |
6079 BlockBegin* end_block = code->at(end_idx); | |
6080 | |
6081 if (end_block->number_of_sux() == 1 && end_block->sux_at(0) == header_block) { | |
6082 // short loop from header_idx to end_idx found -> reorder blocks such that | |
6083 // the header_block is the last block instead of the first block of the loop | |
6084 TRACE_LINEAR_SCAN(1, tty->print_cr("Reordering short loop: length %d, header B%d, end B%d", | |
6085 end_idx - header_idx + 1, | |
6086 header_block->block_id(), end_block->block_id())); | |
6087 | |
6088 for (int j = header_idx; j < end_idx; j++) { | |
6089 code->at_put(j, code->at(j + 1)); | |
6090 } | |
6091 code->at_put(end_idx, header_block); | |
6092 | |
6093 // correct the flags so that any loop alignment occurs in the right place. | |
6094 assert(code->at(end_idx)->is_set(BlockBegin::backward_branch_target_flag), "must be backward branch target"); | |
6095 code->at(end_idx)->clear(BlockBegin::backward_branch_target_flag); | |
6096 code->at(header_idx)->set(BlockBegin::backward_branch_target_flag); | |
6097 } | |
6098 } | |
6099 } | |
6100 | |
6101 void ControlFlowOptimizer::reorder_short_loops(BlockList* code) { | |
6102 for (int i = code->length() - 1; i >= 0; i--) { | |
6103 BlockBegin* block = code->at(i); | |
6104 | |
6105 if (block->is_set(BlockBegin::linear_scan_loop_header_flag)) { | |
6106 reorder_short_loop(code, block, i); | |
6107 } | |
6108 } | |
6109 | |
6110 DEBUG_ONLY(verify(code)); | |
6111 } | |
6112 | |
6113 // only blocks with exactly one successor can be deleted. Such blocks | |
6114 // must always end with an unconditional branch to this successor | |
6115 bool ControlFlowOptimizer::can_delete_block(BlockBegin* block) { | |
6116 if (block->number_of_sux() != 1 || block->number_of_exception_handlers() != 0 || block->is_entry_block()) { | |
6117 return false; | |
6118 } | |
6119 | |
6120 LIR_OpList* instructions = block->lir()->instructions_list(); | |
6121 | |
6122 assert(instructions->length() >= 2, "block must have label and branch"); | |
6123 assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label"); | |
6124 assert(instructions->last()->as_OpBranch() != NULL, "last instrcution must always be a branch"); | |
6125 assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "branch must be unconditional"); | |
6126 assert(instructions->last()->as_OpBranch()->block() == block->sux_at(0), "branch target must be the successor"); | |
6127 | |
6128 // block must have exactly one successor | |
6129 | |
6130 if (instructions->length() == 2 && instructions->last()->info() == NULL) { | |
6131 return true; | |
6132 } | |
6133 return false; | |
6134 } | |
6135 | |
6136 // substitute branch targets in all branch-instructions of this blocks | |
6137 void ControlFlowOptimizer::substitute_branch_target(BlockBegin* block, BlockBegin* target_from, BlockBegin* target_to) { | |
6138 TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting empty block: substituting from B%d to B%d inside B%d", target_from->block_id(), target_to->block_id(), block->block_id())); | |
6139 | |
6140 LIR_OpList* instructions = block->lir()->instructions_list(); | |
6141 | |
6142 assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label"); | |
6143 for (int i = instructions->length() - 1; i >= 1; i--) { | |
6144 LIR_Op* op = instructions->at(i); | |
6145 | |
6146 if (op->code() == lir_branch || op->code() == lir_cond_float_branch) { | |
6147 assert(op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch"); | |
6148 LIR_OpBranch* branch = (LIR_OpBranch*)op; | |
6149 | |
6150 if (branch->block() == target_from) { | |
6151 branch->change_block(target_to); | |
6152 } | |
6153 if (branch->ublock() == target_from) { | |
6154 branch->change_ublock(target_to); | |
6155 } | |
6156 } | |
6157 } | |
6158 } | |
6159 | |
6160 void ControlFlowOptimizer::delete_empty_blocks(BlockList* code) { | |
6161 int old_pos = 0; | |
6162 int new_pos = 0; | |
6163 int num_blocks = code->length(); | |
6164 | |
6165 while (old_pos < num_blocks) { | |
6166 BlockBegin* block = code->at(old_pos); | |
6167 | |
6168 if (can_delete_block(block)) { | |
6169 BlockBegin* new_target = block->sux_at(0); | |
6170 | |
6171 // propagate backward branch target flag for correct code alignment | |
6172 if (block->is_set(BlockBegin::backward_branch_target_flag)) { | |
6173 new_target->set(BlockBegin::backward_branch_target_flag); | |
6174 } | |
6175 | |
6176 // collect a list with all predecessors that contains each predecessor only once | |
6177 // the predecessors of cur are changed during the substitution, so a copy of the | |
6178 // predecessor list is necessary | |
6179 int j; | |
6180 _original_preds.clear(); | |
6181 for (j = block->number_of_preds() - 1; j >= 0; j--) { | |
6182 BlockBegin* pred = block->pred_at(j); | |
6183 if (_original_preds.index_of(pred) == -1) { | |
6184 _original_preds.append(pred); | |
6185 } | |
6186 } | |
6187 | |
6188 for (j = _original_preds.length() - 1; j >= 0; j--) { | |
6189 BlockBegin* pred = _original_preds.at(j); | |
6190 substitute_branch_target(pred, block, new_target); | |
6191 pred->substitute_sux(block, new_target); | |
6192 } | |
6193 } else { | |
6194 // adjust position of this block in the block list if blocks before | |
6195 // have been deleted | |
6196 if (new_pos != old_pos) { | |
6197 code->at_put(new_pos, code->at(old_pos)); | |
6198 } | |
6199 new_pos++; | |
6200 } | |
6201 old_pos++; | |
6202 } | |
6203 code->truncate(new_pos); | |
6204 | |
6205 DEBUG_ONLY(verify(code)); | |
6206 } | |
6207 | |
6208 void ControlFlowOptimizer::delete_unnecessary_jumps(BlockList* code) { | |
6209 // skip the last block because there a branch is always necessary | |
6210 for (int i = code->length() - 2; i >= 0; i--) { | |
6211 BlockBegin* block = code->at(i); | |
6212 LIR_OpList* instructions = block->lir()->instructions_list(); | |
6213 | |
6214 LIR_Op* last_op = instructions->last(); | |
6215 if (last_op->code() == lir_branch) { | |
6216 assert(last_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch"); | |
6217 LIR_OpBranch* last_branch = (LIR_OpBranch*)last_op; | |
6218 | |
6219 assert(last_branch->block() != NULL, "last branch must always have a block as target"); | |
6220 assert(last_branch->label() == last_branch->block()->label(), "must be equal"); | |
6221 | |
6222 if (last_branch->info() == NULL) { | |
6223 if (last_branch->block() == code->at(i + 1)) { | |
6224 | |
6225 TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting unconditional branch at end of block B%d", block->block_id())); | |
6226 | |
6227 // delete last branch instruction | |
6228 instructions->truncate(instructions->length() - 1); | |
6229 | |
6230 } else { | |
6231 LIR_Op* prev_op = instructions->at(instructions->length() - 2); | |
6232 if (prev_op->code() == lir_branch || prev_op->code() == lir_cond_float_branch) { | |
6233 assert(prev_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch"); | |
6234 LIR_OpBranch* prev_branch = (LIR_OpBranch*)prev_op; | |
6235 | |
8860 | 6236 if (prev_branch->stub() == NULL) { |
6237 | |
6238 LIR_Op2* prev_cmp = NULL; | |
6239 | |
6240 for(int j = instructions->length() - 3; j >= 0 && prev_cmp == NULL; j--) { | |
6241 prev_op = instructions->at(j); | |
6242 if (prev_op->code() == lir_cmp) { | |
6243 assert(prev_op->as_Op2() != NULL, "branch must be of type LIR_Op2"); | |
6244 prev_cmp = (LIR_Op2*)prev_op; | |
6245 assert(prev_branch->cond() == prev_cmp->condition(), "should be the same"); | |
6246 } | |
1681
126ea7725993
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|
6247 } |
8860 | 6248 assert(prev_cmp != NULL, "should have found comp instruction for branch"); |
6249 if (prev_branch->block() == code->at(i + 1) && prev_branch->info() == NULL) { | |
6250 | |
6251 TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id())); | |
6252 | |
6253 // eliminate a conditional branch to the immediate successor | |
6254 prev_branch->change_block(last_branch->block()); | |
6255 prev_branch->negate_cond(); | |
6256 prev_cmp->set_condition(prev_branch->cond()); | |
6257 instructions->truncate(instructions->length() - 1); | |
6258 } | |
0 | 6259 } |
6260 } | |
6261 } | |
6262 } | |
6263 } | |
6264 } | |
6265 | |
6266 DEBUG_ONLY(verify(code)); | |
6267 } | |
6268 | |
6269 void ControlFlowOptimizer::delete_jumps_to_return(BlockList* code) { | |
6270 #ifdef ASSERT | |
6271 BitMap return_converted(BlockBegin::number_of_blocks()); | |
6272 return_converted.clear(); | |
6273 #endif | |
6274 | |
6275 for (int i = code->length() - 1; i >= 0; i--) { | |
6276 BlockBegin* block = code->at(i); | |
6277 LIR_OpList* cur_instructions = block->lir()->instructions_list(); | |
6278 LIR_Op* cur_last_op = cur_instructions->last(); | |
6279 | |
6280 assert(cur_instructions->at(0)->code() == lir_label, "first instruction must always be a label"); | |
6281 if (cur_instructions->length() == 2 && cur_last_op->code() == lir_return) { | |
6282 // the block contains only a label and a return | |
6283 // if a predecessor ends with an unconditional jump to this block, then the jump | |
6284 // can be replaced with a return instruction | |
6285 // | |
6286 // Note: the original block with only a return statement cannot be deleted completely | |
6287 // because the predecessors might have other (conditional) jumps to this block | |
6288 // -> this may lead to unnecesary return instructions in the final code | |
6289 | |
6290 assert(cur_last_op->info() == NULL, "return instructions do not have debug information"); | |
6291 assert(block->number_of_sux() == 0 || | |
6292 (return_converted.at(block->block_id()) && block->number_of_sux() == 1), | |
6293 "blocks that end with return must not have successors"); | |
6294 | |
6295 assert(cur_last_op->as_Op1() != NULL, "return must be LIR_Op1"); | |
6296 LIR_Opr return_opr = ((LIR_Op1*)cur_last_op)->in_opr(); | |
6297 | |
6298 for (int j = block->number_of_preds() - 1; j >= 0; j--) { | |
6299 BlockBegin* pred = block->pred_at(j); | |
6300 LIR_OpList* pred_instructions = pred->lir()->instructions_list(); | |
6301 LIR_Op* pred_last_op = pred_instructions->last(); | |
6302 | |
6303 if (pred_last_op->code() == lir_branch) { | |
6304 assert(pred_last_op->as_OpBranch() != NULL, "branch must be LIR_OpBranch"); | |
6305 LIR_OpBranch* pred_last_branch = (LIR_OpBranch*)pred_last_op; | |
6306 | |
6307 if (pred_last_branch->block() == block && pred_last_branch->cond() == lir_cond_always && pred_last_branch->info() == NULL) { | |
6308 // replace the jump to a return with a direct return | |
6309 // Note: currently the edge between the blocks is not deleted | |
6310 pred_instructions->at_put(pred_instructions->length() - 1, new LIR_Op1(lir_return, return_opr)); | |
6311 #ifdef ASSERT | |
6312 return_converted.set_bit(pred->block_id()); | |
6313 #endif | |
6314 } | |
6315 } | |
6316 } | |
6317 } | |
6318 } | |
6319 } | |
6320 | |
6321 | |
6322 #ifdef ASSERT | |
6323 void ControlFlowOptimizer::verify(BlockList* code) { | |
6324 for (int i = 0; i < code->length(); i++) { | |
6325 BlockBegin* block = code->at(i); | |
6326 LIR_OpList* instructions = block->lir()->instructions_list(); | |
6327 | |
6328 int j; | |
6329 for (j = 0; j < instructions->length(); j++) { | |
6330 LIR_OpBranch* op_branch = instructions->at(j)->as_OpBranch(); | |
6331 | |
6332 if (op_branch != NULL) { | |
6333 assert(op_branch->block() == NULL || code->index_of(op_branch->block()) != -1, "branch target not valid"); | |
6334 assert(op_branch->ublock() == NULL || code->index_of(op_branch->ublock()) != -1, "branch target not valid"); | |
6335 } | |
6336 } | |
6337 | |
6338 for (j = 0; j < block->number_of_sux() - 1; j++) { | |
6339 BlockBegin* sux = block->sux_at(j); | |
6340 assert(code->index_of(sux) != -1, "successor not valid"); | |
6341 } | |
6342 | |
6343 for (j = 0; j < block->number_of_preds() - 1; j++) { | |
6344 BlockBegin* pred = block->pred_at(j); | |
6345 assert(code->index_of(pred) != -1, "successor not valid"); | |
6346 } | |
6347 } | |
6348 } | |
6349 #endif | |
6350 | |
6351 | |
6352 #ifndef PRODUCT | |
6353 | |
6354 // Implementation of LinearStatistic | |
6355 | |
6356 const char* LinearScanStatistic::counter_name(int counter_idx) { | |
6357 switch (counter_idx) { | |
6358 case counter_method: return "compiled methods"; | |
6359 case counter_fpu_method: return "methods using fpu"; | |
6360 case counter_loop_method: return "methods with loops"; | |
6361 case counter_exception_method:return "methods with xhandler"; | |
6362 | |
6363 case counter_loop: return "loops"; | |
6364 case counter_block: return "blocks"; | |
6365 case counter_loop_block: return "blocks inside loop"; | |
6366 case counter_exception_block: return "exception handler entries"; | |
6367 case counter_interval: return "intervals"; | |
6368 case counter_fixed_interval: return "fixed intervals"; | |
6369 case counter_range: return "ranges"; | |
6370 case counter_fixed_range: return "fixed ranges"; | |
6371 case counter_use_pos: return "use positions"; | |
6372 case counter_fixed_use_pos: return "fixed use positions"; | |
6373 case counter_spill_slots: return "spill slots"; | |
6374 | |
6375 // counter for classes of lir instructions | |
6376 case counter_instruction: return "total instructions"; | |
6377 case counter_label: return "labels"; | |
6378 case counter_entry: return "method entries"; | |
6379 case counter_return: return "method returns"; | |
6380 case counter_call: return "method calls"; | |
6381 case counter_move: return "moves"; | |
6382 case counter_cmp: return "compare"; | |
6383 case counter_cond_branch: return "conditional branches"; | |
6384 case counter_uncond_branch: return "unconditional branches"; | |
6385 case counter_stub_branch: return "branches to stub"; | |
6386 case counter_alu: return "artithmetic + logic"; | |
6387 case counter_alloc: return "allocations"; | |
6388 case counter_sync: return "synchronisation"; | |
6389 case counter_throw: return "throw"; | |
6390 case counter_unwind: return "unwind"; | |
6391 case counter_typecheck: return "type+null-checks"; | |
6392 case counter_fpu_stack: return "fpu-stack"; | |
6393 case counter_misc_inst: return "other instructions"; | |
6394 case counter_other_inst: return "misc. instructions"; | |
6395 | |
6396 // counter for different types of moves | |
6397 case counter_move_total: return "total moves"; | |
6398 case counter_move_reg_reg: return "register->register"; | |
6399 case counter_move_reg_stack: return "register->stack"; | |
6400 case counter_move_stack_reg: return "stack->register"; | |
6401 case counter_move_stack_stack:return "stack->stack"; | |
6402 case counter_move_reg_mem: return "register->memory"; | |
6403 case counter_move_mem_reg: return "memory->register"; | |
6404 case counter_move_const_any: return "constant->any"; | |
6405 | |
6406 case blank_line_1: return ""; | |
6407 case blank_line_2: return ""; | |
6408 | |
6409 default: ShouldNotReachHere(); return ""; | |
6410 } | |
6411 } | |
6412 | |
6413 LinearScanStatistic::Counter LinearScanStatistic::base_counter(int counter_idx) { | |
6414 if (counter_idx == counter_fpu_method || counter_idx == counter_loop_method || counter_idx == counter_exception_method) { | |
6415 return counter_method; | |
6416 } else if (counter_idx == counter_loop_block || counter_idx == counter_exception_block) { | |
6417 return counter_block; | |
6418 } else if (counter_idx >= counter_instruction && counter_idx <= counter_other_inst) { | |
6419 return counter_instruction; | |
6420 } else if (counter_idx >= counter_move_total && counter_idx <= counter_move_const_any) { | |
6421 return counter_move_total; | |
6422 } | |
6423 return invalid_counter; | |
6424 } | |
6425 | |
6426 LinearScanStatistic::LinearScanStatistic() { | |
6427 for (int i = 0; i < number_of_counters; i++) { | |
6428 _counters_sum[i] = 0; | |
6429 _counters_max[i] = -1; | |
6430 } | |
6431 | |
6432 } | |
6433 | |
6434 // add the method-local numbers to the total sum | |
6435 void LinearScanStatistic::sum_up(LinearScanStatistic &method_statistic) { | |
6436 for (int i = 0; i < number_of_counters; i++) { | |
6437 _counters_sum[i] += method_statistic._counters_sum[i]; | |
6438 _counters_max[i] = MAX2(_counters_max[i], method_statistic._counters_sum[i]); | |
6439 } | |
6440 } | |
6441 | |
6442 void LinearScanStatistic::print(const char* title) { | |
6443 if (CountLinearScan || TraceLinearScanLevel > 0) { | |
6444 tty->cr(); | |
6445 tty->print_cr("***** LinearScan statistic - %s *****", title); | |
6446 | |
6447 for (int i = 0; i < number_of_counters; i++) { | |
6448 if (_counters_sum[i] > 0 || _counters_max[i] >= 0) { | |
6449 tty->print("%25s: %8d", counter_name(i), _counters_sum[i]); | |
6450 | |
6451 if (base_counter(i) != invalid_counter) { | |
6452 tty->print(" (%5.1f%%) ", _counters_sum[i] * 100.0 / _counters_sum[base_counter(i)]); | |
6453 } else { | |
6454 tty->print(" "); | |
6455 } | |
6456 | |
6457 if (_counters_max[i] >= 0) { | |
6458 tty->print("%8d", _counters_max[i]); | |
6459 } | |
6460 } | |
6461 tty->cr(); | |
6462 } | |
6463 } | |
6464 } | |
6465 | |
6466 void LinearScanStatistic::collect(LinearScan* allocator) { | |
6467 inc_counter(counter_method); | |
6468 if (allocator->has_fpu_registers()) { | |
6469 inc_counter(counter_fpu_method); | |
6470 } | |
6471 if (allocator->num_loops() > 0) { | |
6472 inc_counter(counter_loop_method); | |
6473 } | |
6474 inc_counter(counter_loop, allocator->num_loops()); | |
6475 inc_counter(counter_spill_slots, allocator->max_spills()); | |
6476 | |
6477 int i; | |
6478 for (i = 0; i < allocator->interval_count(); i++) { | |
6479 Interval* cur = allocator->interval_at(i); | |
6480 | |
6481 if (cur != NULL) { | |
6482 inc_counter(counter_interval); | |
6483 inc_counter(counter_use_pos, cur->num_use_positions()); | |
6484 if (LinearScan::is_precolored_interval(cur)) { | |
6485 inc_counter(counter_fixed_interval); | |
6486 inc_counter(counter_fixed_use_pos, cur->num_use_positions()); | |
6487 } | |
6488 | |
6489 Range* range = cur->first(); | |
6490 while (range != Range::end()) { | |
6491 inc_counter(counter_range); | |
6492 if (LinearScan::is_precolored_interval(cur)) { | |
6493 inc_counter(counter_fixed_range); | |
6494 } | |
6495 range = range->next(); | |
6496 } | |
6497 } | |
6498 } | |
6499 | |
6500 bool has_xhandlers = false; | |
6501 // Note: only count blocks that are in code-emit order | |
6502 for (i = 0; i < allocator->ir()->code()->length(); i++) { | |
6503 BlockBegin* cur = allocator->ir()->code()->at(i); | |
6504 | |
6505 inc_counter(counter_block); | |
6506 if (cur->loop_depth() > 0) { | |
6507 inc_counter(counter_loop_block); | |
6508 } | |
6509 if (cur->is_set(BlockBegin::exception_entry_flag)) { | |
6510 inc_counter(counter_exception_block); | |
6511 has_xhandlers = true; | |
6512 } | |
6513 | |
6514 LIR_OpList* instructions = cur->lir()->instructions_list(); | |
6515 for (int j = 0; j < instructions->length(); j++) { | |
6516 LIR_Op* op = instructions->at(j); | |
6517 | |
6518 inc_counter(counter_instruction); | |
6519 | |
6520 switch (op->code()) { | |
6521 case lir_label: inc_counter(counter_label); break; | |
6522 case lir_std_entry: | |
6523 case lir_osr_entry: inc_counter(counter_entry); break; | |
6524 case lir_return: inc_counter(counter_return); break; | |
6525 | |
6526 case lir_rtcall: | |
6527 case lir_static_call: | |
6528 case lir_optvirtual_call: | |
6529 case lir_virtual_call: inc_counter(counter_call); break; | |
6530 | |
6531 case lir_move: { | |
6532 inc_counter(counter_move); | |
6533 inc_counter(counter_move_total); | |
6534 | |
6535 LIR_Opr in = op->as_Op1()->in_opr(); | |
6536 LIR_Opr res = op->as_Op1()->result_opr(); | |
6537 if (in->is_register()) { | |
6538 if (res->is_register()) { | |
6539 inc_counter(counter_move_reg_reg); | |
6540 } else if (res->is_stack()) { | |
6541 inc_counter(counter_move_reg_stack); | |
6542 } else if (res->is_address()) { | |
6543 inc_counter(counter_move_reg_mem); | |
6544 } else { | |
6545 ShouldNotReachHere(); | |
6546 } | |
6547 } else if (in->is_stack()) { | |
6548 if (res->is_register()) { | |
6549 inc_counter(counter_move_stack_reg); | |
6550 } else { | |
6551 inc_counter(counter_move_stack_stack); | |
6552 } | |
6553 } else if (in->is_address()) { | |
6554 assert(res->is_register(), "must be"); | |
6555 inc_counter(counter_move_mem_reg); | |
6556 } else if (in->is_constant()) { | |
6557 inc_counter(counter_move_const_any); | |
6558 } else { | |
6559 ShouldNotReachHere(); | |
6560 } | |
6561 break; | |
6562 } | |
6563 | |
6564 case lir_cmp: inc_counter(counter_cmp); break; | |
6565 | |
6566 case lir_branch: | |
6567 case lir_cond_float_branch: { | |
6568 LIR_OpBranch* branch = op->as_OpBranch(); | |
6569 if (branch->block() == NULL) { | |
6570 inc_counter(counter_stub_branch); | |
6571 } else if (branch->cond() == lir_cond_always) { | |
6572 inc_counter(counter_uncond_branch); | |
6573 } else { | |
6574 inc_counter(counter_cond_branch); | |
6575 } | |
6576 break; | |
6577 } | |
6578 | |
6579 case lir_neg: | |
6580 case lir_add: | |
6581 case lir_sub: | |
6582 case lir_mul: | |
6583 case lir_mul_strictfp: | |
6584 case lir_div: | |
6585 case lir_div_strictfp: | |
6586 case lir_rem: | |
6587 case lir_sqrt: | |
6588 case lir_sin: | |
6589 case lir_cos: | |
6590 case lir_abs: | |
6591 case lir_log10: | |
6592 case lir_log: | |
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5906
diff
changeset
|
6593 case lir_pow: |
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5906
diff
changeset
|
6594 case lir_exp: |
0 | 6595 case lir_logic_and: |
6596 case lir_logic_or: | |
6597 case lir_logic_xor: | |
6598 case lir_shl: | |
6599 case lir_shr: | |
6600 case lir_ushr: inc_counter(counter_alu); break; | |
6601 | |
6602 case lir_alloc_object: | |
6603 case lir_alloc_array: inc_counter(counter_alloc); break; | |
6604 | |
6605 case lir_monaddr: | |
6606 case lir_lock: | |
6607 case lir_unlock: inc_counter(counter_sync); break; | |
6608 | |
6609 case lir_throw: inc_counter(counter_throw); break; | |
6610 | |
6611 case lir_unwind: inc_counter(counter_unwind); break; | |
6612 | |
6613 case lir_null_check: | |
6614 case lir_leal: | |
6615 case lir_instanceof: | |
6616 case lir_checkcast: | |
6617 case lir_store_check: inc_counter(counter_typecheck); break; | |
6618 | |
6619 case lir_fpop_raw: | |
6620 case lir_fxch: | |
6621 case lir_fld: inc_counter(counter_fpu_stack); break; | |
6622 | |
6623 case lir_nop: | |
6624 case lir_push: | |
6625 case lir_pop: | |
6626 case lir_convert: | |
6627 case lir_roundfp: | |
6628 case lir_cmove: inc_counter(counter_misc_inst); break; | |
6629 | |
6630 default: inc_counter(counter_other_inst); break; | |
6631 } | |
6632 } | |
6633 } | |
6634 | |
6635 if (has_xhandlers) { | |
6636 inc_counter(counter_exception_method); | |
6637 } | |
6638 } | |
6639 | |
6640 void LinearScanStatistic::compute(LinearScan* allocator, LinearScanStatistic &global_statistic) { | |
6641 if (CountLinearScan || TraceLinearScanLevel > 0) { | |
6642 | |
6643 LinearScanStatistic local_statistic = LinearScanStatistic(); | |
6644 | |
6645 local_statistic.collect(allocator); | |
6646 global_statistic.sum_up(local_statistic); | |
6647 | |
6648 if (TraceLinearScanLevel > 2) { | |
6649 local_statistic.print("current local statistic"); | |
6650 } | |
6651 } | |
6652 } | |
6653 | |
6654 | |
6655 // Implementation of LinearTimers | |
6656 | |
6657 LinearScanTimers::LinearScanTimers() { | |
6658 for (int i = 0; i < number_of_timers; i++) { | |
6659 timer(i)->reset(); | |
6660 } | |
6661 } | |
6662 | |
6663 const char* LinearScanTimers::timer_name(int idx) { | |
6664 switch (idx) { | |
6665 case timer_do_nothing: return "Nothing (Time Check)"; | |
6666 case timer_number_instructions: return "Number Instructions"; | |
6667 case timer_compute_local_live_sets: return "Local Live Sets"; | |
6668 case timer_compute_global_live_sets: return "Global Live Sets"; | |
6669 case timer_build_intervals: return "Build Intervals"; | |
6670 case timer_sort_intervals_before: return "Sort Intervals Before"; | |
6671 case timer_allocate_registers: return "Allocate Registers"; | |
6672 case timer_resolve_data_flow: return "Resolve Data Flow"; | |
6673 case timer_sort_intervals_after: return "Sort Intervals After"; | |
6674 case timer_eliminate_spill_moves: return "Spill optimization"; | |
6675 case timer_assign_reg_num: return "Assign Reg Num"; | |
6676 case timer_allocate_fpu_stack: return "Allocate FPU Stack"; | |
6677 case timer_optimize_lir: return "Optimize LIR"; | |
6678 default: ShouldNotReachHere(); return ""; | |
6679 } | |
6680 } | |
6681 | |
6682 void LinearScanTimers::begin_method() { | |
6683 if (TimeEachLinearScan) { | |
6684 // reset all timers to measure only current method | |
6685 for (int i = 0; i < number_of_timers; i++) { | |
6686 timer(i)->reset(); | |
6687 } | |
6688 } | |
6689 } | |
6690 | |
6691 void LinearScanTimers::end_method(LinearScan* allocator) { | |
6692 if (TimeEachLinearScan) { | |
6693 | |
6694 double c = timer(timer_do_nothing)->seconds(); | |
6695 double total = 0; | |
6696 for (int i = 1; i < number_of_timers; i++) { | |
6697 total += timer(i)->seconds() - c; | |
6698 } | |
6699 | |
6700 if (total >= 0.0005) { | |
6701 // print all information in one line for automatic processing | |
6702 tty->print("@"); allocator->compilation()->method()->print_name(); | |
6703 | |
6704 tty->print("@ %d ", allocator->compilation()->method()->code_size()); | |
6705 tty->print("@ %d ", allocator->block_at(allocator->block_count() - 1)->last_lir_instruction_id() / 2); | |
6706 tty->print("@ %d ", allocator->block_count()); | |
6707 tty->print("@ %d ", allocator->num_virtual_regs()); | |
6708 tty->print("@ %d ", allocator->interval_count()); | |
6709 tty->print("@ %d ", allocator->_num_calls); | |
6710 tty->print("@ %d ", allocator->num_loops()); | |
6711 | |
6712 tty->print("@ %6.6f ", total); | |
6713 for (int i = 1; i < number_of_timers; i++) { | |
6714 tty->print("@ %4.1f ", ((timer(i)->seconds() - c) / total) * 100); | |
6715 } | |
6716 tty->cr(); | |
6717 } | |
6718 } | |
6719 } | |
6720 | |
6721 void LinearScanTimers::print(double total_time) { | |
6722 if (TimeLinearScan) { | |
6723 // correction value: sum of dummy-timer that only measures the time that | |
6724 // is necesary to start and stop itself | |
6725 double c = timer(timer_do_nothing)->seconds(); | |
6726 | |
6727 for (int i = 0; i < number_of_timers; i++) { | |
6728 double t = timer(i)->seconds(); | |
6729 tty->print_cr(" %25s: %6.3f s (%4.1f%%) corrected: %6.3f s (%4.1f%%)", timer_name(i), t, (t / total_time) * 100.0, t - c, (t - c) / (total_time - 2 * number_of_timers * c) * 100); | |
6730 } | |
6731 } | |
6732 } | |
6733 | |
6734 #endif // #ifndef PRODUCT |