Mercurial > hg > truffle
annotate src/os_cpu/windows_x86/vm/windows_x86_64.ad @ 3883:ce9bde819dcb hs22-b04
7086589: bump the hs22 build number to 04
Reviewed-by: johnc
Contributed-by: alejandro.murillo@oracle.com
| author | jcoomes |
|---|---|
| date | Fri, 02 Sep 2011 03:49:30 -0700 |
| parents | 3e8fbc61cee8 |
| children | 9b8ce46870df |
| rev | line source |
|---|---|
| 0 | 1 // |
| 1748 | 2 // Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // AMD64 Win32 Architecture Description File | |
| 26 | |
| 27 //----------OS-DEPENDENT ENCODING BLOCK----------------------------------------------------- | |
| 28 // This block specifies the encoding classes used by the compiler to output | |
| 29 // byte streams. Encoding classes generate functions which are called by | |
| 30 // Machine Instruction Nodes in order to generate the bit encoding of the | |
| 31 // instruction. Operands specify their base encoding interface with the | |
| 32 // interface keyword. There are currently supported four interfaces, | |
| 33 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
| 34 // operand to generate a function which returns its register number when | |
| 35 // queried. CONST_INTER causes an operand to generate a function which | |
| 36 // returns the value of the constant when queried. MEMORY_INTER causes an | |
| 37 // operand to generate four functions which return the Base Register, the | |
| 38 // Index Register, the Scale Value, and the Offset Value of the operand when | |
| 39 // queried. COND_INTER causes an operand to generate six functions which | |
| 40 // return the encoding code (ie - encoding bits for the instruction) | |
| 41 // associated with each basic boolean condition for a conditional instruction. | |
| 42 // Instructions specify two basic values for encoding. They use the | |
| 43 // ins_encode keyword to specify their encoding class (which must be one of | |
| 44 // the class names specified in the encoding block), and they use the | |
| 45 // opcode keyword to specify, in order, their primary, secondary, and | |
| 46 // tertiary opcode. Only the opcode sections which a particular instruction | |
| 47 // needs for encoding need to be specified. | |
| 48 encode %{ | |
| 49 // Build emit functions for each basic byte or larger field in the intel | |
| 50 // encoding scheme (opcode, rm, sib, immediate), and call them from C++ | |
| 51 // code in the enc_class source block. Emit functions will live in the | |
| 52 // main source block for now. In future, we can generalize this by | |
| 53 // adding a syntax that specifies the sizes of fields in an order, | |
| 54 // so that the adlc can build the emit functions automagically | |
| 55 | |
| 56 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime | |
| 57 // No relocation needed | |
| 58 | |
| 59 // movq r10, <meth> | |
| 60 emit_opcode(cbuf, Assembler::REX_WB); | |
| 61 emit_opcode(cbuf, 0xB8 | (R10_enc - 8)); | |
| 62 emit_d64(cbuf, (int64_t) $meth$$method); | |
| 63 | |
| 64 // call (r10) | |
| 65 emit_opcode(cbuf, Assembler::REX_B); | |
| 66 emit_opcode(cbuf, 0xFF); | |
| 67 emit_opcode(cbuf, 0xD0 | (R10_enc - 8)); | |
| 68 %} | |
| 69 | |
| 70 enc_class call_epilog %{ | |
| 71 if (VerifyStackAtCalls) { | |
| 72 // Check that stack depth is unchanged: find majik cookie on stack | |
| 73 int framesize = | |
| 74 ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word)); | |
| 75 if (framesize) { | |
| 76 if (framesize < 0x80) { | |
| 77 emit_opcode(cbuf, Assembler::REX_W); | |
| 78 emit_opcode(cbuf, 0x81); // cmpq [rsp+0],0xbadb1ood | |
| 79 emit_d8(cbuf, 0x7C); | |
| 80 emit_d8(cbuf, 0x24); | |
| 81 emit_d8(cbuf, framesize); // Find majik cookie from ESP | |
| 82 emit_d32(cbuf, 0xbadb100d); | |
| 83 } else { | |
| 84 emit_opcode(cbuf, Assembler::REX_W); | |
| 85 emit_opcode(cbuf, 0x81); // cmpq [rsp+0],0xbadb1ood | |
| 86 emit_d8(cbuf, 0xBC); | |
| 87 emit_d8(cbuf, 0x24); | |
| 88 emit_d32(cbuf, framesize); // Find majik cookie from ESP | |
| 89 emit_d32(cbuf, 0xbadb100d); | |
| 90 } | |
| 91 } | |
| 92 // jmp EQ around INT3 | |
| 93 // QQQ TODO | |
| 94 const int jump_around = 5; // size of call to breakpoint, 1 for CC | |
| 95 emit_opcode(cbuf, 0x74); | |
| 96 emit_d8(cbuf, jump_around); | |
| 97 // QQQ temporary | |
| 98 emit_break(cbuf); | |
| 99 // Die if stack mismatch | |
| 100 // emit_opcode(cbuf,0xCC); | |
| 101 } | |
| 102 %} | |
| 103 %} | |
| 104 | |
| 105 // INSTRUCTIONS -- Platform dependent | |
| 106 | |
| 107 | |
| 108 //----------OS and Locking Instructions---------------------------------------- | |
| 109 | |
| 110 // This name is KNOWN by the ADLC and cannot be changed. | |
| 111 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 112 // for this guy. | |
| 113 instruct tlsLoadP(r15_RegP dst) | |
| 114 %{ | |
| 115 match(Set dst (ThreadLocal)); | |
| 116 effect(DEF dst); | |
| 117 | |
| 118 size(0); | |
| 119 format %{ "# TLS is in R15" %} | |
| 120 ins_encode( /*empty encoding*/ ); | |
| 121 ins_pipe(ialu_reg_reg); | |
| 122 %} | |
| 123 | |
| 124 // Die now | |
| 125 instruct ShouldNotReachHere( ) | |
| 126 %{ | |
| 127 match(Halt); | |
| 128 // Use the following format syntax | |
| 129 format %{ "INT3 ; ShouldNotReachHere" %} | |
| 130 opcode(0xCC); | |
| 131 ins_encode(OpcP); | |
| 132 ins_pipe( pipe_slow ); | |
| 133 %} | |
| 134 | |
| 135 // | |
| 136 // Platform dependent source | |
| 137 // | |
| 138 source %{ | |
| 139 | |
| 140 int MachCallRuntimeNode::ret_addr_offset() | |
| 141 { | |
| 142 return 13; // movq r10,#addr; callq (r10) | |
| 143 } | |
| 144 | |
| 145 // emit an interrupt that is caught by the debugger | |
| 146 void emit_break(CodeBuffer &cbuf) { | |
| 1748 | 147 cbuf.insts()->emit_int8((unsigned char) 0xcc); |
| 0 | 148 } |
| 149 | |
| 150 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 151 emit_break(cbuf); | |
| 152 } | |
| 153 | |
| 154 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { | |
| 155 return 1; | |
| 156 } | |
| 157 | |
| 158 %} |