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comparison src/cpu/sparc/vm/vm_version_sparc.cpp @ 14261:00f5eff62d18

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8002074: Support for AES on SPARC Summary: Add intrinsics/stub routines support for single-block and multi-block (as used by Cipher Block Chaining mode) AES encryption and decryption operations on the SPARC platform. Reviewed-by: kvn, roland Contributed-by: shrinivas.joshi@oracle.com
author kvn
date Tue, 14 Jan 2014 17:46:48 -0800
parents de6a9e811145
children 4ca6dc0799b6 03214612e77e
comparison
equal deleted inserted replaced
14260:8cdf3f43f63e 14261:00f5eff62d18
232 232
233 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); 233 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
234 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); 234 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
235 235
236 char buf[512]; 236 char buf[512];
237 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s", 237 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
238 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")), 238 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
239 (has_hardware_popc() ? ", popc" : ""), 239 (has_hardware_popc() ? ", popc" : ""),
240 (has_vis1() ? ", vis1" : ""), 240 (has_vis1() ? ", vis1" : ""),
241 (has_vis2() ? ", vis2" : ""), 241 (has_vis2() ? ", vis2" : ""),
242 (has_vis3() ? ", vis3" : ""), 242 (has_vis3() ? ", vis3" : ""),
243 (has_blk_init() ? ", blk_init" : ""), 243 (has_blk_init() ? ", blk_init" : ""),
244 (has_cbcond() ? ", cbcond" : ""), 244 (has_cbcond() ? ", cbcond" : ""),
245 (has_aes() ? ", aes" : ""),
245 (is_ultra3() ? ", ultra3" : ""), 246 (is_ultra3() ? ", ultra3" : ""),
246 (is_sun4v() ? ", sun4v" : ""), 247 (is_sun4v() ? ", sun4v" : ""),
247 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")), 248 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
248 (is_sparc64() ? ", sparc64" : ""), 249 (is_sparc64() ? ", sparc64" : ""),
249 (!has_hardware_mul32() ? ", no-mul32" : ""), 250 (!has_hardware_mul32() ? ", no-mul32" : ""),
263 if (!has_vis2()) // Drop to 1 if no VIS2 support 264 if (!has_vis2()) // Drop to 1 if no VIS2 support
264 UseVIS = MIN2((intx)1,UseVIS); 265 UseVIS = MIN2((intx)1,UseVIS);
265 if (!has_vis1()) // Drop to 0 if no VIS1 support 266 if (!has_vis1()) // Drop to 0 if no VIS1 support
266 UseVIS = 0; 267 UseVIS = 0;
267 268
269 // T2 and above should have support for AES instructions
270 if (has_aes()) {
271 if (UseVIS > 0) { // AES intrinsics use FXOR instruction which is VIS1
272 if (FLAG_IS_DEFAULT(UseAES)) {
273 FLAG_SET_DEFAULT(UseAES, true);
274 }
275 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
276 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
277 }
278 // we disable both the AES flags if either of them is disabled on the command line
279 if (!UseAES || !UseAESIntrinsics) {
280 FLAG_SET_DEFAULT(UseAES, false);
281 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
282 }
283 } else {
284 if (UseAES || UseAESIntrinsics) {
285 warning("SPARC AES intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
286 if (UseAES) {
287 FLAG_SET_DEFAULT(UseAES, false);
288 }
289 if (UseAESIntrinsics) {
290 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
291 }
292 }
293 }
294 } else if (UseAES || UseAESIntrinsics) {
295 warning("AES instructions are not available on this CPU");
296 if (UseAES) {
297 FLAG_SET_DEFAULT(UseAES, false);
298 }
299 if (UseAESIntrinsics) {
300 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
301 }
302 }
303
268 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && 304 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
269 (cache_line_size > ContendedPaddingWidth)) 305 (cache_line_size > ContendedPaddingWidth))
270 ContendedPaddingWidth = cache_line_size; 306 ContendedPaddingWidth = cache_line_size;
271 307
272 #ifndef PRODUCT 308 #ifndef PRODUCT