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comparison src/cpu/sparc/vm/assembler_sparc.hpp @ 17910:03214612e77e

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8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc Summary: Fix the arbitrary alignment issue in SPARC AES crypto stub routines. Reviewed-by: kvn, iveresov Contributed-by: shrinivas.joshi@oracle.com
author kvn
date Wed, 30 Apr 2014 14:14:01 -0700
parents 17b2fbdb6637
children 52b4284cb496 b20a35eae442
comparison
equal deleted inserted replaced
17909:85d6efcb1fa3 17910:03214612e77e
1 /* 1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. 2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 * 4 *
5 * This code is free software; you can redistribute it and/or modify it 5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as 6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
121 121
122 fpop1_op3 = 0x34, 122 fpop1_op3 = 0x34,
123 fpop2_op3 = 0x35, 123 fpop2_op3 = 0x35,
124 impdep1_op3 = 0x36, 124 impdep1_op3 = 0x36,
125 aes3_op3 = 0x36, 125 aes3_op3 = 0x36,
126 alignaddr_op3 = 0x36,
127 faligndata_op3 = 0x36,
126 flog3_op3 = 0x36, 128 flog3_op3 = 0x36,
129 edge_op3 = 0x36,
130 fsrc_op3 = 0x36,
127 impdep2_op3 = 0x37, 131 impdep2_op3 = 0x37,
132 stpartialf_op3 = 0x37,
128 jmpl_op3 = 0x38, 133 jmpl_op3 = 0x38,
129 rett_op3 = 0x39, 134 rett_op3 = 0x39,
130 trap_op3 = 0x3a, 135 trap_op3 = 0x3a,
131 flush_op3 = 0x3b, 136 flush_op3 = 0x3b,
132 save_op3 = 0x3c, 137 save_op3 = 0x3c,
173 cc_bit_op3 = 0x10 178 cc_bit_op3 = 0x10
174 }; 179 };
175 180
176 enum opfs { 181 enum opfs {
177 // selected opfs 182 // selected opfs
183 edge8n_opf = 0x01,
184
178 fmovs_opf = 0x01, 185 fmovs_opf = 0x01,
179 fmovd_opf = 0x02, 186 fmovd_opf = 0x02,
180 187
181 fnegs_opf = 0x05, 188 fnegs_opf = 0x05,
182 fnegd_opf = 0x06, 189 fnegd_opf = 0x06,
190
191 alignaddr_opf = 0x18,
183 192
184 fadds_opf = 0x41, 193 fadds_opf = 0x41,
185 faddd_opf = 0x42, 194 faddd_opf = 0x42,
186 fsubs_opf = 0x45, 195 fsubs_opf = 0x45,
187 fsubd_opf = 0x46, 196 fsubd_opf = 0x46,
197
198 faligndata_opf = 0x48,
188 199
189 fmuls_opf = 0x49, 200 fmuls_opf = 0x49,
190 fmuld_opf = 0x4a, 201 fmuld_opf = 0x4a,
191 fdivs_opf = 0x4d, 202 fdivs_opf = 0x4d,
192 fdivd_opf = 0x4e, 203 fdivd_opf = 0x4e,
346 357
347 enum ASIs { // page 72, v9 358 enum ASIs { // page 72, v9
348 ASI_PRIMARY = 0x80, 359 ASI_PRIMARY = 0x80,
349 ASI_PRIMARY_NOFAULT = 0x82, 360 ASI_PRIMARY_NOFAULT = 0x82,
350 ASI_PRIMARY_LITTLE = 0x88, 361 ASI_PRIMARY_LITTLE = 0x88,
362 // 8x8-bit partial store
363 ASI_PST8_PRIMARY = 0xC0,
351 // Block initializing store 364 // Block initializing store
352 ASI_ST_BLKINIT_PRIMARY = 0xE2, 365 ASI_ST_BLKINIT_PRIMARY = 0xE2,
353 // Most-Recently-Used (MRU) BIS variant 366 // Most-Recently-Used (MRU) BIS variant
354 ASI_ST_BLKINIT_MRU_PRIMARY = 0xF2 367 ASI_ST_BLKINIT_MRU_PRIMARY = 0xF2
355 // add more from book as needed 368 // add more from book as needed
582 // AES crypto instructions supported only on certain processors 595 // AES crypto instructions supported only on certain processors
583 static void aes_only() { assert( VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); } 596 static void aes_only() { assert( VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); }
584 597
585 // instruction only in VIS1 598 // instruction only in VIS1
586 static void vis1_only() { assert( VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); } 599 static void vis1_only() { assert( VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
600
601 // instruction only in VIS2
602 static void vis2_only() { assert( VM_Version::has_vis2(), "This instruction only works on SPARC with VIS2"); }
587 603
588 // instruction only in VIS3 604 // instruction only in VIS3
589 static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); } 605 static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
590 606
591 // instruction only in v9 607 // instruction only in v9
1162 inline void wrasi(Register d, int simm13a) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | 1178 inline void wrasi(Register d, int simm13a) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) |
1163 u_field(3, 29, 25) | immed(true) | simm(simm13a, 13)); } 1179 u_field(3, 29, 25) | immed(true) | simm(simm13a, 13)); }
1164 inline void wrfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); } 1180 inline void wrfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
1165 1181
1166 1182
1183 // VIS1 instructions
1184
1185 void alignaddr( Register s1, Register s2, Register d ) { vis1_only(); emit_int32( op(arith_op) | rd(d) | op3(alignaddr_op3) | rs1(s1) | opf(alignaddr_opf) | rs2(s2)); }
1186
1187 void faligndata( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(faligndata_op3) | fs1(s1, FloatRegisterImpl::D) | opf(faligndata_opf) | fs2(s2, FloatRegisterImpl::D)); }
1188
1189 void fsrc2( FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fsrc_op3) | opf(0x7A - w) | fs2(s2, w)); }
1190
1191 void stpartialf( Register s1, Register s2, FloatRegister d, int ia = -1 ) { vis1_only(); emit_int32( op(ldst_op) | fd(d, FloatRegisterImpl::D) | op3(stpartialf_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); }
1192
1193 // VIS2 instructions
1194
1195 void edge8n( Register s1, Register s2, Register d ) { vis2_only(); emit_int32( op(arith_op) | rd(d) | op3(edge_op3) | rs1(s1) | opf(edge8n_opf) | rs2(s2)); }
1196
1167 // VIS3 instructions 1197 // VIS3 instructions
1168 1198
1169 void movstosw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); } 1199 void movstosw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); }
1170 void movstouw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); } 1200 void movstouw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); }
1171 void movdtox( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); } 1201 void movdtox( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); }